Semiconductor structure and method of manufacturing the same, electronic device

Abstract

This application relates to a semiconductor structure, a method for manufacturing the same, and an electronic device. The method for manufacturing the semiconductor structure includes the following steps: forming word lines and a gate dielectric layer surrounding the word lines; sequentially stacking a semiconductor material layer, a doped material layer, and a capping material layer on the surface of the gate dielectric layer opposite to the word lines; the doped material layer containing target dopant ions; and performing a heat treatment process and a patterning process on the resulting structure after forming the semiconductor material layer, the doped layer, and the capping material layer to correspondingly form the capping layer, the doped layer, and the semiconductor layer, and doping the semiconductor layer with target dopant ions. This application aims to improve and enhance the device performance and reliability of semiconductor structures.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor structure and its manufacturing method, and an electronic device. Background Technology

[0002] With the development of integrated circuit technology, the critical dimensions of devices are shrinking. Using metal oxide semiconductor materials as device channel materials is beneficial to improving integration while ensuring device performance and reliability. Summary of the Invention

[0003] Based on this, this application provides a semiconductor structure and its manufacturing method, as well as an electronic device, which can improve and enhance the device performance and reliability of the semiconductor structure.

[0004] In a first aspect, this application provides a method for manufacturing a semiconductor structure, the method comprising the following steps:

[0005] Forming word lines and a surrounding grid dielectric layer;

[0006] A semiconductor material layer, a doped material layer, and a cover material layer are sequentially stacked on the surface of the gate dielectric layer away from the word line; the doped material layer contains target doped ions.

[0007] The resulting structure after forming a semiconductor material layer, a doped material layer, and a capping material layer is subjected to a heat treatment process and a patterning process to form a capping layer, a doped layer, and a semiconductor layer, and the semiconductor layer is doped with target dopant ions.

[0008] In some embodiments of this application, the word lines extend along a first direction parallel to the substrate. The formation of the word lines and the gate dielectric layer surrounding the word lines includes the following steps:

[0009] A substrate is provided, and a stacked structure is formed on the substrate, the stacked structure comprising alternating layers of multiple first dielectric layers and multiple layers of second dielectric layers;

[0010] Etch the stacked structure to form a first trench that penetrates the stacked structure and extends along a first direction;

[0011] A word line receiving groove is formed by etching the first dielectric layer based on the first trench;

[0012] Character lines are formed within the character line receiving groove;

[0013] A patterned stacked structure is formed to create a capacitor accommodating region and a bit line accommodating region on both sides of a word line along a second direction parallel to the substrate, and a second dielectric layer is removed from the capacitor accommodating region, the bit line accommodating region, and the region between them; the second direction intersects with the first direction;

[0014] A gate dielectric material layer is deposited in the capacitor accommodating region, the bit line accommodating region, and the removal region of the second dielectric layer.

[0015] In some embodiments of this application, a portion of the first dielectric layer is retained as a sacrificial layer at the end of the word line near the capacitor containment region. The gate dielectric material layer surrounds the overall structure composed of the word line and the sacrificial layer.

[0016] Accordingly, a patterning process is performed on the resulting structure after forming the semiconductor material layer, the doped material layer, and the capping material layer, including the following steps:

[0017] The cover material layer and the doped material layer are etched based on the bit line accommodating region until the semiconductor material layer is exposed to obtain the initial cover layer and the initial doped layer.

[0018] Based on the capacitor accumulator region, an initial capping layer, an initial doped layer, a semiconductor material layer, a gate dielectric material layer, and a sacrificial layer are etched until the word line is exposed at one end near the capacitor accumulator region, thereby obtaining a capping layer, a doped layer, a semiconductor layer, and a first gate dielectric layer.

[0019] In some embodiments of this application, the method for manufacturing a semiconductor structure further includes the following steps:

[0020] A second gate dielectric layer is formed to cover one end of the word line near the capacitor storage area; the second gate dielectric layer is connected to the first gate dielectric layer;

[0021] A first source / drain is formed on the side of the second gate dielectric layer away from the word line; the first source / drain is connected to the semiconductor layer;

[0022] A first electrode, a dielectric layer, and a second electrode of a capacitor are sequentially formed in the capacitor accommodating region; the first electrode is connected to the corresponding first source / drain electrode.

[0023] In some embodiments of this application, before performing a patterning process on the resulting structure after forming a semiconductor material layer, a doped material layer, and a cover material layer, the manufacturing method further includes: filling a first insulating layer in the capacitor accommodating region, the bit line accommodating region, and the removal region of the second dielectric layer, wherein the first insulating layer covers the cover material layer.

[0024] Accordingly, the etching of the initial capping layer, initial doped layer, semiconductor material layer, gate dielectric material layer, and sacrificial layer based on the capacitor accommodating region until the word line near the capacitor accommodating region is exposed, thereby obtaining the capping layer, doped layer, semiconductor layer, and first gate dielectric layer, includes the following steps:

[0025] Remove the first insulating layer, initial capping layer, and initial doped layer from the capacitor accommodating region and part of the removal region of the second dielectric layer to form the remaining first insulating layer, capping layer, and doped layer;

[0026] Patterning a semiconductor material layer and a gate dielectric material layer to form a semiconductor layer and a first gate dielectric layer, and exposing a sacrificial layer;

[0027] A protective layer and a second insulating layer are sequentially deposited in the removal regions of the semiconductor material layer and the gate dielectric material layer, and the protective layer and the second insulating layer in the capacitor accommodating region are removed.

[0028] The sacrificial layer is removed based on the capacitor containment region, and the first dielectric layer is patterned to expose the word line near the capacitor containment region.

[0029] Accordingly, the manufacturing method further includes: sequentially forming a second gate dielectric layer and a silicon oxide layer in the removal region of the sacrificial layer, wherein the second gate dielectric layer is connected to the first gate dielectric layer and the silicon oxide layer is located on the side of the second gate dielectric layer away from the word line; sequentially forming a first source / drain and a first electrode in the removal regions of the sacrificial layer and the first dielectric layer; forming a dielectric layer covering the first electrode and a second electrode covering the dielectric layer in the removal regions of the sacrificial layer and the first dielectric layer and the capacitor accommodating region.

[0030] In some embodiments of this application, the method for manufacturing a semiconductor structure further includes: forming a bit line connecting the semiconductor layer in the bit line accommodating region; the bit line extending in a direction perpendicular to the substrate.

[0031] In some embodiments of this application, the method for manufacturing a semiconductor structure further includes: patterning a stacked structure to form a process trench; and removing parasitic portions of the semiconductor layer based on the process trench.

[0032] In other embodiments of this application, the word lines extend along a direction perpendicular to the substrate. The formation of the word lines and the gate dielectric layer surrounding the word lines includes the following steps:

[0033] A substrate is provided, and a stacked structure is formed on the substrate; the stacked structure includes multiple layers of first dielectric layers and multiple layers of second dielectric layers stacked alternately;

[0034] Etch the stacked structure to form word line holes that penetrate the stacked structure;

[0035] Character lines are formed within the character line holes;

[0036] Etch the stacked structure to form the first process hole that penetrates the stacked structure;

[0037] Based on the first process hole, the first dielectric layer located around the character line is patterned;

[0038] A gate dielectric material layer is deposited on the inner wall of the first process hole and in the removal area of ​​the first dielectric layer.

[0039] In some embodiments of this application, a patterning process is performed on the resulting structure after forming a semiconductor material layer, a doped material layer, and a cover material layer, including: patterning the cover material layer, the doped material layer, the semiconductor material layer after doping with target doped ions, and the gate dielectric material layer based on a first process hole to obtain a cover layer, a doped layer, a semiconductor layer, and a gate dielectric layer.

[0040] In some embodiments of this application, the doped material layer is a polymer layer containing fluorine ions. The doped material layer is formed using initiated chemical vapor deposition or atomic layer deposition.

[0041] In some embodiments of this application, forming a doped material layer includes: depositing a fluoropolymer on the surface of a semiconductor material layer away from the gate dielectric layer using an atomic layer deposition process to form a precursor-like monomer; and depositing a polymerization initiator on the surface of the precursor-like monomer away from the semiconductor material layer using an initiation chemical vapor deposition or atomic layer deposition process to obtain a doped material layer.

[0042] In some embodiments of this application, the heat treatment process includes annealing; the temperature range for annealing is 150°C to 400°C.

[0043] In some embodiments of this application, the target dopant ions include fluorine ions. The doping concentration of fluorine ions in the semiconductor layer is less than or equal to 4E21cm⁻¹. -3 .

[0044] In some embodiments of this application, the material covering the material layer includes at least one of alumina, silicon oxide, or silicon nitride.

[0045] Secondly, this application also provides a semiconductor structure, including word lines and a stacked gate dielectric layer and semiconductor layer surrounding the word lines; wherein, the semiconductor layer has a stacked structure of doped layers and capping layers on two opposite sides in the target direction; the semiconductor layer is doped with target doped ions contained in the doped layer.

[0046] In some embodiments of this application, word lines extend along a first direction parallel to the substrate. The target direction is a direction perpendicular to the substrate. The semiconductor structure further includes capacitors and bit lines located on both sides of the word lines along a second direction parallel to the substrate. The second direction intersects the first direction. The bit lines are connected to a first end of the semiconductor layer and extend in a direction perpendicular to the substrate. The capacitor includes a first electrode connected to a second end of the semiconductor layer, a second electrode located on the side of the first electrode opposite to the semiconductor layer, and a dielectric layer located between the first and second electrodes.

[0047] In some embodiments of this application, the second end of the semiconductor layer is connected to the first electrode via a first source / drain. The first source / drain surrounds the surface of the first electrode that is away from the dielectric layer.

[0048] Optionally, the first source / drain electrode and the semiconductor layer are made of the same material.

[0049] In other embodiments of this application, the word lines extend along a direction perpendicular to the substrate. The target direction is a first direction parallel to the substrate. The semiconductor structure further includes capacitors and bit lines located on both sides of the word lines along a second direction parallel to the substrate. The second direction intersects the first direction; wherein the bit lines are connected to the semiconductor layer and extend along the first direction.

[0050] Thirdly, this application also provides an electronic device, including a semiconductor structure prepared by the manufacturing method of the semiconductor structure described in some of the above embodiments; or the semiconductor structure described above.

[0051] The embodiments of this application may have, or at least have, the following advantages:

[0052] In the above-described semiconductor structure manufacturing method, after forming word lines and a gate dielectric layer surrounding the word lines, a semiconductor material layer, a doped material layer, and a capping material layer are sequentially stacked on the surface of the gate dielectric layer opposite to the word lines. A heat treatment process and a patterning process are then performed on the resulting structure to correspondingly form a capping layer, a doped layer, and a semiconductor layer, and to dope the semiconductor layer with target doped ions. In the embodiments of this application, the target doped ions contained in the doped material layer can be doped into the semiconductor layer while the capping material layer prevents the target doped ions from diffusing outwards. This repairs vacancies in the semiconductor layer, ensuring improved material properties, thereby enhancing the device performance and reliability of the semiconductor structure. For example, it can promote a positive shift in the device threshold voltage to maintain a higher switching current and improve the transistor's on / off control capability.

[0053] Furthermore, the aforementioned semiconductor structure retains doped and capping layers, meaning that with proper process design, the complete removal of doped and capping layers can be avoided. This prevents the channel region of the semiconductor layer from being etched and damaged by the removal process of doped and capping layers, which helps to further ensure and improve the device performance and reliability of the semiconductor structure. Attached Figure Description

[0054] To more clearly illustrate the technical solutions in the embodiments or conventional technologies of this disclosure, the accompanying drawings used in the description of the embodiments or conventional technologies will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0055] Figure 1 A flowchart illustrating a method for manufacturing a semiconductor structure as provided in some embodiments;

[0056] Figure 2This is a three-dimensional structural diagram of a structure obtained after forming a stacked structure, provided in some embodiments;

[0057] Figure 3 This is a three-dimensional structural diagram of a structure obtained after forming word lines, provided in some embodiments;

[0058] Figure 4 This is a three-dimensional structural diagram of the structure obtained after forming a reference region for a capacitor accommodating region and a bit line accommodating region, as provided in some embodiments.

[0059] Figure 5 This is a three-dimensional structural diagram of a structure obtained after forming a sacrificial layer, provided in some embodiments;

[0060] Figure 6 This is a three-dimensional structural diagram of a structure obtained after forming a semiconductor material layer, provided in some embodiments;

[0061] Figure 7 This is a three-dimensional structural diagram of a structure obtained after forming a doped material layer, provided in some embodiments;

[0062] Figure 8 This is a three-dimensional structural diagram of a structure obtained after forming a covering material layer, provided in some embodiments;

[0063] Figure 9 This is a schematic diagram illustrating the process of heat treatment after sequentially stacking a semiconductor material layer, a doped material layer, and a cover material layer in some embodiments.

[0064] Figure 10 This is a schematic diagram illustrating the process of heat treatment after sequentially stacking a semiconductor material layer, a doped material layer, and a cover material layer in some embodiments.

[0065] Figure 11 This is a three-dimensional structural diagram of a structure obtained after forming a first insulating layer, provided in some embodiments;

[0066] Figure 12 for Figure 11 The diagram shows a three-dimensional structural schematic of a structure obtained when the second dielectric layer is used as the cross-section.

[0067] Figure 13 This is a three-dimensional structural diagram of a structure obtained after forming bit lines, provided in some embodiments;

[0068] Figure 14 This is a three-dimensional structural diagram of the structure obtained after removing the first insulating layer, the initial capping layer and the initial doped layer in the capacitor accommodating trench, as provided in some embodiments.

[0069] Figure 15 This is a three-dimensional structural diagram of a structure obtained after patterning the remaining first insulating layer, initial capping layer and initial doped layer in some embodiments;

[0070] Figure 16 This is a three-dimensional structural diagram of a structure obtained after forming a semiconductor layer and a gate dielectric layer, provided in some embodiments;

[0071] Figure 17 This is a three-dimensional structural diagram of a structure obtained after forming a protective layer and a second insulating layer, provided in some embodiments;

[0072] Figure 18 This is a three-dimensional structural diagram of a structure obtained after a patterned protective layer and a second insulating layer, as provided in some embodiments;

[0073] Figure 19 This is a three-dimensional structural diagram of a structure obtained after removing the sacrificial layer, provided in some embodiments;

[0074] Figure 20 This is a three-dimensional structural diagram of a structure obtained after forming a second gate dielectric material layer and a silicon oxide material layer, as provided in some embodiments;

[0075] Figure 21 This is a three-dimensional structural diagram of a structure obtained after forming a second gate dielectric layer and a silicon oxide layer, provided in some embodiments;

[0076] Figure 22 This is a three-dimensional structural diagram of a structure obtained after a patterned protective layer is provided in some embodiments;

[0077] Figure 23 This is a three-dimensional structural diagram of a structure obtained after forming a source / drain material layer, a first electrode material layer and a third insulating layer, as provided in some embodiments;

[0078] Figure 24 This is a three-dimensional structural schematic diagram of a structure obtained after forming a first source / drain and a first electrode, as provided in some embodiments;

[0079] Figure 25 This is a three-dimensional structural diagram of a structure obtained after forming a capacitor, provided in some embodiments;

[0080] Figure 26 This is a three-dimensional structural diagram of the structure obtained after removing the first isolation structure and the first support structure between adjacent bit lines, as provided in some embodiments.

[0081] Figure 27This is a three-dimensional structural diagram of a structure obtained after removing the parasitic semiconductor layer, provided in some embodiments;

[0082] Figure 28 This is a partial top view of a semiconductor structure provided in some embodiments;

[0083] Figure 29 This is a schematic diagram illustrating the process of heat treatment after sequentially stacking a semiconductor material layer, a doped material layer, and a cover material layer, as provided in some embodiments of another semiconductor structure.

[0084] Figure 30 This is a three-dimensional structural diagram of another structure obtained after forming a stacked structure, as provided in some embodiments;

[0085] Figure 31 This is a three-dimensional structural diagram of a structure obtained after forming word line holes and capacitor holes in some embodiments;

[0086] Figure 32 This is a three-dimensional structural diagram of a structure obtained after forming the first isolation groove, provided in some embodiments;

[0087] Figure 33 This is a three-dimensional structural diagram of a structure obtained after forming a first isolation structure, provided in some embodiments;

[0088] Figure 34 This is a three-dimensional structural diagram of a structure obtained after forming a second isolation structure, provided in some embodiments;

[0089] Figure 35 This is a three-dimensional structural diagram of a structure obtained after forming word lines, provided in some embodiments;

[0090] Figure 36 This is a three-dimensional structural diagram of a structure obtained after forming a first process hole and removing the corresponding first dielectric layer, as provided in some embodiments;

[0091] Figure 37 This is a three-dimensional structural diagram of a structure obtained after the first deposition of a semiconductor material layer, as provided in some embodiments;

[0092] Figure 38 This is a three-dimensional structural diagram of a structure obtained after forming a source / drain electrode material layer, as provided in some embodiments;

[0093] Figure 39 This is a three-dimensional structural diagram of a structure obtained after forming a first source / drain and a second source / drain, provided in some embodiments;

[0094] Figure 40This is a three-dimensional structural diagram of a structure obtained after a second deposition of a semiconductor material layer, as provided in some embodiments;

[0095] Figure 41 This is a three-dimensional structural diagram of a structure obtained after forming a doped material layer, provided in some embodiments;

[0096] Figure 42 This is a three-dimensional structural diagram of a structure obtained after forming a covering material layer, provided in some embodiments;

[0097] Figure 43 This is a partial top view schematic diagram of another semiconductor structure provided in some embodiments.

[0098] Explanation of reference numerals in the attached figures:

[0099] 1-Substrate, 10-Silicon, 11-Etching protection layer, 2-Stacked structure, 21-First dielectric layer, 211-Sacrificial layer, 22-Second dielectric layer, 23-First isolation structure, WL-Word line, YM-Mask layer, YM1-First mask layer, 31-First isolation layer, 32-First support structure, 33-First insulating layer, 34-Block layer, 35-Protective layer, 36-Second insulating layer, 37-Third insulating layer, 38-Second support structure, YM2-Second mask layer, R1-Capacitor accommodating region, R2-Bit line accommodating region, 40-Gate dielectric material layer, 41-First gate dielectric layer, 42-Second gate dielectric layer, 420-Second gate dielectric material layer 43-Silicon oxide layer, 430-Silicon oxide material layer, 4-Gate dielectric layer, 50-Semiconductor material layer, 5-Semiconductor layer, 51-First source / drain, 52-Second source / drain, 60-Doped material layer, 6A-Initial doped layer, 6-Doped layer, 70-Cover material layer, 7A-Initial cover layer, 7-Cover layer, G-Process trench, H1-Word line via, H2-Capacitor via, 81-First sacrificial structure, 82-Second sacrificial structure, G1-First isolation trench, 83-First isolation structure, 84-Second isolation structure, 510-Source / drain material layer, 91-First electrode, 910-First electrode material layer, 92-Dielectric layer, 93-Second electrode. Detailed Implementation

[0100] To facilitate understanding of this disclosure, a more complete description will now be given with reference to the accompanying drawings, in which preferred embodiments of the present disclosure are shown. However, this disclosure may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0101] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure.

[0102] As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. When using “comprising,” “having,” and “including” as described herein, another component may be added unless explicitly qualified terms such as “only,” “consisting of,” etc. are used. Unless otherwise stated, singular terms may include plural forms and should not be construed as having a quantity of one.

[0103] It should be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0104] In the description of this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a direct connection or an indirect connection through an intermediate medium; or they can refer to the internal communication between two components. Those skilled in the art can understand the specific meaning of the above terms in this disclosure based on the specific circumstances.

[0105] It should be noted that the illustrations provided in this embodiment are only schematic representations of the preferred embodiments of this disclosure. The type, quantity, and proportion of each component in this embodiment may also be changed, and the component layout may be more complex.

[0106] Please see Figure 1 This application discloses a flowchart of a method for manufacturing a semiconductor structure, including the following steps S10-S30.

[0107] S10 forms the word lines and the gate dielectric layer surrounding the word lines.

[0108] S20, a semiconductor material layer, a doped material layer and a cover material layer are sequentially stacked on the surface of the gate dielectric layer away from the word line; the doped material layer contains target doped ions.

[0109] S30, perform heat treatment and patterning processes on the structure obtained after forming the semiconductor material layer, the doped material layer and the cover material layer to form the cover layer, the doped layer and the semiconductor layer respectively, and dope the semiconductor layer with target dopant ions.

[0110] It should be added here that, for the structure obtained after forming the semiconductor material layer, the doped material layer, and the cover material layer, the heat treatment process can be performed first, followed by the patterning process, or the patterning process can be performed first, followed by the heat treatment process. This application does not impose any limitations on this.

[0111] In this embodiment, after forming the word line and the gate dielectric layer surrounding the word line, a semiconductor material layer, a doped material layer, and a capping material layer are sequentially stacked on the surface of the gate dielectric layer opposite to the word line. A heat treatment process and a patterning process are then performed on the resulting structure to correspondingly form the capping layer, doped layer, and semiconductor layer, and to dope the semiconductor layer with target doped ions. In this embodiment, the target doped ions contained in the doped material layer can be doped into the semiconductor layer while the capping material layer prevents the target doped ions from diffusing outwards. This repairs vacancies in the semiconductor layer, ensuring improved material properties and thus enhancing the device performance and reliability of the semiconductor structure. For example, it can promote a positive shift in the device threshold voltage to maintain a higher switching current and improve the transistor's on / off control capability.

[0112] It should be understood that, although Figure 1 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 1 At least some of the steps in the process may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least some of the sub-steps or stages of other steps.

[0113] In some embodiments of this application, please refer to Figures 2-7 Understand that the word line WL extends along a first direction (e.g., the Y direction) parallel to the substrate 1. The formation of the word line and the gate dielectric layer surrounding the word line in step S10 may include the following steps S110 to S160.

[0114] S110, please refer to Figure 2 A substrate 1 is provided, and a stacked structure 2 is formed on the substrate 1. The stacked structure 2 includes multiple layers of first dielectric layers 21 and multiple layers of second dielectric layers 22 stacked alternately.

[0115] For example, substrate 1 may include, but is not limited to, a silicon (Si) substrate. The substrate may also include silicon-germanium (SiGe) substrates, silicon-germanium-carbon (SiGeC) substrates, silicon-carbide (SiC) substrates, gallium arsenide (GaAs) substrates, indium arsenide (InAs) substrates, indium phosphide (InP) substrates, or other III / V or II / VI semiconductor substrates. Alternatively, for example, substrate 1 may also include semiconductor substrates such as Si / SiGe, Si / SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator. Therefore, the type of substrate 1 should not limit the scope of protection of this application. Exemplarily, substrate 1 may also refer to a dielectric layer formed on silicon. Or, as... Figure 2 As shown, an etching protection layer 11 may also be formed on the surface of the substrate 1. The etching protection layer 11 includes, but is not limited to, a silicon oxide layer or a silicon nitride layer.

[0116] For example, there is a large etching selectivity between the first dielectric layer 21 and the second dielectric layer 22. The first dielectric layer 21 is, for example, but not limited to, a silicon nitride layer. The second dielectric layer 22 is, for example, but not limited to, a silicon oxide layer. This application does not limit the number of stacked layers or the stacking order of the first dielectric layer 21 and the second dielectric layer 22; that is, the stacking can start from the first dielectric layer 21 and end with the second dielectric layer 22, or start from the first dielectric layer 21 and end with the first dielectric layer 21, or start from the second dielectric layer 22 and end with the first dielectric layer 21, or end with the second dielectric layer 22, etc.

[0117] S120, please refer to Figures 2-4 Understanding, etching the stacked structure 2 to form a first trench that penetrates the stacked structure 2 and extends along a first direction (e.g., the Y direction). Figure 4 (Not shown in the image).

[0118] The through-stacking structure 2 mentioned here and thereafter refers to a structure that penetrates along a direction perpendicular to the substrate 1 (e.g., the Z direction). Furthermore, in the formation of... Figure 4 Prior to the first trench structure shown, optionally, please refer to Figure 3 The stacked structure 2 is etched to form an isolation pattern, and a first isolation structure 23 is formed within the isolation pattern. The first isolation structure 23 can be used to isolate and define the formation location of each memory cell, and at the same time, it can be used as a support material and sacrificial material in the subsequent corresponding film patterning process.

[0119] For example, the first isolation structure 23 may be formed using materials such as polycrystalline silicon, alumina (Al2O3), or a carbon film coating (Spinon Carbon, or SOC for short).

[0120] For example, such as Figure 4As shown, the first trench can be formed by photolithography, that is, the formation position of the first trench can be defined based on the mask pattern of the first mask layer YM1, and then the stacked structure 2 can be etched by dry etching until the etching stops at the substrate 1 to form the trench.

[0121] For example, the first mask layer YM1 includes, but is not limited to, a silicon nitride layer.

[0122] S130, please refer to Figures 2-4 Understanding, based on the etching of the first dielectric layer 21 in the first trench, word line receiving grooves are formed ( Figure 4 (Not shown in the image).

[0123] For example, the word line receiving groove is formed by lateral etching of the first dielectric layer 21 using a wet etching process. The etching depth of the word line receiving groove can be matched with the process design dimensions.

[0124] S140, please refer to Figure 4 The character line WL is formed within the character line receiving groove.

[0125] For example, the word line WL is formed of a conductive material, including but not limited to titanium nitride (TiN) or indium zinc oxide (IZO), tungsten (W), indium tin oxide (ITO), etc.

[0126] For example, the word line WL is formed using an atomic layer deposition process. For instance, word line material can be deposited on the inner wall of the first trench and the word line receiving groove, and then the word line material in the first trench can be removed using a wet etching process, so that the word line material retained in the word line receiving groove constitutes the word line WL.

[0127] For example, after forming the word line WL, a first isolation layer 31 and a first support structure 32 can be sequentially formed in the first trench. Furthermore, after depositing the corresponding materials of the first isolation layer 31 and the first support structure 32, the top surface of the resulting structure can be planarized by chemical mechanical polishing (CMP).

[0128] Optionally, the first isolation layer 31 includes, but is not limited to, a silicon nitride layer, which covers the sidewalls of each word line WL near the first trench and the sidewalls of the first trench. The first support structure 32 includes, but is not limited to, a polysilicon layer, which covers the first isolation layer 31 and fills the first trench.

[0129] S150, please refer to Figure 5 and Figure 6Understand that the patterned stacked structure 2 forms a capacitor accommodating region R1 and a bit line accommodating region R2 located on both sides of the word line WL along a second direction (e.g., the X direction) parallel to the substrate 1, and removes the second dielectric layer 22 located in the capacitor accommodating region R1, the bit line accommodating region R2 and the region between them.

[0130] For example, the second direction (e.g., the X direction) intersects the first direction (e.g., the Y direction), for example, they are orthogonal.

[0131] For example, such as Figure 5 As shown, the reference regions of capacitor accommodating region R1 and bit line accommodating region R2 can be formed by photolithography. That is, the formation positions of each reference region corresponding to capacitor accommodating region R1 and bit line accommodating region R2 can be defined based on the mask pattern of the second mask layer YM2. Then, the stacked structure 2 is etched by dry etching until the etching stops on the surface of substrate 1 or in substrate 1.

[0132] For example, the second mask layer YM2 includes, but is not limited to, a silicon nitride layer.

[0133] For example, the reference regions for the capacitor accommodating region R1 and the bit line accommodating region R2 can be defined and formed using a dry etching process. The formed areas of the capacitor accommodating region R1 and the bit line accommodating region R2 are typically larger than the areas of their corresponding reference regions.

[0134] For example, the bit line accommodating region R2 is formed within the aforementioned first trench. The bit line accommodating region R2 can be formed by etching the aforementioned first isolation layer 31 and first support structure 32. The bit line accommodating region R2 exposes one sidewall corresponding to each word line WL.

[0135] For example, such as Figure 6 As shown, the second dielectric layer 22 located in the capacitor accommodating region R1, the bit line accommodating region R2, and the region between them can be formed by performing a wet etching process based on the reference regions of the capacitor accommodating region R1 and the bit line accommodating region R2.

[0136] In this embodiment, the capacitor accommodating region R1 and the bit line accommodating region R2 are respectively disposed on both sides of the word line WL, which facilitates the contact connection of the semiconductor layer 5 covering the word line WL as described later. That is, this architecture is more conducive to the subsequent wiring connection and makes the parasitic capacitance of the corresponding wiring smaller, so as to improve the reading effect of the read (SA) circuit connected to the bit line BL.

[0137] S160, please refer to Figure 7 A gate dielectric material layer 40 is deposited in the capacitor accommodating region R1, the bit line accommodating region R2, and the removal region of the second dielectric layer 22.

[0138] In some embodiments of this application, please refer to Figure 6 and Figure 7 It is understood that a portion of the first dielectric layer 21 is retained at the end of the word line WL near the capacitor accommodating region R1 as a sacrificial layer 211. The gate dielectric material layer 40 surrounds the overall structure composed of the word line WL and the sacrificial layer 211.

[0139] Here, the gate dielectric material layer 40 surrounds the overall structure composed of word line WL and sacrificial layer 211, which can be represented as follows: the gate dielectric material layer 40 covers the top surface, bottom surface and side surface of the overall structure near the capacitor accommodating region R1, and is exposed on the sidewall of the bit line accommodating region R2.

[0140] For example, the gate dielectric material layer 40 is formed of a High-K dielectric material, which may include one or more High-K dielectric materials, such as dielectric materials with a dielectric constant K ≥ 3.9. In some embodiments, it may include one or more oxides of hafnium, aluminum, lanthanum, zirconium, etc. Exemplary examples include, for instance, at least one of the following: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2), etc., which are High-K dielectric materials.

[0141] Based on this, please combine Figures 7-9 It is understood that a semiconductor material layer 50, a doped material layer 60, and a cover material layer 70 are sequentially deposited on the gate dielectric material layer 40.

[0142] For example, the semiconductor material layer 50 is formed of a metal oxide semiconductor material, and the semiconductor material layer 50 has oxygen vacancies, which are vacancies formed in the crystal structure due to the absence of oxygen atoms.

[0143] In some examples, the semiconductor material layer 50 includes, but is not limited to, a metal oxide semiconductor material layer. Optionally, the metal oxide semiconductor material may comprise one or more of the following: indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), indium gallium tin oxide (InGaSnO), indium gallium zinc tin oxide (InGaZnSnO), indium oxide (InO), tin oxide (SnO), zinc tin oxide (ZnSnO, ZTO), indium aluminum zinc gold oxide (InAlZnO), zinc oxide (ZnO), and indium gallium silicon oxide (InGaSi). Materials include indium tungsten oxide (InWO, IWO), titanium oxide (TiO), zinc oxynitride (ZnON), zinc magnesium oxide (MgZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), and zirconium zinc tin oxide (ZrZnSnO). Specifically, the goal is to ensure that the leakage current of the corresponding device (transistor) meets the requirements, which can be adjusted according to the actual situation.

[0144] As a further example, the semiconductor material layer 50 is an indium gallium zinc oxide (IGZO) layer.

[0145] For example, the doped material layer 60 contains target dopant ions. The target dopant ions are, for example, fluorine ions.

[0146] In some examples, the doped material layer 60 is a polymer layer containing fluorine ions. The doped material layer 60 can be formed using initiated chemical vapor deposition (iCVD) or atomic layer deposition (ALD) processes.

[0147] Optionally, forming the doped material layer 60 includes: depositing a certain thickness of fluoropolymer (F-polymer) on the surface of the semiconductor material layer 50 away from the gate dielectric material layer 40 using atomic layer deposition to form a precursor monomer; and depositing a polymerization initiator on the aforementioned precursor monomer away from the semiconductor material layer 50 using initiation chemical vapor deposition or atomic layer deposition to polymerize the precursor monomer to obtain the doped material layer 60 and ensure that the doped material layer 60 has better fluoride ion diffusion capability. The initiator can be, for example, tert-butyl peroxide (TBPO).

[0148] Optionally, the atomic layer deposition process for forming the doped material layer 60 is an ALD-like process or pure ALD, which can better deposit a thin film of adsorbed fluoropolymer on the semiconductor material layer 50.

[0149] For example, the cover material layer 70 is formed using an atomic layer deposition process. The material of the cover material layer 70 includes, but is not limited to, at least one of dielectric materials such as alumina or silicon oxide, silicon nitride, etc., which can block the diffusion of fluoride ions.

[0150] In one possible implementation, please refer to Figure 10 A heat treatment process is performed on the structure obtained after sequentially stacking a semiconductor material layer 50, a doped material layer 60, and a cover material layer 70 to dop the semiconductor material layer 50 with the target doped ions contained in the doped material layer 60.

[0151] For example, the heat treatment process described above is annealing. The temperature range for annealing is not limited to 150℃~400℃, such as 150℃~400℃, 200℃~400℃, 250℃~400℃, 300℃~400℃, or 350℃~400℃.

[0152] For example, the annealing temperature is 350°C, 360°C, 380°C, or 400°C.

[0153] In another possible implementation, a patterning process can be performed on the structure obtained after sequentially stacking a semiconductor material layer 50, a doped material layer 60, and a cover material layer 70, and then the aforementioned heat treatment process can be performed.

[0154] For example, please combine Figures 8-28 It is understood that performing a patterning process on the resulting structure after forming a semiconductor material layer 50, a doped material layer 60, and a cover material layer 70 may include the following steps S310 and S320.

[0155] S310, based on the bit line accommodating region R2, etch the cover material layer 70 and the doped material layer 60 until the semiconductor material layer 50 is exposed, to obtain the initial cover layer 7A and the initial doped layer 6A.

[0156] S320, based on the capacitor accommodating region R1, the initial capping layer 7A, the initial doped layer 6A, the semiconductor material layer 50, the gate dielectric material layer 40 and the sacrificial layer 211 are etched until the word line WL is exposed near the capacitor accommodating region R1, thereby obtaining the capping layer 7, the doped layer 6, the semiconductor layer 5 and the first gate dielectric layer 41.

[0157] Accordingly, the heat treatment process can be selected to be performed in subsequent steps after the formation of the capping layer 7, the doped layer 6 and the semiconductor layer 5.

[0158] Optionally, in some embodiments of this application, please continue to refer to Figures 8-28 The semiconductor structure manufacturing method also includes the following steps S330 to S350.

[0159] S330, forming a second gate dielectric layer 42 covering one end of the word line WL near the capacitor accommodating region R1; the second gate dielectric layer 42 is connected to the first gate dielectric layer 41.

[0160] For example, the second gate dielectric layer 42 is made of the same material as the first gate dielectric layer 41. The second gate dielectric layer 42 and the first gate dielectric layer 41 are closedly connected, together forming a gate dielectric layer surrounding the word line WL.

[0161] For example, in a design that matches the etching process, the second gate dielectric layer 42 can also retain other dielectric layers on the side opposite to the word line WL, such as... Figure 28 The silicon oxide layer 43 shown in the figure.

[0162] S340, a first source / drain 51 is formed on the side of the second gate dielectric layer 42 away from the word line WL; the first source / drain 51 is connected to the semiconductor layer 5.

[0163] S350, a first electrode 91, a dielectric layer 92, and a second electrode 93 of a capacitor are sequentially formed in the capacitor accommodating region R1; the first electrode 91 is connected to the corresponding first source / drain electrode 51.

[0164] Accordingly, in some embodiments of this application, the method for manufacturing a semiconductor structure further includes step S360.

[0165] S360, a bit line BL is formed in the bit line accommodating region R2 to connect the semiconductor layer 5; the bit line BL extends in a direction perpendicular to the substrate 1 (e.g., the Z direction).

[0166] It should be noted that there is no restriction on the order in which the capacitor is fabricated in the capacitor accommodating region R1 and the bit line BL is fabricated in the bit line accommodating region R2, and they can be fabricated separately using any possible implementation method. Furthermore, the patterning process of the capping layer 7, the doped layer 6, and the semiconductor layer 5 (especially the semiconductor layer 5) can include the etching removal of its parasitic material layer; that is, the etching removal of the parasitic material layer can be performed during the fabrication process of the capacitor and / or the bit line BL, or it can be performed as a separate etching removal step after the capacitor and / or the bit line BL is fabricated, as long as the process design requirements are met.

[0167] In some embodiments of this application, the etching removal of the parasitic material layer can be performed independently. For example, the method for manufacturing a semiconductor structure further includes: patterning a stacked structure to form a process trench; and removing the parasitic portion of the semiconductor layer based on the process trench.

[0168] In some embodiments of this application, before performing a patterning process on the resulting structure after forming a semiconductor material layer, a doped material layer, and a cover material layer in step S30, the manufacturing method further includes: filling a first insulating layer in the capacitor accommodating region, the bit line accommodating region, and the removal region of the second dielectric layer, wherein the first insulating layer covers the cover material layer.

[0169] Accordingly, step S320 etches the initial capping layer, initial doped layer, semiconductor material layer, gate dielectric material layer and sacrificial layer based on the capacitor accommodating region until the word line is exposed near the capacitor accommodating region to obtain the capping layer, doped layer, semiconductor layer and first gate dielectric layer, which may include the following steps S321 to S324.

[0170] S321, remove the first insulating layer, initial capping layer and initial doped layer in the capacitor accommodating region and part of the removal region of the second dielectric layer to form the remaining first insulating layer, capping layer and doped layer;

[0171] S322, patterning a semiconductor material layer and a gate dielectric material layer to form a semiconductor layer and a first gate dielectric layer, and exposing a sacrificial layer;

[0172] S323, a protective layer and a second insulating layer are sequentially deposited in the removal regions of the semiconductor material layer and the gate dielectric material layer, and the protective layer and the second insulating layer in the capacitor accommodating region are removed.

[0173] S324, based on the capacitor containment region, removes the sacrificial layer and patterns the first dielectric layer to expose the word line near the capacitor containment region.

[0174] Accordingly, the manufacturing method further includes the following steps S330'~S350' to prepare a capacitor.

[0175] S330', a second gate dielectric layer and a silicon oxide layer are sequentially formed in the area where the sacrificial layer is removed. The second gate dielectric layer is connected to the first gate dielectric layer, and the silicon oxide layer is located on the side of the second gate dielectric layer away from the word line.

[0176] S340', a first source / drain electrode and a first electrode are sequentially formed in the removal regions of the sacrificial layer and the first dielectric layer.

[0177] S350', a dielectric layer covering the first electrode and a second electrode covering the dielectric layer are formed in the removal region of the sacrificial layer and the first dielectric layer and the capacitor accommodating region.

[0178] To more clearly illustrate the manufacturing method provided in the above embodiments of this application, the following embodiments are combined with... Figures 8-28 An exemplary fabrication process for the bit lines and capacitors in this semiconductor structure is described in detail.

[0179] Please see Figure 11 and Figure 12 After sequentially depositing a semiconductor material layer 50, a doped material layer 60, and a cover material layer 70 on the gate dielectric material layer 40, a first insulating layer 33 is filled into the capacitor accommodating region R1, the bit line accommodating region R2, and the removed region of the second dielectric layer 22. The first insulating layer 33 covers the cover material layer 70.

[0180] Optionally, the first insulating layer 33 may be an insulating dielectric layer formed by a low-temperature (e.g., <400°C) deposition process, including but not limited to silicon oxide (SiO2), which may be selected and set according to process and device requirements.

[0181] Please see Figure 13 In step S360, the first insulating layer 33, the cover material layer 70, and the doped material layer 60 in the bit line accommodating region R2 can be removed first to obtain the initial cover layer 7A and the initial doped layer 6A, exposing the semiconductor material layer 50. Then, a bit line BL connecting the semiconductor layer 5 (i.e., the semiconductor material layer 50) is formed in the bit line accommodating region R2.

[0182] Optionally, the first insulating layer 33, the cover material layer 70, and the doped material layer 60 within the bit line accommodating region R2 are removed by dry etching.

[0183] Optionally, the bit line BL is a conductive layer formed using a low-temperature (e.g., <400°C) deposition process, including but not limited to a titanium nitride layer.

[0184] Please refer to the following for further information. Figure 13 The mask layers retained in the foregoing embodiments can be used as barrier layers 34 in subsequent processes, or they can be removed by grinding, and barrier layers 34 can be prepared on the ground surface. This application does not limit this.

[0185] Please see Figure 14 and Figure 15 In step S321, the first insulating layer 33, the initial capping layer 7A and the initial doped layer 6A in the capacitor accommodating region R1 and part of the removal area of ​​the second dielectric layer 22 are removed to form the remaining first insulating layer, capping layer 7 and doped layer 6.

[0186] Please see Figure 16 In step S322, the semiconductor material layer 50 and the gate dielectric material layer 40 are patterned to form the semiconductor layer 5 and the first gate dielectric layer 41, and the sacrificial layer 211 is exposed.

[0187] Here, semiconductor layer 5 still contains parasitic portions, which need to be patterned and removed in subsequent processes.

[0188] Please see Figure 17 and Figure 18 In step S323, a protective layer 35 and a second insulating layer 36 are sequentially deposited in the removal areas of the semiconductor material layer 50 and the gate dielectric material layer 40, and the protective layer 35 and the second insulating layer 36 in the capacitor accommodating area R1 are removed.

[0189] Optionally, the protective layer 35 is a thin-layer material, and it needs to have a certain etching selectivity with the sacrificial layer 211 and the second insulating layer 36. The sacrificial layer 211 is, for example, a silicon nitride layer, and the second insulating layer 36 is, for example, a silicon oxide layer.

[0190] Please see Figure 19 In step S324, the sacrificial layer 211 is removed based on the capacitor accommodating region R1, and the first dielectric layer 21 is patterned to expose the word line WL near the end of the capacitor accommodating region R1.

[0191] Here, patterning the first dielectric layer 21 can be represented by: laterally etching the first dielectric layer 21 based on the capacitor accommodating region R1 to expose the sidewall of the first isolation structure 23.

[0192] Please see Figure 20 and Figure 21 In step S330', a second gate dielectric layer 42 and a silicon oxide layer 43 are sequentially formed in the removal region of the sacrificial layer 211. The second gate dielectric layer 42 is connected to the first gate dielectric layer 41, and the silicon oxide layer 43 is located on the side of the second gate dielectric layer 42 away from the word line WL.

[0193] Optionally, the second gate dielectric layer 42 and the silicon oxide layer 43 can be obtained by first depositing the second gate dielectric material layer 420 and the silicon oxide material layer 430 as a whole, and then patterning the second gate dielectric material layer 420 and the silicon oxide material layer 430.

[0194] Optionally, the second gate dielectric layer 42 and the first gate dielectric layer 41 are made of the same material, which can enclose the surrounding word line WL.

[0195] Optionally, the silicon oxide layer 43 has a gap between its two ends along the direction perpendicular to the substrate (e.g., the Z direction) and the adjacent protective layer 36.

[0196] Optionally, please refer to Figure 22 The protective layer 35 is patterned based on the removal region of the sacrificial layer 211 to expose the second end of the semiconductor layer 5. Here, the protective layer 35 may only retain the portion covering the sidewalls of the first insulating layer 33, the capping layer 7, and the doped layer 6.

[0197] Please see Figure 23 and Figure 24 In step S340', a first source / drain electrode 51 and a first electrode 91 are sequentially formed in the removal regions of the sacrificial layer 211 and the aforementioned first dielectric layer 21.

[0198] Here, the first source / drain 51 is arranged in a ring, which allows for a larger contact area with the first electrode 91, which is beneficial for matching the process design to a smaller size, thereby achieving high integration.

[0199] Optionally, the first source / drain 51 and the first electrode 91 can be obtained by first depositing the source / drain material layer 510, the first electrode material layer 910 and the third insulating layer 37 as a whole, and then patterning the third insulating layer 37, the first electrode material layer 910 and the source / drain material layer 510.

[0200] Optionally, the source / drain material layer 510 is made of the same material as the semiconductor layer 5.

[0201] Optionally, the first electrode material layer 910 is a conductive layer formed by a low-temperature (e.g., <400°C) deposition process, including but not limited to a titanium nitride layer.

[0202] Optionally, the third insulating layer 37 may be an insulating dielectric layer formed by a low-temperature (e.g., <400°C) deposition process, including but not limited to silicon oxide (SiO2), which may be selected according to process and device requirements.

[0203] Please see Figure 25 In step S350', a dielectric layer 92 covering the first electrode 91 and a second electrode 93 covering the dielectric layer 92 are formed in the sacrificial layer 211 and the removal area of ​​the first dielectric layer 21 and the capacitor accommodating area R1.

[0204] Optionally, both the dielectric layer 92 and the second electrode 93 are thin-layer structures. The method for fabricating the semiconductor structure further includes forming a second support structure 38 that covers the second electrode 93 and fills the sacrificial layer 211 and the areas where the first dielectric layer 21 was removed and the capacitor accommodating area R1.

[0205] Alternatively, the second support structure 38 may also be formed of a semiconductor material or a conductive material as a component of the second electrode 93.

[0206] For example, the second support structure 38 may include, but is not limited to, a polycrystalline silicon structure.

[0207] Please see Figure 26 The methods for fabricating semiconductor structures also include: patterning stacked structures to form process trenches G.

[0208] Here, matching the aforementioned process on the stacked structure, the process slot G can be formed by removing the first isolation structure 23 and the first support structure 32 and the first isolation layer 31 between the adjacent bit lines BL.

[0209] For example, please continue reading Figure 26A patterned mask layer YM can be formed on the surface of the stacked structure first, and then the stacked structure can be etched based on the pattern of the mask layer YM until the substrate is exposed to form a process trench G.

[0210] Accordingly, please refer to Figure 27 Parasitic portions of semiconductor layer 5 are removed based on process trench G.

[0211] It is understandable that after forming the process trench G, the process trench G can expose the area between adjacent memory cells, which facilitates the removal of parasitic parts of semiconductor layer 5 through etching process. The operation is simple and easy to implement, with low process challenge, which is conducive to realizing the stacking of multi-layer memory cells.

[0212] In other embodiments of this application, please refer to Figures 29-43 Understand that the word line WL extends along a direction perpendicular to the substrate 1 (e.g., the Z direction). The formation of the word line and the gate dielectric layer surrounding the word line in step S10 may include the following steps S110' to S160'.

[0213] S110', please refer to Figure 30 A substrate 1 is provided, and a stacked structure 2 is formed on the substrate 1. The stacked structure 2 includes multiple layers of first dielectric layers 21 and multiple layers of second dielectric layers 22 stacked alternately.

[0214] For example, substrate 1 may be a dielectric layer formed on silicon 10. An etch protection layer 11 may also be formed on the surface of substrate 1. The etch protection layer 11 may include, but is not limited to, a silicon oxide layer or a silicon nitride layer.

[0215] For example, the first dielectric layer 21 may include, but is not limited to, a silicon nitride layer. The second dielectric layer 22 may include, but is not limited to, a silicon oxide layer.

[0216] S120', please refer to Figure 31 The stacked structure 2 is etched to form a word line hole H1 that penetrates the stacked structure 2.

[0217] For example, such as Figure 31 As shown, the word line hole H1 can be formed using a photolithography process. Specifically, the formation location of the word line hole H1 can be defined based on the mask pattern of the first mask layer YM1, and then a dry etching process is used to etch the stacked structure 2 until etching stops at the substrate 1. Optionally, a capacitor hole H2 can also be formed simultaneously with the word line hole H1.

[0218] Here, the word line hole H1 is used to define the formation position of the subsequent word line WL, and the capacitor hole H2 is used to define the formation position of the subsequent capacitor.

[0219] For example, the first mask layer YM1 includes, but is not limited to, a silicon nitride layer.

[0220] S130', please refer to Figures 31-35 It is understood that the word line WL is formed within the word line hole H1.

[0221] In some embodiments, please continue reading Figure 31 A first sacrificial structure 81 is formed in the word line hole H1, and a second sacrificial structure 82 is formed in the capacitor hole H2. The first sacrificial structure 81 and the second sacrificial structure 82 may be composed of a silicon oxide layer and a polysilicon layer, for example, to provide support material and sacrificial material for the implementation of subsequent steps.

[0222] Please see Figure 32 The stacked structure 2 is etched to form a first isolation trench G1 that penetrates the stacked structure 2. The first isolation trench G1 is located between adjacent groups, with word line vias H1 and their corresponding capacitor vias H2 forming a group. The first isolation trench G1 can be formed, for example, by dry etching.

[0223] Please see Figure 33 A first isolation structure 83 is formed within the first isolation trench G1. The first isolation structure 83 may be composed of, for example, a silicon nitride layer and a polysilicon layer, to provide support and sacrificial materials for subsequent steps.

[0224] Please see Figure 34 The stacked structure 2 is etched to form a second isolation trench that penetrates the stacked structure 2 and extends along a second direction (e.g., the Y direction) parallel to the substrate 1, and a second isolation structure 84 is formed within the second isolation trench. The second isolation structure 84 may be formed, for example, using a carbon film coating (Spin on Carbon, or SOC) to provide support and sacrificial materials for subsequent steps.

[0225] Please see Figure 35 Remove the first sacrificial structure 81 inside the word line hole H1 and form the word line WL inside the word line hole H1.

[0226] For example, the first sacrificial structure 81 can be removed by wet etching.

[0227] For example, the word line WL is formed of a conductive material, including but not limited to titanium nitride (TiN) or indium zinc oxide (IZO), tungsten (W), indium tin oxide (ITO), etc.

[0228] S140', please refer to Figure 36 The stacked structure 2 is etched to form a first process hole H3 that penetrates the stacked structure 2.

[0229] S150', please continue reading Figure 18 Based on the first process hole H3, the first dielectric layer 21 located around the character line WL is patterned.

[0230] S160', please refer to Figure 37 A gate dielectric material layer 40 is deposited on the inner wall of the first process hole H3 and in the removal area of ​​the first dielectric layer 21.

[0231] For example, please combine Figure 37 and Figure 38 Understand that a semiconductor material layer 50 and a source / drain material layer 90 are sequentially deposited on the gate dielectric material layer 40. The source / drain material layer 90 includes, but is not limited to, a titanium nitride metal layer. Based on this, please refer to... Figure 39 Based on the first process hole H3, a wet etching process is used to etch and remove the source / drain material layer 90 and the semiconductor material layer 50 located on both sides of the word line WL along the first direction (e.g., the Y direction), exposing the gate dielectric material layer 40. At this time, the source / drain material layers 90 remaining on both sides of the word line WL along the second direction (e.g., the X direction) can respectively constitute the first source / drain 51 and the second source / drain 52.

[0232] Please combine Figures 40-43 It is understood that a second semiconductor material layer 50 is deposited on the gate dielectric material layer 40 and the aforementioned first source / drain 51 and second source / drain 52, and a doped material layer 60 and a capping material layer 70 are sequentially stacked on the semiconductor material layer 50. The materials of the semiconductor material layer 50, the doped material layer 60 and the capping material layer 70 and their formation processes can be referred to the relevant descriptions in some of the foregoing embodiments, and will not be detailed here.

[0233] As described above, after sequentially stacking the semiconductor material layer 50, the doped material layer 60, and the cover material layer 70, a heat treatment process can be performed on the resulting structure to dope the semiconductor material layer 50 with the target doped ions contained in the doped material layer 60. For example, the heat treatment process described above is an annealing process, and the annealing temperature range includes 150°C to 400°C.

[0234] In this embodiment, annealing can uniformly dope the semiconductor material layer 50 with target dopant ions, such as fluorine ions, contained in the dopant material layer 60. This improves the material stability of the semiconductor material layer 50 by allowing the target dopant ions to occupy oxygen vacancies in the semiconductor material layer 50, and also facilitates passivation of interface defects at the interface between the semiconductor material layer 50 and the gate dielectric material layer 40. Furthermore, in this embodiment, the second-deposited semiconductor material layer 50 is located on both sides of the word line WL along the first direction (e.g., the Y direction), i.e., in the channel region. Therefore, the doped material layer 60 and the capping material layer 70 deposited on the semiconductor material layer 50 in the channel region do not need to be removed after the heat treatment process, effectively avoiding etching damage to the semiconductor material layer 50 in the channel region caused by removing the doped material layer 60 and the capping material layer 70.

[0235] It should be added that, in some embodiments of this application, performing a patterning process on the structure obtained after forming the semiconductor material layer, the doped material layer and the cover material layer further includes: based on the aforementioned first process hole, patterning the cover material layer, the doped material layer, the semiconductor material layer doped with target doped ions and the gate dielectric material layer to obtain the cover layer, the doped layer, the semiconductor layer and the gate dielectric layer.

[0236] Here, the patterning process of the cover material layer, doped material layer, semiconductor material layer after doping with target doped ions and gate dielectric material layer refers to the etching of materials in the non-channel region, such as the etching removal of parasitic materials in the cover layer, doped layer and semiconductor layer (especially semiconductor layer).

[0237] Furthermore, in some embodiments of this application, after forming a semiconductor layer doped with the target dopant ions, the resulting structure can be subjected to subsequent processing to form related structures such as capacitors and / or bit lines. The embodiments of this application do not limit the fabrication process of related structures such as capacitors and / or bit lines.

[0238] Furthermore, in some embodiments of this application, the target dopant ion is a fluoride ion. The doping concentration of the fluoride ions is less than or equal to 4E21cm. -3 As a further example, the doping concentration of fluoride ions ranges from 1E13 cm⁻¹. -3 ~1E21 cm -3 In the embodiments of this application, the doping concentration of fluorine ions is less than or equal to 4E21cm. -3 This can effectively balance the electron transport capability of the semiconductor layer and the switching electrical properties of the corresponding devices to achieve better performance improvement.

[0239] Some embodiments of this application also provide a semiconductor structure that can be prepared using the manufacturing method described above. This semiconductor structure also possesses all the technical advantages of the aforementioned manufacturing methods.

[0240] Please see Figure 28 and Figure 43 The semiconductor structure includes a word line WL and a gate dielectric layer (e.g., stacked around the word line WL) Figure 10 The first gate dielectric layer 41 shown is or Figure 25 The gate dielectric layer 4 and semiconductor layer 5 are shown in the figure; wherein, the semiconductor layer 5 has a stacked structure of doped layer 6 and capping layer 7 on two opposite sides in the target direction; the semiconductor layer 5 is doped with the target doped ions contained in the doped layer 6.

[0241] Here, the extension direction of the matching word line WL can be directed towards the channel region of semiconductor layer 5; that is, the doped layer 6 and the capping layer 7 located in the channel region of semiconductor layer 5 can be retained on semiconductor layer 5. Semiconductor layer 5 is the structure obtained after removing its parasitic portions.

[0242] For example, the target dopant ion includes, but is not limited to, fluoride ions. The doping concentration of the target dopant ion is less than or equal to 4E21cm. -3 For example, its value range can be 1E13 cm. -3 ~1E21 cm -3 .

[0243] Please refer to some embodiments of this application. Figure 28 The character line WL extends along a first direction parallel to substrate 1 (e.g., the Y direction). The aforementioned target direction corresponds to a direction perpendicular to substrate 1 (e.g., the Z direction).

[0244] For example, please continue reading Figure 28 The semiconductor structure also includes capacitors and bit lines BL located on both sides of word line WL along a second direction (e.g., the X direction) parallel to substrate 1. The second direction (e.g., the X direction) intersects, for example, the first direction (e.g., the Y direction) orthogonally.

[0245] Optionally, such as Figure 28 As shown, bit line BL is connected to the first end of semiconductor layer 5 and extends in a direction perpendicular to substrate 1 (e.g., the Z direction).

[0246] Optionally, such as Figure 28 As shown, the capacitor includes: a first electrode 91 connected to the second end of the semiconductor layer 5, a second electrode 93 located on the side of the first electrode 91 away from the semiconductor layer 5, and a dielectric layer 92 located between the first electrode 91 and the second electrode 93.

[0247] Further optional, such as Figure 28 As shown, the first electrode 91 of the capacitor is connected to the second end of the semiconductor layer 5 via a first source / drain 51. The first source / drain 51 surrounds and covers the surface of the first electrode 91 that faces away from the dielectric layer 92. The first source / drain 51 and the first electrode 91 can have a large contact area.

[0248] Optionally, the first source / drain 51 is made of the same material as the semiconductor layer 5. That is, the first source / drain 51 can also be regarded as a component of the semiconductor layer 5, or as a contact layer.

[0249] Further optional, such as Figure 28As shown, the semiconductor structure further includes, for example, a second gate dielectric layer 42 connecting the first gate dielectric layer 41, and a silicon oxide layer 43 located between the first source / drain electrode 51 and the second gate dielectric layer 42. The second gate dielectric layer 42 of the first gate dielectric layer 41 encloses the surrounding word line WL.

[0250] In other embodiments of this application, please refer to Figure 43 The character line WL extends along a direction perpendicular to substrate 1 (e.g., the Z direction). The target direction is a first direction parallel to substrate 1 (e.g., the Y direction).

[0251] For example, the semiconductor structure also includes capacitors located on both sides of the word line WL along a second direction (e.g., the X direction) parallel to the substrate 1. Figure 43 (Not shown in the diagram) and bit line BL. The bit line BL is connected to the semiconductor layer 5 and can extend along a first direction (e.g., the Y direction). The embodiments of this application do not limit the structure of the capacitor; specific configurations can be selected to meet specific needs.

[0252] This application also provides an electronic device in some embodiments. The electronic device includes one or more semiconductor structures as described in the above embodiments, or semiconductor structures prepared by the manufacturing method of the semiconductor structures described in the above embodiments.

[0253] For example, electronic devices include data storage devices, photocopiers, network devices, home appliances, instruments, mobile phones, computers, and other devices with data storage functions.

[0254] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0255] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A method of manufacturing a semiconductor structure, characterized by, include: Forming word lines and a gate dielectric layer surrounding the word lines; A semiconductor material layer, a doped material layer, and a cover material layer are sequentially stacked on the surface of the gate dielectric layer opposite to the word line; The doped material layer contains the target doped ions; A heat treatment process and a patterning process are performed on the structure obtained after forming the semiconductor material layer, the doped material layer and the cover material layer to form the cover layer, the doped layer and the semiconductor layer respectively, and the semiconductor layer is doped with the target dopant ions.

2. The method of manufacturing a semiconductor structure according to claim 1, wherein The word lines extend along a first direction parallel to the substrate; the gate dielectric layer forming the word lines and surrounding the word lines includes: A substrate is provided, and a stacked structure is formed on the substrate, the stacked structure comprising alternating layers of multiple first dielectric layers and multiple layers of second dielectric layers; The stacked structure is etched to form a first trench that penetrates the stacked structure and extends along the first direction; The first dielectric layer is etched based on the first trench to form a word line receiving groove; The character line is formed within the character line receiving groove; The stacked structure is patterned to form capacitor accommodating regions and bit line accommodating regions located on both sides of the word line along a second direction parallel to the substrate, and a second dielectric layer located in the capacitor accommodating regions, the bit line accommodating regions, and the region between them is removed; the second direction intersects the first direction; A gate dielectric material layer is deposited in the capacitor accommodating region, the bit line accommodating region, and the removal region of the second dielectric layer.

3. The method of manufacturing a semiconductor structure according to claim 2, wherein The word line retains a portion of the first dielectric layer as a sacrificial layer at one end near the capacitor storage area; the gate dielectric material layer surrounds the overall structure formed by the word line and the sacrificial layer; Perform a patterning process on the structure obtained after forming the semiconductor material layer, the doped material layer, and the capping material layer, including: Based on the bit line accommodating region, the capping material layer and the doped material layer are etched until the semiconductor material layer is exposed to obtain the initial capping layer and the initial doped layer; Based on the capacitor accommodating region, the initial capping layer, the initial doped layer, the semiconductor material layer, the gate dielectric material layer, and the sacrificial layer are etched until the word line is exposed at one end near the capacitor accommodating region, thereby obtaining the capping layer, the doped layer, the semiconductor layer, and the first gate dielectric layer.

4. The method for manufacturing a semiconductor structure according to claim 3, characterized in that, Also includes: A second gate dielectric layer is formed to cover one end of the word line near the capacitor storage region; the second gate dielectric layer is connected to the first gate dielectric layer. A first source / drain is formed on the side of the second gate dielectric layer opposite to the word line; the first source / drain is connected to the semiconductor layer; A first electrode, a dielectric layer, and a second electrode of a capacitor are sequentially formed in the capacitor accommodating region; the first electrode is connected to the corresponding first source / drain electrode.

5. The method for manufacturing a semiconductor structure according to claim 4, characterized in that, Before performing a patterning process on the resulting structure after forming the semiconductor material layer, the doped material layer, and the cover material layer, the manufacturing method further includes: filling the capacitor accommodating region, the bit line accommodating region, and the removal region of the second dielectric layer with a first insulating layer, the first insulating layer covering the cover material layer; The step of etching the initial capping layer, the initial doped layer, the semiconductor material layer, the gate dielectric material layer, and the sacrificial layer based on the capacitor accommodating region until the word line near the capacitor accommodating region is exposed, thereby obtaining the capping layer, the doped layer, the semiconductor layer, and the first gate dielectric layer, includes: Remove the first insulating layer, the initial capping layer, and the initial doped layer from the capacitor accommodating region and part of the removal region of the second dielectric layer to form the remaining first insulating layer, the capping layer, and the doped layer; The semiconductor material layer and the gate dielectric material layer are patterned to form the semiconductor layer and the first gate dielectric layer, and the sacrificial layer is exposed. A protective layer and a second insulating layer are sequentially deposited in the removal regions of the semiconductor material layer and the gate dielectric material layer, and the protective layer and the second insulating layer in the capacitor accommodating region are removed. The sacrificial layer is removed based on the capacitor containment area, and the first dielectric layer is patterned to expose one end of the word line near the capacitor containment area; The manufacturing method further includes: A second gate dielectric layer and a silicon oxide layer are sequentially formed in the removal region of the sacrificial layer. The second gate dielectric layer is connected to the first gate dielectric layer, and the silicon oxide layer is located on the side of the second gate dielectric layer away from the word line. The first source / drain and the first electrode are sequentially formed in the removal regions of the sacrificial layer and the first dielectric layer; A dielectric layer covering the first electrode and a second electrode covering the dielectric layer are formed in the removal regions of the sacrificial layer and the first dielectric layer and the capacitor accommodating region.

6. The method for manufacturing a semiconductor structure according to claim 3, characterized in that, Also includes: A bit line connecting the semiconductor layer is formed in the bit line accommodating region; The bit line extends in a direction perpendicular to the substrate.

7. The method for manufacturing a semiconductor structure according to claim 3, characterized in that, Also includes: Patterned stacked structures form process grooves; The parasitic portion of the semiconductor layer is removed using the process tank.

8. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, The word lines extend along a direction perpendicular to the substrate; the gate dielectric layer forming the word lines and surrounding the word lines includes: A substrate is provided, and a stacked structure is formed on the substrate, the stacked structure comprising alternating layers of multiple first dielectric layers and multiple layers of second dielectric layers; The stacked structure is etched to form word line holes that penetrate the stacked structure; The character line is formed within the character line hole; The stacked structure is etched to form a first process hole penetrating the stacked structure; Based on the first process hole, the first dielectric layer located around the character line is patterned; A gate dielectric material layer is deposited on the inner wall of the first process hole and in the removal area of ​​the first dielectric layer.

9. The method for manufacturing a semiconductor structure according to claim 8, characterized in that, Perform a patterning process on the structure obtained after forming the semiconductor material layer, the doped material layer, and the cover material layer, including: patterning the cover material layer, the doped material layer, the semiconductor material layer, and the gate dielectric material layer based on the first process hole to obtain a cover layer, a doped layer, a semiconductor layer, and a gate dielectric layer.

10. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, The doped material layer is a polymer layer containing fluorine ions; the doped material layer is formed by initiation chemical vapor deposition or atomic layer deposition.

11. The method for manufacturing a semiconductor structure according to claim 10, characterized in that, Forming the doped material layer includes: A fluoropolymer is deposited on the surface of the semiconductor material layer away from the gate dielectric layer using an atomic layer deposition process to form a precursor-like monomer. A polymerization initiator is deposited on the surface of the precursor monomer away from the semiconductor material layer using initiation chemical vapor deposition or atomic layer deposition to obtain the doped material layer.

12. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, The heat treatment process includes annealing; the temperature range for the annealing process is 150℃~400℃.

13. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, The target doping ions include fluorine ions; a doping concentration of the fluorine ions in the semiconductor layer is less than or equal to 4E21cm -3 .

14. The method for manufacturing a semiconductor structure according to any one of claims 1 to 13, characterized in that, Its features are, The material of the covering layer includes at least one of aluminum oxide, silicon oxide, or silicon nitride.

15. A semiconductor structure, characterized in that, include: The word line and a gate dielectric layer and a semiconductor layer stacked around the word line; wherein the semiconductor layer has a stacked structure of a doped layer and a capping layer on two opposite sides in the target direction; the semiconductor layer is doped with the target dopant ions contained in the doped layer.

16. The semiconductor structure as described in claim 15, characterized in that, The word line extends along a first direction parallel to the substrate; the target direction is a direction perpendicular to the substrate; the semiconductor structure further includes: capacitors and bit lines located on both sides of the word line along a second direction parallel to the substrate; the second direction intersects the first direction; wherein the bit line is connected to a first end of the semiconductor layer and extends along a direction perpendicular to the substrate; the capacitor includes: a first electrode connected to a second end of the semiconductor layer, a second electrode located on the side of the first electrode away from the semiconductor layer, and a dielectric layer located between the first electrode and the second electrode.

17. The semiconductor structure as claimed in claim 16, characterized in that, The second end of the semiconductor layer is connected to the first electrode via a first source / drain; the first source / drain surrounds and covers the surface of the first electrode away from the dielectric layer.

18. The semiconductor structure as claimed in claim 17, characterized in that, The first source / drain electrode and the semiconductor layer are made of the same material.

19. The semiconductor structure as described in claim 15, characterized in that, The word line extends along a direction perpendicular to the substrate; the target direction is a first direction parallel to the substrate; the semiconductor structure further includes: capacitors and bit lines located on both sides of the word line along a second direction parallel to the substrate; the second direction intersects the first direction; wherein the bit line is connected to the semiconductor layer and extends along the first direction.

20. An electronic device, characterized in that, Includes semiconductor structures prepared by the manufacturing method of any one of claims 1 to 14; Alternatively, the semiconductor structure as described in any one of claims 15 to 19.

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