Memory preparation method, memory, device and equipment

Abstract

The invention provides a memory preparation method, a memory, a device and equipment, and the method comprises the steps: sequentially stacking a first material layer and a second material layer on a substrate in a first direction, and enabling the doping concentration of the first material layer to be different from the doping concentration of the second material layer; etching the first material layer and the second material layer in the WL region to form a semiconductor structure and a BL structure; depositing an insulating medium on two sides of the BL structure in the WL region to form a medium layer; reversing and removing the substrate to expose the semiconductor structure; etching the semiconductor structure in the BL region to form an active structure; and forming the memory based on the active structure, and taking the BL structure as a source-drain structure of a transistor in the memory. According to the invention, the dielectric layers are formed at the two sides of the BL structure in the WL region, so that the parasitic capacitance of the BL structure can be reduced, and the performance optimization of the device is facilitated.

Description

Technical Field

[0001] The present application relates to the field of integrated semiconductors, and in particular to a method for preparing a memory, a memory, a device and an apparatus. Background Art

[0002] Dynamic random access memory (DRAM) usually uses a one transistor and one capacitor (1T1C) structure as the memory cell of the chip. However, the BL structure of the bottom-up DRAM has a large parasitic capacitance. Summary of the invention

[0003] The present application provides a method for preparing a memory, a memory, a device and an apparatus, which can reduce the parasitic capacitance of a BL structure and facilitate the optimization of device performance.

[0004] In a first aspect, an embodiment of the present application provides a method for preparing a memory, the method comprising: stacking a first material layer and a second material layer in sequence along a first direction on a substrate, the doping concentration of the first material layer and the doping concentration of the second material layer being different; etching the first material layer and the second material layer in a word line WL region to form a semiconductor structure and a bit line BL structure; depositing an insulating medium on both sides of the BL structure in the WL region to form a dielectric layer; inverting and removing the substrate to expose the semiconductor structure; etching the semiconductor structure in the BL region to form an active structure; based on the active structure, forming a memory, the BL structure serving as a source-drain structure of a transistor in the memory.

[0005] In one possible embodiment, a first material layer and a second material layer are etched in a word line WL region to form a semiconductor structure and a bit line BL structure, including: forming a first mask on the second material layer, the first mask being used to locate the WL region; based on the first mask, etching the second material layer and the first material layer to form a BL structure and a semiconductor structure.

[0006] In a possible implementation, an insulating medium is deposited on both sides of the BL structure in the WL region to form a dielectric layer, including: forming an isolation structure on both sides of the semiconductor structure in the WL region; depositing an insulating medium on the isolation structure to form a dielectric layer, and the height of the dielectric layer is the same as the height of the BL structure.

[0007] In a possible implementation, forming a memory based on an active structure includes: forming a transistor based on the active structure; and forming a capacitor structure on the transistor.

[0008] In one possible implementation, a transistor is formed based on an active structure, including: forming a gate structure based on the active structure; removing the gate structure in the BL region to form a first groove; depositing an insulating material on the gate structure in the WL region and in the first groove to form an insulating layer, wherein the upper surface of the insulating layer is flush with the upper surface of a third mask, and the third mask is located on the active structure; removing the third mask to form a second groove; and forming a source-drain structure in the second groove.

[0009] In a possible embodiment, the gate structure includes a gate electrode layer and a gate dielectric layer surrounding the gate electrode layer, the height of the gate electrode layer is lower than the height of the gate dielectric layer; the gate structure in the BL region is removed to form a first groove, including: forming a sacrificial layer on the gate electrode layer located in the BL region, the upper surface of the sacrificial layer is flush with the upper surface of the gate dielectric layer; anisotropically etching the bottom of the sacrificial layer and the gate electrode layer located below the sacrificial layer to form the first groove; and removing the sacrificial layer.

[0010] In a second aspect, an embodiment of the present application provides a method for preparing a memory, the method comprising: forming an active structure on a substrate, the active structure comprising a first active structure and a second active structure, the first active structure being farther away from the substrate than the second active structure; forming a memory based on the first active structure; flipping the memory and removing the substrate to expose the second active structure; performing ion implantation on the second active structure to form a bit line BL structure, the BL structure serving as a source-drain structure of a transistor in the memory; and depositing an insulating medium on both sides of the BL structure in a word line WL region to form a dielectric layer.

[0011] In one possible embodiment, an active structure is formed on a substrate, including: stacking a first material layer and a second material layer in sequence along a first direction on the substrate; etching the second material layer and a portion of the first material layer in the BL region to form a first semiconductor structure and a second semiconductor structure; etching the first semiconductor structure and the second semiconductor structure in the WL region to form a first active structure and a second active structure.

[0012] In a possible implementation, a memory is formed based on an active structure, including: forming an isolation structure on both sides of a second active structure; forming a transistor on the isolation structure based on the first active structure; and forming a capacitor structure on the transistor.

[0013] In one possible embodiment, a transistor is formed on the isolation structure based on the first active structure, including: forming a gate structure based on the first active structure; removing the gate structure in the BL area to form a third groove; depositing an insulating material on the gate structure in the WL area and in the third groove to form an insulating layer, the upper surface of the insulating layer is flush with the upper surface of the third mask, and the third mask is located on the first active structure; removing the third mask to form a fourth groove; forming a source-drain structure in the fourth groove.

[0014] In a possible embodiment, the gate structure includes a gate electrode layer and a gate dielectric layer surrounding the gate electrode layer, the height of the gate electrode layer is lower than the height of the gate dielectric layer; the gate structure in the BL region is removed to form a third groove, including: forming a sacrificial layer on the gate electrode layer located in the BL region, the upper surface of the sacrificial layer is flush with the upper surface of the gate dielectric layer; anisotropically etching the bottom of the sacrificial layer and the gate electrode layer located below the sacrificial layer to form the third groove; and removing the sacrificial layer.

[0015] In one possible embodiment, ion implantation is performed on the second active structure to form a bit line BL structure, including: removing the substrate to expose the first material layer retained in the BL region, and the isolation structure and the second active structure in the WL region; forming a fourth mask on the isolation structure; based on the fourth mask, ion implantation is performed on the first material layer retained in the BL region and the second active structure in the WL region to form the BL structure.

[0016] In one possible implementation, an insulating medium is deposited on both sides of the BL structure in the WL region to form a dielectric layer, including: thinning the isolation structure in the WL region so that the upper surface of the retained isolation structure is flush with the upper surface of the second active structure; and depositing an insulating medium on the retained isolation structure to form a dielectric layer, wherein the height of the dielectric layer is the same as the height of the BL structure.

[0017] In a third aspect, an embodiment of the present application provides a memory, which is manufactured using the manufacturing method described in the first aspect and any embodiment thereof, or manufactured using the manufacturing method described in the second aspect and any embodiment thereof, and includes: a BL structure and a memory, the BL structure serving as a source-drain structure of a transistor in the memory; and a dielectric layer, the dielectric layer being located on both sides of the BL structure in the WL region.

[0018] In a fourth aspect, an embodiment of the present application provides a semiconductor device, comprising: a memory as described in the third aspect above.

[0019] In a fifth aspect, an embodiment of the present application provides an electronic device, comprising: a circuit board and a semiconductor device as described in the fourth aspect above, wherein the semiconductor device is arranged on the circuit board.

[0020] In the present application, firstly, a first material layer and a second material layer with different doping concentrations are stacked in sequence along a first direction on a substrate, and the first material layer and the second material layer are etched in the WL region to form a semiconductor structure and a BL structure; an insulating medium is deposited on both sides of the BL structure in the WL region to form a dielectric layer; then the wafer is flipped and the substrate is removed to expose the semiconductor structure; the semiconductor structure is etched in the BL region to form an active structure, and a memory is formed based on the active structure. The present application ensures self-alignment of the active area by partially integrating the BL. Moreover, the present application deposits insulating dielectrics on both sides of the BL structure in the WL region, and there is an air gap in the insulating dielectric, which can reduce the parasitic capacitance of the BL structure and is beneficial to the optimization of device performance.

[0021] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0023] Figure 1 A schematic diagram of an implementation process of a method for preparing a memory in an embodiment of the present application;

[0024] Figure 2 It is another implementation flow diagram of the method for preparing a memory in an embodiment of the present application;

[0025] Figure 3 A schematic top view of a memory in an embodiment of the present application;

[0026] Figures 4 to 13 This is a schematic diagram of the structure of the memory in the first preparation process in the embodiment of the present application;

[0027] Fig.14 This is a schematic diagram of the first structure of the memory in the embodiment of the present application;

[0028] Figures 15 to 26 This is a schematic diagram of the structure of the memory in the second preparation process in the embodiment of the present application;

[0029] Fig. 27 This is a schematic diagram of the second structure of the memory in the embodiment of the present application.

[0030] The above pictures:

[0031] 10. Memory; 11. Transistor; 111. Active structure (first active structure); 112. Source-drain structure; 113. Gate structure; 1131. Gate dielectric layer; 1132. Gate electrode layer; 12. First insulating layer; 13. Carrier wafer; 20. Substrate; 21. First material layer; 22. Second material layer; 23. First mask; 24. Semiconductor structure; 25. BL structure; 26. First isolation structure; 27. First dielectric layer; 28. Second mask; 29. ​​Second isolation structure; 30. Oxide layer; 31. Second insulating layer; 32. Second dielectric layer; 33. Capacitor structure; 34. First semiconductor structure; 35. Second semiconductor structure; 36. Third isolation structure; 37. Third mask; 38. Second active structure; 39. Fourth isolation structure; 40. Fourth mask. DETAILED DESCRIPTION

[0032] Here, exemplary embodiments are described in detail, and examples thereof are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application.

[0033] As Moore's Law continues to deepen, continuing to promote the miniaturization of transistor size is a hot issue in the current industry research and development. Stacked transistors can achieve the integration of two or more layers of transistors in a vertical space through three-dimensional transistor stacking, which helps to further improve the integration density of transistors.

[0034] In DRAM, ferroelectric random access memory (FeRAM) or other memory, a memory cell may include a transistor and a capacitor structure, wherein the transistor is disposed on a substrate, the capacitor structure is located at an end of the transistor away from the substrate, and the transistor and the capacitor structure are electrically connected.

[0035] Take DRAM as an example. The basic structure of DRAM is 1T1C. Currently, there are three main types of DRAM. The first type of DRAM has an area of ​​8F. 2 , which is achieved by placing transistors and capacitors horizontally; the second type of DRAM has an area of ​​6F 2 By tilting the placement of transistors and capacitors, the arrangement density can be increased, thereby achieving a smaller integration area; the area of ​​the third DRAM is 4F 2 By placing transistors and capacitor structures vertically, the vertical volume is fully utilized to achieve smaller DRAM area scaling. 2DRAM, which makes vertical capacitors on vertical transistors, helps to further improve DRAM integration density and circuit performance, and is considered to be one of the important technologies for continuing the miniaturization of integrated circuits. However, the BL structure of DRAM made from the bottom up has a large parasitic capacitance, which will affect the performance of the device.

[0036] Based on this, an embodiment of the present application provides a method for preparing a memory, which can reduce the parasitic capacitance of the BL structure and is beneficial to the optimization of device performance.

[0037] In some embodiments, the memory may include a plurality of memory cells, each of which may include a flip-stacked transistor and a capacitance structure (capacitor), wherein the capacitance structure is electrically connected to the transistor.

[0038] In some embodiments, the transistor may include a gate structure, a source structure, and a drain structure. The capacitor structure and the transistor may be electrically connected by the source structure of the transistor and the capacitor structure, or by the drain structure of the transistor and the capacitor structure. The transistor controls the writing, modification, or reading of information in the capacitor structure. That is, the transistor acts as a selection device (or a switching device) to control the writing, modification, or reading of information in the capacitor structure.

[0039] In some embodiments, the capacitor structure may include a first electrode, a second electrode, and a dielectric layer between the first electrode and the second electrode. Exemplarily, the first electrode may be electrically connected to a drain structure of the transistor, and the second electrode may be grounded.

[0040] In some embodiments, the memory cell may further include a plurality of word line (WL) structures and a plurality of bit line (BL) structures, wherein the WL structure may be connected to the gate structure of the transistor to control the on and off of the transistor. The BL structure may be connected to the source structure or the drain structure of the transistor to write data into the capacitor structure connected to the transistor when the transistor is turned on.

[0041] In the embodiment of the present application, the transistor may be illustratively a vertical channel transistor (VCT), which may also be referred to as a vertical gate-all-around transistor.

[0042] Figure 1 FIG. 1 is a schematic diagram of an implementation process of a method for preparing a memory in an embodiment of the present application. Figure 1 As shown, the method for preparing the memory in the embodiment of the present application may include:

[0043] Step S110: stacking a first material layer and a second material layer in sequence along a first direction on a substrate.

[0044] In some embodiments, the doping concentration of the first material layer is different from the doping concentration of the second material layer. The first direction is a direction perpendicular to the extension direction of the substrate.

[0045] By way of example, the substrate may be any semiconductor substrate such as a silicon substrate, a germanium substrate, a silicon-germanium substrate, or a silicon carbide substrate.

[0046] It can be understood that the doping concentration of the first material layer is different from the doping concentration of the second material layer. In this way, the first material layer can be etched and used as the active structure of the transistor in the memory, and the second material layer with different doping can be used as the BL structure of the memory.

[0047] In some embodiments, the doping concentration of the second material layer may be higher than the doping concentration of the first material layer. As a channel for data transmission, the doping concentration of the BL structure mainly affects the efficiency and noise performance of data transmission. A higher doping concentration can improve the conductivity of the BL structure, reduce resistance, and thus speed up data transmission.

[0048] Step S120: etching the first material layer and the second material layer in the WL region to form a semiconductor structure and a BL structure.

[0049] In some embodiments, the implementation process of step S120 may be: forming a first mask on the second material layer, the first mask being used to locate the WL region; etching the second material layer and the first material layer based on the first mask to form a BL structure and a semiconductor structure.

[0050] Since the memory cell of the memory includes a WL region and a BL region, after the first material layer and the second material layer are stacked in sequence on the substrate, the WL region and the BL region can be etched to form an active structure. First, the first material layer and the second material layer can be etched in the WL region to form a semiconductor structure and a BL structure. That is, after a mask is formed by photolithography, etching is performed along the BL direction to form a semiconductor structure and a BL structure.

[0051] It can be understood that when etching the WL region, a first mask can be first formed on the second material layer. The first mask is used to locate the WL region. Therefore, the first mask covers a portion of the second material layer in the WL region and covers the entire second material layer in the BL region. In this way, the second material layer and the first material layer are etched based on the first mask to form a BL structure and a semiconductor structure. Among them, the BL structure in the WL region is discontinuous, while the BL structure in the BL region is continuous. The semiconductor structure includes an active structure in the WL region and a first material layer in the BL region.

[0052] For example, the etching process may be at least one of dry etching, wet etching, reactive ion etching, etc.

[0053] In some embodiments, after the semiconductor structure and the BL structure are formed, the first mask may be removed.

[0054] Step S130: depositing an insulating dielectric on both sides of the BL structure in the WL region to form a dielectric layer.

[0055] In some embodiments, the implementation process of step S130 may be: forming an isolation structure on both sides of the semiconductor structure in the WL region; depositing an insulating medium on the isolation structure to form a dielectric layer, the height of the dielectric layer being the same as the height of the BL structure. For ease of distinction, the isolation structure here is referred to as a first isolation structure.

[0056] In some embodiments, after etching the substrate, a trench may be formed at the etched position, and an oxide may be filled in the trench to form a first isolation structure. By way of example, the first isolation structure may also be referred to as a shallow trench isolation (STI) structure. The oxide forming the first isolation structure may be, by way of example, silicon nitride (SiN, Si3N4), silicon dioxide (SiO2), or silicon oxycarbide (SiCO), etc.

[0057] In some embodiments, to facilitate subsequent processing, after the first isolation structure is formed, the first isolation structure can be polished or chemical-mechanical planarization (CMP) treated so that when the first isolation structure is subsequently etched, different regions of the first isolation structure have the same etching depth, thereby making the top height of the exposed active structure the same.

[0058] In some embodiments, a portion of the first isolation structure may be etched first so that the upper surface of the first isolation structure is lower than the lower surface of the BL structure, that is, the BL structure is exposed, so as to facilitate subsequent operations on the BL structure. The solvent used to etch the first isolation structure may be, for example, a dilute hydrofluoric acid (DHF) solution or a buffered oxide etch (BOE) solution.

[0059] It is understandable that after forming the first isolation structure, an insulating medium can be deposited on both sides of the BL structure on the first isolation structure to form a first dielectric layer. Since the BL structure is discontinuous in the WL region, the parasitic capacitance between the discontinuous BL structures is large, so the rate of depositing the insulating medium can be controlled so that there is a gap in the first dielectric layer during the deposition process, and the air gap formed in this way can reduce the parasitic capacitance between the BL structures. By way of example, the insulating medium can be a dielectric material such as silicon nitride and silicon oxide.

[0060] Step S140: flipping the wafer and removing the substrate to expose the semiconductor structure.

[0061] It is understandable that after forming the BL structure and the dielectric layer, the BL structure and the dielectric layer can be bonded to the carrier wafer, and then flipped over to place the substrate on top. The substrate is then removed to expose the semiconductor structure, facilitating subsequent preparation of the memory.

[0062] In some embodiments, an insulating material (such as silicon oxide) may be deposited on the BL structure and the dielectric layer to form a first insulating layer, and the first insulating layer may be bonded to a carrier wafer, and then the wafer may be flipped over and the substrate may be removed.

[0063] In one example, after flipping, the substrate may be removed by polishing or chemical mechanical planarization.

[0064] Step S150: etching the semiconductor structure in the BL region to form an active structure.

[0065] It can be understood that the semiconductor structure formed above includes the active structure in the WL region and the first material layer in the BL region. Therefore, after flipping the wafer, it is necessary to etch the back region and stop at the BL structure to form an active structure, that is, to etch the first material layer along the WL direction to form an active structure, and the active structure includes the active structure in the WL region and the active structure in the BL region.

[0066] In some embodiments, a second mask can be formed on the first material layer in the BL region and the active structure in the WL region. The second mask is used to locate the active structure in the BL region. Therefore, when etching downward based on the second mask, the first material layer in the BL region can be etched, thereby forming the active structure in the BL region, and the structure in the WL region is not affected.

[0067] In some embodiments, after the active structures are formed, the second mask may be removed.

[0068] In some embodiments, after forming the active structure, an oxide material may be deposited on the BL structure in the BL region to form a second isolation structure.

[0069] It can be understood that after the first isolation structure and the second isolation structure, the first isolation structure and the second isolation structure can be thinned to a preset height to expose the gate region of the back transistor so as to subsequently prepare the gate structure of the back transistor.

[0070] Step S160: forming a memory based on the active structure.

[0071] In some embodiments, the implementation process of step S160 may include the following two steps: forming a transistor based on the active structure; and forming a capacitor structure on the transistor.

[0072] In some embodiments, based on the active structure, the implementation process of forming a transistor may be: based on the active structure, forming a gate structure; removing the gate structure in the BL region to form a first groove; depositing an insulating material on the gate structure in the WL region and in the first groove to form an insulating layer, the upper surface of the insulating layer is flush with the upper surface of the third mask, and the third mask is located on the active structure; removing the third mask to form a second groove; forming a source-drain structure in the second groove. For ease of distinction, the insulating layer here is referred to as a second insulating layer.

[0073] In some embodiments, after the active structure is formed, a third mask may be formed on the active structure in the WL region and the BL region, the third mask exposing the gate region.

[0074] It can be understood that after thinning the first isolation structure and the second isolation structure to a preset height, the gate region of the back transistor is exposed, that is, a gate groove is formed between the active structures, so that an insulating material can be deposited at the gate groove to form a gate dielectric layer, and a metal material can be deposited on the gate dielectric layer to form a gate electrode layer. The gate dielectric layer and the gate electrode layer together constitute a gate structure. Among them, the height of the gate electrode layer can be lower than the height of the gate dielectric layer.

[0075] For example, the gate dielectric layer may be composed of a silicon oxide layer and a hafnium oxide layer with a high K value, and the thicknesses of the silicon oxide layer and the hafnium oxide layer may be determined according to the polarity and performance of the transistor.

[0076] By way of example, the gate electrode layer may be composed of multiple layers of electrode materials, and the electrode material of each layer includes, but is not limited to, hafnium, zirconium, titanium, tantalum, aluminum, and alloys of these metals.

[0077] Since the WL structure in the WL region is connected to the gate structure of the transistor, the gate structure in the WL region is necessary, while the gate structure in the BL region should not exist, so the gate structure in the BL region can be selectively removed.

[0078] In some embodiments, the gate structure is removed in the BL region to form a first groove by: forming a sacrificial layer on the gate electrode layer in the BL region, wherein the upper surface of the sacrificial layer is flush with the upper surface of the gate dielectric layer; and anisotropically etching the bottom of the sacrificial layer and the gate electrode layer below the sacrificial layer to form a first groove.

[0079] It can be understood that a sacrificial layer attached to the bottom of the gate electrode layer, the sidewall of the gate dielectric layer, and the sidewall of the mask can be deposited on the gate electrode layer in the BL region, and the upper surface of the sacrificial layer is flush with the upper surface of the gate dielectric layer, and then the bottom of the sacrificial layer and the gate electrode layer below the sacrificial layer are anisotropically etched to obtain a first groove. Since the anisotropic etching is etched downward from the bottom of the sacrificial layer, and there is still a portion of the gate electrode layer below the sidewall of the sacrificial layer, this portion of the gate electrode layer is retained. Among them, the insulating material can be exemplified by oxides, nitrides and other materials. When depositing the sacrificial layer, a very thin film can be deposited on the surface of the substrate by atomic layer deposition (ALD).

[0080] In some embodiments, after the first recess is formed, the sacrificial layer may be removed.

[0081] It can be understood that after forming the first groove, an insulating material can be deposited on the gate structure in the WL region and in the first groove to form a second insulating layer, and the upper surface of the second insulating layer is flush with the upper surface of the third mask. The third mask can then be removed to form a second groove, and a source-drain structure of the transistor is formed in the second groove. Among them, the second insulating layer is used to isolate the source-drain structure of the transistor. In the case where the transistor formed in the embodiment of the present application is a VCT, the source structure and drain structure of the VCT are approximately symmetrical. Therefore, for ease of explanation, the source-drain structure mentioned in the embodiment of the present application is abbreviated, specifically referring to the source structure and / or drain structure.

[0082] For example, ion implantation can be performed in the second groove to deposit metal material, and then annealing can be performed to form silicide, and the silicide can be used as the source-drain structure. This is only an exemplary description, and can be determined as needed in actual operation. When the silicide is used as the source structure, the BL structure can be used as the drain structure. When the silicide is used as the drain structure, the BL structure can be used as the source structure.

[0083] In some embodiments, an insulating material may be deposited on the gate structure in the WL region to form an isolation layer so that only the BL region is processed. In this way, after removing the sacrificial layer, the isolation layer above the WL region may be removed so that a second insulating layer is formed on both the WL region and the BL region.

[0084] In some embodiments, after removing the sacrificial layer, an oxide material may be deposited in the groove in the BL region to form an oxide layer. Then, a second insulating layer is formed on the oxide layer in the BL region and the gate structure in the WL region. The oxide layer may also be formed by ALD deposition, for example.

[0085] After the source-drain structure is formed, a capacitor structure of the memory may be formed on the transistor.

[0086] In some embodiments, the process of forming a capacitor structure on a transistor may be: forming a dielectric layer on the source-drain structure; etching a portion of the dielectric layer to expose the source-drain structure; and forming a capacitor structure on the source-drain structure. For ease of distinction, the dielectric layer here is referred to as a second dielectric layer.

[0087] It can be understood that an insulating dielectric can be deposited on the source-drain structure to form a second dielectric layer, and then a portion of the second dielectric layer is etched to expose the source-drain structure below, and a layer of metal material is first deposited on the source-drain structure, and then a dielectric material is deposited, and then another layer of metal material is deposited, so that a capacitor structure including a first electrode and a second electrode, and a dielectric layer located between the first electrode and the second electrode can be formed, and the memory can be prepared in this way. Among them, the dielectric layer located between the capacitor structures can serve as an isolation structure between the capacitor structures.

[0088] In the present application, firstly, a first material layer and a second material layer with different doping concentrations are stacked in sequence along a first direction on a substrate, and the first material layer and the second material layer are etched in the WL region to form a semiconductor structure and a BL structure; an insulating medium is deposited on both sides of the BL structure in the WL region to form a dielectric layer; then the wafer is flipped and the substrate is removed to expose the semiconductor structure; the semiconductor structure is etched in the BL region to form an active structure, and a memory is formed based on the active structure. The present application ensures self-alignment of the active region by integrated molding of the BL region. Moreover, the present application deposits insulating dielectrics on both sides of the BL structure in the WL region, and the presence of air gaps in the insulating dielectric can reduce the parasitic capacitance of the BL structure, which is beneficial to the optimization of device performance.

[0089] Figure 2 FIG. 1 is another schematic diagram of the process flow of the memory manufacturing method in the embodiment of the present application. Figure 2 As shown, the method for preparing the memory of the embodiment of the present application may include:

[0090] Step S210: forming an active structure on a substrate.

[0091] In some embodiments, the active structure includes a first active structure and a second active structure, the first active structure being further away from the substrate than the second active structure.

[0092] In some embodiments, the implementation process of step S210 can be divided into the following three steps: step one: stacking in sequence along a first direction on a substrate to form a first material layer and a second material layer; step two: etching the second material layer and a portion of the first material layer in the BL area to form a first semiconductor structure and a second semiconductor structure; step three: etching the first semiconductor structure and the second semiconductor structure in the WL area to form a first active structure and a second active structure.

[0093] In step 1, the first material layer and the second material layer are doped the same.

[0094] By way of example, the substrate may be any semiconductor substrate such as a silicon substrate, a germanium substrate, a silicon-germanium substrate, a silicon carbide substrate, or a silicon-on-insulator substrate.

[0095] Since the memory cell of the memory includes a WL region and a BL region, after the first material layer and the second material layer are stacked sequentially on the substrate, the WL region and the BL region can be etched to form an active structure. First, based on step 2, the first material layer and the second material layer can be etched in the BL region to form a first semiconductor structure and a second semiconductor structure.

[0096] In some embodiments, the implementation process of step 2 may be: forming a second mask on the second material layer, the first mask is used to locate the BL region; based on the second mask, etching the second material layer and a portion of the first material layer to form the first semiconductor structure and the second semiconductor structure. That is, after forming the mask by photolithography, etching is performed along the WL direction to form the first semiconductor structure and the second semiconductor structure.

[0097] It can be understood that first, a second mask can be formed on the second material layer, and the second mask is used to locate the BL region. Therefore, the second mask covers a portion of the second material layer in the BL region and covers the entire second material layer in the WL region. In this way, the second material layer and a portion of the first material layer are etched based on the second mask to form a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes a first active structure in the BL region and a second material layer in the WL region. The second semiconductor structure includes a second active structure and a portion of the first material layer in the WL region, and the first material layer in the BL region.

[0098] For example, the etching process may be at least one of dry etching, wet etching, reactive ion etching, etc.

[0099] After forming the first semiconductor structure and the second semiconductor structure, the first semiconductor structure and the second semiconductor structure can be etched in the WL region based on step 3 to form the first active structure and the second active structure. That is, etching is performed along the BL direction and the etching stops on the first material layer to form the first active structure and the second active structure.

[0100] In some embodiments, the implementation process of step three may be: forming a first mask on the second mask, the first mask being used to locate the BL area; based on the first mask, etching the second mask, the first semiconductor structure and the second semiconductor structure to form a first active structure and a second active structure.

[0101] It can be understood that the BL region can be positioned by the first mask, and the first mask can be formed on the second mask. The first mask covers the entire second mask in the BL region and covers a portion of the second mask in the WL region. In this way, when etching downward based on the first mask, the second mask, the second material layer and the first material layer in the WL region can be etched to form the first active structure and the second active structure, and the structure in the BL region is not affected.

[0102] In some embodiments, after etching the BL region to form the first semiconductor structure and the second semiconductor, an oxide material may be deposited on the first material layer remaining in the BL region to form a third isolation structure.

[0103] It is understandable that an oxide material may be deposited on the retained first material layer so that the upper surface of the formed third isolation structure is flush with the upper surface of the second mask. By way of example, the third isolation structure may also be referred to as a shallow trench isolation structure. The oxide forming the third isolation structure may be, by way of example, silicon nitride, silicon dioxide, or silicon oxycarbide.

[0104] In some embodiments, the third isolation structure may be further polished or chemically mechanically planarized so that when the third isolation structure is subsequently etched, different regions of the third isolation structure have the same etching depth, thereby making the top heights of the exposed active structures the same.

[0105] Step S220: forming a memory based on the first active structure.

[0106] In some embodiments, the implementation process of step S220 may be: forming an isolation structure on both sides of the second active structure; forming a transistor on the isolation structure based on the first active structure; and forming a capacitor structure on the transistor.

[0107] It can be understood that after etching the WL region to form the first active structure and the second active structure, an oxide material can be deposited on the substrate in the WL region to form a fourth isolation structure, and after forming the third isolation structure and the fourth isolation structure, the third isolation structure and the fourth isolation structure can be thinned to a preset height to expose the first active structure, so as to subsequently prepare a transistor based on the first active structure.

[0108] In some embodiments, based on the first active structure, the implementation process of forming a transistor may be: based on the first active structure, forming a gate structure; removing the gate structure in the BL region to form a third groove; depositing an insulating material on the gate structure in the WL region and in the third groove to form an insulating layer, the upper surface of the insulating layer is flush with the upper surface of the third mask, and the third mask is located on the first active structure; removing the third mask to form a fourth groove; forming a source-drain structure in the fourth groove. For ease of distinction, the insulating layer here is referred to as a second insulating layer.

[0109] It can be understood that after the first isolation structure and the second isolation structure are thinned to a preset height, the gate region of the back transistor is exposed, that is, a gate groove is formed between the first active structure, so that an insulating material can be deposited at the gate groove to form a gate dielectric layer, and a metal material can be deposited on the gate dielectric layer to form a gate electrode layer. The gate dielectric layer and the gate electrode layer together constitute a gate structure. Among them, the height of the gate electrode layer can be lower than the height of the gate dielectric layer.

[0110] For example, the gate dielectric layer may be composed of a silicon oxide layer and a hafnium oxide layer with a high K value, and the thicknesses of the silicon oxide layer and the hafnium oxide layer may be determined according to the polarity and performance of the transistor.

[0111] By way of example, the gate electrode layer may be composed of multiple layers of electrode materials, and the electrode material of each layer includes, but is not limited to, hafnium, zirconium, titanium, tantalum, aluminum, and alloys of these metals.

[0112] Since the WL structure in the WL region is connected to the gate structure of the transistor, the gate structure in the WL region is necessary, while the gate structure in the BL region may not exist, and thus the gate structure in the BL region may be selectively removed.

[0113] In some embodiments, the process of removing the gate structure in the BL region to form the third groove may be: forming a sacrificial layer on the gate electrode layer located in the BL region, and the upper surface of the sacrificial layer is flush with the upper surface of the gate dielectric layer; anisotropically etching the bottom of the sacrificial layer and the gate electrode layer located below the sacrificial layer to form the third groove.

[0114] It can be understood that a sacrificial layer attached to the bottom of the gate electrode layer, the sidewall of the gate dielectric layer, and the sidewall of the mask can be deposited on the gate electrode layer in the BL region, and the upper surface of the sacrificial layer is flush with the upper surface of the gate dielectric layer, and then the bottom of the sacrificial layer and the gate electrode layer below the sacrificial layer are anisotropically etched to obtain a third groove. Since the anisotropic etching is etched downward from the bottom of the sacrificial layer, and there is still a portion of the gate electrode layer below the sidewall of the sacrificial layer, this portion of the gate electrode layer is retained. Among them, the insulating material can be exemplified by oxides, nitrides and other materials. When depositing the sacrificial layer, a very thin film can be deposited on the surface of the substrate by ALD.

[0115] In some embodiments, after the third recess is formed, the sacrificial layer may be removed.

[0116] It can be understood that after forming the third groove, an insulating material can be deposited on the gate structure in the WL region and in the third groove to form a second insulating layer, and the upper surface of the second insulating layer is flush with the upper surface of the third mask. The third mask can then be removed to form a fourth groove, and a source-drain structure of the transistor is formed in the fourth groove. Among them, the second insulating layer is used to isolate the source-drain structure of the transistor. In the case where the transistor formed in the embodiment of the present application is a VCT, the source structure and drain structure of the VCT are approximately symmetrical. Therefore, for ease of explanation, the source-drain structure mentioned in the embodiment of the present application is abbreviated, specifically referring to the source structure and / or drain structure.

[0117] For example, ion implantation may be performed in the fourth groove to deposit metal material, which is then annealed to form silicide, and the silicide is used as a source-drain structure. This is only an exemplary description and may be determined as needed in actual operation.

[0118] In some embodiments, an insulating material may be deposited on the gate structure in the WL region to form an isolation layer so that only the BL region is processed. In this way, after removing the sacrificial layer, the isolation layer above the WL region may be removed so that a second insulating layer is formed on both the WL region and the BL region.

[0119] In some embodiments, after removing the sacrificial layer, an oxide material may be deposited in the groove in the BL region to form an oxide layer. Then, a second insulating layer is formed on the oxide layer in the BL region and the gate structure in the WL region. The oxide layer may also be formed by ALD deposition, for example.

[0120] After the source-drain structure is formed, a capacitor structure of the memory may be formed on the transistor.

[0121] In some embodiments, the process of forming a capacitor structure on a transistor may be: forming a dielectric layer on the source-drain structure; etching a portion of the dielectric layer to expose the source-drain structure; and forming a capacitor structure on the source-drain structure. For ease of distinction, the dielectric layer here is referred to as a second dielectric layer.

[0122] It can be understood that an insulating dielectric can be deposited on the source-drain structure to form a second dielectric layer, and then a portion of the second dielectric layer is etched to expose the source-drain structure below, and a layer of metal material is first deposited on the source-drain structure, and then a dielectric material is deposited, and then another layer of metal material is deposited, so that a capacitor structure including a first electrode and a second electrode, and a dielectric layer located between the first electrode and the second electrode can be formed, and the memory can be prepared in this way. Among them, the dielectric layer located between the capacitor structures can serve as an isolation structure between the capacitor structures.

[0123] Step S230: flipping the memory and removing the substrate to expose the second active structure.

[0124] It can be understood that after forming the memory, the memory can be bonded to the carrier wafer, then flipped over, the substrate is placed on top, and then the substrate is removed. Since in step S210, during etching, the entire first material layer in the WL region is etched, and a portion of the first material layer in the BL region is etched, after the memory is flipped over and the substrate is removed, the first material layer retained in the BL region, the second active structure in the WL region, and the fourth isolation structures on both sides are exposed.

[0125] In some embodiments, an insulating material (such as silicon oxide) may be deposited on the flip chip to form a first insulating layer, and the first insulating layer may be bonded to the carrier wafer, followed by flipping the chip and removing the substrate.

[0126] In one example, after flipping, the substrate may be removed by polishing or chemical mechanical planarization.

[0127] Step S240: performing ion implantation on the second active structure to form a BL structure.

[0128] In some embodiments, the implementation process of step S240 may be: forming a fourth mask on the fourth isolation structure in the WL region; based on the fourth mask, ion implanting the first material layer retained in the BL region and the second active structure in the WL region to form a BL structure.

[0129] It can be understood that after removing the substrate, the first material layer retained in the BL region, the second active structure in the WL region, and the fourth isolation structure on both sides are exposed. A fourth mask is formed on the fourth isolation structure, and ion implantation is performed based on the fourth mask, so that the area covered by the fourth mask will not be implanted with ions. Therefore, after the ion implantation, the first material layer in the BL region and a portion of the second active structure in the WL region after ion implantation can form a BL structure. In the case where the silicide formed in the above step S220 is used as the source structure, the BL structure can be used as the drain structure. In the case where the silicide is used as the drain structure, the BL structure can be used as the source structure.

[0130] Step S250: depositing an insulating dielectric on both sides of the BL structure in the WL region to form a dielectric layer.

[0131] In some embodiments, the implementation process of step S250 may be: thinning the fourth isolation structure in the WL region so that the upper surface of the retained fourth isolation structure is flush with the upper surface of the second active structure; depositing an insulating medium on the retained fourth isolation structure to form a first dielectric layer, and the height of the first dielectric layer is the same as the height of the BL structure.

[0132] It can be understood that after the BL structure is formed, the upper surface of the fourth isolation structure is flush with the upper surface of the BL structure, so the fourth isolation structure can be thinned to the bottom of the BL structure to expose the BL structure in the WL region. Then, an insulating medium is deposited on both sides of the BL structure on the fourth isolation structure to form a first dielectric layer. Since the BL structure is discontinuous in the WL region, the parasitic capacitance between the discontinuous BL structures is large, so the rate of depositing the insulating medium can be controlled so that there is a gap in the first dielectric layer during the deposition process, and the air gap formed in this way can reduce the parasitic capacitance between the BL structures. By way of example, the insulating medium can be a dielectric material such as silicon nitride and silicon oxide.

[0133] In an embodiment of the present application, an active structure is first formed on a substrate, and a memory is formed based on a first active structure away from the substrate; the memory is flipped and the substrate is removed to expose the second active structure; an insulating medium is deposited on both sides of the BL structure in the WL region to form a dielectric layer. The present application ensures self-alignment of the active area by integrally forming the WL part. Moreover, the present application deposits an insulating medium on both sides of the BL structure in the WL region, and the presence of an air gap in the insulating medium can reduce the parasitic capacitance of the BL structure, which is beneficial to the optimization of device performance.

[0134] Furthermore, the two solutions provided in this application correspond to the integrated molding of BL and WL, respectively, which can achieve self-alignment of the active area before and after flipping. Moreover, the two solutions of this application separate the production of BL and WL, which is conducive to the process optimization of the two key production processes respectively, with little impact on each other, and are compatible with the current DRAM production process.

[0135] The following uses the nanowire structure as an example to illustrate the preparation method of the memory provided by the embodiment of the present application. First, the first preparation process is introduced, that is, preparing the BL structure on the front side and preparing the transistor and capacitor structure on the back side. Figure 3 This is a schematic top view of the memory in the embodiment of the present application. It should be noted that, for ease of understanding, only the nanowire structure, BL structure and WL structure are shown in the top view. The AA' direction is the cross-sectional direction of the memory along the BL structure; the BB' direction is the cross-sectional direction of the memory along the WL structure. Figures 4 to 13 This is a schematic diagram of the structure of the memory in the first preparation process in the embodiment of the present application. Fig.14 This is a schematic diagram of the first structure of the memory in the embodiment of the present application. Figures 4 to 14 (a) is a cross-sectional view of the memory along the cross-sectional direction of the BL structure (i.e., the AA' direction). Figures 4 to 14 (b) is a cross-sectional view of the memory along the cross-sectional direction of the WL structure (ie, the BB' direction).

[0136] In one example, the preparation process of the memory 10 may include the following steps:

[0137] Step 1: sequentially forming a first material layer 21 and a second material layer 22 on an original substrate 20 to obtain Figure 4 The structure shown.

[0138] In the embodiment of the present application, the doping concentration of the second material layer is higher than the doping concentration of the first material layer.

[0139] For example, a layer of highly doped silicon may be epitaxially grown on a silicon substrate to serve as a BL structure of the memory.

[0140] In some embodiments, a highly doped BL layer may be formed on the top layer on the silicon substrate by ion implantation.

[0141] Step 2: Form a first mask 23 on the second material layer 22. The first mask 23 is used to define the active structure of the WL region. Then, based on the first mask 23, the second material layer 22 and the first material layer 21 of the WL region are sequentially etched until the substrate 20 to form a semiconductor structure 24 and a BL structure 25 in the WL region. Figure 5 The structure shown.

[0142] like Figure 5 As shown in (a) in FIG. 3 , in the BL region, the BL structure is a connected structure. Figure 5 As shown in (b), in the WL region, the BL structure is a disconnected structure.

[0143] Step 3: Deposit oxide material on both sides of the semiconductor structure 24 to form a first isolation structure 26, as shown in FIG. Figure 6 The structure shown.

[0144] It can be understood that the upper surface of the first isolation structure 26 is lower than the lower surface of the BL structure 25 .

[0145] Step 4: Remove the first mask 23 and deposit an insulating dielectric on both sides of the BL structure 25 in the WL region to form a first dielectric layer 27. Figure 7 The structure shown.

[0146] It can be understood that the parasitic capacitance of the BL structure can be reduced by controlling the deposition rate to form an air gap.

[0147] Step 5: Deposit insulating material on the BL structure 25 to form a first insulating layer 12, and bond the first insulating layer 12 to the carrier wafer 13, and then flip the wafer to obtain Figure 8 The structure shown.

[0148] Step 6: Remove the substrate 20 to the isolation structure 26 to obtain Fig. 9 The structure shown.

[0149] Step 7: Form a second mask 28 on the first material layer in the BL region and the semiconductor structure and the first isolation structure 26 in the WL region. The second mask 28 is used to define the active structure in the BL region. Fig.10 The structure shown.

[0150] Step 8: Etching is performed based on the second mask 28 to form an active structure 111, and the following is obtained: Fig.11 The structure shown.

[0151] Step 9: Remove the second mask 28 to obtain Fig.12 The structure shown.

[0152] Step 10: Deposit an oxide material on the BL structure 25 in the BL region to form a second isolation structure 29, as shown in FIG. Fig.13 The structure shown.

[0153] It can be understood that the height of the second isolation structure 29 is the same as the height of the first isolation structure 26 .

[0154] Step 11: Prepare transistor and capacitor structures to obtain Fig.14The structure shown.

[0155] It can be understood that first, a third mask can be formed on the active structure 111, and then an insulating material is selectively deposited on the surface of the active structure 111 to form a gate dielectric layer 1131. A metal material is deposited on the gate dielectric layer 1131 and CMPed to a certain height to form a gate electrode layer 1132, so as to form a gate structure 113. Then, an isolation layer is formed by photolithography and etching to cover the WL region, so as to facilitate processing of the BL region. Then, a sacrificial layer attached to the bottom of the gate electrode layer 1132, the sidewalls of the gate dielectric layer 1131, and the sidewalls of the third mask can be deposited on the gate electrode layer 1132, the bottom of the sacrificial layer and the gate electrode layer 1132 located below the sacrificial layer are anisotropically etched, and then the sacrificial layer is removed to form a groove, and an oxide material is deposited in the groove to form an oxide layer 30, the isolation layer above the WL region is removed, and an insulating material (such as SiN) is deposited in the two regions to form a second insulating layer 31, the third mask is selectively etched to form a groove, a source-drain structure 112 is formed in the groove, and an insulating dielectric is deposited on the source-drain structure 112 to form a second dielectric layer 32, a portion of the second dielectric layer 32 is etched to expose the source-drain structure 112, and a capacitor structure 33 is formed on the source-drain structure 112. The capacitor structure may include the deposition of a metal upper plate, the deposition of a dielectric layer, and the deposition of a metal lower plate. Fig.14 Here, the drain structure of the transistor is connected to the BL structure 25 , and the source structure of the transistor is connected to the capacitor structure 33 .

[0156] In an embodiment of the present application, firstly, a first material layer and a second material layer with different doping concentrations are stacked in sequence along a first direction on a substrate, and the first material layer and the second material layer are etched in the WL region to form a semiconductor structure and a BL structure; an insulating medium is deposited on both sides of the BL structure in the WL region to form a dielectric layer; then the wafer is flipped and the substrate is removed to expose the semiconductor structure; the semiconductor structure is etched in the BL region to form an active structure, and a memory is formed based on the active structure. The present application ensures self-alignment of the active area by partially integrating the BL. Moreover, the present application deposits insulating dielectrics on both sides of the BL structure in the WL region, and there is an air gap in the insulating dielectric, which can reduce the parasitic capacitance of the BL structure and is beneficial to the optimization of device performance.

[0157] The second preparation process is introduced below, that is, preparing the transistor and capacitor structure on the front side and preparing the BL structure on the back side. Figures 15 to 26 This is a schematic diagram of the structure of the memory in the second preparation process in the embodiment of the present application. Fig. 27 This is a schematic diagram of the second structure of the memory in the embodiment of the present application. Figures 15 to 27(a) is a cross-sectional view of the memory along the cross-sectional direction of the BL structure (i.e., the AA' direction). Figures 15 to 27 (b) is a cross-sectional view of the memory along the cross-sectional direction of the WL structure (ie, the BB' direction).

[0158] In one example, the preparation process of the memory 10 may include the following steps:

[0159] Step 1: sequentially forming a first material layer 21 and a second material layer 22 on a substrate 20 to obtain Fig.15 The structure shown.

[0160] Step 2: Form a second mask 28 on the second material layer 22. The second mask 28 is used to define the active structure of the BL region. Then, based on the second mask 28, the second material layer 22 and a portion of the first material layer 21 in the BL region are etched to form a first semiconductor structure 34 and a second semiconductor structure 35 in the BL region. Fig.16 The structure shown.

[0161] Step 3: Deposit an oxide material on the first material layer retained in the BL region to form a third isolation structure 36, as shown in FIG. Fig.17 The structure shown.

[0162] Step 4: Form a first mask 23 on the second mask. The first mask 23 is used to locate the active structure of the WL region. Based on the first mask 23, the second mask 28, the second material layer and the first material layer of the WL region are etched to form a third mask 37, the first active structure 111 and the second active structure 38, and obtain the following: Fig.18 The structure shown.

[0163] Step 5: Remove the first mask 23 to obtain Fig.19 The structure shown.

[0164] Step 6: Deposit an oxide material on the substrate in the WL region and perform CMP to form a fourth isolation structure 39, as shown in FIG. Fig. 20 The structure shown.

[0165] It can be understood that the height of the fourth isolation structure 39 is higher than that of the third isolation structure 36 .

[0166] Step 7: Thinning the third isolation structure 36 and the fourth isolation structure 39 to a preset height to expose the first active structure 111, and obtaining Fig.21 The structure shown.

[0167] Step 8: Based on the first active structure 111, a transistor and a capacitor structure 33 are formed to obtain Fig. 22 The structure shown.

[0168] It is understandable that an insulating material can be selectively deposited on the surface of the first active structure 111 to form a gate dielectric layer 1131, and a metal material can be deposited on the gate dielectric layer 1131 and CMPed to a certain height to form a gate electrode layer 1132, so as to form a gate structure 113. Then, an isolation layer is formed by photolithography and etching to cover the WL region, so as to facilitate the processing of the BL region. Afterwards, a sacrificial layer may be deposited on the gate electrode layer 1132 to form a bottom portion of the gate electrode layer 1142, the sidewalls of the gate dielectric layer 1131, and the sidewalls of the third mask 37. The bottom portion of the sacrificial layer and the gate electrode layer 1132 below the sacrificial layer may be anisotropically etched. The sacrificial layer may then be removed to form a groove, and an oxide material may be deposited in the groove to form an oxide layer 30. The isolation layer above the WL region may then be removed, and an insulating material (such as SiN) may be deposited in the two regions to form a second insulating layer 31. The third mask 37 may then be selectively etched to form a groove, a source-drain structure 112 may be formed in the groove, and an insulating dielectric may be deposited on the source-drain structure 112 to form a second dielectric layer 32. A portion of the second dielectric layer 32 may be etched to expose the source-drain structure 112, and a capacitor structure 33 may be formed on the source-drain structure 112.

[0169] Step 9: Deposit insulating material on the transistor to form a first insulating layer 12, and bond the first insulating layer 12 to the carrier wafer 13, and then flip the wafer to obtain Fig.23 The structure shown.

[0170] Step 10: Remove the substrate 20 to expose the first material layer retained in the BL region, the second active structure in the WL region, and the fourth isolation structure 39 on both sides, then form a fourth mask 40 on the fourth isolation structure 39, and perform ion implantation on the first material layer in the BL region and the second active structure in the WL region based on the fourth mask 40 to form a BL structure 25, and obtain the following: Fig.24 The structure shown.

[0171] Step 11: Remove the fourth mask 40 to obtain Fig.25 The structure shown.

[0172] Step 12: Thin the fourth isolation structure 39 to the lower surface of the BL structure 25 so that the height of the thinned fourth isolation structure 39 is the same as the height of the third isolation structure 36, and the following is obtained: Fig.26 The structure shown.

[0173] Step 13: Deposit insulating dielectric on both sides of the BL structure 25 in the WL region to form a first dielectric layer 27, as shown in FIG. Fig. 27 The structure shown.

[0174] In an embodiment of the present application, an active structure is first formed on a substrate, and a memory is formed based on a first active structure away from the substrate; the memory is flipped and the substrate is removed to expose the second active structure; an insulating medium is deposited on both sides of the BL structure in the WL region to form a dielectric layer. The present application ensures self-alignment of the active area by integrally forming the WL part. Moreover, the present application deposits an insulating medium on both sides of the BL structure in the WL region, and the presence of an air gap in the insulating medium can reduce the parasitic capacitance of the BL structure, which is beneficial to the optimization of device performance.

[0175] Furthermore, based on the self-alignment of the active area, the present application can optimize the BL and WL parts separately. Except for the thermal budget, there is no need to consider the impact of the WL on the BL when making the WL. Therefore, the process of BL and WL can be optimized separately. For example, introducing an air gap in the isolated WL part can effectively reduce the parasitic capacitance of the BL part, which is beneficial to the optimization of device performance.

[0176] Furthermore, the memory provided in the embodiment of the present application can be tested using a testing and analysis instrument, such as a scanning electron microscope (SEM), a transmission electron microscope (TEM), a scanning transmission electron microscope (STEM), etc. Taking TEM as an example, the embodiment of the present application can use TEM slicing to detect the structure of the above memory, and it can be observed that the cross section has a 1T1C structure in the basic structure of the memory, and an air gap exists in the BL part.

[0177] The present application embodiment provides a semiconductor device, including: a memory as described in the above embodiment. The specific definition of the memory can refer to the above memory, which will not be described in detail here.

[0178] The embodiment of the present application provides an electronic device, including: a circuit board and a semiconductor device as in the above embodiment, the semiconductor device is arranged on the circuit board. The semiconductor device includes the above memory. The specific definition of the memory can refer to the above memory, which is not repeated here.

[0179] In the description of the embodiments of the present application, the description with reference to the terms "one embodiment", "an embodiment", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the embodiments of the present application. In the present application, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine the different embodiments or examples described in the present application and the features of the different embodiments or examples without contradiction.

[0180] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method for preparing a memory, characterized in that: The method comprises: A first material layer and a second material layer are stacked in sequence along a first direction on a substrate, wherein the doping concentration of the first material layer is different from the doping concentration of the second material layer; Etching the first material layer and the second material layer in the word line WL region to form a semiconductor structure and a bit line BL structure; Depositing an insulating dielectric on both sides of the BL structure in the WL region to form a dielectric layer; Flipping and removing the substrate to expose the semiconductor structure; Etching the semiconductor structure in the BL region to form an active structure; A memory is formed based on the active structure, and the BL structure serves as a source-drain structure of a transistor in the memory.

2. The method according to claim 1, characterized in that The etching of the first material layer and the second material layer in the word line WL region to form a semiconductor structure and a bit line BL structure includes: forming a first mask on the second material layer, wherein the first mask is used to locate the WL region; Based on the first mask, the second material layer and the first material layer are etched to form the BL structure and the semiconductor structure.

3. The method according to claim 1, characterized in that: Depositing an insulating medium on both sides of the BL structure in the WL region to form a dielectric layer includes: forming an isolation structure on both sides of the semiconductor structure in the WL region; An insulating medium is deposited on the isolation structure to form the dielectric layer, and the height of the dielectric layer is the same as the height of the BL structure.

4. The method according to claim 1, characterized in that: The forming of a memory based on the active structure includes: Based on the active structure, forming a transistor; A capacitor structure is formed on the transistor.

5. The method according to claim 4, characterized in that The forming of a transistor based on the active structure comprises: Based on the active structure, forming a gate structure; Removing the gate structure in the BL region to form a first groove; Depositing an insulating material on the gate structure in the WL region and in the first groove to form an insulating layer, wherein an upper surface of the insulating layer is flush with an upper surface of a third mask, and the third mask is located on the active structure; removing the third mask to form a second groove; A source-drain structure is formed in the second groove.

6. The method according to claim 5, characterized in that The gate structure comprises a gate electrode layer and a gate dielectric layer surrounding the gate electrode layer, wherein the height of the gate electrode layer is lower than the height of the gate dielectric layer; The step of removing the gate structure in the BL region to form a first groove includes: forming a sacrificial layer on the gate electrode layer in the BL region, wherein an upper surface of the sacrificial layer is flush with an upper surface of the gate dielectric layer; Anisotropically etching the bottom of the sacrificial layer and the gate electrode layer located below the sacrificial layer to form the first groove; The sacrificial layer is removed.

7. A method for preparing a memory, characterized in that: The method comprises: forming an active structure on a substrate, the active structure comprising a first active structure and a second active structure, the first active structure being farther from the substrate than the second active structure; Based on the first active structure, forming a memory; Flipping the memory and removing the substrate to expose the second active structure; Performing ion implantation on the second active structure to form a bit line BL structure, wherein the BL structure serves as a source-drain structure of a transistor in the memory; An insulating dielectric is deposited on both sides of the BL structure in the word line WL region to form a dielectric layer.

8. The method according to claim 7, characterized in that The forming of an active structure on a substrate comprises: stacking a first material layer and a second material layer in sequence along a first direction on the substrate; Etching the second material layer and a portion of the first material layer in the BL region to form a first semiconductor structure and a second semiconductor structure; The first semiconductor structure and the second semiconductor structure are etched in the WL region to form the first active structure and the second active structure.

9. The method according to claim 8, characterized in that The forming of a memory based on the active structure includes: forming isolation structures on both sides of the second active structure; On the isolation structure, based on the first active structure, a transistor is formed; A capacitor structure is formed on the transistor.

10. The method according to claim 9, characterized in that The step of forming a transistor on the isolation structure based on the first active structure includes: Based on the first active structure, forming a gate structure; Removing the gate structure in the BL region to form a third groove; Depositing an insulating material on the gate structure in the WL region and in the third groove to form an insulating layer, wherein an upper surface of the insulating layer is flush with an upper surface of a third mask, and the third mask is located on the first active structure; removing the third mask to form a fourth groove; A source-drain structure is formed in the fourth groove.

11. The method according to claim 10, characterized in that The gate structure comprises a gate electrode layer and a gate dielectric layer surrounding the gate electrode layer, wherein the height of the gate electrode layer is lower than the height of the gate dielectric layer; The step of removing the gate structure in the BL region to form a third groove comprises: forming a sacrificial layer on the gate electrode layer in the BL region, wherein an upper surface of the sacrificial layer is flush with an upper surface of the gate dielectric layer; Anisotropically etching the bottom of the sacrificial layer and the gate electrode layer located below the sacrificial layer to form the third groove; The sacrificial layer is removed.

12. The method according to claim 9, characterized in that The step of performing ion implantation on the second active structure to form a bit line BL structure comprises: forming a fourth mask on the isolation structure in the WL region; Based on the fourth mask, ion implantation is performed on the first material layer retained in the BL region and the second active structure in the WL region to form the BL structure.

13. The method according to claim 9, characterized in that The step of depositing an insulating medium on both sides of the BL structure in the WL region to form a dielectric layer comprises: thinning the isolation structure in the WL region so that an upper surface of the remaining isolation structure is flush with an upper surface of the second active structure; An insulating dielectric is deposited on the remaining isolation structure to form the dielectric layer, and the height of the dielectric layer is the same as that of the BL structure.

14. A memory, prepared by the preparation method according to any one of claims 1 to 6 or any one of claims 7 to 13, characterized in that: include: A bit line BL structure and a memory, wherein the BL structure serves as a source-drain structure of a transistor in the memory; A dielectric layer is located at two sides of the BL structure in the word line WL region.

15. A semiconductor device, characterized in that: include: A memory as claimed in claim 14.

16. An electronic device, characterized in that: include: A circuit board and a semiconductor device as claimed in claim 15, wherein the semiconductor device is arranged on the circuit board.

Images