Semiconductor structure and method of manufacturing the same

Abstract

Provided is a semiconductor structure manufacturing method, comprising: providing a first wafer, the upper surface of the first wafer having a void structure extending to the interior of the first wafer; providing a second wafer, the lower surface of the second wafer having an insulating layer; bonding the second wafer and the first wafer with the insulating layer and the upper surface of the first wafer as the bonding surface, the insulating layer sealing the void structure; manufacturing a device on the upper surface of the second wafer; and forming a through-silicon via structure, at least part of the side surface of the through-silicon via structure being surrounded by the void structure. The application can seal the void structure with the existing insulating layer, thereby maintaining the design pattern of the void structure, ensuring the stress release effect of the subsequently formed through-silicon via structure, increasing the area of the region around the through-silicon via structure that is not affected by internal stress, increasing the number of transistors arranged, and improving the performance of the semiconductor structure. In addition, the device is formed on the insulating layer, which can greatly reduce the parasitic capacitance, improve the clock, reduce the current leakage current of the device, and improve the performance of the semiconductor structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor structure and its manufacturing method. Background Technology

[0002] Through-Silicon Via (TSV) technology is a novel technical solution for interconnecting stacked chips in three-dimensional integrated circuits. TSVs enable maximum chip stacking density in the vertical direction, minimize interconnect lines between chips, and reduce overall form factor. Compared to two-dimensional integrated packaging, TSV-based three-dimensional integration technology can further reduce chip integration area and volume, increase integration density, and significantly improve chip speed and low-power performance. It has become one of the most compelling technologies in electronic packaging and is considered capable of extending Moore's Law in the post-Moore's Law era.

[0003] However, in traditional through-silicon via (TSV) structures, the internal stress generated when the TSV structure contracts / expands can be transmitted to adjacent transistors, affecting their electrical performance. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a semiconductor structure and a method for manufacturing the same, which can effectively block the propagation of internal stress generated during the contraction / expansion of the through-silicon via structure to the surrounding transistors, thereby increasing the area of ​​the region around the through-silicon via structure that is not affected by internal stress, so as to increase the number of transistors.

[0005] To address the aforementioned problems, the present invention provides a method for manufacturing a semiconductor structure, comprising: providing a first wafer having a void structure extending into the interior of the first wafer on its upper surface; providing a second wafer having an insulating layer on its lower surface; bonding the second wafer to the first wafer using the insulating layer and the upper surface of the first wafer as bonding surfaces, wherein the insulating layer seals the void structure; fabricating a device on the upper surface of the second wafer; and forming a through-silicon via (TSV) structure that penetrates both the second wafer and the first wafer, wherein at least a portion of the TSV structure is surrounded by the void structure.

[0006] Optionally, in the step of providing a first wafer having a void structure extending into the interior of the first wafer on its upper surface, the upper surface of the first wafer is patterned to form the void structure.

[0007] Optionally, in the step of providing a second wafer having an insulating layer on its lower surface, the second wafer includes a supporting silicon layer and the insulating layer disposed sequentially; after the step of bonding the second wafer to the first wafer with the insulating layer and the upper surface of the first wafer as bonding surfaces, the step further includes: thinning the supporting silicon layer; forming a silicon substrate layer on the supporting silicon layer using an epitaxial process; and forming a device on the upper surface of the second wafer, the step further includes: fabricating the device on the silicon substrate layer.

[0008] Optionally, the surface of the insulating layer facing the void structure is flush with the upper surface of the first wafer.

[0009] Optionally, the step of forming a through-silicon via (TSV) structure, wherein the TSV structure penetrates the second wafer and the first wafer, and at least a portion of the TSV structure is surrounded by the void structure, further includes: forming a via, wherein the via penetrates the second wafer and extends into the first wafer, and at least a portion of the via is surrounded by the void structure; forming an isolation layer within the via, wherein the isolation layer covers the inner wall of the via, the upper surface of the second wafer, and the device; forming a conductive fill layer, wherein the conductive fill layer fills the via; and removing a portion of the first wafer from the lower surface of the first wafer to expose the bottom of the conductive fill layer, thereby forming the TSV structure.

[0010] Optionally, the step of forming a conductive fill layer, wherein the conductive fill layer fills the via, further includes: forming a barrier layer, wherein the barrier layer covers the isolation layer; forming a seed layer, wherein the seed layer covers the barrier layer; and forming an electroplated layer on the seed layer, wherein the electroplated layer fills the via.

[0011] Optionally, after the step of forming an electroplated layer on the seed layer and filling the via with the electroplated layer, the method further includes: removing the barrier layer, seed layer and electroplated layer corresponding to the upper surface of the first wafer, leaving only the barrier layer, seed layer and electroplated layer located in the via.

[0012] The present invention also provides a semiconductor structure comprising: a first substrate having a void structure extending into the interior of the first substrate on its upper surface; a second substrate having an insulating layer on its lower surface, the insulating layer being bonded to the first substrate as a bonding layer and sealing the void structure, and a device being disposed on the upper surface of the second substrate; and a through-silicon via structure penetrating the second substrate and the first substrate, wherein at least a portion of the sides of the through-silicon via structure are surrounded by the void structure.

[0013] Optionally, the void structure is an annulus surrounding the through-silicon via structure.

[0014] Optionally, the void structure is composed of multiple concentric rings.

[0015] Optionally, the through-silicon via structure is coaxial with the void structure.

[0016] Optionally, the device is disposed corresponding to the void structure in the extending direction of the through-silicon via structure.

[0017] Optionally, the device is misaligned with the void structure in the extending direction of the through-silicon via structure.

[0018] Optionally, the second substrate further includes a supporting silicon layer and a silicon substrate layer disposed on the insulating layer, wherein the silicon substrate layer is epitaxially formed on the supporting silicon layer.

[0019] Optionally, the through-silicon via structure includes: a via penetrating the first substrate and the second substrate;

[0020] An isolation layer covers the inner wall of the via, the upper surface of the second substrate, and the device; a conductive filling layer fills the via.

[0021] Optionally, the conductive filling layer includes: a barrier layer covering the isolation layer; a seed layer covering the barrier layer; and an electroplated layer covering the seed layer and filling the via.

[0022] The advantages of this invention are that by using an existing insulating layer to seal the void structure, the design pattern of the void structure is maintained, ensuring the stress release effect of the subsequently formed through-silicon via (TSV) structure, increasing the area of ​​the region around the TSV structure that is not affected by internal stress, thereby increasing the number of transistors and improving the performance of the semiconductor structure; in addition, the device is formed on the insulating layer, which can greatly reduce parasitic capacitance, increase clock speed, reduce device leakage current, and improve the performance of the semiconductor structure. Attached Figure Description

[0023] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments of this application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 This is a schematic diagram of the steps in the manufacturing method of the semiconductor structure provided in the first embodiment of the present invention;

[0025] Figures 2A to 2J This is a schematic cross-sectional view of the semiconductor structure prepared by the manufacturing method provided in the first embodiment of the present invention;

[0026] Figure 3 yes Figure 2A A top view of the semiconductor structure shown;

[0027] Figure 4 yes Figure 2G A top view of the semiconductor structure shown;

[0028] Figure 5A This is a cross-sectional schematic diagram of the semiconductor structure after the through-silicon via structure is formed by the manufacturing method provided in the second embodiment of the present invention;

[0029] Figure 5B yes Figure 5A A top view of the semiconductor structure shown;

[0030] Figure 6A This is a cross-sectional schematic diagram of the semiconductor structure provided in the third embodiment of the present invention;

[0031] Figure 6B yes Figure 6A A top view of the semiconductor structure shown;

[0032] Figure 7A This is a cross-sectional schematic diagram of the semiconductor structure provided in the fourth embodiment of the present invention;

[0033] Figure 7B yes Figure 7A A top view of the semiconductor structure shown. Detailed Implementation

[0034] To make the objectives, technical means, and effects of this application clearer, the following description, in conjunction with the accompanying drawings, will further illustrate this application. It should be understood that the embodiments described herein are merely some embodiments of this application, not all embodiments, and are not intended to limit this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0035] Figure 1 This is a schematic diagram illustrating the steps of a semiconductor structure manufacturing method provided in the first embodiment of the present invention. Please refer to [link / reference]. Figure 1 The manufacturing method includes the following steps: Step S10, providing a first wafer, the upper surface of the first wafer having a void structure extending into the interior of the first wafer; Step S11, providing a second wafer, the lower surface of the second wafer having an insulating layer; Step S12, bonding the second wafer to the first wafer using the insulating layer and the upper surface of the first wafer as bonding surfaces, the insulating layer sealing the void structure; Step S13, fabricating a device on the upper surface of the second wafer; Step S14, forming a through-silicon via (TSV) structure, the TSV structure penetrating the second wafer and the first wafer, and at least a portion of the sides of the TSV structure being surrounded by the void structure.

[0036] Figures 2A to 2J This is a schematic cross-sectional view of the semiconductor structure prepared by the manufacturing method provided in the first embodiment of the present invention.

[0037] Please refer to step S10 and Figure 2A A first wafer 200 is provided, the upper surface of the first wafer 200 having a void structure 201 extending into the interior of the first wafer 200.

[0038] exist Figure 2A Only one void structure 201 is schematically shown. In practice, the upper surface of the first wafer 200 may have multiple void structures 201, which are arranged according to a predetermined pattern. Furthermore, the number of void structures 201 is the same as the number of subsequently formed through-silicon via structures.

[0039] In this step, the void structure 201 extends into the first wafer 200, but does not penetrate the first wafer 200. Furthermore, the depth to which the void structure 201 extends into the first wafer 200 is less than the height of the subsequently formed through-silicon via (TSV) structure, to avoid the void structure 201 affecting the TSV process.

[0040] The void structure 201 is a closed structure to effectively prevent the propagation of internal stress generated during the contraction / expansion of the through-silicon via structure to surrounding devices. For example... Figure 3 As shown, it is Figure 2A The diagram shows a top view of the semiconductor structure. In this embodiment, the gap structure 201 is a closed ring.

[0041] Furthermore, in Figure 3 In the semiconductor structure shown, the gap structure 201 is a ring structure formed by a circular shape. In other embodiments of the present invention, the gap structure 201 may be a ring structure formed by geometric shapes such as rectangles, triangles, or regular polygons.

[0042] In this embodiment, the manufacturing method forms the void structure 201 by patterning the upper surface of the first wafer 200. The patterning can be achieved through photolithography and etching processes.

[0043] Please refer to step S11 and Figure 2B A second wafer 210 is provided, the lower surface of which has an insulating layer 211.

[0044] In this embodiment, the second wafer 210 includes a supporting silicon layer 212 and an insulating layer 211 disposed sequentially. The insulating layer 211 may be a silicon oxide layer.

[0045] Please refer to step S12 and Figure 2C The second wafer 210 is bonded to the first wafer 200 using the insulating layer 211 and the upper surface of the first wafer 200 as bonding surfaces, and the insulating layer 211 seals the void structure 201.

[0046] In this step, a semiconductor wafer bonding process is used to bond the first wafer 200 and the second wafer 210. After bonding, the insulating layer 211 contacts the upper surface of the first wafer 200, and the void structure 201 is covered by the insulating layer 211, thereby achieving the sealing of the void structure 201.

[0047] In semiconductor manufacturing processes, if an insulating layer is deposited using processes such as chemical vapor deposition to seal the void structure 201, the deposited insulating layer will extend into the void structure 201, causing the pattern of the void structure 201 to deviate from the original design pattern and reducing the stress relief effect of the subsequently formed through-silicon via (TSV) structure. However, the manufacturing method of this invention utilizes the existing insulating layer 211 to seal the void structure 201. The insulating layer 211 does not extend into the void structure 201, thereby maintaining the original design pattern of the void structure 201, preventing the design pattern from being destroyed, ensuring the stress relief effect of the subsequently formed TSV structure, and improving the performance of the semiconductor structure.

[0048] Furthermore, the surface of the insulating layer 211 facing the void structure 201 is flush with the upper surface of the first wafer 200, that is, the insulating layer 211 does not extend into the void structure 201, but only seals its surface.

[0049] Furthermore, in this embodiment, after performing the bonding process in step S12, the following steps are also included:

[0050] Please see Figure 2D The supporting silicon layer 212 is thinned. In this step, a grinding process is used to thin the supporting silicon layer 212 so that only the insulating layer 211 and the thinned supporting silicon layer 212 remain on the first wafer 200.

[0051] Please see Figure 2E A silicon substrate layer 213 is formed on the supporting silicon layer 212 using an epitaxial process. In this step, the silicon substrate layer 213 is epitaxially grown on the supporting silicon layer 212 as a substrate.

[0052] After the supporting silicon layer 212 is thinned, the surface of the supporting silicon layer 212 is not flat, which will affect the formation of subsequent devices. Therefore, in this step, the silicon substrate layer 213 is epitaxially grown on the supporting silicon layer 212 as a substrate. The surface of the final silicon substrate layer 213 is flat, thereby avoiding affecting the formation of subsequent devices.

[0053] Please refer to step S13 and Figure 2F Device 230 is fabricated on the upper surface of the second wafer 210. Specifically, in this embodiment, device 230 is fabricated on the silicon substrate layer 213. The device 230 may be a MOS transistor or the like.

[0054] The manufacturing method of the present invention fabricates device 230 on the insulating layer 211 and silicon substrate layer 213, which can greatly reduce parasitic capacitance, increase clock speed, reduce current leakage current of device 230, and improve the performance of semiconductor structure.

[0055] Please refer to step S14 and Figures 2G to 2J A through-silicon via (TSV) structure 240 is formed, which penetrates the second wafer 210 and the first wafer 200, and at least a portion of the TSV structure 240's side surfaces are surrounded by the void structure 201. In this step, the TSV structure 240 is formed inside the void structure 201 such that at least a portion of the TSV structure 240's side surfaces are surrounded by the void structure 201.

[0056] This embodiment provides a method for forming the through-silicon via structure 240. The method includes the following steps:

[0057] Please see Figure 2G ,exist Figure 2F Based on the semiconductor structure shown, a via 202 is formed, which penetrates the second wafer 210 and extends into the first wafer 200, and at least a portion of the sidewalls of the via 202 are surrounded by the void structure 201.

[0058] In this step, the via 202 does not penetrate the first wafer 200, but only extends into the interior of the first wafer 200 to provide a basis for the subsequent formation of a conductive filling layer. Furthermore, the depth to which the via 202 extends into the first wafer 200 is greater than the depth to which the void structure 201 extends into the first wafer 200, such that at least a portion of the sidewalls of the via 201 are surrounded by the void structure 201.

[0059] Furthermore, the via 202 is formed inside the void structure 201. Specifically, please refer to... Figure 4 , it is Figure 2G The diagram shows a top view of the semiconductor structure, in which the via 202 is formed inside the void structure 201, i.e., the annular void structure 201 surrounds the via 202.

[0060] Please see Figure 2HAn isolation layer 241 is formed within the via 202, covering the inner wall of the via 202, the upper surface of the second wafer 210, and the device 230. In this step, the isolation layer 241 can be formed using processes such as chemical vapor deposition. The isolation layer 241 can be an insulating layer, for example, silicon oxide or silicon nitride.

[0061] Please see Figure 2I A conductive filling layer is formed, which fills the via 202.

[0062] The conductive filling layer includes a barrier layer 242, a seed layer 243, and an electroplated layer 244 disposed within the via 202.

[0063] Further, in this step, the method for forming the conductive filling layer may include the following steps: forming a barrier layer 242, the barrier layer 242 covering the isolation layer 241; forming a seed layer 243, the seed layer 243 covering the barrier layer 242; forming an electroplated layer 244 on the seed layer 243, the electroplated layer 244 filling the via 202. In actual processes, the formed barrier layer 242, seed layer 243, and electroplated layer 244, in addition to filling the via 202, also cover the upper surface of the first wafer 200. Therefore, after the above steps, the method further includes removing the barrier layer, seed layer, and electroplated layer corresponding to the upper surface of the first wafer 200, retaining only the barrier layer 242, seed layer 243, and electroplated layer 244 located within the via 202 to form the conductive filling layer.

[0064] Furthermore, the barrier layer 242 is made of a material containing tantalum or titanium, and the seed layer 243 and the electroplating layer 244 are made of a material containing copper or tungsten.

[0065] Please see Figure 2J A portion of the first wafer 200 is removed from its lower surface to expose the bottom of the conductive filling layer, forming the through-silicon via (TSV) structure 240. In this step, a grinding process is used to remove a portion of the first wafer 200 from its lower surface. After the bottom of the conductive filling layer is exposed, the bottoms of the barrier layer 242, seed layer 243, and electroplated layer 244 are also removed, forming a TSV structure 240 composed of an insulating layer 241, a barrier layer 242, a seed layer 243, and an electroplated layer 244 arranged sequentially in a horizontal direction. The TSV structure 240 is used for subsequent electrical connection with other semiconductor structures.

[0066] Furthermore, the device 230 can be disposed directly opposite the gap structure 201, or it can be disposed on one side of the gap structure 201, away from the subsequently formed through-silicon via structure. As shown in the figure, in this embodiment, the device 230 is disposed on one side of the gap structure 201, away from the through-silicon via structure.

[0067] The semiconductor structure manufacturing method of the present invention can seal the gap structure using an existing insulating layer, thereby maintaining the design pattern of the gap structure, ensuring the stress release effect of the subsequently formed through-silicon via (TSV) structure, increasing the area of ​​the region around the TSV structure that is not affected by internal stress, thereby increasing the number of transistors and improving the performance of the semiconductor structure; and the device is formed on the insulating layer, which can greatly reduce parasitic capacitance, reduce the leakage current of device 230, and improve the performance of the semiconductor structure.

[0068] In the first embodiment described above, the gap structure 201 is a circular ring. However, in other embodiments of the present invention, the gap structure 201 may also be multiple circular rings arranged sequentially. For example... Figure 5A and Figure 5B As shown, Figure 5A This is a cross-sectional schematic diagram of the semiconductor structure after the through-silicon via (TSV) structure 240 is formed by the manufacturing method provided in the second embodiment of the present invention. Figure 5B for Figure 5A A top-down view, in which... Figure 5B In the diagram, the gap structure 201 and the device 230 are obscured and are therefore shown as dashed lines. In the second embodiment, the gap structure 201 consists of multiple concentric rings arranged sequentially, with the through hole 202 located at the center of each ring. Only three rings are illustrated in this embodiment; in other embodiments of the invention, the number of rings can be adjusted according to actual needs.

[0069] Furthermore, in the second embodiment, the device 230 is disposed above the gap structure 201, which can reduce the impact of stress while increasing the number of devices 230 that can be placed and improving the integration of the semiconductor structure.

[0070] The present invention also provides a semiconductor structure manufactured using the above-described manufacturing method. Please refer to [link / reference]. Figure 6A and Figure 6B , Figure 6A This is a cross-sectional schematic diagram of the semiconductor structure provided in the third embodiment of the present invention. Figure 6B for Figure 6A The diagram shows a top view of the semiconductor structure, wherein... Figure 6B In the diagram, the void structure 601 and device 630 are obscured and are therefore shown as dashed lines. The semiconductor structure includes a first substrate 600, a second substrate 610, and a through-silicon via (TSV) structure 640.

[0071] The upper surface of the first substrate 600 has a void structure 601 extending into the interior of the first substrate 600. Figure 6A and Figure 6B Only one void structure 601 is schematically shown. In practice, the upper surface of the first substrate 600 may have multiple void structures 601, which are arranged according to a predetermined pattern. Furthermore, the number of void structures 601 is the same as the number of through-silicon via structures 640.

[0072] The second substrate 610 has an insulating layer 611 on its lower surface. The insulating layer 611 serves as a bonding layer, bonding to the first substrate 600 and sealing the void structure 601. A device 630 is disposed on the upper surface of the second substrate 610. In this embodiment, the second substrate 610 includes the insulating layer 611, a supporting silicon layer 612 disposed on the insulating layer 611, and a silicon substrate layer 613. The silicon substrate layer 613 is epitaxially grown based on the supporting silicon layer 612. After the supporting silicon layer 612 is thinned by grinding, its surface is uneven, which can affect the formation of the device. Therefore, the silicon substrate layer 613 is epitaxially grown based on the supporting silicon layer 612, resulting in a flat surface for the final silicon substrate layer 613, thereby avoiding interference with device formation.

[0073] The device 630 is disposed on the silicon substrate layer 613, which can greatly reduce parasitic capacitance, reduce device leakage current, and improve the performance of semiconductor structure.

[0074] The through-silicon via (TSV) structure 640 penetrates both the second substrate 610 and the first substrate 600, and at least a portion of the TSV structure 640's sides are surrounded by the void structure 601. In this embodiment, the TSV structure 640 is disposed inside the void structure 601.

[0075] The semiconductor structure of this invention utilizes a gap structure 601 to prevent the propagation of internal stress generated during the contraction / expansion of the through-silicon via (TSV) structure 640 to surrounding devices 630. Simultaneously, the semiconductor structure of this invention utilizes a sealing layer 611 to seal the gap structure 601, allowing the gap structure 601 to maintain its original design pattern, thereby ensuring the stress release effect of the subsequently formed TSV structure.

[0076] Furthermore, the void structure 601 is a closed structure to further and effectively block the propagation of internal stress generated during the contraction / expansion of the through-silicon via structure 640 to surrounding devices. Figure 6BAs shown, in this embodiment, the gap structure 601 is a closed ring surrounding the through-silicon via structure 640. In other embodiments of the present invention, the gap structure 601 may be a closed ring structure formed by geometric shapes such as rectangles, triangles, or regular polygons.

[0077] Furthermore, in this embodiment, the through-silicon via structure 640 and the void structure 601 are coaxial, so that the void structure 601 can be evenly distributed around the through-silicon via structure 640, further effectively blocking the propagation of the internal stress generated by the through-silicon via structure 640 during contraction / expansion to surrounding devices.

[0078] Furthermore, in the extending direction of the through-silicon via structure 640 (e.g.) Figure 6A In the Y direction, the device 630 is offset from the gap structure 601, that is, the device 630 is disposed on one side of the gap structure 601. In other embodiments of the present invention, the device 630 may also be disposed correspondingly to the gap structure 601.

[0079] Further, the through-silicon via (TSV) structure 640 includes a via 602, an isolation layer 641, and a conductive filling layer. The via 602 penetrates the first substrate 600 and the second substrate 610. The isolation layer 641 covers the inner wall of the via 602, the upper surface of the second substrate 610, and the device 630. The isolation layer 641 may be an insulating layer, such as a silicon oxide layer or a silicon nitride layer. The conductive filling layer fills the via 602. Optionally, the conductive filling layer includes a barrier layer 642, a seed layer 643, and an electroplated layer 644. The barrier layer 642 covers the isolation layer 641 and may be made of a material containing tantalum or titanium; the seed layer 643 covers the barrier layer 642, and the electroplated layer 644 covers the seed layer 643 and fills the via 602; the seed layer 643 and the electroplated layer 644 may be made of a material containing copper or tungsten.

[0080] In the third embodiment, the gap structure 601 of the semiconductor structure is a ring. In another embodiment of the invention, the gap structure is composed of multiple concentric rings. Specifically, please refer to... Figure 7A and Figure 7B , Figure 7A This is a cross-sectional schematic diagram of the semiconductor structure provided in the fourth embodiment of the present invention. Figure 7B for Figure 7A The diagram shows a top view of the semiconductor structure, wherein... Figure 7B In the diagram, the gap structure 601 and device 630 are obscured and are therefore shown as dashed lines. In the fourth embodiment, the gap structure 601 is composed of multiple concentric rings. Figure 6A and Figure 6BOnly three rings are schematically shown in this illustration. In other embodiments, the number of rings may be set according to actual needs.

[0081] Furthermore, in the fourth embodiment, the through-silicon via structure 640 is coaxial with the void structure 601, that is, the through-silicon via structure 640 is coaxial with the plurality of the rings, so that the void structure 601 can be evenly distributed around the through-silicon via structure 640, further effectively blocking the propagation of the internal stress generated by the through-silicon via structure 640 during contraction / expansion to the surrounding devices.

[0082] In the fourth embodiment, in the extending direction of the through-silicon via structure 640 (e.g., Figure 7A In the Y direction), the device 630 is arranged correspondingly to the gap structure 601, which can reduce the influence of stress while increasing the number of devices 630 that can be placed and improving the integration of the semiconductor structure.

[0083] The above description is only a preferred embodiment of the present invention. It should be noted that those skilled in the art can make several improvements and modifications without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A method of manufacturing a semiconductor structure, characterized by, The method comprises: providing a first wafer, an upper surface of the first wafer having a void structure extending into the first wafer; providing a second wafer, a lower surface of the second wafer having an insulating layer; bonding the second wafer and the first wafer with the insulating layer and the upper surface of the first wafer as bonding surfaces, the insulating layer sealing the void structure; forming a device on an upper surface of the second wafer; forming a through-silicon via structure, the through-silicon via structure penetrating the second wafer and the first wafer, and at least part of side surfaces of the through-silicon via structure being surrounded by the void structure.

2. The method of manufacturing a semiconductor structure according to claim 1, wherein In the step of providing the first wafer, the upper surface of the first wafer is patterned to form the void structure.

3. The method of manufacturing a semiconductor structure according to claim 1, wherein In the step of providing the second wafer, the second wafer comprises a support silicon layer and the insulating layer arranged in sequence; after the step of bonding the second wafer and the first wafer with the insulating layer and the upper surface of the first wafer as bonding surfaces, the method further comprises: thinning the support silicon layer; forming a silicon substrate layer on the support silicon layer by epitaxy; the step of forming a device on the upper surface of the second wafer further comprises forming a device on the silicon substrate layer.

4. The method of manufacturing a semiconductor structure according to claim 1, wherein A surface of the insulating layer facing the void structure is flush with the upper surface of the first wafer.

5. The method of manufacturing a semiconductor structure according to claim 1, wherein The step of forming a through-silicon via structure, the through-silicon via structure penetrating the second wafer and the first wafer, and at least part of side surfaces of the through-silicon via structure being surrounded by the void structure further comprises: forming a via, the via penetrating the second wafer and extending into the first wafer, and at least part of side surfaces of the via being surrounded by the void structure; forming an isolation layer in the via, the isolation layer covering inner walls of the via, an upper surface of the second wafer and the device; forming a conductive filling layer, the conductive filling layer filling the via; from a lower surface of the first wafer, removing part of the first wafer to expose a bottom of the conductive filling layer, forming the through-silicon via structure.

6. The method of manufacturing a semiconductor structure according to claim 5, wherein The step of forming a conductive filling layer, the conductive filling layer filling the via further comprises: forming a barrier layer, the barrier layer covering the isolation layer; forming a seed layer, the seed layer covering the barrier layer; forming an electroplated layer on the seed layer, the electroplated layer filling the via.

7. The method of manufacturing a semiconductor structure according to claim 6, wherein The step of forming an electroplated layer on the seed layer, the electroplated layer filling the via is followed by further comprising: removing the barrier layer, the seed layer and the electroplated layer on the upper surface of the first wafer, only leaving the barrier layer, the seed layer and the electroplated layer located in the via.

8. A semiconductor structure, characterized by The method comprises: a first substrate, an upper surface of the first substrate having a void structure extending into the first substrate; a second substrate, a lower surface of the second substrate having an insulating layer, the insulating layer being bonded with the first substrate as a bonding layer and sealing the void structure, a device being arranged on an upper surface of the second substrate; a through-silicon via structure, the through-silicon via structure penetrating the second substrate and the first substrate, and at least part of side surfaces of the through-silicon via structure being surrounded by the void structure.

9. The semiconductor structure of claim 8, wherein, The void structure is a circular ring surrounding the through-silicon via structure.

10. The semiconductor structure of claim 8, wherein, The void structure is composed of a plurality of concentric circular rings.

11. The semiconductor structure of any one of claims 9 or 10, wherein, The through-silicon via structure is coaxial with the void structure.

12. The semiconductor structure of claim 8, wherein, The device is correspondingly arranged with the void structure in the extension direction of the through-silicon via structure.

13. The semiconductor structure of claim 8, wherein, The device is staggered arranged with the void structure in the extension direction of the through-silicon via structure.

14. The semiconductor structure of claim 8, wherein, The second substrate further comprises a support silicon layer and a silicon substrate layer arranged on the insulating layer, and the silicon substrate layer is epitaxially formed on the support silicon layer.

15. The semiconductor structure of claim 8, wherein, The through-silicon via structure comprises: A via hole penetrating through the first substrate and the second substrate; An isolation layer covering the inner wall of the via hole, the upper surface of the second substrate and the device; A conductive filling layer filling the via hole.

16. The semiconductor structure of claim 15, wherein, The conductive filling layer comprises: A barrier layer covering the isolation layer; A seed layer covering the barrier layer; An electroplated layer covering the seed layer and filling the via hole.

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