A semiconductor device and its manufacturing method

Abstract

This invention discloses a semiconductor device and its manufacturing method, relating to the field of semiconductor technology, for reducing parasitic capacitance between adjacent memory contacts and improving the driving capability of the semiconductor device. The semiconductor device includes: a substrate, bit line structures, memory contacts, and an isolation portion. The substrate has an active region. The bit line structures are formed on the substrate and contact a portion of the active region. The memory contacts and the isolation portion are formed between two adjacent bit line structures. The memory contacts contact another portion of the active region. The isolation portion isolates two adjacent memory contacts. The material contained in the isolation portion includes a low-k material. The manufacturing method of the semiconductor device is used to manufacture the semiconductor device provided by the above-described technical solution.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor device and its manufacturing method. Background Technology

[0002] A contact structure is a structure that interconnects the active region within a semiconductor device with metal leads located outside the dielectric layer. Electrical signals within the active region or within the metal leads can be transmitted through the contact structure, thereby enabling corresponding operations on the semiconductor device.

[0003] However, as semiconductor devices are miniaturized, parasitic capacitance is generated between adjacent storage contacts, which reduces the driving capability of the semiconductor device and thus makes the semiconductor device perform poorly. Summary of the Invention

[0004] The purpose of this invention is to provide a semiconductor device and a method for manufacturing the same, which reduces the parasitic capacitance between adjacent storage contacts and improves the driving capability of the semiconductor device.

[0005] To achieve the above objectives, the present invention provides a semiconductor device comprising:

[0006] A substrate with an active region;

[0007] A bitline structure formed on the substrate and in contact with a portion of the active region;

[0008] A storage contact and an isolation portion are formed between two adjacent bit line structures. The storage contact is in contact with another part of the active region, and the isolation portion is used to isolate two adjacent storage contacts. The material contained in the isolation portion includes a low-k material.

[0009] Compared to existing technologies, the semiconductor device provided by this invention includes a storage contact and an isolation portion formed between two adjacent bit line structures. The isolation portion isolates two adjacent storage contacts. Furthermore, the isolation portion is formed from a low-k material. Specifically, the isolation portion formed from a low-k material has a lower dielectric constant. Since capacitance is proportional to dielectric constant, reducing the dielectric constant of the isolation portion between adjacent storage contacts can reduce the parasitic capacitance between adjacent storage contacts, thereby improving the driving capability and operating performance of the semiconductor device.

[0010] The present invention also provides a method for manufacturing a semiconductor device, the method comprising:

[0011] Provide a substrate with an active region;

[0012] A bitline structure is formed on the substrate that contacts a portion of the active region;

[0013] It also forms a storage contact and an isolation portion between two adjacent bit line structures. The storage contact is in contact with another part of the active region, and the isolation portion is used to isolate two adjacent storage contacts. The material contained in the isolation portion includes a low-k material.

[0014] Compared with the prior art, the beneficial effects of the semiconductor device manufacturing method provided by the present invention are the same as those of the semiconductor device provided by the above-mentioned technical solutions, and will not be repeated here. Attached Figure Description

[0015] The accompanying drawings, which are included to provide a further understanding of the invention and constitute a part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings, the subscripts a and b denote sectional views along the AA' and BB' directions in the top view, respectively.

[0016] Figure 1 This is a top view of the completed bitline structure according to an embodiment of the present invention. Figure 1a for Figure 1 The top view shown is along AA'. Figure 1b for Figure 1 The top view shown is a cross-sectional view along the BB' direction;

[0017] Figure 2 This is a top view of the structure after the sacrificial layer is formed in an embodiment of the present invention. Figure 2a for Figure 2 The top view shown is a cross-sectional view along the AA' direction. Figure 2b for Figure 2 The top view shown is a cross-sectional view along the BB' direction;

[0018] Figure 3 This is a top view of the structure after the first groove is formed according to an embodiment of the present invention. Figure 3a for Figure 3 The top view shown is a cross-sectional view along the AA' direction. Figure 3b for Figure 3 The top view shown is a cross-sectional view along the BB' direction;

[0019] Figure 4 This is a top view of the structure formed with low-k material according to an embodiment of the present invention. Figure 4a for Figure 4 The top view shown is a cross-sectional view along the AA' direction. Figure 4b for Figure 4 The top view shown is a cross-sectional view along the BB' direction;

[0020] Figure 5 This is a top view of the structure after the isolation section is formed according to an embodiment of the present invention. Figure 5a for Figure 5The top view shown is a cross-sectional view along the AA' direction. Figure 5b for Figure 5 The top view shown is a cross-sectional view along the BB' direction;

[0021] Figure 6 This is a top view of the structure after the second groove is formed according to an embodiment of the present invention. Figure 6a for Figure 6 The top view shown is a cross-sectional view along the AA' direction. Figure 6b for Figure 6 The top view shown is a cross-sectional view along the BB' direction;

[0022] Figure 7 This is a top view of the structure after the storage contact portion is formed according to an embodiment of the present invention. Figure 7a for Figure 7 The top view shown is a cross-sectional view along the AA' direction. Figure 7b for Figure 7 The top view shown is a cross-sectional view along the BB' direction;

[0023] Figure 8 This diagram illustrates the relationship between the volume percentage of BN in a Si3N4 film containing BN and the dielectric constant and dielectric loss (tanδ) of the film.

[0024] Figure label:

[0025] 1 is the base, 2 is the bit line structure, 21 is the bit line body, 22 is the sidewall, 3 is the storage contact part, 4 is the isolation part, 5 is the sacrificial layer, 6 is the first groove, 7 is the low-k material, and 8 is the second groove. Detailed Implementation

[0026] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0027] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0028] In the context of this disclosure, when a layer / element is referred to as being "on top of" another layer / element, the layer / element may be directly on top of the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "on top of" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element. To make the technical problems, technical solutions, and beneficial effects of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0029] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified. "Several" means one or more, unless otherwise explicitly specified.

[0030] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0031] In memory manufacturing, after the transistors, the dielectric layer covering the transistors, and the bit line structures are fabricated, memory contacts and isolation portions are typically formed between adjacent bit line structures. The isolation portions isolate adjacent memory contacts. The bottom of each memory contact contacts the corresponding active region to facilitate the transmission of electrical signals, enabling corresponding operations on the semiconductor device. Specifically, in existing memory manufacturing processes, several memory contacts are formed between adjacent bit line structures (each memory contact contacts the drain or source region included in the corresponding transistor). Then, the isolation portions can be fabricated using the insulating material Si3N4 via a damascus process to separate adjacent memory contacts.

[0032] However, as semiconductor devices shrink, the spacing between adjacent memory contacts gradually decreases. Furthermore, the high dielectric constant of the isolation portion formed from Si3N4 material results in high dielectric loss, leading to significant parasitic capacitance between adjacent memory contacts. This parasitic capacitance affects charge movement on the memory contacts during semiconductor device operation, reducing the device's driving capability and consequently causing poor memory performance.

[0033] To address the aforementioned technical problems, embodiments of the present invention provide a semiconductor device and a method for manufacturing the same. In the semiconductor device provided by the present invention, the material contained in the isolation portion includes a low-k material, which reduces the dielectric constant of the isolation portion, thereby reducing the parasitic capacitance between adjacent memory contacts, improving the driving capability of the semiconductor device, and enhancing memory performance.

[0034] This invention provides a semiconductor device that can be applied to electronic devices such as DRAM (Dynamic Random Access Memory), FLASH (Flash Memory), MRAM (Magnetic RAM), or RRAM (Resistive Random Access Memory).

[0035] like Figure 7 , Figure 7a and Figure 7b As shown, the semiconductor device includes at least: a substrate 1, a bit line structure 2, a storage contact portion 3, and an isolation portion 4.

[0036] The substrate 1 described above can be a stacked layer with partially formed semiconductor structures. The substrate 1 has active regions, such as source and drain regions already formed. The number and arrangement of the active regions can be set according to the actual application scenario, as long as they can be applied to the semiconductor device provided in this embodiment of the invention. For example, the active regions can be arranged in an intersecting direction with the bit line structure 2. The substrate 1 may also include a gate (word line), which, together with the source and drain regions, forms a transistor structure, serving as a switching transistor for the memory.

[0037] In some cases, the substrate 1 described above also has an isolation region (not shown in the figure). The isolation region is used to isolate two adjacent active regions. For the isolation region described above, the material contained in the isolation region can be an insulating material such as silicon oxide or silicon nitride.

[0038] In other cases, the substrate 1 also has a protective layer (not shown in the figure) covering the surfaces of the active and isolated regions. The protective layer may consist of an insulating layer and a buffer layer, typically a dielectric layer, and the insulating and buffer layers may contain insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride.

[0039] like Figure 7 , Figure 7aand Figure 7b As shown, the bit line structure 2 is formed on the substrate 1. Furthermore, the bit line structure 2 is in contact with a portion of the active region. The bit line structure 2 may include a bit line body 21, a capping layer (not shown) formed on the bit line body 21, and sidewalls 22 located on both sides of the bit line body 21 and the capping layer. The bit line body 21 may include a bit line contact portion and a conductive layer. The bit line contact portion is electrically connected to the source region (or drain region). The material of the bit line contact portion may include doped polysilicon or boron-doped silicon-germanium and other conductive materials. The conductive layer may include doped polysilicon and a metal layer, or it may be a barrier layer and a metal layer. The material of the barrier layer may include TiN or TaN, and the material contained in the metal layer may include tungsten (W), aluminum (Al), copper (Co), nickel (Ni), or cobalt (Co). For the capping layer and sidewalls 22, the materials contained in the capping layer and sidewalls 22 are insulating materials, commonly SiCN, SiOCN, SiON, or SiN.

[0040] like Figure 7 , Figure 7a and Figure 7b As shown, the aforementioned storage contact 3 and isolation portion 4 are formed between two adjacent bit line structures 2. The storage contact 3 contacts another portion of the active region. The isolation portion 4 is used to isolate two adjacent storage contact portions 3. The material contained in the isolation portion 4 includes a low-k material. It should be understood that the region where the other portion of the active region is located is the region where the drain region (or source region) formed on the active region is located. The storage contact 3 contacts the drain region (or source region) on the active region.

[0041] In addition, such as Figure 7 , Figure 7a and Figure 7b As shown, the storage contact portion 3 can be formed both within the protective layer of the substrate 1 and extend into a portion of the active region. In this case, the storage contact portion 3 extends to a greater depth into the substrate 1. Furthermore, the bottom of the storage contact portion 3 contacts multiple surface portions of the drain region (or source region) of the active region after processing, increasing the contact area between the storage contact portion 3 and the drain region (or source region) included in the active region. As for the isolation portion 4 mentioned above, as... Figure 7b As shown, the isolation portion 4 can be formed only within the protective layer of the substrate 1. In this case, the depth to which the isolation portion 4 extends into the substrate 1 is small, and the bottom of the isolation portion 4 is higher than the bottom of the storage contact portion 3.

[0042] The material contained in the aforementioned storage contact portion 3 can be conductive materials such as doped polycrystalline silicon or boron-doped silicon-germanium. For the isolation portion 4, the material contained in the isolation portion 4 includes low-k materials. Generally, insulating materials with a k value less than or equal to 2.8 are considered low-k materials. The isolation portion 4 formed by manufacturing a low-k material has a low dielectric constant, thereby resulting in lower dielectric loss. Since capacitance is proportional to dielectric constant, reducing the dielectric constant of the isolation portion 4 between adjacent storage contacts 3 can reduce the parasitic capacitance between adjacent storage contacts 3, thereby improving the driving capability of the semiconductor device and enhancing the operating performance of the memory.

[0043] For example, the aforementioned low-k material can be one or more of BN, SiBN, and SiCN.

[0044] For example, Figure 8 This diagram illustrates the relationship between the volume percentage of BN in a Si3N4 film and the dielectric constant and dielectric loss (tanδ) of the film. Here, tanδ is the dielectric loss tangent, and tanδ is proportional to the dielectric loss. Figure 8 It can be seen that the higher the volume percentage of BN in the Si3N4 film, the lower the dielectric constant and dielectric loss of the film. Based on this, when the low-k material is BN, the isolation part 4 formed by the low-k material has a lower dielectric constant and dielectric loss.

[0045] In summary, in practical applications, such as Figure 7 , Figure 7a and Figure 7b As shown, when the above-described semiconductor device is applied in DRAM, the substrate 1 can be a semiconductor substrate on which a transistor structure has already been formed. Furthermore, a protective layer consisting of an insulating layer and a buffer layer is formed on the transistor structure. The insulating layer and buffer layer can contain insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride. The above-described bit line structure 2, and storage contact portions 3 and isolation portions 4 located between adjacent bit line structures 2 are formed on the substrate 1. When the isolation portion 4 is formed of the above-described low-k material, the parasitic capacitance between adjacent storage contact portions 3 can be reduced, thereby improving the driving capability and operating performance of the DRAM device. Of course, the semiconductor device provided in this embodiment of the invention can also be applied to other electronic devices and is not limited to the above-described DRAM device.

[0046] This invention also provides a method for manufacturing a semiconductor device. The following will use DRAM manufacturing as an example, according to... Figures 1 to 7bThe top or cross-sectional views shown illustrate the manufacturing method provided by the embodiments of the present invention. The subscripts a or b in each figure represent cross-sectional views along the AA' or BB' direction in the corresponding top view. AA' corresponds to the position where the storage contact portion 3 is to be formed, and BB' corresponds to the position of the isolation portion 4 between the storage contact portions 3. This will not be explained further below.

[0047] First, a substrate 1 with active regions is provided. The structure, number, and arrangement of the active regions can be found in the previous text and will not be repeated here. In some cases, the substrate 1 also has an isolation region and a protective layer. The isolation region is used to isolate two adjacent active regions. The protective layer covers the isolation region and the active regions. The materials contained in the isolation region and the protective layer can be found in the previous text.

[0048] Reference Figure 1 , Figure 1a and Figure 1b Bitline structure 2 is formed on substrate 1.

[0049] As described above, the bitline structure 2 may include a bitline contact portion, a bitline body 21, a capping layer, and a sidewall 22. The bitline contact portion, bitline body 21, capping layer, and sidewall 22 may be formed sequentially on the substrate 1.

[0050] For example: First, contact holes can be formed on the substrate 1 at the locations where bit line contacts are to be formed, and bit line contacts can be formed within the contact holes. Next, a bit line material layer is deposited on the substrate 1. For example, the bit line material layer can be a stacked structure of polysilicon and metal W. Then, a capping layer pattern is formed on the stacked structure, and using the capping layer pattern as a mask, the stacked structure and the substrate 1 are etched to form the bit line body 21. Finally, sidewalls 22 are formed on both sides of the bit line body 21 and the capping layer included in the capping layer pattern. Specifically, a sidewall material layer can be deposited on the entire substrate 1 and the bit line body 21, and the sidewalls 22 can be formed by anisotropic etching. The materials contained in the bit line contacts, bit line body 21, capping layer, and sidewalls 22 can be referred to the previous text and will not be elaborated here.

[0051] It should be noted that the bitline structure 2 described above can be formed in various ways. How the bitline structure 2 is formed is not a key feature of the embodiments of this invention; therefore, it is only briefly described in this specification so that those skilled in the art can easily implement the embodiments provided by this invention. Those skilled in the art can certainly imagine other ways to manufacture the bitline structure 2.

[0052] Reference Figure 2 , Figure 2a and Figure 2b A sacrificial layer 5 is formed between two adjacent bitline structures 2.

[0053] For example, a sacrificial layer 5 can be formed directly between two adjacent bit line structures 2 using methods such as chemical vapor deposition. The sacrificial layer 5 can contain materials that are easy to remove. For example, the sacrificial layer 5 can contain SiO2 and / or a carbon polymer. The specific composition of the carbon polymer can be set according to actual conditions and is not specifically limited here. For example, the carbon polymer may include propylene glycol monomethyl ether, propylene glycol monoethyl ether, amide methyl ether crosslinking agent, acrylic polymer, 2-methoxy-1-propanol, and surfactant. The content of each substance included in the above-mentioned carbon polymer can be set according to actual conditions.

[0054] The top height of the sacrificial layer 5 should be equal to or greater than the top height of the bit line structure 2. When the top height of the formed sacrificial layer 5 is greater than the top height of the bit line structure 2, the sacrificial layer 5 can be planarized after its formation until the top of the bit line structure 2 is exposed.

[0055] In another example, after forming bit line structures 2 on substrate 1, the protective layer included in substrate 1 can be etched using the bit line structures 2 as a mask until the active region between adjacent bit line structures 2 is exposed. Then, sacrificial material is filled into the trenches formed by etching substrate 1 to form a sacrificial layer 5.

[0056] Reference Figure 3 , Figure 3a and Figure 3b The sacrificial layer 5 located within the predetermined area is processed to form the first groove 6.

[0057] For example, a photolithographic mask pattern can be formed over the substrate 1 filled with the sacrificial layer 5, exposing the location where the isolation region needs to be etched. Plasma etching, reactive ion etching, or other etching methods are used to remove the sacrificial layer 5 outside the corresponding active region, leaving the sacrificial layer 5 on the active region to form a first groove 6. The depth of the first groove 6 can be at least equal to the thickness of the sacrificial layer 5. Specifically, the shape parameters (depth, width, etc.) of the first groove 6 determine the shape parameters (depth, width, etc.) of the subsequently formed isolation portion 4; therefore, the shape parameters of the first groove 6 can be set according to the shape parameters of the isolation portion 4.

[0058] Reference Figure 4 , Figure 4a and Figure 4b A low-k material 7 covering the bit line structure 2 and the first groove 6 can be formed on the substrate 1. For example, the low-k material 7 covering the bit line structure 2 and the first groove 6 can be formed using methods such as chemical vapor deposition. Specifically, the k value of the low-k material 7 is less than or equal to 2.8.

[0059] For example, the low-k material 7 can be one or more of BN, SiBN, and SiCN.

[0060] Reference Figure 5 , Figure 5a and Figure 5b An isolation portion 4 is formed within the first groove 6. It should be understood that, to ensure the low-k material 7 fills the first groove 6, the top of the low-k material 7 is higher than the top of the bit line structure 2. At this time, the low-k material 7 both fills the first groove 6 and is formed on the bit line structure 2. To form the mutually separated isolation portions 4, the low-k material 7 also needs to undergo node separation processing, retaining only the low-k material 7 located within the first groove 6. Correspondingly, the remaining low-k material 7 within the first groove 6 forms the isolation portion 4.

[0061] Specifically, low-k material 7 can be separated into nodes using either plasma etching or wet etching. When using plasma etching, the specific operating parameters can be set according to the actual application scenario and are not specifically limited here. When using wet etching, the solution used can be an HF solution or a mixed solution containing HF, H2SO4, H2O2, and deionized water. The proportions of HF, H2SO4, H2O2, and deionized water in the mixed solution can be set according to the actual application scenario and are not specifically limited here.

[0062] The remaining sacrificial layer 5 can then be removed, for example, by wet etching or dry etching, to expose the surface of the substrate 1 covered by the remaining sacrificial layer 5.

[0063] Reference Figure 6 , Figure 6a and Figure 6b Next, a second groove 8 is formed between adjacent bit line structures 2. It should be understood that, in order to form a memory contact portion 3 that contacts the corresponding active region, the substrate 1 can be etched downwards using the bit line structure 2 and the isolation portion 4 as a mask to form the second groove 8, thereby exposing the active region located between adjacent bit line structures 2. Of course, after exposing the active region located between adjacent bit line structures 2, the substrate 1 can continue to be etched downwards to increase the contact area between the drain region (or source region) included in the active region and the subsequently formed memory contact portion 3.

[0064] Reference Figure 7 , Figure 7a and Figure 7b Storage contact 3 is formed within the second groove 8. For example, storage contact 3 can be formed on the active region exposed between adjacent bit line structures 2 by means of epitaxy or chemical vapor deposition.

[0065] It should be noted that in the process of forming the storage contact 3 and the isolation portion 4, the sacrificial layer 5 in the predetermined area is first removed to form the first groove 6, and the isolation portion 4 is formed within the first groove 6. Then, the remaining sacrificial layer 5 and the substrate 1 located between adjacent bit line structures 2 are processed to form the second groove 8, and the storage contact 3 is formed within the second groove 8. In practical applications, the formation order of the storage contact 3 and the isolation portion 4 can be interchanged; that is, the storage contact 3 can be formed first, followed by the isolation portion 4. Specifically, the formation order of the storage contact 3 and the isolation portion 4 can be set according to the actual situation and is not limited here.

[0066] The beneficial effects of the semiconductor device manufacturing method provided in the embodiments of the present invention are the same as those of the semiconductor device provided in the above embodiments, and will not be repeated here.

[0067] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0068] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A semiconductor device, characterized in that, include: A substrate with an active region; A bitline structure formed on the substrate and in contact with a portion of the active region; A storage contact and an isolation portion are formed between two adjacent bit line structures. The storage contact is in contact with another part of the active region. The isolation portion is used to isolate two adjacent storage contacts. The material contained in the isolation portion includes a low-k material. The k value of the low-k material is less than or equal to 2.8, and the low-k material is one or more of BN, SiBN, and SiCN.

2. The semiconductor device according to claim 1, characterized in that, The bottom of the isolation section is higher than the bottom of the storage contact section.

3. The semiconductor device according to claim 1 or 2, characterized in that, The bitline structure includes a bitline body, a capping layer on the bitline body, and sidewalls on both sides of the bitline body and the capping layer.

4. A method for manufacturing a semiconductor device, characterized in that, include: Provide a substrate with an active region; A bit line structure is formed on the substrate that contacts a portion of the active region; A storage contact and an isolation portion are formed between two adjacent bit line structures. The storage contact is in contact with another part of the corresponding active region. The isolation portion is used to isolate two adjacent storage contacts. The material contained in the isolation portion includes a low-k material. The k value of the low-k material is less than or equal to 2.8, and the low-k material is one or more of BN, SiBN, and SiCN.

5. The method for manufacturing a semiconductor device according to claim 4, characterized in that, The process of forming a storage contact and an isolation portion between two adjacent bit line structures includes: A sacrificial layer is formed between two adjacent bitline structures; The sacrificial layer located within the predetermined area is processed to form a first groove; The isolation portion is formed within the first groove; Remove the remaining sacrificial layer, and using the bit line structure and the isolation portion as a mask, etch the substrate downwards to form a second groove to expose another portion of the active region located between adjacent bit line structures; The storage contact portion is formed in the second groove.

6. The method for manufacturing a semiconductor device according to claim 5, characterized in that, The step of forming a sacrificial layer between two adjacent bitline structures includes: Using the bit line structure as a mask, the substrate is etched until the active region is exposed to form a trench parallel to the bit line structure; The trench is filled with sacrificial material to form a sacrificial layer.

7. The method for manufacturing a semiconductor device according to claim 5 or 6, characterized in that, The sacrificial layer contains materials including SiO2 and / or carbon polymers.

8. The method for manufacturing a semiconductor device according to claim 5 or 6, characterized in that, The process of forming the isolation portion within the first groove includes: On the substrate, a low-k material is formed covering the bit line structure and the first groove; The low-k material is subjected to node separation processing to obtain the isolation section.

9. The method for manufacturing a semiconductor device according to claim 8, characterized in that, The low-k material is subjected to node separation processing using either plasma etching or wet etching.

10. The method for manufacturing a semiconductor device according to claim 8, characterized in that, When the low-k material is subjected to node separation using wet etching, the solution used is an HF solution, or a mixed solution containing HF, H2SO4, H2O2 and deionized water.

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