A current-mode sense amplifier circuit and process mismatch cancellation method

Abstract

The application discloses a current-mode sensitive amplifier circuit and a process mismatch elimination method. The circuit comprises a current sampling circuit. The current sampling circuit comprises a first charge-discharge module, a path switching module, a first pre-charge current module and a second pre-charge current module. One end of the first pre-charge current module is used for accessing a reference current of a resistive random access memory (RRAM) unit circuit, and one end of the second pre-charge current module is used for accessing a unit current of the RRAM unit circuit. The path switching module is used for conducting the first pre-charge current module and a first end of the first charge-discharge module, and conducting the second pre-charge current module and a second end of the first charge-discharge module, so as to form a current sampling stage. The path switching module is also used for conducting the first pre-charge current module and the second end of the first charge-discharge module, and conducting the second pre-charge current module and the first end of the first charge-discharge module, so as to form a current amplification stage. The sensing margin of the existing RRAM can be improved.

Description

Technical Field

[0001] This application relates to the field of circuit technology, and in particular to a current-type sensitive amplifier circuit and a method for eliminating process mismatch. Background Technology

[0002] In recent years, due to the advantages of resistive random access memory (RRAM), such as high speed, simple structure, compatibility with CMOS technology, and good miniaturization, the application range of resistive random access memory has become wider and wider.

[0003] However, as integrated circuit scale increases, device size and operating voltage continue to decrease, leading to a decline in the sensing margin (SM) of resistive random access memory (IRRAM). Therefore, improving the sensing margin of IRRAM has become one of the key research topics. Summary of the Invention

[0004] This application provides a current-mode sensitive amplifier circuit and a method for eliminating process mismatch, which can improve the sensing margin of existing resistive random access memory.

[0005] In a first aspect, a current-type sensitive amplifier circuit includes: a current sampling circuit;

[0006] The current sampling circuit includes a first charging and discharging module, a path switching module, a first pre-charge current module, and a second pre-charge current module. One end of the first pre-charge current module is used to connect to the reference current of the resistive switching memory unit circuit, and one end of the second pre-charge current module is used to connect to the unit current of the resistive switching memory unit circuit. The other ends of the first pre-charge current module and the second pre-charge current module are electrically connected and used to connect to a high level.

[0007] The path switching module is used to connect the first terminal of the first pre-charge current module to the first terminal of the first charge-discharge module, and to connect the second terminal of the second pre-charge current module to the second terminal of the first charge-discharge module, so as to form a current sampling stage.

[0008] The path switching module is also used to connect the second terminal of the first pre-charge current module to the first charge-discharge module, and to connect the second pre-charge current module to the first terminal of the first charge-discharge module, so as to form a current amplification stage.

[0009] In one feasible implementation, the first charge / discharge module includes a capacitor.

[0010] In one feasible implementation, both the first pre-charge current module and the second pre-charge current module include a pre-charge MOS transistor;

[0011] During the current sampling phase, the path switching module is used to control the reference current of the drain of the pre-charge MOS transistor of the first pre-charge current module connected to the resistive random access memory cell circuit, the cell current of the drain of the pre-charge MOS transistor of the second pre-charge current module connected to the resistive random access memory cell circuit, the source of the pre-charge MOS transistor of the first pre-charge current module and the source of the pre-charge MOS transistor of the second pre-charge current module being electrically connected and then connected to a high level, the gate of the pre-charge MOS transistor of the first pre-charge current module being electrically connected to the second terminal of the first charge-discharge module, and the gate of the pre-charge MOS transistor of the second pre-charge current module being electrically connected to the first terminal of the first charge-discharge module;

[0012] During the current amplification stage, the path switching module is used to control the gate of the pre-charge MOS transistor of the first pre-charge current module to be electrically connected to the second terminal of the first charge-discharge module, and the gate of the pre-charge MOS transistor of the second pre-charge current module to be electrically connected to the first terminal of the first charge-discharge module.

[0013] In one feasible implementation, the path switching module includes multiple switches;

[0014] A switch is provided between the drain of the precharge MOS transistor in the first precharge current module and the first terminal of the first charge and discharge module, and a switch is provided between the drain of the precharge MOS transistor in the second precharge current module and the second terminal of the first charge and discharge module.

[0015] A switch is provided between the gate of the precharge MOS transistor of the first precharge current module and the first terminal of the first charge-discharge module, and a switch is provided between the gate of the precharge MOS transistor of the first precharge current module and the second terminal of the first charge-discharge module.

[0016] A switch is provided between the gate of the precharge MOS transistor of the second precharge current module and the first terminal of the first charge-discharge module, and a switch is provided between the gate of the precharge MOS transistor of the second precharge current module and the second terminal of the first charge-discharge module.

[0017] In one feasible implementation, it further includes: a latch comparator, the latch comparator comprising two inverter units;

[0018] A switch is provided between the input and output terminals of the inverter unit. When the switch is closed, it is used to connect the input and output terminals of the inverter unit to form an adapter comparator stage.

[0019] The latch comparator further includes a second charge / discharge module, one end of which is electrically connected to the input terminal of one of the inverter units, and the other end of which is electrically connected to the output terminal of another inverter unit.

[0020] In one feasible implementation, a switch is provided between the input terminal of the inverter unit and the ground point. When the switch is closed, it is used to ground the input terminal of the inverter unit to form a pre-charging phase.

[0021] A switch is provided between the output terminal of one inverter unit and the input terminal of another inverter unit, the switch being used to close during the pre-charging phase, the current sampling phase, the current amplification phase, and the data readout phase.

[0022] In one feasible implementation, the input terminal of one of the inverter units is used to access the reference current of the resistive random access memory (RRAM) cell circuit during the current sampling phase and the current amplification phase, and the input terminal of the other inverter unit is used to access the cell current of the RRAM cell circuit during the current sampling phase and the current amplification phase.

[0023] The input terminal of one of the inverter units is also used to connect the reference current of the resistive random access memory (RRAM) cell circuit outside the current sampling stage and the current amplification stage, and the input terminal of the other inverter unit is also used to connect the cell current of the RRAM cell circuit outside the current sampling stage and the current amplification stage to form a data readout stage.

[0024] Secondly, a method for eliminating process mismatch in a current-mode sensitive amplifier circuit includes:

[0025] By controlling the path switching module, the first terminal of the first pre-charge current module is connected to the first terminal of the first charge-discharge module, the first terminal of the first charge-discharge module is connected to the reference current of the resistive random access memory (RRAM) cell circuit, the second terminal of the second pre-charge current module is connected to the second terminal of the first charge-discharge module, and the second terminal of the first charge-discharge module is connected to the cell current of the RRAM cell circuit, so that the first pre-charge current module charges the first terminal of the first charge-discharge module with pre-charge current, and the second pre-charge current module charges the second terminal of the first charge-discharge module with pre-charge current, thus forming a current sampling stage;

[0026] By controlling the path switching module, the second terminal of the first pre-charge current module is connected to the second terminal of the first charge-discharge module, and the first terminal of the second pre-charge current module is connected to the first terminal of the first charge-discharge module, thus forming a current amplification stage.

[0027] In one feasible implementation, prior to the formation of the current sampling phase, the method further includes:

[0028] The input and output terminals of the inverter unit are connected to charge the second charge / discharge module, so that the trip voltages of the two inverter units are stored at both ends of the second charge / discharge module, forming the adapter comparator stage.

[0029] In one feasible implementation, after the adapter comparator stage is formed, the method further includes:

[0030] The input terminals of the two inverter units are connected to the ground point so that the output terminals of the two inverter units are precharged to 0. The output terminal of one inverter unit is connected to the input terminal of the other inverter unit so that the performance parameters of the two inverter units are matched to form a precharge stage.

[0031] After the current amplification stage is formed, the following is also included:

[0032] The output terminal of one inverter unit is connected to the input terminal of another inverter unit. The input terminal of one inverter unit is connected to the first terminal of the first charge-discharge module, and the input terminal of the other inverter unit is connected to the second terminal of the first charge-discharge module. This is so that when the unit current is greater than the reference current, the potential of the first terminal of the first charge-discharge module is pulled to a high level, and the potential of the second terminal of the first charge-discharge module is pulled to 0, thus outputting a storage signal to the resistive random access memory unit circuit and forming a data read-out stage.

[0033] The current-type sensitive amplifier circuit and process mismatch elimination method provided in this application embodiment, by setting a first charging / discharging module and a path switching module, controls the path switching module to charge and discharge the first charging / discharging module to form a current sampling stage and a current amplification stage. This allows the current difference between the original first potential point and the second potential point to be amplified to twice its original value through the current-type sensitive amplifier circuit. Finally, based on the voltages of the first and second potential points after the current difference is amplified, one is pulled high and the other low to achieve the judgment and output of the stored signal. This two-stage circuit (current sampling stage and current amplification stage) achieves rail-to-rail output of the current-type sensitive amplifier circuit, improving the driving capability of the current-type sensitive amplifier circuit and achieving double the readout sensing margin of the resistive random access memory (RRAM), thus improving the sensitivity of the RRAM. In addition, since the current difference between the first potential point and the second potential point is amplified to twice the current difference in the existing current sampling circuit, the increase in the current difference can reduce the impact of the process mismatch between the symmetrically arranged first pre-charge current module and second pre-charge current module on the current sampling circuit. That is, the increase in the current difference can reduce the sensitivity of the current sampling circuit to the process mismatch between the first pre-charge current module and the second pre-charge current module, and can weaken the impact of the process mismatch between the first pre-charge current module and the second pre-charge current module within a certain range. Attached Figure Description

[0034] Figure 1 A schematic circuit block diagram of a current-type sensitive amplifier circuit provided for embodiments of this application;

[0035] Figure 2 A schematic circuit diagram of a current-mode sensitive amplifier circuit provided for an embodiment of this application;

[0036] Figure 3 A schematic circuit diagram of another current-mode sensitive amplifier circuit provided for an embodiment of this application;

[0037] Figure 4 A schematic flowchart illustrating a process mismatch elimination method for a current-mode sensitive amplifier circuit provided in this application embodiment;

[0038] Figure 5 This is a schematic timing diagram illustrating a process mismatch elimination method for a current-mode sensitive amplifier circuit provided in an embodiment of this application. Detailed Implementation

[0039] To better understand the technical solutions provided in the embodiments of this specification, the technical solutions of the embodiments of this specification will be described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the embodiments of this specification and the specific features in the embodiments are detailed descriptions of the technical solutions of the embodiments of this specification, rather than limitations on the technical solutions of this specification. In the absence of conflict, the embodiments of this specification and the technical features in the embodiments can be combined with each other.

[0040] In this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, without necessarily requiring or implying any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element. The term "two or more" includes two or more cases.

[0041] In recent years, resistive random access memory (IRRAM) has seen increasingly wider applications due to its advantages such as high speed, simple structure, compatibility with CMOS processes, and good miniaturization. However, as integrated circuit scale increases, device size and operating voltage continue to decrease, leading to a decline in the sensing margin of IRRAM. Therefore, improving the sensing margin of IRRAM has become one of the key research topics.

[0042] In view of this, embodiments of this application provide a current-type sensitive amplifier circuit and a method for eliminating process mismatch.

[0043] Firstly, Figure 1This is a schematic circuit block diagram of a current-type sensitive amplifier circuit provided in an embodiment of this application. As shown in the figure, the current-type sensitive amplifier circuit provided in this application includes: a current sampling circuit 100 and a latch 200. The current sampling circuit 100 may include a first charging / discharging module 110, a path switching module 120, a first pre-charge current module 130, and a second pre-charge current module 140; one end of the first pre-charge current module 130 is used to connect to the reference current Iref of the resistive switching memory cell circuit, one end of the second pre-charge current module 140 is used to connect to the cell current Icell of the resistive switching memory cell circuit, and the other ends of the first pre-charge current module 130 and the second pre-charge current module 140 are electrically connected and used to connect to the high level VDD. The path switching module 120 is used to connect the first pre-charge current module 130 to the first terminal 111 of the first charging / discharging module 110, and to connect the second pre-charge current module 140 to the second terminal 112 of the first charging / discharging module 110, to form a current sampling stage. The path switching module 120 is also used to connect the second terminal 112 of the first pre-charge current module 130 to the first charge / discharge module 110, and to connect the second pre-charge current module 140 to the first terminal 111 of the first charge / discharge module 110, to form a current amplification stage. The two ends of the latch 200 can be respectively connected to the reference current Iref and the unit current Icell of the resistive switching memory cell circuit. The reference current input terminal DBL and the unit current input terminal BL of the reference current Iref and the unit current Icell can both serve as the input terminals of the current-type sensitive amplifier circuit; this application does not specifically limit this.

[0044] During the current sampling phase, the control path switching module 120 can connect the first pre-charge current module 130 to the first terminal 111 of the first charge-discharge module 110, connect the first terminal 111 of the first charge-discharge module 110 to the reference current Iref of the resistive random access memory (RRAM) cell circuit, connect the second pre-charge current module 140 to the second terminal 112 of the first charge-discharge module 110, and connect the second terminal 112 of the first charge-discharge module 110 to the cell current Icell of the RRAM cell circuit. This allows the first pre-charge current module 130 to pre-charge the first terminal 111 of the first charge-discharge module 110, and the second pre-charge current module 140 to pre-charge the second terminal 112 of the first charge-discharge module 110. During the current sampling phase, as the first pre-charge current module 130 pre-charges the first terminal 111 of the first charge / discharge module 110 and the second pre-charge current module 140 pre-charges the second terminal 112 of the first charge / discharge module 110, the voltage at the first terminal 111 and the second terminal 112 of the first charge / discharge module 110 continuously increases, and the voltage V on the first pre-charge current module 130 increases. 130 The voltage V on the second pre-charge current module 140 140Stored at both ends of the first charge and discharge module 110, when Icell > Iref or Icell < Iref, then V 130 > V 140 or V 130 < V 140 , therefore, the voltage V1 at the first potential point A and the voltage V2 at the second potential point B satisfy V1 > V2 or V1 < V2.

[0045] In the current amplification stage, by controlling the path switching module 120, the first pre-charge current module 130 can be connected to the second end 112 of the first charge and discharge module 110, and the second pre-charge current module 140 can be connected to the first end 111 of the first charge and discharge module 110. When Icell > Iref, the charging current at the first end 111 of the first charge and discharge module 110 is Icell, the discharging current at the first end 111 of the first charge and discharge module 110 is Iref, the charging current at the second end 112 of the first charge and discharge module 110 is Iref, and the discharging current at the second end 112 of the first charge and discharge module 110 is Icell. Then the voltage V1 at the first potential point A will continue to increase, and the voltage V2 at the second potential point B will decrease. Finally, the current flowing through the first potential point A is Icell - Iref, and the current flowing through the second potential point B is Iref - Icell. Then the current difference between the second potential point B and the first potential point A is Icell - Iref - (Iref - Icell) = 2(Icell - Iref). At this time, the latch 200 starts to work, pulling the voltage V1 at the first potential point A to a high level (VDD), and pulling the voltage V2 at the second potential point B to a low level (0). Exemplarily, if the first potential point A is used as the potential output point, the sensitive amplifier outputs a storage signal of "1" at this time, and when Icell < Iref, the output storage signal is "0". If the second potential point B is used as the potential output point, when Icell > Iref, the output storage signal is "0", and when Icell < Iref, the output storage signal is "1".

[0046] The current-type sensitive amplifier circuit provided in this application embodiment, by setting a first charging / discharging module 110 and a path switching module 120, controls the path switching module 120 to charge and discharge the first charging / discharging module 110, thereby forming a current sampling stage and a current amplification stage. This allows the current difference (Icell-Iref) between the original first potential point A and the second potential point B to be amplified to 2 (Icell-Iref) through the current-type sensitive amplifier circuit. Finally, based on the voltages of the first potential point A and the second potential point B after amplification of the current difference, one is pulled high and the other low, to achieve the judgment and output of the stored signal. This two-stage circuit (current sampling stage and current amplification stage) achieves rail-to-rail output of the current-type sensitive amplifier circuit, improving the driving capability of the current-type sensitive amplifier circuit and achieving double the readout sensing margin of the resistive random access memory, thus improving the sensitivity of the resistive random access memory. Furthermore, since the current difference between the first potential point A and the second potential point B is amplified to 2 (Icell-Iref), which is twice the current difference in the existing current sampling circuit, the increase in the current difference can reduce the impact of the process mismatch between the symmetrically arranged first pre-charge current module 130 and second pre-charge current module 140 on the current sampling circuit 100. That is, the increase in the current difference can reduce the sensitivity of the current sampling circuit 100 to the process mismatch between the first pre-charge current module 130 and second pre-charge current module 140, and can weaken the impact of the process mismatch between the first pre-charge current module 130 and second pre-charge current module 140 within a certain range.

[0047] In one feasible implementation, Figure 2 This is a schematic circuit diagram of a current-mode sensitive amplifier circuit provided for an embodiment of this application. Figure 2 As shown, the first charging and discharging module 110 may include a capacitor C1.

[0048] The current-type sensitive amplifier circuit provided in this application embodiment includes a first charging / discharging module 110 with a capacitor C1. Its structure is simple and easy to implement. Compared to the multiple capacitors in existing amplifier circuits for resistive random access memory (RRAM), the current sampling circuit 100 in the current-type sensitive amplifier circuit provided in this application embodiment only uses one capacitor. This saves on the number of capacitors, reduces space requirements, and thus reduces the area of ​​the current-type sensitive amplifier circuit. Furthermore, it achieves the amplification effect of the two-stage circuit on the difference in unit current. While achieving double the readout sensitivity margin of the RRAM and improving the sensitivity of the RRAM, it also reduces the circuit area and saves space.

[0049] In one feasible implementation, continue to refer to Figure 2Both the first pre-charge current module 130 and the second pre-charge current module 140 include pre-charge MOSFETs, which can be pre-charge MOSFET M1 and pre-charge MOSFET M2, respectively. During the current sampling stage, the path switching module 120 can be used to control the reference current Iref of the resistive random access memory cell circuit connected to the drain of the pre-charge MOSFET M1 of the first pre-charge current module 130, the cell current Icell of the resistive random access memory cell circuit connected to the drain of the pre-charge MOSFET M2 of the second pre-charge current module 140, the high level VDD connected to the source of the pre-charge MOSFET M1 of the first pre-charge current module 130 and the source of the pre-charge MOSFET M2 of the second pre-charge current module 140, the second terminal 112 of the first charge-discharge module 110 connected to the gate of the pre-charge MOSFET M1 of the first pre-charge current module 130, and the first terminal 111 of the first charge-discharge module 110 connected to the gate of the pre-charge MOSFET M2 of the second pre-charge current module 140. During the current amplification stage, the path switching module 120 is also used to control the gate of the pre-charge MOS transistor M1 of the first pre-charge current module 130 to be electrically connected to the second terminal 112 of the first charge-discharge module 110, and the gate of the pre-charge MOS transistor M2 of the second pre-charge current module 140 to be electrically connected to the first terminal 111 of the first charge-discharge module 110. The voltage V on the first pre-charge current module 130 mentioned in the above embodiment... 130 The voltage V on the second pre-charge current module 140 140 These correspond to the gate voltages of precharged MOSFETs M1 and M2, respectively.

[0050] The current-type sensitive amplifier circuit provided in this application embodiment can achieve the same potential between the drain of the pre-charge MOS transistor M1 and the first potential point A, and the drain of the pre-charge MOS transistor M2 and the second potential point B through MOS, which can realize the charging and discharging process of the first charging and discharging module 110. The structure is simple and easy to implement.

[0051] In one feasible implementation, continue to refer to Figure 2The path switching module 120 may include multiple switches. Specifically, a switch S3 is provided between the drain of the pre-charge MOSFET M1 of the first pre-charge current module 130 and the first terminal 111 of the first charge / discharge module 110; a switch S3 is provided between the drain of the pre-charge MOSFET M2 of the second pre-charge current module 140 and the second terminal 112 of the first charge / discharge module 110; a switch S3 is provided between the gate of the pre-charge MOSFET M1 of the first pre-charge current module 130 and the first terminal 111 of the first charge / discharge module 110; a switch S4 is provided between the gate of the pre-charge MOSFET M1 of the first pre-charge current module 130 and the second terminal 112 of the first charge / discharge module 110; a switch S4 is provided between the gate of the pre-charge MOSFET M2 of the second pre-charge current module 140 and the first terminal 111 of the first charge / discharge module 110; and a switch S3 is provided between the gate of the pre-charge MOSFET M2 of the second pre-charge current module 140 and the second terminal 112 of the first charge / discharge module 110. A switch S3-4 is provided between the drain of the precharge MOS transistor M1 in the first precharge current module 130 and the reference current input terminal DBL, and a switch S3-4 is provided between the drain of the precharge MOS transistor M2 in the second precharge current module 140 and the unit current input terminal BL.

[0052] During the current sampling phase, switches S3 and S3-4 are both closed, while switch S4 is open. During the current amplification phase, switches S4 and S3-4 are closed, while switch S3 is open.

[0053] The current-type sensitive amplifier circuit provided in this application embodiment achieves path switching of the path switching module 120 by opening and closing a switch. The circuit structure is simple, and the switch is easy to control. At the same time, the opening and closing of the switch can accurately control the conduction and disconnection of the path.

[0054] In one feasible implementation, Figure 3 A schematic circuit diagram of another current-type sensitive amplifier circuit provided for an embodiment of this application. (See attached diagram.) Figure 3As shown, the current-type sensitive amplifier circuit also includes a latch comparator 300. The latch comparator 300 can perform the function of the latch 200, therefore, the latch comparator 300 can replace the latch 200. The latch comparator 300 may include two inverter units, namely a first inverter unit 310 and a second inverter unit 320, which can be symmetrically arranged. A switch S1 is provided between the input and output terminals of the inverter units, that is, a switch S1 is provided between the input terminal In1 and the output terminal OU1 of the first inverter unit 310, and a switch S1 is provided between the input terminal In2 and the output terminal OU2 of the second inverter unit 320. When the switch S1 is closed, it is used to connect the input and output terminals of the inverter units to form an adapter comparator stage. The first inverter unit 310 may include MOSFETs M4 and M6 connected in series, and the second inverter unit 320 may include MOSFETs M5 and M7 connected in series. The latch comparator 300 also includes a second charge-discharge module, which may include a capacitor C2. One end of the second charge-discharge module is electrically connected to the input terminal In1 of the first inverter unit 310, and the other end is electrically connected to the output terminal OU2 of the second inverter unit 320.

[0055] In one feasible implementation, continue to refer to Figure 3 A switch S2 is provided between the input terminal of the inverter unit and the ground point. When closed, switch S2 is used to ground the input terminal of the inverter unit to form a pre-charging phase. That is, during the pre-charging phase, the input terminal In1 of the first inverter unit 310 is grounded, and the input terminal In2 of the second inverter unit 320 is grounded. A switch S2-3-4-5 is provided between the output terminal OU1 of the first inverter unit 310 and the input terminal In2 of the second inverter unit 320. Switch S2-3-4-5 is used to close during the pre-charging phase, the current sampling phase, the current amplification phase, and the data readout phase.

[0056] In one feasible implementation, continue to refer to Figure 3A switch S3-4-5 is provided between the input terminal In1 of the first inverter unit 310 and the reference current input terminal DBL. Closing switch S3-4-5 allows access to the first potential point A during the current sampling and current amplification stages. Similarly, a switch S3-4-5 is provided between the input terminal In2 of the second inverter unit 320 and the unit current input terminal BL. Closing switch S3-4-5 allows access to the second potential point B during the current sampling and current amplification stages. Closing switch S3-4-5 allows the input terminal In1 of the first inverter unit 310 to access the reference current Iref of the resistive random access memory (RRAM) unit circuit outside of the current sampling and current amplification stages, and the input terminal In2 of the second inverter unit 320 to access the unit current Icell of the RRAM unit circuit outside of the current sampling and current amplification stages, thus forming a data readout stage.

[0057] In one feasible implementation, continue to refer to Figure 3 One end of the first inverter unit 310 and the second inverter unit 320 are electrically connected to the drain of the enable transistor M3. The source of the enable transistor M3 is connected to a high level VDD, and the gate of the enable transistor M3 can be connected to an enable signal. The enable transistor M3 is a PMOS transistor. The other end of the first inverter unit 310 and the second inverter unit 320 are electrically connected to the source of the enable transistor M8. The drain of the enable transistor M8 is grounded, and the gate of the enable transistor M8 can be connected to an enable signal. When the gate of the enable transistor M3 is connected to a low level and the gate of the enable transistor M8 is connected to a high level, the enable transistors M3 and M8 can be turned on during the comparator adaptation stage and the data readout stage, so that the latch comparator path is turned on and the latch comparator starts running. The first inverter unit 310 and the second inverter unit 320.

[0058] Continue to refer to Figure 3 During the comparator adaptation stage, a low-level enable signal is provided to the gate of enable transistor M3, and a high-level enable signal is provided to the gate of enable transistor M8. The latch comparator is turned on, connecting the input and output terminals of the inverter unit to charge the second charge / discharge module C2. This allows the trip voltages of the two inverter units to be stored at both ends of the second charge / discharge module C2. Specifically, the input terminal In1 of the first inverter unit 310 is connected to the output terminal OU1, and the input terminal In2 of the second inverter unit 320 is connected to the output terminal OU2. This allows the second charge / discharge module C2 to be charged, so that the trip voltage VT1 of the first inverter unit 310 is stored at one end of the second charge / discharge module C2, and the trip voltage VT2 of the second inverter unit 320 is stored at the other end of the second charge / discharge module C2.

[0059] Continue to refer to Figure 3, in the pre-charge stage, control switches S2 and S23-4-5 are closed, which can connect the input ends of the two inverter units to the ground point, so that the output ends of the two inverter units are pre-charged to 0, and the output end OU1 of the first inverter unit 310 is connected to the input end In2 of the second inverter unit 320. At this time, the input voltage of the second inverter unit 320 is pulled to the difference between the trip voltages of the two inverter units (VT1 - VT2). At this time, the trip voltage of the first inverter unit 310 and the trip voltage of the second inverter unit 320 are balanced, that is, the performance parameters of the two inverter units can be made to match.

[0060] The current-mode sense amplifier circuit provided by the embodiment of the present application is directed to the large volatility caused by random factors in the process and the readout efficiency of the sense amplifier being more easily affected by device mismatch caused by random factors in the process as the operating voltage decreases and the process size decreases in the prior art. The current-mode sense amplifier circuit provided by the embodiment of the present application realizes the balancing of device process mismatch in the two inverter units by setting a second charge-discharge module and controlling the opening or closing of the corresponding switches between the two inverter units, so that the performance parameters of the two balanced inverter units tend to be consistent, enabling the two symmetrically arranged inverter units to better realize the function of the latch and improving the problem of process mismatch of the existing latch.

[0061] Continue to refer to Figure 3 , in the data readout stage, control to provide an enable signal with a low level to the gate of the enable transistor M3 and an enable signal with a high level to the gate of the enable transistor M8. The latch comparator connects the output end OU1 of the first inverter unit 310 to the input end In2 of the second inverter unit 320. The input end In1 of the first inverter unit 310 is connected to the reference current Iref of the resistive random access memory cell circuit, and the input end In2 of the second inverter unit 320 is connected to the cell current Icell of the resistive random access memory cell circuit. When Icell > Iref, the potential of the first potential point A is pulled to the high level VDD, the potential of the second potential point B is pulled to 0, and a storage signal is output to the resistive random access memory cell circuit. At this time, the output storage signal is "1". When Icell < Iref, the potential of the first end 111 of the first charge-discharge module (capacitor C1) is pulled to the low level 0, the potential of the second end 112 of the first charge-discharge module (capacitor C1) is pulled to the high level VDD, and a storage signal is output to the resistive random access memory cell circuit. At this time, the output storage signal is "0".

[0062] When the process mismatch between M1 and M2 exceeds 225mV (the trip voltage difference between M1 and M2 is 225mV), the swing between the first potential point A and the second potential point B is even lower, sometimes only tens of millivolts. At this point, the process mismatch between MOSFETs M4 and M5, and between MOSFETs M6 and M7 in the latch comparator will cause the current-mode sensitive amplifier circuit to fail to read the data (data readout failure). Therefore, it is essential to introduce a cross-coupling capacitor C2 into the latch comparator to eliminate these process mismatches, thereby further improving the accuracy of the current-mode sensitive amplifier circuit. The introduction of the coupling capacitor C2 allows the latch comparator to tolerate voltage mismatches exceeding 60% of the threshold voltage.

[0063] The current-type sensitive amplifier circuit provided in this application embodiment, by setting a first charging / discharging module 110 and a path switching module 120, controls the path switching module 120 to charge and discharge the first charging / discharging module 110, thereby forming a current sampling stage and a current amplification stage. This allows the current difference (Icell-Iref) between the original first potential point A and the second potential point B to be amplified to 2 (Icell-Iref) through the current-type sensitive amplifier circuit. Finally, based on the voltages of the first potential point A and the second potential point B after amplification of the current difference, one is pulled high and the other low, to achieve the judgment and output of the stored signal. This two-stage circuit (current sampling stage and current amplification stage) achieves rail-to-rail output of the current-type sensitive amplifier circuit, improving the driving capability of the current-type sensitive amplifier circuit and achieving double the readout sensing margin of the resistive random access memory, thus improving the sensitivity of the resistive random access memory. Furthermore, since the current difference between the first potential point A and the second potential point B is amplified to 2 (Icell-Iref), which is twice the current difference in existing current sampling circuits, the increase in current difference reduces the impact of process mismatch between the symmetrically arranged first pre-charge current module 130 and second pre-charge current module 140 on the current sampling circuit 100. In other words, the increase in current difference reduces the sensitivity of the current sampling circuit 100 to process mismatch between the first pre-charge current module 130 and second pre-charge current module 140, thus mitigating the impact of process mismatch within a certain range. By setting a second charge / discharge module (capacitor C2) between the two inverter units and controlling the opening and closing of the corresponding switch, the process mismatch in the two inverter units is balanced, making the performance parameters of the two inverter units more consistent after balancing. This allows the symmetrically arranged inverter units to better perform the latch function and improves the problem of process mismatch in existing latches.

[0064] Secondly, Figure 4This is a schematic flowchart illustrating a method for eliminating process mismatch in a current-mode sensitive amplifier circuit, as provided in an embodiment of this application. Figure 4 As shown in the figure, this application provides a method for eliminating process mismatch in a current-mode sensitive amplifier circuit, including:

[0065] S100: By controlling the path switching module, the first terminal of the first pre-charge current module and the first charge-discharge module are connected, the first terminal of the first charge-discharge module is connected to the reference current of the resistive random access memory (RRAM) cell circuit, the second terminal of the second pre-charge current module and the first charge-discharge module are connected, and the second terminal of the first charge-discharge module is connected to the cell current of the RRAM cell circuit, so that the first pre-charge current module charges the first terminal of the first charge-discharge module with pre-charge current, and the second pre-charge current module charges the second terminal of the first charge-discharge module with pre-charge current, thus forming a current sampling stage.

[0066] S200: By controlling the path switching module, the second terminal of the first pre-charge current module is connected to the second terminal of the first charge-discharge module, and the first terminal of the second pre-charge current module is connected to the first charge-discharge module, thus forming a current amplification stage.

[0067] In one possible implementation, prior to the formation of the current sampling phase, i.e., before step S100, the method further includes:

[0068] The input and output terminals of the inverter unit are connected to charge the second charge / discharge module, so that the trip voltages of the two inverter units are stored at both ends of the second charge / discharge module, forming the adapter comparator stage.

[0069] In one feasible implementation, after the adapter comparator stage is formed, the following is also included:

[0070] Connect the input terminals of the two inverter units to the ground point so that the output terminals of the two inverter units are precharged to 0. Then connect the output terminal of one inverter unit to the input terminal of the other inverter unit so that the performance parameters of the two inverter units are matched, forming a precharge stage.

[0071] After the current amplification stage is formed, that is, after step S200, the following is also included:

[0072] The output of one inverter unit is connected to the input of another inverter unit. The input of one inverter unit is connected to the first terminal of the first charge-discharge module, and the input of the other inverter unit is connected to the second terminal of the first charge-discharge module. This is so that when the unit current is greater than the reference current, the potential of the first terminal of the first charge-discharge module is pulled to a high level, and the potential of the second terminal of the first charge-discharge module is pulled to 0, thus outputting a storage signal to the resistive random access memory unit circuit and forming the data read-out stage.

[0073] Figure 5 This is a schematic timing diagram illustrating a method for eliminating process mismatch in a current-mode sensitive amplifier circuit provided in an embodiment of this application. Figure 5 As shown, the comparator adaptation stage P1, pre-charging stage P2, current sampling stage P3, current amplification stage P4, and data readout stage P5 are performed sequentially. When Icell > Iref, the voltage changes at the first potential point A and the second potential point B during the process from P1 to P2 to P3 to P4 to P5 are as follows. Figure 5 As shown.

[0074] Although preferred embodiments have been described in this specification, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this specification.

[0075] Obviously, those skilled in the art can make various modifications and variations to this specification without departing from its spirit and scope. Therefore, if such modifications and variations fall within the scope of the claims and their equivalents, this specification is also intended to include such modifications and variations.

Claims

1. A current-mode sensitive amplifier circuit, characterized in that, include: Current sampling circuit; The current sampling circuit includes a first charging and discharging module, a path switching module, a first pre-charge current module, and a second pre-charge current module. One end of the first pre-charge current module is used to connect to the reference current of the resistive switching memory unit circuit, and one end of the second pre-charge current module is used to connect to the unit current of the resistive switching memory unit circuit. The other ends of the first pre-charge current module and the second pre-charge current module are electrically connected and used to connect to a high level. The path switching module is used to connect the first terminal of the first pre-charge current module to the first terminal of the first charge-discharge module, and to connect the second terminal of the second pre-charge current module to the second terminal of the first charge-discharge module, so as to form a current sampling stage. The path switching module is also used to connect the second terminal of the first pre-charge current module to the first charge-discharge module, and to connect the second pre-charge current module to the first terminal of the first charge-discharge module, so as to form a current amplification stage. A latch comparator, the latch comparator comprising two inverter units; A switch is provided between the input and output terminals of the inverter unit. When the switch is closed, it is used to connect the input and output terminals of the inverter unit to form an adapter comparator stage. The latch comparator further includes a second charge / discharge module, one end of which is electrically connected to the input terminal of one of the inverter units, and the other end of which is electrically connected to the output terminal of another inverter unit.

2. The current-mode sensitive amplifier circuit according to claim 1, characterized in that, The first charging and discharging module includes a capacitor.

3. The current-mode sensitive amplifier circuit according to claim 1, characterized in that, Both the first pre-charge current module and the second pre-charge current module include a pre-charge MOS transistor; During the current sampling phase, the path switching module is used to control the reference current of the drain of the pre-charge MOS transistor of the first pre-charge current module connected to the resistive random access memory cell circuit, the cell current of the drain of the pre-charge MOS transistor of the second pre-charge current module connected to the resistive random access memory cell circuit, the source of the pre-charge MOS transistor of the first pre-charge current module and the source of the pre-charge MOS transistor of the second pre-charge current module being electrically connected and then connected to a high level, the gate of the pre-charge MOS transistor of the first pre-charge current module being electrically connected to the second terminal of the first charge-discharge module, and the gate of the pre-charge MOS transistor of the second pre-charge current module being electrically connected to the first terminal of the first charge-discharge module; During the current amplification stage, the path switching module is used to control the gate of the pre-charge MOS transistor of the first pre-charge current module to be electrically connected to the second terminal of the first charge-discharge module, and the gate of the pre-charge MOS transistor of the second pre-charge current module to be electrically connected to the first terminal of the first charge-discharge module.

4. The current-mode sensitive amplifier circuit according to claim 3, characterized in that, The path switching module includes multiple switches; A switch is provided between the drain of the precharge MOS transistor in the first precharge current module and the first terminal of the first charge and discharge module, and a switch is provided between the drain of the precharge MOS transistor in the second precharge current module and the second terminal of the first charge and discharge module. A switch is provided between the gate of the precharge MOS transistor of the first precharge current module and the first terminal of the first charge-discharge module, and a switch is provided between the gate of the precharge MOS transistor of the first precharge current module and the second terminal of the first charge-discharge module. A switch is provided between the gate of the precharge MOS transistor of the second precharge current module and the first terminal of the first charge-discharge module, and a switch is provided between the gate of the precharge MOS transistor of the second precharge current module and the second terminal of the first charge-discharge module.

5. The current-mode sensitive amplifier circuit according to claim 4, characterized in that, A switch is provided between the input terminal of the inverter unit and the ground point. When the switch is closed, it is used to ground the input terminal of the inverter unit to form a pre-charging phase. A switch is provided between the output terminal of one inverter unit and the input terminal of another inverter unit, the switch being closed during the pre-charging phase, the current sampling phase, the current amplification phase, and the data readout phase.

6. The current-mode sensitive amplifier circuit according to claim 5, characterized in that, The input terminal of one of the inverter units is used to connect the reference current of the resistive random access memory (RRAM) cell circuit during the current sampling phase and the current amplification phase, and the input terminal of the other inverter unit is used to connect the cell current of the RRAM cell circuit during the current sampling phase and the current amplification phase. The input terminal of one of the inverter units is also used to connect the reference current of the resistive random access memory (RRAM) cell circuit outside the current sampling stage and the current amplification stage, and the input terminal of the other inverter unit is also used to connect the cell current of the RRAM cell circuit outside the current sampling stage and the current amplification stage to form a data readout stage.

7. A method for eliminating process mismatch in a current-mode sensitive amplifier circuit, characterized in that, The method, applied to a current-mode sensitive amplifier circuit as described in any one of claims 1 to 6, comprises: The input and output terminals of the inverter unit are connected to charge the second charge-discharge module, so that the trip voltages of the two inverter units are stored at both ends of the second charge-discharge module, forming the adapter comparator stage. By controlling the path switching module, the first terminal of the first pre-charge current module is connected to the first terminal of the first charge-discharge module, the first terminal of the first charge-discharge module is connected to the reference current of the resistive random access memory (RRAM) cell circuit, the second terminal of the second pre-charge current module is connected to the second terminal of the first charge-discharge module, and the second terminal of the first charge-discharge module is connected to the cell current of the RRAM cell circuit, so that the first pre-charge current module charges the first terminal of the first charge-discharge module with pre-charge current, and the second pre-charge current module charges the second terminal of the first charge-discharge module with pre-charge current, thus forming a current sampling stage; By controlling the path switching module, the second terminal of the first pre-charge current module is connected to the second terminal of the first charge-discharge module, and the first terminal of the second pre-charge current module is connected to the first terminal of the first charge-discharge module, thus forming a current amplification stage.

8. The method for eliminating process mismatch in the current-mode sensitive amplifier circuit according to claim 7, characterized in that, After the adapter comparator stage is formed, the following is also included: The input terminals of the two inverter units are connected to the ground point so that the output terminals of the two inverter units are precharged to 0. The output terminal of one inverter unit is connected to the input terminal of the other inverter unit so that the performance parameters of the two inverter units are matched to form a precharge stage. After the current amplification stage is formed, the following is also included: The output terminal of one inverter unit is connected to the input terminal of another inverter unit. The input terminal of one inverter unit is connected to the first terminal of the first charge-discharge module, and the input terminal of the other inverter unit is connected to the second terminal of the first charge-discharge module. This is so that when the unit current is greater than the reference current, the potential of the first terminal of the first charge-discharge module is pulled to a high level, and the potential of the second terminal of the first charge-discharge module is pulled to 0, thus outputting a storage signal to the resistive random access memory unit circuit and forming a data read-out stage.

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