Semiconductor structure and method of manufacturing the same

Abstract

The application relates to a semiconductor structure and a preparation method thereof, which comprises the following steps: providing a substrate, and forming a first stack structure on the substrate, wherein the first stack structure comprises a plurality of alternately formed doped layers and sacrificial layers; etching the first stack structure to form a word line hole penetrating to the substrate; removing the sacrificial layers through the word line hole, and forming a metal material layer between adjacent doped layers; performing a heat treatment to make the doped layers and the metal material layer react and transform into a metalloid film layer; filling a first isolation layer between adjacent metalloid film layers; and forming a transistor structure based on the word line hole. Since the metalloid film layer formed based on the preparation method of the semiconductor structure of the application has good compactness and conductivity, can bear a larger driving current, and thus the transistor structure and the process thereof are more optimized.

Description

Technical Field

[0001] This application relates to the field of semiconductor device manufacturing technology, and in particular to a semiconductor structure and its preparation method. Background Technology

[0002] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and number of devices contained in a single chip are increasing, which means that any slight difference in the manufacturing process can affect the performance of the devices.

[0003] To minimize product costs, the goal is to fabricate as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet current product demands. Summary of the Invention

[0004] Therefore, it is necessary to provide a semiconductor structure and its fabrication method.

[0005] To achieve the above objectives, this application provides a method for fabricating a semiconductor structure, comprising:

[0006] A substrate is provided, and a first stacked structure is formed on the substrate, the first stacked structure comprising a plurality of alternately formed doped layers and sacrificial layers;

[0007] The first stacked structure is etched to form word line holes that extend through the substrate;

[0008] The sacrificial layer is removed through the word line hole, and a metal material layer is formed between adjacent doped layers;

[0009] The doped layer is heat-treated to react with the metal material layer and transform into a metallization film layer.

[0010] A first insulating layer is filled between adjacent metallide film layers;

[0011] A transistor structure is formed based on the word line hole.

[0012] The aforementioned semiconductor structure fabrication method transforms the doped layer into a metallide film through heat treatment and forms a first isolation layer between the metallide films, thereby enabling the fabrication of a transistor structure based on the stacked structure formed by the metallide films and the first isolation layer. Since the metallide films formed by the semiconductor structure fabrication method of this application have good density and conductivity, they can carry a large driving current, thus optimizing the transistor structure and its fabrication process.

[0013] In one embodiment, the material of the doped layer has the same lattice as the material of the sacrificial layer.

[0014] In this embodiment, the first stacked structure is formed by alternating doped layers and sacrificial layers. The doped layers and sacrificial layers have the same crystal lattice and are quite similar, resulting in low interlayer stress and enabling a high-density semiconductor structure. Simultaneously, the similarity in the materials of the doped and sacrificial layers enhances etching feasibility, making the sidewalls of the formed word lines less prone to bending and deformation, and improving their verticality.

[0015] In one embodiment, the doped layer comprises doped polysilicon, and the metallization film comprises metal silicide.

[0016] In one embodiment, the sacrificial layer is removed through the word line via, and a metal material layer is formed between adjacent doped layers, including:

[0017] The sacrificial layer is removed through the word line hole;

[0018] The metal material layer is filled in the region between adjacent doped layers;

[0019] After heat treatment to allow the doped layer to react with the metal material layer to form a metallization film, the process includes:

[0020] Remove the remaining layer of the metal material.

[0021] In one embodiment, a first insulating layer is filled between adjacent metallide film layers, including:

[0022] A first isolation layer with an internal air gap is formed between adjacent metallide film layers.

[0023] In one embodiment, the first isolation layer includes a first isolation sublayer, a second isolation sublayer, and a third isolation sublayer stacked together.

[0024] A first insulating layer is filled between adjacent metallide film layers, comprising:

[0025] A first isolation sublayer, a second isolation sublayer, and a third isolation sublayer are formed between adjacent metallide film layers, wherein the third isolation sublayer is located between the first isolation sublayer and the second isolation sublayer.

[0026] In one embodiment, after forming the transistor structure based on the word line via, the process includes:

[0027] Remove the third isolation sublayer to form an air gap.

[0028] In one embodiment, a transistor structure is formed based on the word line via, including:

[0029] The metallization film layers are etched through the word line holes to form side holes surrounding the word line holes, and the side holes separate the metallization film layers in the same layer.

[0030] A channel layer material and a gate dielectric material layer are sequentially formed on the surface of the structure obtained after the side hole is formed;

[0031] Remove the channel layer material and the gate dielectric material layer located outside the side hole to form a channel layer and a gate dielectric layer, and expose the first isolation layer;

[0032] The third isolation sublayer of the first isolation layer is removed through the word line hole to form an air gap;

[0033] A character line is formed within the character line hole.

[0034] In one embodiment, before removing the channel layer material and the gate dielectric material layer located outside the side via, the process includes:

[0035] A conductive protective material layer is formed covering the surface of the gate dielectric material layer;

[0036] Remove the conductive protective material layer located outside the side hole to form a conductive protective layer inside the side hole.

[0037] In one embodiment, a substrate is provided, and a first stacked structure is formed on the substrate, including:

[0038] Provide a base;

[0039] By using an epitaxial process, doped material layers and sacrificial material layers are alternately stacked on the substrate;

[0040] The doped material layer and the sacrificial material layer are etched to form the first stacked structure. The first stacked structure includes a first main body and a first branch. The first main body extends along a first direction, and the first branch extends along a second direction. The second direction intersects with the first direction. A plurality of the first branches are arranged at intervals along the first direction and disposed on both sides of the first main body and the second direction.

[0041] Etching the first stacked structure to form a word line hole extending through the substrate includes:

[0042] The end of the first branch closest to the first main branch is etched to form the letter hole.

[0043] This application also provides a semiconductor structure, including:

[0044] Base;

[0045] The second stacked structure, located on the substrate, includes multiple alternating metallide films and a first isolation layer, wherein the metallide films are formed by the reaction and transformation of a doped layer and a metal material layer;

[0046] At least one transistor structure, including a word line hole extending through the substrate.

[0047] In one embodiment, the metallization film layer comprises a metal silicide.

[0048] In one embodiment, the first isolation layer has an air gap inside.

[0049] In one embodiment, the first isolation layer includes a first isolation sublayer and a second isolation sublayer, the first isolation sublayer being located on the lower surface of the upper metallization film layer, and the second isolation sublayer being located on the upper surface of the lower metallization film layer, with an air gap between the first isolation sublayer and the second isolation sublayer.

[0050] In one embodiment, the second stacking structure further includes:

[0051] Side holes, which connect to and surround the letter hole, and are disposed in the same layer as the metallide film layer;

[0052] The transistor structure includes:

[0053] The channel layer is located within the side hole;

[0054] A gate dielectric layer is located within the side hole and on the surface of the channel layer opposite to the side hole;

[0055] A conductive protective layer is located inside the side hole and on the side of the gate dielectric layer opposite to the channel layer;

[0056] The character line is located inside the character line hole.

[0057] In one embodiment, the second stacking structure includes a second main branch and a second branch. The second main branch extends along a first direction, and the second branch extends along a second direction. The second direction intersects the first direction. A plurality of second branches are arranged at intervals along the first direction on both sides of the second main branch along the second direction. The word line is located at one end of the second branch near the second main branch. Attached Figure Description

[0058] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0059] Figure 1 This is a flowchart of a method for fabricating a semiconductor structure provided in one embodiment;

[0060] Figure 2 This is a top view schematic diagram of a semiconductor structure provided in one embodiment;

[0061] Figures 3 to 18 This is a schematic diagram of the cross-sectional structure corresponding to the aa, bb, cc, and dd directions of the structure obtained in different steps of the semiconductor structure fabrication method provided in one embodiment;

[0062] Figure 19 This is a schematic diagram of the cross-sectional structure corresponding to the aa direction in a method for fabricating a semiconductor structure provided in one embodiment;

[0063] Figures 20 to 30 This is a three-dimensional structural diagram of the structure obtained in different steps of the semiconductor structure fabrication method provided in one embodiment.

[0064] Explanation of reference numerals in the figures: 100 - Doped layer, 200 - Sacrificial layer, 310 - First mask layer, 320 - Second mask layer, 330 - Third mask layer, 340 - First patterned photoresist, 350 - Second patterned photoresist, 400 - Metal material layer, 500 - Metallization film layer, 600 - First isolation layer, 610 - First isolation sublayer, 620 - Second isolation sublayer, 630 - Third isolation sublayer, 71 0 - Word line via, 720 - Side via, 810 - Channel layer, 811 - Channel layer material, 820 - Gate dielectric layer, 821 - Gate dielectric material layer, 830 - Conductive protective layer, 831 - Conductive protective material layer, 840 - Word line, 910 - Memory cell, 920 - Capacitor structure, 930 - Bit line, 940 - First main trunk, 950 - First branch, 960 - Second main trunk, 970 - Second branch. Detailed Implementation

[0065] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0066] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0067] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this application, the first element, part, region, layer, doping type, or portion discussed below may be referred to as a second element, part, region, layer, or portion.

[0068] Spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, an element or feature described as “below,” “below,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0069] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising,” “including,” or “having,” etc., specify the presence of the stated feature, whole, step, operation, component, part, or combination thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof.

[0070] In one embodiment, see Figure 1A method for fabricating a semiconductor structure is provided, comprising the following steps:

[0071] Step S100: Provide a substrate and form a first stacked structure on the substrate. The first stacked structure includes a plurality of alternately formed doped layers 100 and sacrificial layers 200.

[0072] Step S200: Etch the first stacked structure to form a word line hole 710 that extends through to the substrate;

[0073] In step S300, the sacrificial layer 200 is removed through the word line hole 710, and a metal material layer 400 is formed between adjacent doped layers 100.

[0074] In step S400, heat treatment is performed to allow the doped layer 100 to react with the metal material layer 400 and be transformed into a metallide film layer 500.

[0075] Step S500: Fill the space between adjacent metallide film layers 500 with a first isolation layer 600;

[0076] Step S600: Based on the word line hole 710, a transistor structure is formed.

[0077] In step S100, the substrate may consist only of a substrate, or it may include a substrate and a film layer formed on the substrate. The substrate may be, for example, a silicon (Si) substrate, a silicon-germanium (SiGe) substrate, a silicon-germanium-carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V or II / VI semiconductor substrates. The substrate can provide support for the entire semiconductor structure.

[0078] A first stacked structure is formed on a substrate. Specifically, the first stacked structure can be formed directly on the substrate or on a film layer on the substrate.

[0079] The first stacked structure may include multiple alternately formed doped layers 100 and sacrificial layers 200. The number of sacrificial layers 200 and doped layers 100 is not limited here; they can be selected according to actual needs, for example, as shown below. Figure 5 As shown, the first stacked structure can be formed by alternating three sacrificial layers 200 and three doped layers 100. At the same time, the thickness of the sacrificial layer 200 and the doped layer 100 is not limited here, and they can be deposited as needed. For example, a doped layer 100 can be deposited with a thickness of 50 nm, and a sacrificial layer 200 can be deposited with a thickness of 50 nm.

[0080] In step S200, please refer to Figures 6 to 9 as well as Figures 22 to 24The first stacked structure is etched to form word line holes 710 within the first stacked structure, extending through the first stacked structure to the substrate surface. As an example, a first mask layer 310 and a first photoresist layer can be sequentially formed on the first stacked structure first; then, the first photoresist layer is patterned to form a first patterned photoresist 340. The first patterned photoresist 340 has openings that define the position and shape of the word line holes 710. The pattern of the first patterned photoresist 340 is then transferred to the first mask layer 310 to form a first patterned mask layer. Finally, the first stacked structure is etched based on the first patterned mask layer to form the word line holes 710.

[0081] In step S300, please refer to Figure 10 , Figure 11 , Figure 25 as well as Figure 26 The sacrificial layer 200 in the first stacked structure is removed through the word line hole 710, and a metal material layer 400 is formed between adjacent doped layers 100.

[0082] As an example, an atomic layer deposition (ALD) process can be used to form a metal material layer 400, which can be made of cobalt (Co) metal material.

[0083] Furthermore, after the metal material layer 400 is formed, it can be etched to reform the word line hole 710. Of course, it can also be left unetched, and there is no restriction on this.

[0084] In step S400, please refer to Figure 12 as well as Figure 27 Through heat treatment, the doped layer 100 reacts with the metal material layer 400, thereby transforming the doped layer 100 into a metallide film layer 500. As an example, the metallide film layer 500 includes a metal silicide. Specifically, when the metal material layer 400 is made of cobalt (Co) metal, the metal silicide is silicon cobaltide (SiCo).

[0085] In step S500, please refer to Figure 13 , Figure 29 as well as Figure 30 A first isolation layer 600 is filled between adjacent metallization film layers 500.

[0086] A first isolation material layer can be formed first between adjacent metallization film layers 500 and within word line holes 710. Then, the first isolation material layer located within word line holes 710 can be etched, and the remaining first isolation material layer forms a first isolation layer 600.

[0087] In step S600, a transistor structure is formed based on the word line hole 710.

[0088] The transistor structure may include a source, a drain, and a gate. The source and drain may be formed based on a metallization film layer 500, and the gate may be formed in a word line hole 710.

[0089] In this embodiment, the doped layer 100 is transformed into a metallide film layer 500 through heat treatment, and a first isolation layer 600 is formed between the metallide film layers 500. This allows for the fabrication of a transistor structure based on the stacked structure formed by the metallide film layers 500 and the first isolation layer 600. Since the metallide film layer 500 formed by the semiconductor structure fabrication method of this application has good density and conductivity, it can carry a large driving current, thus optimizing the transistor structure and its fabrication process.

[0090] In one embodiment, the material of the doped layer 100 and the material of the sacrificial layer 200 may have the same crystal lattice.

[0091] As an example, the material of the doped layer 100 may include, but is not limited to, silicon (Si). Specifically, heavily doped polycrystalline silicon may be used as the doped layer 100 to improve the conductivity of the subsequently formed device. The material of the sacrificial layer 200 may be, for example, silicon-germanium (SiGe).

[0092] In this embodiment, the first stacked structure is formed by alternating doped layers 100 and sacrificial layers 200. The doped layers 100 and sacrificial layers 200 have the same crystal lattice and are relatively similar, resulting in low interlayer stress and enabling a high-density semiconductor structure. Simultaneously, the similar materials of the doped layers 100 and sacrificial layers 200 provide greater etching feasibility, thus making the sidewalls of the formed word line vias 710 less prone to bending and deformation, and improving their verticality.

[0093] In one embodiment, step S300 includes:

[0094] Step S310: Remove the sacrificial layer 200 through the word line hole 710;

[0095] Step S320: Fill the region between adjacent doped layers 100 with metal material layer 400;

[0096] Step S400 includes:

[0097] Step S410: Remove the remaining metal material layer 400.

[0098] In step S310, please refer to Figure 10 as well as Figure 25As an example, the sacrificial layer 200 can be removed by wet etching. The etching solution is injected through the word line hole 710 to etch the sacrificial layer 200 laterally. Specifically, the etching solution can be a mixed solution of hydrofluoric acid (HF), hydrogen peroxide (H2O2), and acetic acid (CH3COOH).

[0099] In step S320, please refer to Figure 11 as well as Figure 26 The region between adjacent doped layers 100 is filled with a metal material layer 400.

[0100] As an example, an atomic layer deposition (ALD) process can be used to form a metal material layer 400 between adjacent doped layers 100 and within word line vias 710. Then, the metal material layer 400 within the word line vias 710 is etched away, leaving the metal material layer 400 located between adjacent doped layers 100.

[0101] The region between adjacent doped layers 100 is filled with a metal material layer 400 to ensure that the doped layer 100 is fully formed.

[0102] The metal material layer 400 may, but is not limited to, use cobalt (Co) metal material.

[0103] In step S410, please refer to Figure 12 as well as Figure 28 After heat treatment, the remaining metal material layer 400 is removed. Since the metal material layer 400 fills the area between adjacent doped layers 100 and is relatively thick, it may not be able to completely react with the doped layers 100, meaning that some metal material layer 400 may remain after heat treatment. Therefore, the excess metal material layer 400 needs to be removed. As an example, wet etching can be used to remove the excess metal material layer 400, and the etching solution can be, but is not limited to, ammonia monohydrate (NH3H2O).

[0104] In this embodiment, the area between adjacent doped layers 100 is filled with a metal material layer 400. The metal material layer 400 is relatively thick. When the thicker metal material layer 400 reacts with the doped layer 100 after heat treatment, the reaction between the two can be more complete, thereby making it easier to ensure that the doped layer 100 completely forms a metallide film layer 500 with better conductivity.

[0105] In one embodiment, step S500 includes:

[0106] Step S510: A first isolation layer 600 with an internal air gap is formed between adjacent metallization film layers 500.

[0107] As an example, the first isolation layer 600 can be formed using atomic layer deposition (ALD). Since ALD easily deposits films at corners, air gaps are easily formed within the first isolation dielectric layer formed by ALD. Furthermore, since air has a dielectric constant of 1, the formation of air gaps helps reduce parasitic capacitance between adjacent metallide film layers 500.

[0108] Of course, other feasible processes can also be used to form the first isolation layer 600 with internal air gaps. The process for forming the first isolation layer 600 is not limited here.

[0109] In one embodiment, see Figure 19 The first isolation layer 600 includes a first isolation sublayer 610, a second isolation sublayer 620, and a third isolation sublayer 630 stacked together. Step S500 includes:

[0110] In step S520, a first isolation sublayer 610, a second isolation sublayer 620, and a third isolation sublayer 630 are formed between adjacent metallide film layers 500, with the third isolation sublayer 630 located between the first isolation sublayer 610 and the second isolation sublayer 620.

[0111] When forming the first isolation layer 600, a first isolation material layer can first be deposited on the surface of the structure obtained after forming the metallization film layer 500. Then, the first isolation material layer is etched to remove the first isolation material layer outside the region between adjacent metallization film layers 500, and the first isolation material layer remaining between adjacent metallization film layers 500 forms a first isolation sublayer 610 and a second isolation sublayer 620, respectively. As an example, the first isolation sublayer 610 can be located on the lower surface of the upper metallization film layer 500, and the second isolation sublayer 620 can be located on the upper surface of the lower metallization film layer 500.

[0112] Subsequently, a third isolation material sublayer is deposited, which fills the area between the first isolation sublayer 610 and the second isolation sublayer 620. Then, the third isolation material sublayer outside the area between the first isolation sublayer 610 and the second isolation sublayer 620 is removed, leaving the third isolation material sublayer between the first isolation sublayer 610 and the second isolation sublayer 620 to form the third isolation sublayer 630.

[0113] As an example, the first isolation sublayer 610 and the second isolation sublayer 620 can both be formed of oxides, and the third isolation sublayer 630 can be formed of nitrides.

[0114] In one embodiment, after step S600, the following is included:

[0115] Step S700: Remove the third isolation sublayer 630 to form an air gap.

[0116] After forming a transistor structure based on word line holes 710, the third isolation sublayer 630 can be removed to form an air gap. The dielectric constant of air is 1, and the air gap helps to reduce the parasitic capacitance between adjacent metallization film layers 500.

[0117] In this embodiment, after the transistor structure is formed, the third isolation sublayer 630 is removed to prevent related film layers of the transistor structure (such as the channel layer 810, gate dielectric layer 820, conductive protective layer 830, and word line 840, especially word line 840) from entering the removal area of ​​the third isolation sublayer 630 during the formation of the transistor structure, thereby ensuring the reliability of the transistor structure.

[0118] In one embodiment, step S600 includes:

[0119] In step S610, each metallization film layer 500 is etched through the word line hole 710 to form a side hole 720 surrounding the word line hole 710. The side hole 720 separates the metallization film layers 500 of the same layer.

[0120] In step S620, a channel layer material 811 and a gate dielectric material layer 821 are sequentially formed on the surface of the structure obtained after forming the side hole 720.

[0121] Step S650: Remove the channel layer material 811 and the gate dielectric material layer 821 located outside the side hole 720 to form the channel layer 810 and the gate dielectric layer 820, and expose the first isolation layer 600.

[0122] In step S660, the third isolation sublayer 630 of the first isolation layer 600 is removed through the word line hole 710 to form an air gap;

[0123] In step S670, a character line 840 is formed within the character line hole 710.

[0124] In step S610, please refer to Figure 14 The metallization film layers 500 are etched through the word line hole 710 to form side holes 720. The side holes 720 surround the word line hole 710 and separate the metallization film layers 500 of the same layer.

[0125] As an example, a wet etching process can be used to laterally hollow out the metallization film 500 to form a side hole 720. The radius of the side hole 720 is 20 nm to 25 nm larger than the radius of the word line hole 710. The side hole 720 separates the metallization film 500 in the same layer, so that a part of the metallization film 500 serves as the source of the transistor structure and the other part serves as the drain of the transistor structure.

[0126] In step S620, please refer to Figure 15 After the side hole 720 is formed, a channel layer material 811 and a gate dielectric material layer 821 are sequentially formed on the surface of the structure. The channel layer material 811 covers the surface of the side hole 720, the surface of the word line hole 710, and the upper surface of the second stacked layer. The gate dielectric layer 820 is formed on the surface of the channel layer material 811.

[0127] As an example, the channel layer material 811 can be formed by deposition, and can be deposited to a thickness of 6 nm. It can be made of indium gallium zinc oxide (IGZO). The gate dielectric layer 820 can also be formed by deposition, and can be formed of a material with a high dielectric constant (e.g., alumina), with a deposition thickness of 10 nm.

[0128] In step S650, please refer to Figure 16 as well as Figure 17 The channel layer material 811 and gate dielectric material layer 821 located outside the side hole 720 are removed to form the channel layer 810 and gate dielectric layer 820, exposing the first isolation layer 600. The channel layer material 811 and gate dielectric material layer 821 on the surface of the word line hole 710 and the upper surface of the second stacked layer are removed, so that the channel layer 810 and gate dielectric layer 820 are formed within the side hole 720. At this time, the first isolation layer 600 is exposed, effectively reducing parasitic MOS transistor effects. The channel layer 810 serves as the channel of the transistor structure, providing a conductive channel for the source and drain of the transistor structure.

[0129] In step S660, since the first isolation layer 600 is exposed, the third isolation sub-layer 630 of the first isolation layer 600 can be removed through the word line hole 710, forming an air gap between the first isolation sub-layer 610 and the second isolation sub-layer 620.

[0130] In step S670, please refer to Figure 18 Word lines 840 are formed within word line vias 710. As an example, an atomic layer deposition (ALD) method can be used to deposit a 2nm to 5nm metal diffusion barrier layer; then, word line 840 material is deposited within word line vias 710 and side vias 720, filling word line vias 710; subsequently, chemical mechanical polishing (CMP) is performed to remove word line 840 material outside word line vias 710, forming the word lines 840. The diameter of the word lines 840 can be 25nm, and they can be fabricated using indium tin oxide (ITO) thin films.

[0131] In this embodiment, the third isolation sublayer 630 is removed before forming the transistor structure. Since the word line via 710 is not filled at this time, the removal of the third isolation sublayer 630 is more convenient and feasible.

[0132] In one embodiment, prior to step S650, the following is included:

[0133] Step S630: A conductive protective material layer 831 is formed covering the surface of the gate dielectric material layer 821;

[0134] Step S640: Remove the conductive protective material layer 831 located outside the side hole to form a conductive protective layer inside the side hole 720.

[0135] Please see Figure 15 Before removing the trench material other than the side hole 720 and the gate dielectric material layer 821, a conductive protective layer 830 may be applied to the surface of the gate dielectric material layer 821.

[0136] Specifically, please refer to Figure 16 First, a conductive protective material layer 831 is formed over the gate dielectric material layer 821. Then, the conductive protective material layer 831 located on the gate dielectric material layer 821 on the sidewall of the word line via 710 and on the upper surface of the second stacked layer is removed, leaving the conductive protective material layer 831 on the gate dielectric material layer 821 inside the side via 720, thereby forming a conductive protective layer 830. For example, the conductive protective layer 830 can be made of indium tin oxide (ITO) film with a thickness of 15 nm. At this point, the word line via 710 is not completely filled, leaving a space with a diameter of 25 nm.

[0137] In one embodiment, step S100 includes:

[0138] Step S110, providing a substrate;

[0139] Step S120: A semiconductor doped material layer and a sacrificial material layer are stacked on the substrate through an epitaxial process.

[0140] Step S130: Etch semiconductor doped material layer and sacrificial material layer to form a first stacked structure. The first stacked structure includes a first main stem 940 and a first branch 950. The first main stem 940 extends along a first direction, and the first branch 950 extends along a second direction. The second direction intersects the first direction. A plurality of first branches 950 are arranged at intervals along the first direction and disposed on both sides of the first main stem 940 along the second direction.

[0141] Step S200 includes:

[0142] Step S210: Etch the first branch 950 to form the word line hole 710.

[0143] In step S120, please refer to Figure 3 as well as Figure 20Through epitaxial growth processes, doped material layers and sacrificial material layers are alternately stacked on a substrate. As an example, a sacrificial material layer can be deposited on the substrate first, then a doped material layer can be deposited on the sacrificial material layer, and then another sacrificial material layer can be deposited on the doped material layer, and so on, to form multiple alternating sacrificial material layers and doped material layers.

[0144] In step S130, please refer to Figure 4 , Figure 5 as well as Figure 21 The doped material layer and the sacrificial material layer are etched to form the first stacked structure.

[0145] For example, please refer to Figure 4 In forming the first stacked structure, a second mask layer 320, a third mask layer 330, and a second photoresist layer can be sequentially formed on the uppermost doped material layer. Then, the second photoresist layer is patterned to form a second patterned photoresist 350. The second patterned photoresist 350 defines the structure of the first stacked structure. Next, the pattern of the second patterned photoresist 350 is transferred to the third mask layer 330 to form a third patterned mask layer. Then, based on the pattern of the third patterned mask layer, the second mask layer 320 is etched to form a second patterned mask layer. Finally, using the second patterned mask layer as a mask, the first stacked structure is etched to form.

[0146] The second mask layer 320 may include an oxide film layer and a nitride film layer, both of which can be formed by deposition. The oxide film layer can be deposited with a thickness of 50 nm, and the nitride film layer can be deposited with a thickness of 20 nm. Specifically, the oxide film layer can be made of silicon dioxide (SiO2), and the nitride film layer can be made of silicon nitride (SiN). The third mask layer 330 can be a carbon mask. In addition, a silicon oxynitride (SiON) film layer can also be formed between the third mask layer 330 and the second photoresist layer.

[0147] The first stacked structure includes a first main stem 940 and a first branch 950. The first main stem 940 extends along a first direction, and the first branch 950 extends along a second direction. The first direction and the second direction intersect. A plurality of first branches 950 are arranged at intervals along the first direction and are disposed on both sides of the first main stem 940 along the second direction.

[0148] In step S210, the word line hole 710 is located in the first branch 950. Since the two first branches 950 are symmetrically arranged based on the first main branch 940, the two word line holes 710 located on the two symmetrical first branches 950 are also symmetrical based on the first main branch 940.

[0149] After steps S100 to S500, the first stacked structure can be transformed into a second stacked structure comprising alternating metallide film layers 500 and first insulating layers 600. At this time, the first main branch 940 becomes the second main branch 960, and the first branch 950 becomes the second branch 970. (See also...) Figure 2 The metallization film 500 located on the second main branch 960 can form a bit line 930. Furthermore, a capacitor structure 920 can be formed on the side of the second branch 970 away from the second main branch 960. The capacitor structure 920 can use the metallization film 500 as its lower electrode. The capacitor structure 920 and the transistor structure can constitute a memory cell 910.

[0150] Bit line 930 and capacitor structure 920 are located on both sides of transistor structure in the second direction, and are connected to the source and drain of transistor structure respectively. The second main branch 960 is symmetrically provided with two second branches 970 along both sides of the second direction, so that the same bit line 930 can simultaneously supply power to the memory cells 910 on both sides.

[0151] It should be understood that, although Figure 1 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 1 At least some of the steps in the process may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least some of the steps or stages in other steps.

[0152] In one embodiment, please refer to... Figure 18 The invention also provides a semiconductor structure comprising: a substrate, a second stacked structure, and at least one transistor structure.

[0153] The substrate may consist only of the substrate itself, or it may include the substrate and the films formed on the substrate. The substrate may be, for example, a silicon (Si) substrate, a silicon-germanium (SiGe) substrate, a silicon-germanium-carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V or II / VI semiconductor substrates. The substrate can provide support for the entire semiconductor structure.

[0154] The second stacked structure is located on the substrate and includes multiple alternately arranged metallide film layers 500 and first isolation layers 600. The metallide film layers 500 are formed by the reaction of the doped layer 100 and the metal material layer 400. The number of metallide film layers 500 and first isolation layers 600 is not limited and can be selected according to actual needs, for example... Figure 30 As shown, the second stacked structure can be formed by alternating three metallide film layers 500 and three first isolation layers 600.

[0155] As an example, the metallization film 500 includes a metal silicide. Specifically, when the metal material layer 400 uses cobalt (Co) metal material, the metal silicide is silicon cobaltide (SiCo).

[0156] Furthermore, the first isolation layer 600 may have an air gap inside. Since the dielectric constant of air is 1, the formation of the air gap helps to reduce the parasitic capacitance between adjacent metallide film layers 500.

[0157] At least one transistor structure includes a word line via 710 extending through to the substrate. Specifically, the word line via 710 may extend through the second stacked structure to the substrate.

[0158] In one embodiment, the first isolation layer 600 includes a first isolation sublayer 610 and a second isolation sublayer 620.

[0159] The first isolation sublayer 610 is located on the lower surface of the upper metallization film layer 500, and the second isolation sublayer 620 is located on the upper surface of the lower metallization film layer 500. There is an air gap between the first isolation sublayer 610 and the second isolation sublayer 620.

[0160] As an example, the first isolation sublayer 610 and the second isolation sublayer 620 can be formed using oxides.

[0161] In this embodiment, an air gap exists between the first isolation sublayer 610 and the second isolation sublayer 620. Since the dielectric constant of air is 1, the formation of the air gap helps to reduce the parasitic capacitance between adjacent metallide film layers 500.

[0162] In one embodiment, the stacked structure further includes a side hole 720, and the transistor structure includes a channel layer 810, a gate dielectric layer 820, a conductive protective layer 830, and a word line 840.

[0163] The side hole 720 connects to and surrounds the word line hole 710 and is located between the adjacent first isolation layer 600 along with the metallization film layer 500.

[0164] The channel layer 810 is located within the side via 720. The channel layer 810 serves as the channel for the transistor structure, providing a conduction path between the source and drain of the transistor structure. As an example, the channel layer 810 can be made of indium gallium zinc oxide (IGZO).

[0165] The gate dielectric layer 820 is located within the side hole 720 and on the surface of the channel layer 810 opposite to the side hole 720. As an example, the gate dielectric layer 820 may be made of a material with a high dielectric constant (e.g., aluminum oxide).

[0166] A conductive protective layer 830 is located within the side hole 720 and on the side of the gate dielectric layer 820 opposite to the channel layer 810. As an example, the material of the conductive protective layer 830 includes, but is not limited to, indium tin oxide (ITO) thin film.

[0167] Word line 840 is located within word line hole 710. For example, the diameter of word line 840 can be 25 nm, and it can be made of indium tin oxide (ITO) thin film material.

[0168] In one embodiment, see Figure 30 The second stacked structure includes a second main stem 960 and a second branch 970.

[0169] The second main stem 960 extends along the first direction, and the second branch 970 extends along the second direction. The second direction intersects with the first direction. Multiple second branches 970 are arranged at intervals along the first direction on both sides of the second main stem 960 along the second direction. The character line 840 is located at the end of the second branch 970 near the second main stem 960.

[0170] Understandably, the number of letter hole 710 can be consistent with the number of second branch 970.

[0171] At this time, please refer to Figure 2 The metallization film 500 located on the second main branch 960 can form a bit line 930. Furthermore, a capacitor structure 920 can be formed on the side of the second branch 970 away from the second main branch 960. The capacitor structure 920 can use the metallization film 500 as its lower electrode. The capacitor structure 920 and the transistor structure can constitute a memory cell 910.

[0172] Bit line 930 and capacitor structure 920 are located on both sides of transistor structure in the second direction, and are connected to the source and drain of transistor structure respectively. The second main branch 960 is symmetrically provided with two second branches 970 along both sides of the second direction, so that the same bit line 930 can simultaneously supply power to the memory cells 910 on both sides.

[0173] In the description of this specification, the references to terms such as "some embodiments," "other embodiments," "ideal embodiments," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example that are included in at least one embodiment or example of this application. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0174] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0175] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided, and a first stacked structure is formed on the substrate, the first stacked structure comprising a plurality of alternately formed doped layers and sacrificial layers; The first stacked structure is etched to form word line holes that extend through the substrate; The sacrificial layer is removed through the word line hole, and a metal material layer is formed between adjacent doped layers; The doped layer is heat-treated to react with the metal material layer and transform into a metallization film layer. A first insulating layer is filled between adjacent metallide film layers; A transistor structure is formed based on the word line hole.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that, The material of the doped layer has the same crystal lattice as that of the sacrificial layer.

3. The method for preparing a semiconductor structure according to claim 1, characterized in that, The doped layer comprises doped polycrystalline silicon, and the metallization film comprises metal silicide.

4. The method for preparing a semiconductor structure according to claim 1, characterized in that, The sacrificial layer is removed through the word line via, and a metal material layer is formed between adjacent doped layers, including: The sacrificial layer is removed through the word line hole; The metal material layer is filled in the region between adjacent doped layers; After heat treatment to allow the doped layer to react with the metal material layer to form a metallization film, the process includes: Remove the remaining layer of the metal material.

5. The method for preparing a semiconductor structure according to claim 1, characterized in that, A first insulating layer is filled between adjacent metallide film layers, comprising: A first isolation layer with an internal air gap is formed between adjacent metallide film layers.

6. The method for preparing a semiconductor structure according to claim 1, characterized in that, The first isolation layer includes a first isolation sublayer, a second isolation sublayer, and a third isolation sublayer stacked together. A first insulating layer is filled between adjacent metallide film layers, comprising: A first isolation sublayer, a second isolation sublayer, and a third isolation sublayer are formed between adjacent metallide film layers, wherein the third isolation sublayer is located between the first isolation sublayer and the second isolation sublayer.

7. The method for preparing a semiconductor structure according to claim 6, characterized in that, After forming the transistor structure based on the word line hole, the following is included: Remove the third isolation sublayer to form an air gap.

8. The method for preparing a semiconductor structure according to claim 6, characterized in that, Based on the word line via, a transistor structure is formed, including: The metallization film layers are etched through the word line holes to form side holes surrounding the word line holes, and the side holes separate the metallization film layers in the same layer. A channel layer material and a gate dielectric material layer are sequentially formed on the surface of the structure obtained after the side hole is formed; Remove the channel layer material and the gate dielectric material layer located outside the side hole to form a channel layer and a gate dielectric layer, and expose the first isolation layer; The third isolation sublayer of the first isolation layer is removed through the word line hole to form an air gap; A character line is formed within the character line hole.

9. The method for preparing the semiconductor structure according to claim 8, characterized in that, Before removing the channel layer material and the gate dielectric material layer located outside the side vias, the process includes: A conductive protective material layer is formed covering the surface of the gate dielectric material layer; Remove the conductive protective material layer located outside the side hole to form a conductive protective layer inside the side hole.

10. The method for preparing a semiconductor structure according to claim 1, characterized in that, Providing a substrate, and forming a first stacked structure on the substrate, comprising: Provide a base; By using an epitaxial process, doped material layers and sacrificial material layers are alternately stacked on the substrate; The doped material layer and the sacrificial material layer are etched to form the first stacked structure. The first stacked structure includes a first main body and a first branch. The first main body extends along a first direction, and the first branch extends along a second direction. The second direction intersects the first direction. A plurality of the first branches are arranged at intervals along the first direction and disposed on both sides of the first main body along the second direction. Etching the first stacked structure to form a word line hole extending through the substrate includes: The end of the first branch closest to the first main branch is etched to form the letter hole.

11. A semiconductor structure, characterized in that, include: Base; The second stacked structure, located on the substrate, includes multiple alternating metallide films and a first isolation layer, wherein the metallide films are formed by the reaction and transformation of a doped layer and a metal material layer; At least one transistor structure, including a word line via extending through the substrate; The second stacking structure also includes: Side holes, which connect to and surround the letter hole, and are disposed in the same layer as the metallide film layer; The transistor structure includes: The channel layer is located within the side hole; A gate dielectric layer is located within the side hole and on the surface of the channel layer opposite to the side hole; A conductive protective layer is located inside the side hole and on the side of the gate dielectric layer opposite to the channel layer; The character line is located inside the character line hole.

12. The semiconductor structure according to claim 11, characterized in that, The metallization film includes metal silicides.

13. The semiconductor structure according to claim 11, characterized in that, The first isolation layer has an air gap inside.

14. The semiconductor structure according to claim 11, characterized in that, The first isolation layer includes a first isolation sublayer and a second isolation sublayer. The first isolation sublayer is located on the lower surface of the upper metallization film layer, and the second isolation sublayer is located on the upper surface of the lower metallization film layer. An air gap exists between the first isolation sublayer and the second isolation sublayer.

15. The semiconductor structure according to claim 11, characterized in that, The second stacking structure includes a second main branch and a second branch. The second main branch extends along a first direction, and the second branch extends along a second direction. The second direction intersects with the first direction. A plurality of second branches are arranged at intervals along the first direction on both sides of the second main branch along the second direction. The word line is located at one end of the second branch near the second main branch.

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