Semiconductor device and method of manufacturing the same
By forming vertically stacked semiconductor layers on a substrate and etching and filling contact holes, the problems of memory cell density and parasitic capacitance in the prior art are solved, realizing the fabrication of highly integrated memory cells and meeting the needs for larger capacity and smaller size of memory devices.
CN122248725APending Publication Date: 2026-06-19SK HYNIX INC
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SK HYNIX INC
- Filing Date
- 2025-09-18
- Publication Date
- 2026-06-19
AI Technical Summary
Technical Problem
Existing technologies are insufficient to effectively increase the storage cell density and reduce parasitic capacitance of three-dimensional storage devices, thus failing to meet the demands for larger capacity and smaller size of storage devices.
Method used
By forming vertically stacked semiconductor layers on a substrate and forming pads by etching and filling contact holes, combined with the replacement of dummy semiconductor layers and pads, high integration of memory cells can be achieved.
Benefits of technology
This increases the density of memory cells, reduces parasitic capacitance, and meets the needs for larger capacity and smaller size of memory devices.
✦ Generated by Eureka AI based on patent content.
Smart Images
Figure CN122248725A_ABST
Abstract
This application relates to semiconductor devices and methods for manufacturing the same. A semiconductor device including highly integrated memory cells and a method for manufacturing the same are provided. The method includes: forming a first vertical stack on a substrate, wherein first semiconductor layers are vertically stacked; etching the first semiconductor layers of the first vertical stack to form a first contact hole; forming a dummy semiconductor layer from the uppermost first semiconductor layer of the first vertical stack; forming a second semiconductor layer on the dummy semiconductor layer to form a second vertical stack; etching the second semiconductor layer of the second vertical stack to form a second contact hole; and replacing the first and second semiconductor layers with pads.
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