Semiconductor memory device and method of manufacturing the same

Abstract

Embodiments of this disclosure relate to a semiconductor memory device and a method of manufacturing the semiconductor memory device. The semiconductor memory device includes: a stacked structure including alternately stacked interlayer insulating layers and conductive patterns; and a channel structure configured to penetrate the stacked structure. Each of the channel structures includes: a doped semiconductor pattern disposed at the core of each channel structure, the doped semiconductor pattern at least partially overlapping at least one upper conductive pattern among the conductive patterns; a vertical channel layer including a first region and a second region, the first region being configured to surround the doped semiconductor pattern, and the second region being configured to extend below the first region; and a memory layer being configured to surround the vertical channel layer, wherein the thickness of the first region is greater than the thickness of the second region.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0189784, filed on December 18, 2024, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] The various embodiments disclosed herein generally relate to a semiconductor memory device and a method of manufacturing the same, and more specifically, to a three-dimensional semiconductor memory device and a method of manufacturing the same. Background Technology

[0004] Semiconductor memory devices store data under the control of host devices such as computers and smartphones. Semiconductor memory devices can be classified into volatile memory devices and non-volatile memory devices.

[0005] Volatile memory devices store data only while power is supplied, and the stored data is lost when the power supply is cut off. Volatile memory devices include static random access memory (SRAM), dynamic random access memory (DRAM), etc.

[0006] Non-volatile memory devices are memory devices whose data is not lost even when power is cut off, such as read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), and flash memory.

[0007] Semiconductor memory devices include memory cells capable of storing data. Three-dimensional semiconductor memory devices include memory cells arranged in a three-dimensional manner, thereby reducing the area occupied by the memory cells per unit area of ​​substrate.

[0008] To improve the integration density of three-dimensional semiconductor memory devices, the number of stacked memory cells can be increased. However, as the number of stacked memory cells increases, the operational reliability of the three-dimensional semiconductor memory device may decrease. Summary of the Invention

[0009] The embodiments of this disclosure are intended to provide a semiconductor memory device and a method for manufacturing the same, which can improve operational reliability.

[0010] According to embodiments of this disclosure, a semiconductor memory device may include: a stacked structure including alternately stacked interlayer insulating layers and conductive patterns; and a channel structure configured to penetrate the stacked structure. Each of the channel structures includes: a doped semiconductor pattern disposed in the core of each channel structure, the doped semiconductor pattern at least partially overlapping at least one upper conductive pattern among the conductive patterns; a vertical channel layer including a first region and a second region, the first region being configured to surround a sidewall of the doped semiconductor pattern, and the second region being configured to extend below the first region; and a memory layer being configured to surround the vertical channel layer, wherein the thickness of the first region is greater than the thickness of the second region.

[0011] According to embodiments of this disclosure, a semiconductor memory device may include: a stacked structure including alternately stacked interlayer insulating layers and conductive patterns; and a channel structure penetrating the stacked structure. Each of the channel structures includes: a core insulating layer disposed at the core of each channel structure and extending in a vertical direction; a doped semiconductor pattern disposed on the core insulating layer and at least partially overlapping at least one upper conductive pattern of the conductive patterns; a vertical channel layer configured to extend in a vertical direction around the core insulating layer and the doped semiconductor pattern; and a memory layer configured to extend in a vertical direction around the vertical channel layer, wherein the vertical channel layer surrounding the doped semiconductor pattern includes a first channel layer and a second channel layer.

[0012] According to embodiments of the present disclosure, a method of manufacturing a semiconductor memory device may include: forming a stacked structure comprising alternating stacked interlayer insulating layers and sacrificial layers; forming a channel via through the stacked structure; forming a memory layer extending along the sidewall of the channel via; forming a first channel layer extending on the surface of the memory layer; forming a core insulating layer on the surface of the first channel layer to fill the channel via; etching back the core insulating layer to expose the first channel layer on top of the channel via; forming a second channel layer on the exposed first channel layer; and forming a doped semiconductor pattern to fill the channel via. Attached Figure Description

[0013] Figure 1 This is a block diagram illustrating a semiconductor memory device according to an embodiment of the present disclosure;

[0014] Figure 2 This is a circuit diagram illustrating a memory block according to an embodiment of the present disclosure;

[0015] Figure 3A and Figure 3B This is a perspective view schematically illustrating a semiconductor memory device according to an embodiment of the present disclosure;

[0016] Figure 4This is a perspective view illustrating the gate stack of a semiconductor memory device according to an embodiment of the present disclosure;

[0017] Figure 5 According to embodiments of this disclosure Figure 4 An enlarged cross-sectional view of region A shown in the figure;

[0018] Figure 6 This is a cross-sectional view showing the source layer and channel structure according to an embodiment of the present disclosure;

[0019] Figure 7 This is a cross-sectional view showing the source layer and channel structure according to an embodiment of the present disclosure;

[0020] Figures 8A to 8C , Figures 9A to 9D and Figures 10A to 10C This is a cross-sectional view illustrating a method for manufacturing a memory cell array according to an embodiment of the present disclosure;

[0021] Figure 11 This illustrates embodiments according to the present disclosure, including... Figure 1 A block diagram of a memory system for a semiconductor memory device;

[0022] Figure 12 This illustrates an embodiment according to the present disclosure. Figure 11 A block diagram illustrating application examples of the memory system; and

[0023] Figure 13 This illustrates embodiments according to the present disclosure, including references. Figure 12 A block diagram of the computing system describing the memory system. Detailed Implementation

[0024] The specific structural or functional descriptions of embodiments based on the concepts disclosed in this specification are shown only to illustrate embodiments that may be implemented in various forms. However, these descriptions are not limited to the embodiments described in this specification and include modifications to the described embodiments.

[0025] While terms such as "first" and "second" may be used to describe various components, these components should not be construed as being limited to the terms described above. The terms described above are used to distinguish one component from another; for example, without departing from the concepts according to this disclosure, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component.

[0026] Figure 1 This is a block diagram illustrating a semiconductor memory device 10 according to an embodiment of the present disclosure.

[0027] Reference Figure 1 The semiconductor memory device 10 includes peripheral circuitry PC and memory cell array 20.

[0028] The peripheral circuit PC can control programming operations to store data in the memory cell array 20, control read operations to output the data stored in the memory cell array 20, and control erase operations to erase the data stored in the memory cell array 20.

[0029] In an embodiment, the peripheral circuit PC may include a voltage generator 31, a line decoder 33, a control circuit 35, and a page buffer group 37.

[0030] The memory cell array 20 may include multiple memory blocks. The memory cell array 20 may be connected to the row decoder 33 via word line WL and to the page buffer group 37 via bit line BL.

[0031] Control circuit 35 can control peripheral circuit PC in response to command CMD and address ADD.

[0032] Voltage generator 31 can generate various operating voltages for programming, reading and erasing operations in response to control of control circuit 35, such as pre-erase voltage, erase voltage, ground voltage, programming voltage, verification voltage, pass voltage and read voltage.

[0033] The line decoder 33 can select a memory block in response to the control circuit 35. The line decoder 33 can apply an operating voltage to the word line WL connected to the selected memory block.

[0034] Page buffer group 37 can be connected to memory cell array 20 via bit line BL. Page buffer group 37 can temporarily store data received from input / output circuitry (not shown) during programming operations in response to control of control circuitry 35. Page buffer group 37 can sense the voltage or current of bit line BL during read or verification operations in response to control of control circuitry 35. Page buffer group 37 can select bit line BL in response to control of control circuitry 35.

[0035] Structurally, the memory cell array 20 can overlap with a portion of the peripheral circuit PC.

[0036] Figure 2 This is a circuit diagram illustrating a memory block according to an embodiment of the present disclosure.

[0037] Reference Figure 2 The memory block may include a source layer SL and multiple cell strings CS1 and CS2 that are connected to multiple word lines WL1 to WLn. The multiple cell strings CS1 and CS2 may be connected to multiple bit lines BL.

[0038] Each of the multiple cell strings CS1 and CS2 may include: at least one source select transistor SST connected to the source layer SL; at least one drain select transistor DST connected to the bit line BL; and multiple memory cells MC1 to MCn connected in series between the source select transistor SST and the drain select transistor DST.

[0039] The gates of multiple memory cells MC1 to MCn can be respectively connected to multiple word lines WL1 to WLn stacked separately. The multiple word lines WL1 to WLn can be arranged between the source select line SSL and two or more drain select lines DSL1 and DSL2. The two or more drain select lines DSL1 and DSL2 can be spaced apart from each other at the same height.

[0040] The gate of the source-select transistor (SST) can be connected to the source-select line (SSL). The gate of the drain-select transistor (DST) can be connected to the drain-select line corresponding to the gate of the drain-select transistor (DST).

[0041] The source layer SL can be connected to the source of the source select transistor SST. The drain of the drain select transistor DST can be connected to the bit line corresponding to the drain of the drain select transistor DST.

[0042] Multiple unit strings CS1 and CS2 can be grouped into strings, which are connected to each of two or more drain select lines DSL1 and DSL2. Unit strings connected to the same word line and the same bit line can be independently controlled by different drain select lines. Furthermore, unit strings connected to the same drain select line can be independently controlled by different bit lines.

[0043] In an embodiment, two or more drain select lines DSL1 and DSL2 may include a first drain select line DSL1 and a second drain select line DSL2. Multiple unit strings CS1 and CS2 may include a first unit string CS1 of a first string group connected to the first drain select line DSL1 and a second unit string CS2 of a second string group connected to the second drain select line DSL2.

[0044] Figure 3A and Figure 3B This is a perspective view schematically illustrating semiconductor memory devices 10A and 10B according to embodiments of the present disclosure.

[0045] Reference Figure 3A and Figure 3B Each of the semiconductor memory devices 10A and 10B may include peripheral circuitry PC disposed on a substrate SUB and a gate stack GST superimposed on the peripheral circuitry PC.

[0046] Each of the gate stacks GST may include a source select line SSL, multiple word lines WL1 to WLn, and two or more drain select lines DSL1 and DSL2 spaced apart from each other at the same height through a first slit S1.

[0047] The source select line SSL and multiple word lines WL1 to WLn extend in a first direction X and a second direction Y, and can be formed into a flat plate shape parallel to the upper surface of the substrate SUB. The first direction X can be the direction toward the X-axis of the XYZ coordinate system, and the second direction Y can be the direction toward the Y-axis of the XYZ coordinate system.

[0048] Multiple word lines WL1 to WLn can be stacked separately on a third direction Z. The third direction Z can be the direction toward the Z-axis of the XYZ coordinate system. Multiple word lines WL1 to WLn can be arranged between two or more drain select lines DSL1 and DSL2 and source select line SSL.

[0049] The gate stack GST can be separated from each other by the second slit S2. The first slit S1 is formed on the third direction Z as shorter than the second slit S2 and can overlap with multiple word lines WL1 to WLn.

[0050] Each of the first slit S1 and the second slit S2 can extend in a straight line, a zigzag pattern, or a wavy pattern. The width of each of the first slit S1 and the second slit S2 can be varied according to design rules.

[0051] Reference Figure 3A According to an embodiment, the source select line SSL can be arranged closer to the peripheral circuit PC than the two or more drain select lines DSL1 and DSL2.

[0052] The semiconductor memory device 10A may include: a source layer SL disposed between a gate stack GST and a peripheral circuit PC; and multiple bit lines BL disposed further away from the peripheral circuit PC than the source layer SL. The gate stack GST may be disposed between the multiple bit lines BL and the source layer SL.

[0053] Reference Figure 3B According to an embodiment, two or more drain select lines DSL1 and DSL2 can be arranged closer to the peripheral circuit PC than the source select line SSL.

[0054] The semiconductor memory device 10B may include: multiple bit lines BL disposed between a gate stack GST and a peripheral circuit PC; and a source layer SL disposed further away from the peripheral circuit PC than the multiple bit lines BL. The gate stack GST may be disposed between the multiple bit lines BL and the source layer SL.

[0055] Refer again Figure 3A and Figure 3B The multiple bit lines BL can comprise various conductive materials. The source layer SL can comprise a doped semiconductor layer. In an embodiment, the source layer SL can comprise an n-type doped silicon layer.

[0056] although Figure 3A and Figure 3B Although not shown, the peripheral circuit PC can be electrically connected to multiple bit lines BL, source layer SL, and multiple word lines WL1 to WLn through interconnects with various structures.

[0057] Figure 4 This is a perspective view illustrating the gate stacks GSTA, GSTb, and GSTc of a semiconductor memory device according to an embodiment of the present disclosure.

[0058] Reference Figure 4 Each of the gate stacks GSTA, GSTb, and GSTc may include a first stack ST1 and a second stack ST2. The first stack ST1 and the second stack ST2 may be arranged between multiple bit lines BL and the source layer SLa.

[0059] Multiple bit lines BL can overlap with the first stack ST1, and the second stack ST2 can be arranged between the first stack ST1 and the multiple bit lines BL. The multiple bit lines BL can overlap with the source layer SLa.

[0060] The first stack ST1 may include a first interlayer insulating layer ILD1 and a first conductive pattern CP1 stacked alternately on top of each other. The first conductive pattern CP1 may be used as a source select line SSL and multiple word lines WL1 to WLn.

[0061] The second stack ST2 may include a second conductive pattern CP2 and a second interlayer insulating layer ILD2. The second conductive pattern CP2 may be disposed between the first interlayer insulating layer ILD1 and the second interlayer insulating layer ILD2 disposed on the first stack ST1. The second conductive pattern CP2 and the second interlayer insulating layer ILD2 may be disposed sequentially on the first stack ST1 to overlap with the first stack ST1. The second conductive pattern CP2 may be used as drain selection lines DSL1 and DSL2.

[0062] The second stack ST2 can be penetrated by the first slit S1. The second conductive pattern CP2 of the second stack ST2 can be separated into drain select lines DSL1 and DSL2 by the first slit S1. In an embodiment, each of the gate stacks GSTA, GSTb, and GSTc may include a first drain select line DSL1 and a second drain select line DSL2 separated by the first slit S1.

[0063] The gate stacks GSTA, GSTb, and GSTc can be separated from each other by forming a second slit S2 that is deeper than the first slit S1. A spacer insulating layer SP can be formed on the sidewalls of each of the second slits S2, and a vertical structure 60 can be formed in each of the second slits S2. In an embodiment, the vertical structure 60 may include a conductive material that contacts and fills the interior of each second slit S2 with the source layer SLa. However, embodiments of this disclosure are not limited thereto. In one embodiment, the vertical structure 60 may include an insulator.

[0064] Each of the gate stacks GSTA, GSTb, and GSTc, including its first stack ST1 and second stack ST2, can be penetrated by multiple channel structures CH. The multiple channel structures CH can be arranged in multiple channel columns. The channel structures CH arranged in each channel column can include channel structures arranged in rows along the direction of the bit line BL. In an embodiment, the channel structures CH arranged in each channel column can include first channel structures CH11 and CH12 and second channel structures CH21 and CH22. The first channel structures CH11 and CH12 can be arranged on one side of the first slit S1, and the second channel structures CH21 and CH22 can be arranged on the other side of the first slit S1. The first slit S1 can be arranged between the first channel structures CH11 and CH12 and the second channel structures CH21 and CH22.

[0065] In an embodiment, first channel structures CH11 and CH12 may extend through the first drain select line DSL1 and the first stack ST1. Second channel structures CH21 and CH22 may extend through the second drain select line DSL2 and the first stack ST1. Each of the second conductive pattern CP2, the second interlayer insulating layer ILD2, the first conductive pattern CP1, and the first interlayer insulating layer ILD1 may extend to surround the first channel structures CH11 and CH12 and the second channel structures CH21 and CH22.

[0066] Each bit line BL can be electrically connected via a drain contact plunger (DCT) to one of the first channel structures CH11 and CH12 and one of the second channel structures CH21 and CH22.

[0067] The virtual channel structure DCH can be arranged between the first channel structures CH11 and CH12 and the second channel structures CH21 and CH22. The virtual channel structure DCH can penetrate the first stack ST1. The first slit S1 can overlap with the virtual channel structure DCH.

[0068] Each of the channel structures CH can include a core insulating layer CO, a doped semiconductor pattern DP, and a (vertical) channel layer CL (see [link to documentation]). Figure 5The virtual channel structure (DCH) may include a virtual core insulating layer (CO') and a virtual channel layer (CL').

[0069] A core insulating layer CO can be vertically disposed at the center (i.e., the core) of each of the channel structures CH and can be surrounded by a first stack ST1. A doped semiconductor pattern DP can overlap with the core insulating layer CO and is surrounded by a second conductive pattern CP2 and a second interlayer insulating layer ILD2. In an embodiment, the doped semiconductor pattern DP can include an n-type doped silicon layer. A channel layer CL can extend along the sidewalls of the core insulating layer CO and the sidewalls of the doped semiconductor pattern DP. That is, the channel layer CL can surround the sidewalls of the core insulating layer CO and the sidewalls of the doped semiconductor pattern DP.

[0070] The thickness of a first region of the channel layer CL surrounding the sidewalls of the doped semiconductor pattern DP can be greater than the thickness of a second region of the channel layer CL surrounding the sidewalls of the core insulating layer CO. The second region of the channel layer CL extends below the first region. For example, the first region of the channel layer CL surrounding the sidewalls of the doped semiconductor pattern DP can have a multilayer structure, and the second region of the channel layer CL surrounding the sidewalls of the core insulating layer CO can have a single-layer structure. One end of the channel layer CL can be connected to one of the bit lines BL via a contact plunger DCT. One end of the channel layer CL can directly contact the contact plunger DCT. The other end of the channel layer CL extends between the source layer SLa and the core insulating layer CO, and can contact the source layer SLa. In an embodiment, each of the channel layer CL and the dummy channel layer CL' can include an undoped silicon layer.

[0071] The virtual memory layer ML' may extend on the sidewall of the isolation insulating layer 50. The isolation insulating layer 50 may be disposed between the first drain select line DSL1 and the second drain select line DSL2. The isolation insulating layer 50 may fill the first slit S1 and overlap with the virtual channel structure DCH. The virtual memory layer ML' may include the same material layer as the memory layer ML.

[0072] Although Figure 4 It is not shown in the figure, but an upper insulating layer penetrated by the contact plunger DCT can be arranged between multiple bit lines BL and the second stack ST2.

[0073] Each channel structure CH has its sidewalls surrounded by a memory layer ML. The virtual channel structure DCH has its sidewalls surrounded by a virtual memory layer ML'.

[0074] The thickness of the first region of the channel layer CL surrounding the doped semiconductor pattern DP is greater than the thickness of the second region of the channel layer CL surrounding the core insulating layer CO. That is, the thickness of the region of the channel layer CL adjacent to the second conductive pattern CP2 is relatively large, thereby easily ensuring a bonding overlap region in the channel below the drain select transistor. Furthermore, since the doped semiconductor pattern DP can be surrounded by at least a portion of the second conductive pattern CP2, a bonding overlap region can be easily ensured in the channel below the drain select transistor. Therefore, during the erase operation of the semiconductor memory device, the gate-induced drain leakage (GIDL) current generated in the lower channel of the drain select transistor may increase. The GIDL current can be generated by the difference between the erase voltage applied to the bit line BL and the gate voltage applied to the second conductive pattern CP2.

[0075] A first barrier layer (not shown) may be disposed between the first stack ST1 and the memory layer ML, and between the second conductive pattern CP2 and the memory layer ML.

[0076] Figure 5 yes Figure 4 An enlarged cross-sectional view of region A shown in the figure.

[0077] Reference Figure 5 The memory layer ML may include a tunnel isolation layer TI and a data storage layer DL. The tunnel isolation layer TI may surround the sidewalls of the channel layer CL. The tunnel isolation layer TI may include an insulating material capable of charge tunneling. In one embodiment, the tunnel isolation layer TI may include a silicon oxide layer. The data storage layer DL may surround the sidewalls of the tunnel isolation layer TI. The data storage layer DL may include a material layer capable of storing data. The data storage layer DL may include a nitride layer capable of trapping charge. However, the embodiments are not limited thereto; the data storage layer DL may include phase change materials, nanodots, etc.

[0078] The memory layer ML can extend to the height of the sidewalls of the first interlayer insulating layer ILD1 and the first conductive pattern CP1, as well as the height of the sidewalls of the second conductive pattern CP2 and the second interlayer insulating layer ILD2.

[0079] The channel layer CL can surround the sidewalls of the core insulating layer CO and the sidewalls of the doped semiconductor pattern DP. The channel layer CL can overlap with the sidewalls of the second conductive pattern CP2.

[0080] In an embodiment, the second thickness X2 of the channel layer CL surrounding the sidewalls of the doped semiconductor pattern DP can be greater than the first thickness X1 of the channel layer CL surrounding the sidewalls of the core insulating layer CO. The channel layer CL can include a first channel layer CL1 and a second channel layer CL2. The first channel layer CL1 can extend along the inner sidewall of the memory layer ML, and the first channel layer CL1 can surround both the sidewalls of the core insulating layer CO and the sidewalls of the doped semiconductor pattern DP. The first channel layer CL1 can directly contact the outer wall of the core insulating layer CO. The second channel layer CL2 can surround the sidewalls of the doped semiconductor pattern DP. The second channel layer CL2 can contact a portion of the inner wall of the first channel layer CL1. The second channel layer CL2 can be disposed between a portion of the inner wall of the first channel layer CL1 and the outer wall of the doped semiconductor pattern DP. The second channel layer CL2 can be configured to have a height that at least partially overlaps with the sidewall of the second conductive pattern CP2. The channel layer CL overlapping the sidewall of the second conductive pattern CP2 includes the first channel layer CL1 and the second channel layer CL2, thereby ensuring sufficient thickness.

[0081] The first barrier insulating layer BI1 may surround the sidewall of the data memory layer DL. The first barrier insulating layer BI1 may extend along the sidewall of the doped semiconductor pattern DP. The first barrier insulating layer BI1 may be arranged along the sidewall of the first conductive pattern CP1, the first interlayer insulating layer ILD1, the second conductive pattern CP2, and the second interlayer insulating layer ILD2. The first barrier insulating layer BI1 may include an oxide.

[0082] A first conductive pattern CP1 may surround a memory layer ML between first interlayer insulating layers ILD1. The first conductive pattern CP1 may include a conductive material with a resistance lower than silicon. In an embodiment, the first conductive pattern CP1 may include a metal layer.

[0083] A second barrier insulating layer BI2 may be further formed between the first conductive pattern CP1 and the first barrier insulating layer BI1. The second barrier insulating layer BI2 may include an insulating material with a dielectric constant higher than that of the first barrier insulating layer BI1. In an embodiment, the second barrier insulating layer BI2 may include a metal oxide layer. In an embodiment, the metal oxide may include an aluminum oxide layer. The second barrier insulating layer BI2 may extend along the interface between the first conductive pattern CP1 and the first interlayer insulating layer ILD1.

[0084] The second conductive pattern CP2 may surround the memory layer ML between the first interlayer insulating layer ILD1 and the second interlayer insulating layer ILD2. Alternatively, the second conductive pattern CP2 may include a doped semiconductor pattern DP between the first interlayer insulating layer ILD1 and the second interlayer insulating layer ILD2, a first channel layer CL1, and a second channel layer CL2, thereby surrounding the channel layer CL. For example, the lower end of the sidewall of the second conductive pattern CP2 may surround the first channel layer CL1, and the upper end of the sidewall of the second conductive pattern CP2 may surround both the first channel layer CL1 and the second channel layer CL2. That is, the first channel layer CL1 and the second channel layer CL2 may overlap with the upper end of the sidewall of the second conductive pattern CP2. In another embodiment, the first channel layer CL1 and the second channel layer CL2 may overlap with the entire sidewall of the second conductive pattern CP2.

[0085] like Figure 2 As shown, the second conductive pattern CP2 can be used as a drain select line DSL connected to the gate of the drain select transistor DST.

[0086] Figure 4 and Figure 5 The semiconductor memory device shown can be applied to Figure 3A The semiconductor memory device 10A shown is illustrated. Figure 4 and Figure 5 The semiconductor memory device shown can be inverted and applied to Figure 3B The semiconductor memory device 10B shown is shown.

[0087] like Figure 4 As shown, the channel layer CL may include a bottom surface that penetrates the memory layer ML and contacts the source layer SLa. Embodiments of this disclosure are not limited thereto.

[0088] Figure 6 This is a cross-sectional view showing the source layer SLb and the channel structure CH according to an embodiment of the present disclosure. Figure 6 The structure shown can be applied to Figure 3A The semiconductor memory device 10A shown is illustrated.

[0089] Reference Figure 6 The source layer SLb may include a first layer SL1 and a second layer SL2, or it may include a first layer SL1, a second layer SL2, and a third layer SL3. The first layer SL1 may overlap with the first stack ST1. The second layer SL2 may be disposed between the first stack ST1 and the first layer SL1. The third layer SL3 may be disposed between the second layer SL2 and the first stack ST1.

[0090] Each of the first layer SL1, the second layer SL2, and the third layer SL3 may include a doped semiconductor layer. In an embodiment, each of the first layer SL1, the second layer SL2, and the third layer SL3 may include n-type doped silicon.

[0091] The first stack ST1 may include, as referenced Figure 4 The first interlayer insulating layer ILD1 and the first conductive pattern CP1 are alternately stacked and can be penetrated by the channel structure CH.

[0092] The end EP of the channel structure CH passes through the third layer SL3 and the second layer SL2, and can extend into the first layer SL1. In an embodiment, the first channel layer CL1 and the core insulating layer CO can penetrate the third layer SL3 and the second layer SL2, and extend into the first layer SL1.

[0093] Each of the data storage layer DL and the tunnel isolation layer TI can be separated by a second layer SL2 into a first memory pattern ML1 and a second memory pattern ML2. The second layer SL2 protrudes further toward the first channel layer CL1 than the first layer SL1 and the third layer SL3, and can contact the first channel layer CL1. A first barrier insulating layer BI1 can be arranged to contact the sidewall of the first memory pattern ML1. That is, the first barrier insulating layer BI1 can be arranged between the sidewall of the first memory pattern ML1 and the sidewall of the third layer SL3, the first interlayer insulating layer ILD1, and the first conductive pattern CP1. In addition, the first barrier insulating layer BI1 can be arranged to contact the sidewall and lower surface of the second memory pattern ML2. That is, the first barrier insulating layer BI1 can be arranged between the sidewall and lower surface of the second memory pattern ML2 and the sidewall and lower surface of the first layer SL1.

[0094] The first barrier insulating layer BI1, the data storage layer DL, and the tunnel isolation layer TI can extend from between the first stack ST1 and the first channel layer CL1 to between the third layer SL3 and the first channel layer CL1. The first barrier insulating layer BI1, the data storage layer DL, and the tunnel isolation layer TI of the second memory pattern ML2 can extend between the first layer SL1 and the first channel layer CL1.

[0095] The second barrier insulating layer BI2 can be disposed between the first barrier insulating layer BI1 and the first conductive pattern CP1 of the first memory pattern ML1.

[0096] Figure 7 This is a cross-sectional view showing the source layer SLc and the channel structure CH according to an embodiment of the present disclosure. Figure 7 The structure shown can be applied to Figure 3B The semiconductor memory device 10B shown is shown.

[0097] Reference Figure 7 The source layer SLc may overlap with the first stack ST1 and includes a doped semiconductor layer. In an embodiment, the source layer SLc may include n-type doped silicon. The first stack ST1 may be disposed on the source layer SLc and as shown in the reference. Figure 4 Between the second stack ST2.

[0098] The first stack ST1 may include, as referenced Figure 4 The first interlayer insulating layer ILD1 and the first conductive pattern CP1 are alternately stacked and can be penetrated by the channel structure CH.

[0099] The end EP' of the channel structure CH can penetrate the first barrier insulating layer BI1, the data storage layer DL of the memory layer ML, and the tunnel isolation layer TI, and can extend into the source layer SLc. In an embodiment, the first channel layer CL1 and the core insulating layer CO can extend into the source layer SLc. A portion of the first channel layer CL1 constituting the end EP' of the channel structure CH can contact the source layer SLc.

[0100] Figures 8A to 8C , Figures 9A to 9D and Figures 10A to 10C This is a cross-sectional view illustrating a method for manufacturing a memory cell array according to an embodiment of the present disclosure.

[0101] Figures 8A to 8C This is a cross-sectional view showing the process of forming the initial stack 110 and the process of forming the initial channel structure that penetrates the initial stack 110 and is surrounded by the memory layers ML.

[0102] Reference Figure 8A The process of forming the initial stack 110 may include alternately stacking a first interlayer insulating layer 101 and a sacrificial layer 103. Each of the sacrificial layers 103 may include a material that is etch-selective to the first interlayer insulating layer 101. In an embodiment, the first interlayer insulating layer 101 may include silicon oxide, and the sacrificial layer 103 may include silicon nitride. Subsequently, a second interlayer insulating layer 105 is formed on the uppermost sacrificial layer 103. For example, the initial stack 110 is formed by alternately stacking the first interlayer insulating layer 101 and the sacrificial layer 103 on a semiconductor substrate and stacking the second interlayer insulating layer 105 on the uppermost sacrificial layer 103.

[0103] Subsequently, a mask layer 121 is formed over the initial stack 110. The mask layer 121 may include a nitride layer.

[0104] Reference Figure 8BA via 125A can be formed by etching the mask layer 121 and the initial stack 110. The via 125A can penetrate the initial stack 110. During the process of forming the via 125A, a virtual via 125B that penetrates the initial stack 110 can be formed simultaneously with the via 125A.

[0105] The channel via 125A and the dummy via 125B can be defined by using a photoresist pattern (not shown) formed by a photolithography process as an etch barrier layer to etch the mask layer 121 and the initial stack 110. After the channel via 125A and the dummy via 125B are formed, the photoresist pattern can be removed.

[0106] Reference Figure 8C A memory layer ML can be formed on the surface covering the channel holes and virtual holes and extending to the surface of the mask layer 121. The memory layer ML may include a data memory layer and a tunnel isolation layer. Subsequently, a first channel layer CL1 may be formed on the surface of the memory layer ML.

[0107] After the first channel layer CL1 is formed, the core insulating layer CO can be used to fill the central region of the channel holes and virtual holes.

[0108] Figures 9A to 9D This is an enlarged cross-sectional view illustrating an embodiment of the process of forming a memory layer ML, a first channel layer CL1, a second channel layer CL2, a core insulating layer CO, and a doped semiconductor pattern DP in a channel via.

[0109] Reference Figure 9A , forming as Figure 8C The process of forming the memory layer ML, the first channel layer CL1, and the core insulating layer CO may include forming a first barrier insulating layer BI1 on the surface of each channel via and virtual via. The first barrier insulating layer BI1 may include an oxide.

[0110] Subsequently, a data storage layer DL and a tunnel isolation layer TI can be sequentially formed on the surface of the first barrier insulating layer BI1 to form the storage layer ML. The tunnel isolation layer TI may include an insulating material capable of charge tunneling. In an embodiment, the tunnel isolation layer TI may include a silicon oxide layer. The data storage layer DL may include a material layer capable of storing data. The data storage layer DL may include a nitride layer capable of trapping charge. However, embodiments of this disclosure are not limited thereto; the data storage layer DL may include phase change materials, nanodots, etc.

[0111] Subsequently, a first trench layer CL1 may be formed on the surface of the tunnel isolation layer TI. The first trench layer CL1 may include a silicon layer.

[0112] Subsequently, a core insulating layer CO can be formed on the surface of the first channel layer CL1, and can be configured such that the interior of the channel vias is filled with the core insulating layer CO. The core insulating layer CO can be formed by depositing an oxide layer using the ALD method. Afterward, an etch-back process can be performed on the core insulating layer CO, so that the core insulating layer CO remains only within the channel vias.

[0113] Reference Figure 9B The core insulating layer CO can be etched using a dry etching process, such that, by performing the etching process, the upper surface of the core insulating layer CO can be located below the upper surface of at least one of the top sacrificial layers 103 within the sacrificial layers 103. For example, the upper surface of the core insulating layer CO can be located above the sacrificial layer within the sacrificial layers 103 corresponding to the word lines.

[0114] Reference Figure 9C The second channel layer CL2 can be located in the form of a pad on the sidewall surface of the first channel layer CL1 and the upper surface of the core insulating layer CO. The second channel layer CL2 may include a silicon layer. The second channel layer CL2 may include the same material as the first channel layer CL1.

[0115] Reference Figure 9D A doped semiconductor layer is deposited in the space where the core insulating layer CO is etched, and a planar etching process is performed so that the mask layer can be exposed to form a doped semiconductor pattern DP on top of the core insulating layer CO.

[0116] In this way, the channel layer CL, including the second channel layer CL2 and the first channel layer CL1, can surround the sidewalls of the doped semiconductor pattern DP, and the sidewalls of the core insulating layer CO can surround the first channel layer CL1.

[0117] Through the planar etching process described above, the memory layer ML, the first channel layer CL1, the second channel layer CL2, and the doped semiconductor pattern DP can be partially protruded above the upper surface of the second interlayer insulating layer 105.

[0118] A doped semiconductor pattern DP is formed on the upper sidewall of the sacrificial layer 103 located at the top, and a first barrier insulating layer BI1 is located between the sacrificial layer 103 and the doped semiconductor pattern DP.

[0119] Figures 10A to 10C An embodiment of the process of forming a first conductive pattern and a second conductive pattern in the space between the first interlayer insulating layers 101 is shown.

[0120] Reference Figure 10A ,exist Figure 9DFollowing the illustrated process, a slot formation mask layer 131 is formed over the entire structure including the doped semiconductor pattern DP. Subsequently, an etching process is performed using the slot formation mask layer 131 to sequentially etch the second interlayer insulating layer 105 and the sacrificial layers and first interlayer insulating layers 101 stacked alternately to form a second slot 141. The sacrificial layers exposed through the second slot 141 are then removed. Thus, empty spaces are formed between the first interlayer insulating layers 101 and between the first interlayer insulating layer 101 and the second interlayer insulating layer 105.

[0121] Reference Figure 10B Conductive material is filled into the spaces between the first interlayer insulating layers 101 and between the first interlayer insulating layer 101 and the second interlayer insulating layer 105 to form a first conductive pattern CP1 and a second conductive pattern CP2. The first conductive pattern CP1 and the second conductive pattern CP2 may include a conductive material with a resistance lower than that of silicon. In an embodiment, the first conductive pattern CP1 and the second conductive pattern CP2 may include a metal layer. The first conductive pattern CP1 is formed in the space between the first interlayer insulating layers 101, and the second conductive pattern CP2 is formed in the space between the top first interlayer insulating layer 101 and the second interlayer insulating layer 105.

[0122] A second barrier insulating layer BI2 can be formed on the surface of the empty space before the formation of the first conductive pattern CP1 and the second conductive pattern CP2. The second barrier insulating layer BI2 may include an insulating material with a dielectric constant higher than that of the first barrier insulating layer BI1. In an embodiment, the second barrier insulating layer BI2 may include an aluminum oxide layer.

[0123] Reference Figure 10C The second slit 141 is filled with insulating material 142. Then, a first slit 151 is formed on top of the virtual channel structure. The first slit 151 can be formed as a line and is separated at both ends by the first slit 151 around the second conductive pattern CP2 of the virtual channel structure. Subsequently, the first slit 151 is filled with insulating material 152.

[0124] Figure 11 This illustrates embodiments according to the present disclosure, including... Figure 1 A diagram of a memory system 1000 of a semiconductor memory device 10.

[0125] Reference Figure 11 The memory system 1000 may include a semiconductor memory device 100 and a controller 1100. The semiconductor memory device 100 may be as described above. Figure 1 The semiconductor memory device 10 is described.

[0126] Controller 1100 can be coupled to a host computer and semiconductor memory device 100. In response to a request from the host computer, controller 1100 can access the memory device. For example, controller 1100 can control write operations, read operations, erase operations, and background operations of the memory device. Controller 1100 can provide an interface between semiconductor memory device 100 and the host computer. Controller 1100 can drive firmware for controlling semiconductor memory device 100.

[0127] The controller 1100 may include random access memory (RAM) 1110, a processing unit 1120, a host interface 1130, a memory interface 1140, and an error correction code (ECC) block 1150. RAM 1110 may be used as at least one of working memory, cache memory between the semiconductor memory device 100 and the host, and buffer memory between the semiconductor memory device 100 and the host. The processing unit 1120 may control the overall operation of the controller 1100. Additionally, the controller 1100 may temporarily store programming data provided from the host during write operations.

[0128] The host interface 1130 may include protocols for exchanging data between the host and the controller 1100. According to embodiments, the controller 1100 may communicate with the host via one or more of various communication interfaces or standards such as: Universal Serial Bus (USB) protocol, Multimedia Card (MMC) protocol, Peripheral Component Interconnect (PCI) protocol, High Speed ​​PCI (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer System Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Electronic Integrated Drive (IDE) protocol, proprietary protocols, etc.

[0129] The memory interface 1140 can interface with the semiconductor memory device 100. For example, the memory interface 1140 may include a NAND interface or a NOR interface.

[0130] ECC block 1150 can be configured to detect and correct errors in data received from semiconductor memory device 100. Processing unit 1120 can control semiconductor memory device 100 to control the read voltage and perform a reread based on the error detection result. According to an embodiment, ECC block 1150 can be configured as a component of controller 1100.

[0131] The controller 1100 and the semiconductor memory device 100 can be integrated into a single semiconductor device to form a memory card. For example, the controller 1100 and the semiconductor memory device 100 can be integrated into a single semiconductor device to form memory cards such as those from the Personal Computer Memory Card International Association (PCMCIA), Compact Flash (CF) cards, Smart Media Cards (SM or SMC), Memory Sticks, Multimedia Cards (MMC, RS-MMC, or Micro MMC), SD cards (SD, Mini SD, Micro SD, or SDHC), Universal Flash Memory (UFS), etc.

[0132] The controller 1100 and the semiconductor memory device 100 can be integrated into a single semiconductor device to form a solid-state drive (SSD). The SSD may include a storage device configured to store data in the semiconductor memory. When the memory system 1000 is used as an SSD, the operating speed of a host connected to the memory system 1000 can be significantly improved.

[0133] In another embodiment, the memory system 1000 may be configured as one of a variety of elements among electronic devices such as: computer, ultra-mobile PC (UMPC), workstation, netbook, personal digital assistant (PDA), portable computer, network tablet, wireless phone, mobile phone, smartphone, e-book, portable multimedia player (PMP), gaming device, navigation device, black box, digital camera, 3D TV, digital audio recorder, digital audio player, digital picture recorder, digital picture player, digital video recorder, digital video player, device capable of transmitting / receiving information in a wireless environment, one of a variety of devices for forming a home network, one of a variety of electronic devices for forming a computer network, one of a variety of electronic devices for forming a telematics network, RFID device, etc.

[0134] In embodiments, the semiconductor memory device 100 or memory system 1000 can be mounted in various forms of packages. For example, the semiconductor memory device 100 or memory system 1000 can be embedded in packages such as: stacked package (POP), ball grid array (BGA), chip-scale package (CSP), plastic leaded chip carrier (PLCC), plastic dual in-line package (PDIP), die in stacked package, die in wafer form, chip on board (COB), ceramic dual in-line package (CERDIP), plastic metric quad flat package (MQFP), thin quad flat package (TQFP), small outline integrated circuit (SOIC) package, reduced small outline package (SSOP), thin small outline package (TSOP), system-in-package (SIP), multi-chip package (MCP), wafer-level fabrication package (WFP), wafer-level processing stacked package (WSP), etc.

[0135] Figure 12 This illustrates an embodiment according to the present disclosure. Figure 11 A block diagram illustrating the application of the memory system 1000.

[0136] Reference Figure 12 The memory system 2000 may include a semiconductor memory device 2100 and a controller 2200. The semiconductor memory device 2100 may include semiconductor memory chips. The semiconductor memory chips may be divided into multiple groups.

[0137] Figure 12 This illustrates multiple groups communicating with controller 2200 via channels CH1 to CHk from the first to the kth. Each of the semiconductor memory chips can communicate with the controller 2200 via the channels CH1 to CHk mentioned above. Figure 1 The semiconductor memory device 10 described is configured and operated in a substantially the same manner.

[0138] Each group can communicate with controller 2200 through a single common channel. Controller 2200 can communicate with reference to... Figure 11 The controller 1100 described is configured in a substantially similar manner and is configured to control multiple memory chips of the semiconductor memory device 2100 via multiple channels CH1 to CHk.

[0139] Figure 13 This illustrates embodiments according to the present disclosure, including the foregoing reference. Figure 12 A block diagram of the memory system 2000 and the computing system 3000 described.

[0140] The computing system 3000 may include a central processing unit 3100, random access memory (RAM) 3200, a user interface 3300, a power supply 3400, a system bus 3500, and a memory system 2000.

[0141] The memory system 2000 can be electrically connected to the central processing unit 3100, RAM 3200, user interface 3300, and power supply 3400 via the system bus 3500. Data provided through the user interface 3300 or processed by the central processing unit 3100 can be stored in the memory system 2000.

[0142] like Figure 13 As shown, the semiconductor memory device 2100 can be connected to the system bus 3500 via the controller 2200. However, the semiconductor memory device 2100 can be directly connected to the system bus 3500. The central processing unit 3100 and RAM 3200 can perform the functions of the controller 2200.

[0143] like Figure 13 As shown, it can provide Figure 12The memory system 2000 is shown. However, the memory system 2000 can be derived from... Figure 11 The memory system 1000 shown is replaced. According to an embodiment, the computing system 3000 may include the above-mentioned reference... Figure 11 and Figure 12 The memory systems 1000 and 2000 are described.

[0144] According to embodiments of the present disclosure, the characteristics of a drain-select transistor can be improved to stably generate a gate-induced drain leakage (GIDL) current for erase operations, thereby improving the operational reliability of the semiconductor memory device.

[0145] While embodiments of this disclosure have been described and illustrated with reference to specific examples and accompanying drawings, the disclosed embodiments are not intended to be limiting. Furthermore, it should be noted that those skilled in the art will recognize, without departing from the spirit and / or scope of this disclosure and the appended claims, that the embodiments can be implemented in various ways through substitutions, alterations, and modifications. Additionally, embodiments can be combined to form other embodiments.

Claims

1. A semiconductor memory device, comprising: Stacked structures, including alternating stacked interlayer insulating layers and conductive patterns; as well as The channel structure is configured to penetrate the stacked structure. Each of the channel structures includes: A doped semiconductor pattern is disposed in the core of each channel structure, the doped semiconductor pattern at least partially overlapping with at least one upper conductive pattern among the conductive patterns; A vertical channel layer includes a first region and a second region, the first region being configured to surround the doped semiconductor pattern, and the second region being configured to extend below the first region; and The memory layer is configured to surround the vertical channel layer. The thickness of the first region is greater than the thickness of the second region.

2. The semiconductor memory device according to claim 1, wherein, Each of the channel structures further includes a core insulating layer disposed beneath the doped semiconductor pattern.

3. The semiconductor memory device according to claim 2, wherein, The second region of the vertical channel layer is configured to surround the core insulating layer.

4. The semiconductor memory device according to claim 1, wherein, The first region of the vertical channel layer at least partially overlaps with the sidewall of the at least one upper conductive pattern.

5. The semiconductor memory device according to claim 1, further comprising: A first barrier insulating layer is configured to surround the memory layer.

6. The semiconductor memory device according to claim 1, wherein, The at least one upper conductive pattern includes: a drain select line corresponding to a drain select transistor included in the cell string.

7. The semiconductor memory device according to claim 1, wherein: The doped semiconductor pattern includes an n-type doped silicon layer; and The vertical channel layer includes an undoped silicon layer.

8. The semiconductor memory device according to claim 2, wherein, The first region of the vertical channel layer includes: The first channel layer is configured to contact the inner wall of the memory layer; and A second channel layer is disposed between the first channel layer and the doped semiconductor pattern.

9. The semiconductor memory device according to claim 8, wherein, The second region of the vertical channel layer includes a second channel layer disposed between the memory layer and the core insulating layer.

10. A semiconductor memory device, comprising: Stacked structures, including alternating stacked interlayer insulating layers and conductive patterns; as well as The channel structure penetrates the stacked structure. Each of the channel structures includes: A core insulating layer is provided at the core of each channel structure to extend in the vertical direction; A doped semiconductor pattern is disposed on the core insulating layer and at least partially overlaps with at least one of the upper conductive patterns; A vertical channel layer is configured to extend in the vertical direction to surround the core insulating layer and the doped semiconductor pattern; and A memory layer is configured to extend in the vertical direction to surround the vertical channel layer, and The vertical channel layer surrounding the doped semiconductor pattern includes a first channel layer and a second channel layer.

11. The semiconductor memory device of claim 10, wherein, The vertical channel layer surrounding the core insulating layer includes the first channel layer.

12. The semiconductor memory device according to claim 10, wherein, The thickness of the first region of the vertical channel layer surrounding the doped semiconductor pattern is greater than the thickness of the second region of the vertical channel layer surrounding the core insulating layer.

13. The semiconductor memory device according to claim 12, wherein, The first region of the vertical channel layer at least partially overlaps with the sidewall of the at least one upper conductive pattern.

14. The semiconductor memory device of claim 10, further comprising: A first barrier insulating layer is configured to surround the memory layer.

15. The semiconductor memory device according to claim 10, wherein, The at least one upper conductive pattern includes: a drain select line corresponding to a drain select transistor included in the cell string.

16. The semiconductor memory device of claim 10, wherein: The doped semiconductor pattern includes an n-type doped silicon layer; and The vertical channel layer includes an undoped silicon layer.

17. A method for manufacturing a semiconductor memory device, comprising: This forms a stacked structure comprising alternating interlayer insulating layers and sacrificial layers; Forming channel holes through the stacked structure; A memory layer is formed extending along the sidewall of the channel hole; A first channel layer extending on the surface of the memory layer is formed; A core insulating layer is formed on the surface of the first channel layer to fill the channel holes; The core insulating layer is etched back to expose the first channel layer at the top of the channel hole; A second trench layer is formed on the exposed first trench layer; as well as A doped semiconductor pattern is formed to fill the channel hole.

18. The method according to claim 17, wherein, Etching back the core insulating layer includes etching the core insulating layer such that the height of the upper surface of the core insulating layer is lower than at least a portion of at least one of the plurality of sacrificial layers, the upper sacrificial layer.

19. The method of claim 17, further comprising: Before forming the memory layer, a barrier insulating layer extending along the sidewall of the channel hole is formed.

20. The method of claim 17, further comprising: Forming a slit that penetrates the stacked structure; Remove the sacrificial layer exposed through the slit; as well as A conductive pattern is formed in the space where the sacrificial layer has been removed.

21. The method according to claim 20, wherein, The upper conductive pattern of the conductive pattern is formed to at least partially overlap with the first channel layer and the second channel layer.

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