Magnetic random access memory cell and method of information operation control thereof, array

Abstract

This invention provides a magnetic random access memory (MRM) cell and its information operation control method and array, belonging to the field of semiconductor technology. The MRM cell includes: a magnetic tunnel junction stacked structure, comprising at least a spin-orbit torque layer, a free layer, a barrier layer, and a reference layer stacked sequentially, wherein the free layer and the reference layer have perpendicular magnetic anisotropy; and an integrated auxiliary magnetic field generating structure for introducing an auxiliary current to generate an in-plane magnetic field in the plane containing the free layer. This invention solves the defects of existing MRMs that require an external auxiliary magnetic field or the existence of existing field-free schemes, and realizes a universal, high-integration-density, and field-free information operation scheme compatible with semiconductor processes.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a magnetic random access memory cell and its information operation control method and array. Background Technology

[0002] Magnetic Random-Access Memory (MRAM), as a novel type of memory with high speed, high durability, and non-volatility, is one of the key candidate technologies for overcoming the memory wall bottleneck in traditional computing architectures and realizing in-memory computing. Among them, vertical magnetic anisotropic spin-orbit torque MRAM has attracted widespread attention due to its potential for higher integration density.

[0003] The core storage unit of a vertically anisotropic spin-orbit torque magnetic random access memory (MRAM) is a magnetic tunneling junction (MTJ), which typically includes a vertically anisotropic free layer, a barrier layer, and a vertically anisotropic reference layer. Writing information relies on a write current being supplied to the spin-orbit torque layer adjacent to the free layer. This current generates a spin current through the spin Hall effect and is injected into the free layer, thus generating a spin-orbit torque. However, for a vertically anisotropic free layer, the spin-orbit torque alone is insufficient to achieve a deterministic flip of its magnetic moment; an in-plane magnetic field parallel to the write current flow must be applied simultaneously to break the symmetry of the flip. Existing technologies typically use an external magnetic field source to provide this in-plane magnetic field, but this severely limits the device's integration density and practical applications. While some schemes exist that achieve field-free flipping through material or structural design, they often face problems such as poor process compatibility, weak universality, susceptibility to crosstalk, or impact on device durability. Summary of the Invention

[0004] This invention provides a magnetic random access memory cell and its information operation control method and array, which solves the defects of existing magnetic random access memory that require an external auxiliary magnetic field or the existing field-free scheme, and realizes a universal high integration density information operation scheme that is compatible with semiconductor processes.

[0005] In a first aspect, the present invention provides a magnetic random access memory cell, comprising: A magnetic tunnel junction stacked structure includes at least a spin-orbit torque layer, a free layer, a barrier layer and a reference layer stacked sequentially, wherein the free layer and the reference layer have perpendicular magnetic anisotropy; An integrated auxiliary magnetic field generating structure is used to introduce an auxiliary current to generate an in-plane magnetic field in the plane where the free layer is located.

[0006] In some embodiments, the integrated auxiliary magnetic field generating structure is disposed on the side of the spin-orbit torque layer away from the free layer and is electrically isolated from the spin-orbit torque layer, and the extension direction of the integrated auxiliary magnetic field generating structure is perpendicular to the stacking direction of the magnetic tunnel junction stack structure.

[0007] In some embodiments, in the projection along the stacking direction, at least a portion of the integrated auxiliary magnetic field generating structure overlaps with the magnetic tunnel junction stack structure.

[0008] In some embodiments, the magnetic random access memory unit further includes: The bottom electrode is electrically connected to the spin-orbit torque layer. The integrated auxiliary magnetic field generating structure is fabricated in the same layer as the first metal interconnect and is electrically isolated. The bottom electrode is connected to an external circuit through the first metal interconnect.

[0009] In some embodiments, the integrated auxiliary magnetic field generating structure reuses word lines or bit lines in the array containing the magnetic random access memory cells.

[0010] In some embodiments, the integrated auxiliary magnetic field generating structure includes: A conductive core layer and a magnetic flux gathering coating layer, wherein the magnetic flux gathering coating layer covers at least a portion of the sidewalls and / or at least a portion of the bottom wall of the conductive core layer.

[0011] In a second aspect, the present invention also provides an information operation control method for a magnetic random access memory (MRMemory) cell, used to control the MRMemory cell as described in the first aspect, the information operation control method comprising: An auxiliary current is supplied to the integrated auxiliary magnetic field generating structure to generate the in-plane magnetic field in the plane where the free layer is located; A write current is controlled to be supplied to the spin-orbit torque layer to generate a spin-orbit torque on the free layer; The effective pulse of the auxiliary current overlaps the effective pulse of the write current in time, and the direction of the in-plane magnetic field is parallel to the flow direction of the write current in the spin-orbit torque layer.

[0012] In some embodiments, controlling the flow of a write current into the spin-orbit torque layer and controlling the flow of an auxiliary current into the integrated auxiliary magnetic field generating structure include: The polarity of the write current and the polarity of the auxiliary current are controlled such that the polarity combination corresponds to the final resistance state of the magnetic tunnel junction stack structure in an XOR logic manner; wherein, the polarity combination is the combination of the polarity of the write current and the polarity of the auxiliary current.

[0013] In some embodiments, after controlling the flow of a write current into the spin-orbit torque layer and controlling the flow of an auxiliary current into the integrated auxiliary magnetic field generating structure, the method further includes: A read signal is applied to the magnetic tunnel junction stack structure to read the resistance state of the magnetic tunnel junction stack structure and obtain the operation result of the XOR logic.

[0014] Thirdly, the present invention also provides a magnetic random access memory array, comprising a plurality of magnetic random access memory cells as described in the first aspect, arranged in an array. Multiple magnetic random access memory (MRM) cells located in the same row share the integrated auxiliary magnetic field generating structure, and multiple MRM cells located in the same column share the spin-orbit torque layer.

[0015] In some embodiments, the magnetic random access memory array is used to perform XOR logic operations in parallel on the multi-row, multi-column magnetic random access memory cells.

[0016] Fourthly, an in-memory computing device includes a magnetic random access memory array as described in the third aspect, the magnetic random access memory array being used to perform computing tasks according to an XOR logic operation while storing data.

[0017] This invention achieves on-chip field-free writing by replacing an external magnetic field source with a built-in integrated auxiliary magnetic field generating structure. This solution does not require changing the core film material of the magnetic tunnel junction stack or introducing a complex multilayer coupling structure, and is compatible with current conventional semiconductor processes and conventional magnetic tunnel junction stacks. Furthermore, since the magnetic field is generated instantaneously by the current inside the magnetic random access memory (MRRAM) cell, it avoids crosstalk problems caused by stray magnetic fields between adjacent MRRAM cells, which is beneficial for achieving high-density integration. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced one by one below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0019] Figure 1 This is a cross-sectional structural schematic diagram of a magnetic random access memory cell provided in an embodiment of the present invention; Figure 2 This is a cross-sectional structural schematic diagram of another magnetic random access memory cell provided in an embodiment of the present invention; Figure 3 This is a cross-sectional structural schematic diagram of another magnetic random access memory cell provided in an embodiment of the present invention; Figure 4This is a three-dimensional structural schematic diagram of another magnetic random access memory cell provided in an embodiment of the present invention; Figure 5 This is a cross-sectional structural schematic diagram of another magnetic random access memory cell provided in an embodiment of the present invention; Figure 6 This is a flowchart illustrating an information operation control method for a magnetic random access memory cell provided in an embodiment of the present invention; Figure 7 This is a current timing diagram of an information writing operation on a magnetic random access memory cell provided in an embodiment of the present invention; Figure 8 This is a schematic diagram of the high and low resistance states of a magnetic tunnel junction stack structure corresponding to different polarity combinations provided in an embodiment of the present invention; Figure 9 This is a three-dimensional structural schematic diagram of a magnetic random access memory array provided in an embodiment of the present invention; Figure 10 This is a cross-sectional structural diagram of a magnetic random access memory array provided in an embodiment of the present invention. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0021] The rapid development of emerging technologies such as the Internet of Things (IoT) and artificial intelligence (AI) has presented numerous challenges to mainstream computing hardware architectures in handling massive amounts of data. Traditional hardware systems based on the von Neumann architecture suffer from slow speeds and increased power consumption due to the physical separation between the processor and memory, resulting in the memory wall problem. The emergence of new computing architectures, such as in-memory computing, offers a viable solution. New non-volatile memories (NMRs) offer advantages such as data retention during power loss and low power consumption, making them well-suited for in-memory computing. Among current mainstream NMRs, magnetic random access memory (MRRAM) boasts high write speeds, high erase / write cycles, and high stability, attracting widespread attention in the in-memory computing field and becoming a leading candidate for next-generation NMRs.

[0022] The core structure of magnetic random access memory (MRM) is the magnetic tunnel junction, a sandwich structure consisting of two ferromagnetic layers sandwiching an oxide barrier layer. When the magnetic moments of the two ferromagnetic layers are in the same direction, the magnetic tunnel junction is in a low-resistance state; when the magnetic moments are in opposite directions, it is in a high-resistance state. Based on different methods of changing the resistance state of the magnetic tunnel junction, MRM has undergone three generations of development. As the third generation of MRM, Spin-Orbit Torque MRAM (SOT-MRAM) boasts sub-ns ultrafast write speeds and sub-pJ cell write power consumption. In a spin-orbit torque magnetic random access memory (SRAM), the cell structure consists of a spin-orbit torque layer and a magnetic tunnel junction placed on top of it. When current is passed into the spin-orbit torque layer, a spin current is generated by the spin Hall effect. This spin current is then injected into the magnetic layer adjacent to the spin-orbit torque layer, generating a spin-orbit torque to change the direction of its magnetic moment. This alters the relative orientation between the magnetic moments of the two ferromagnetic layers, ultimately changing the resistance state of the magnetic tunnel junction and completing the writing of information.

[0023] Based on the different magnetic anisotropies of the magnetic layers in the magnetic tunnel junction, spin-orbit torque magnetic random access memories (p-SOT-MRAMs) can be divided into in-plane magnetic anisotropy (IMA) and perpendicular magnetic anisotropy (PMA). In-plane MMA cells require a specific aspect ratio, such as an ellipse, to stabilize the easy magnetization axis; perpendicular MMA cells can be circular. Therefore, perpendicular MMA can achieve high-density device arrays, potentially enabling larger-scale and more efficient in-memory computing hardware. However, writing to p-SOT-MRAM states requires applying an external magnetic field along the write current direction to assist in deterministic state flipping of the magnetic tunnel junction, a characteristic that limits the practical application of p-SOT-MRAM.

[0024] Achieving information writing to p-SOT-MRAM without an external auxiliary magnetic field is a current hot research topic. Existing technical solutions mainly achieve field-free flipping through the design of spin-orbit torque layer materials, film stack structures, device structures, and information writing strategies. For example, the first existing solution uses a low-symmetry single-crystal thin film material as the spin-orbit torque material; its low-symmetry plane has natural symmetry breaking on both sides, thus enabling field-free information writing. The second existing solution uses an in-plane magnetic layer to generate an interlayer coupling effect between the in-plane magnetic layer and the perpendicular magnetic layer through a heavy metal layer, providing an effective in-plane field for field-free information writing. The third existing solution integrates a magnetic hard mask structure on the p-SOT-MRAM cell; the magnetic hard mask structure can generate a stray magnetic field to provide an in-plane magnetic field. The fourth existing solution uses the spin-transfer torque effect to assist the spin-orbit torque for information writing.

[0025] However, in the first existing scheme, the growth of single-crystal thin-film materials is difficult to integrate with existing magnetic tunnel junction stacks, and large-area growth of single-crystal thin-film materials is challenging, making large-scale fabrication difficult. While the second existing scheme is well-compatible with current magnetic tunnel junction stacks, its versatility is poor, limited to a three-layer structure of in-plane ferromagnetic layer / heavy metal layer / vertical magnetic layer. It cannot incorporate materials with higher spin-orbit torque efficiency, such as topological insulators. Furthermore, the in-plane magnetic layer shunts the write current flowing into the spin-orbit torque layer, reducing information writing efficiency. In the third existing scheme, when the distance between two unit structures decreases, crosstalk of stray magnetic fields occurs between the magnetic hard masks of adjacent units, reducing information writing stability and device density. Moreover, as device size shrinks, the stray magnetic field provided by the magnetic hard mask becomes unstable. In the fourth existing scheme, since a large current flowing vertically through the magnetic tunnel junction is still required to generate spin-orbit torque, the write endurance of the device is reduced to some extent.

[0026] To address the aforementioned technical problems, this invention proposes a magnetic random access memory cell and its information operation control method and array. Figure 1 This is a cross-sectional structural diagram of a magnetic random access memory (MRM) cell provided in an embodiment of the present invention. Figure 1 As shown, the magnetic random access memory cell includes a magnetic tunnel junction stacked structure 1 and an integrated auxiliary magnetic field generating structure 2. The magnetic tunnel junction stacked structure 1 includes at least a spin-orbit torque layer 11, a free layer 12, a barrier layer 13, and a reference layer 14 stacked sequentially. The free layer 12 and the reference layer 14 have perpendicular magnetic anisotropy. The integrated auxiliary magnetic field generating structure 2 is used to pass an auxiliary current I. Oe This generates an in-plane magnetic field within the plane of free layer 12.

[0027] Specifically, the integrated auxiliary magnetic field generating structure 2 refers to the structure built into the magnetic random access memory unit and used to carry the auxiliary current I. Oe And utilize the Oersted field B generated by this auxiliary current Oe Conductive components are used to generate a local magnetic field. The integrated auxiliary magnetic field generating structure 2 is electrically isolated from the write path used to generate spin-orbit torque, i.e., the spin-orbit torque layer 11.

[0028] The core physical mechanism for field-free writing in magnetic random access memory (MRM) cells lies in the synergistic effect of the Oersted effect and the spin-orbit torque effect in the magnetic field generated by current, as well as the design of the built-in integrated auxiliary magnetic field generating structure 2 for localization and directionality of the magnetic field. When an auxiliary current I is applied to the integrated auxiliary magnetic field generating structure 2... Oe At that time, the auxiliary current I Oe It will generate a ring-shaped Oersted field B in the surrounding space. Oe By integrating the auxiliary magnetic field generator 2 within the magnetic random access memory unit and designing its spatial position and geometry relative to the magnetic tunnel junction stack structure 1, the Oersted field B can be precisely controlled. Oe Vector distribution within the spatial region where free layer 12 is located. The key design objective is to make the Oersted field B... Oe There is a significant component within the plane of the free layer 12, namely the in-plane magnetic field, and the direction of this in-plane component is set to be consistent with the write current I that will be subsequently introduced into the spin-orbit torque layer 11. SOT The directions are parallel. This built-in design ensures that the required guiding magnetic field comes directly from the wire current inside the chip, rather than from an external, separate magnet.

[0029] In terms of control timing, an auxiliary current I can be supplied to the integrated auxiliary magnetic field generating structure 2. Oe At that time, a writing current I is passed into the spin-orbit torque layer 11. SOT The write current I SOT A spin-polarized current is generated and injected into the adjacent free layer 12 via the spin Hall effect or the Rashba-Edelstein effect. The injected spin current exerts a spin-orbit torque on the magnetic moment of the free layer 12. For the free layer 12, which has perpendicular magnetic anisotropy, the direction of this torque is primarily in-plane and perpendicular to the write current I. SOT The direction it attempts to cause the magnetic moment to precess around its easy axis. Based solely on the spin-orbit torque, the magnetic moment of free layer 12 will exist in two possible stable states, either upward or downward, and cannot definitively flip to the target state. At this point, the direction generated by the integrated auxiliary magnetic field generating structure 2 is related to the write current I. SOTThe parallel in-plane magnetic field plays a crucial role in breaking symmetry. This in-plane magnetic field exerts an additional torque on the magnetic moment of free layer 12, acting in conjunction with the spin-orbit torque. Through their combined action, the precessing magnetic moment is effectively pulled to a deterministic magnetic moment state. Ultimately, the relative orientation of the magnetic moments of free layer 12 and reference layer 14 is altered, leading to a change in the resistance state of the magnetic tunnel junction stack structure 1, thus completing the information writing process.

[0030] Therefore, in this embodiment of the invention, when information needs to be written, a writing current I is supplied to the spin-orbit torque layer 11 as a writing channel. SOT Apply writing current I SOT Subsequently, the spin-orbit torque layer 11 generates a spin current that is injected into the free layer 12, meaning that the spin-orbit torque layer 11 generates a spin-orbit torque acting on the free layer 12. On the other hand, an auxiliary current I is supplied to the integrated auxiliary magnetic field generating structure 2. Oe By designing the position of the integrated auxiliary magnetic field generating structure 2 relative to the free layer 12, it acts as the Oersted field B of the local auxiliary magnetic field. Oe The region where free layer 12 is located has a current I that is similar to the write current. SOT The parallel in-plane magnetic field components break the symmetry of the system and work together with the spin orbital torque to drive the magnetic moment of the free layer 12 to complete the precession and deterministic flip, thereby changing the resistance state of the magnetic tunnel junction stack structure 1 and realizing information writing.

[0031] In summary, this embodiment of the invention achieves on-chip fieldless writing by replacing an external magnetic field source with a built-in integrated auxiliary magnetic field generating structure 2. This solution does not require changing the core film material of the magnetic tunnel junction stack structure 1 or introducing a complex multilayer coupling structure, and is compatible with current conventional semiconductor processes and conventional magnetic tunnel junction stacks. Furthermore, since the magnetic field is generated instantaneously by the current inside the magnetic random access memory chip, the crosstalk problem of stray magnetic fields between adjacent magnetic random access memory cells is avoided, which is beneficial for achieving high-density integration.

[0032] In some embodiments, the integrated auxiliary magnetic field generating structure 2 is disposed on the side of the spin-orbit torque layer 11 away from the free layer 12 and is electrically isolated from the spin-orbit torque layer 11. The extension direction of the integrated auxiliary magnetic field generating structure 2 is perpendicular to the stacking direction of the magnetic tunnel junction stack structure 1.

[0033] Specifically, the stacking direction refers to the vertical direction in which each film layer in the magnetic tunnel junction stacked structure 1 is deposited sequentially. The integrated auxiliary magnetic field generating structure 2 can be, for example, a metal interconnect, and the extension direction refers to the length direction of the metal interconnect. Placing the integrated auxiliary magnetic field generating structure 2 below the spin-orbit torque layer 11, i.e., on the side of the spin-orbit torque layer 11 away from the free layer 12, is a preferred and easily integrated layout. The extension direction of the integrated auxiliary magnetic field generating structure 2 is perpendicular to the stacking direction. When the auxiliary current I... Oe When passing along this extension direction, a ring-shaped Oersted field B will be generated around it, surrounding the current lines. Oe At the horizontal position of free layer 12, the Oersted field B Oe The in-plane component and the writing current I SOT The flow direction within the spin-orbit torque layer 11 is parallel, thus satisfying the magnetic field direction condition required for deterministic flipping. Simultaneously, the integrated auxiliary magnetic field generating structure 2 is electrically isolated from the spin-orbit torque layer 11, ensuring the write current I... SOT Path and auxiliary current I Oe The paths are independent of each other and do not interfere with each other.

[0034] Therefore, in this embodiment of the invention, by setting the integrated auxiliary magnetic field generating structure 2 on the side of the spin-orbit torque layer 11 away from the free layer 12 and electrically isolating it from the spin-orbit torque layer 11, and by extending the integrated auxiliary magnetic field generating structure 2 perpendicular to the stacking direction of the magnetic tunnel junction stack structure 1, the integrated auxiliary magnetic field generating structure 2 can be conveniently implemented using the metal interconnect layer in the back-end process of integrated circuits, has good compatibility with standard semiconductor processes, and has a simple overall structure that is easy to fabricate and integrate.

[0035] In some embodiments, in the projection along the stacking direction, at least a portion of the integrated auxiliary magnetic field generating structure 2 overlaps with the magnetic tunnel junction stack structure 1.

[0036] Specifically, projection overlap refers to the overlap between the integrated auxiliary magnetic field generating structure 2 and the magnetic tunnel junction stacked structure 1 on a plane when viewed from the stacking direction. By ensuring that the integrated auxiliary magnetic field generating structure 2 and the magnetic tunnel junction stacked structure 1 at least partially overlap in the vertical projection, the auxiliary current I in the integrated auxiliary magnetic field generating structure 2 can be ensured. Oe The generated Oersted field B Oe It can more directly and effectively cover the free layer 12 region, optimize the magnetic field coupling efficiency, and make the auxiliary current I used to generate the effective in-plane magnetic field component more efficient. OeMinimizing the area helps reduce power consumption. Simultaneously, the larger the overlap area between the integrated auxiliary magnetic field generating structure 2 and the magnetic tunnel junction stacked structure 1 in the projection along the stacking direction, the more uniform the magnetic field effect. Preferably, in the projection along the stacking direction, the integrated auxiliary magnetic field generating structure 2 completely covers the magnetic tunnel junction stacked structure 1, the width of the integrated auxiliary magnetic field generating structure 2 is greater than or equal to the width of the magnetic tunnel junction stacked structure 1, and the two are centered to ensure that the in-plane magnetic field component of the Oersted field generated by the current in the integrated auxiliary magnetic field generating structure 2 is as large as possible within the plane of the magnetic tunnel junction stacked structure 1.

[0037] Therefore, by integrating at least a portion of the auxiliary magnetic field generating structure 2 into the projection in the stacking direction, the present invention improves the utilization efficiency of the auxiliary magnetic field, helps to reduce the total energy consumption of the write operation, and facilitates obtaining more stable and consistent flip-flop behavior, thereby improving the reliability of the magnetic random access memory cell.

[0038] Figure 2 This is a cross-sectional structural schematic diagram of another magnetic random access memory cell provided in an embodiment of the present invention. (Combined with...) Figure 1 and Figure 2 The magnetic random access memory unit also includes a bottom electrode 3, which is electrically connected to the spin-orbit torque layer 11. The integrated auxiliary magnetic field generating structure 2 is fabricated in the same layer as the first metal interconnect 5 and is electrically isolated. The bottom electrode 3 is connected to an external circuit through the first metal interconnect 5.

[0039] Specifically, the bottom electrode 3 refers to the electrode used to introduce or extract write current I from the external circuit to the spin-orbit torque layer 11. SOT Conductive electrodes, for example Figure 2 As shown, the bottom electrode 3 can be electrically connected to the first metal interconnects 5 on both sides through the first metal via 4, thereby achieving electrical connection with external circuits, such as control transistors and other devices. Furthermore, the magnetic random access memory cell also includes an insulating dielectric layer 6 filled to isolate electrical connections between the metal parts. Co-layer fabrication refers to the integrated auxiliary magnetic field generating structure 2 and the first metal interconnect 5 being formed on the same dielectric layer plane using the same material deposition and patterning process in the same process step. In integrated circuit manufacturing, the first metal interconnect 5 is formed from a single layer of metal. In this invention, the first metal interconnect 5 and the integrated auxiliary magnetic field generating structure 2 are simultaneously patterned and formed in the same process layer. Although they are located on the same horizontal plane in space, they can be physically separated through patterning design, thereby achieving electrical isolation between the integrated auxiliary magnetic field generating structure 2 and the first metal interconnect 5. The first metal interconnect 5 is dedicated to connecting the spin-orbit torque layer 11, while the integrated auxiliary magnetic field generating structure 2 is dedicated to carrying the auxiliary current I. Oe .

[0040] Therefore, by setting the integrated auxiliary magnetic field generating structure 2 and the first metal interconnect 5 to be fabricated in the same layer and electrically isolated, the integrated auxiliary magnetic field generating structure 2 does not require the introduction of additional, independent process steps or masks, and can be compatible with conventional magnetic random access memory processes, which is conducive to realizing industrial applications.

[0041] In some embodiments, the integrated auxiliary magnetic field generating structure 2 reuses word lines or bit lines in the array where the magnetic random access memory cells are located.

[0042] Specifically, in a magnetic random access memory (MRM) array, word lines are control lines used to select or activate all MRM cells in a specific row. By applying a selection voltage to a word line, the selection transistor of that row of MRM cells can be turned on, putting it into a read / write state. Bit lines are signal lines used to read the data status of MRM cells or write data to MRM cells. Bit lines can be connected to a sense amplifier to detect changes in the resistance of MRM cells to read data, or to carry the voltage corresponding to the written data during writing.

[0043] The reuse of the integrated auxiliary magnetic field generating structure 2 is not physically an additional, single-function wire, but rather a metal interconnect already existing in the magnetic random access memory array that performs one of the aforementioned inherent functions. The key to achieving this without affecting the original function of the metal interconnect lies in time-sharing operation and circuit design. Regarding time-sharing operation, the operation of the magnetic random access memory array is divided into different timing stages, such as the addressing stage, writing stage, reading stage, and standby stage. An auxiliary current I is then supplied to the integrated auxiliary magnetic field generating structure 2. Oe This operation is performed only during specific write operation periods. During other periods, such as addressing, reading, or standby, the corresponding metal interconnects continue to perform their original word line, bit line, or ground line functions. Precise timing control ensures that these two functions do not conflict at the same time.

[0044] Regarding circuit multiplexing, taking the selection of a specific word line as an example, during normal addressing or read operations, this word line is connected to the row decoder to transmit the row selection signal. When write and logical operations are required, the word line is temporarily switched from the row decoder to the auxiliary current source while the selected row is activated. At this time, in addition to selecting the magnetic random access memory cell for that row, the word line also functions as an integrated auxiliary magnetic field generator 2, carrying the auxiliary current I used to generate the in-plane auxiliary magnetic field. Oe Auxiliary current I Oe After completion, the word line connection is switched back to the row decoder, restoring its normal word line function. The principle is similar for bit line multiplexing; both utilize appropriate switching or driving circuit designs to temporarily connect them to an auxiliary current source during the write phase.

[0045] Therefore, this invention achieves the generation of an auxiliary magnetic field without altering the basic wiring architecture of the magnetic random access memory (MRMemory) array, avoiding the need to reserve wiring space for dedicated auxiliary lines and significantly improving the integration density of the MRMemory array, which is crucial for memory chips pursuing high capacity. Furthermore, it eliminates the need to introduce new, complex metal layers or change existing interconnect topologies, exhibiting excellent compatibility with standard MRMemory design flows and manufacturing processes.

[0046] Figure 3 This is a cross-sectional structural schematic diagram of another magnetic random access memory cell provided in an embodiment of the present invention. (Combined with...) Figures 1 to 3 Based on the above embodiments, the integrated auxiliary magnetic field generating structure 2 includes a conductive core layer 21 and a magnetic flux gathering coating layer 22, wherein the magnetic flux gathering coating layer 22 covers at least part of the sidewalls and / or at least part of the bottom wall of the conductive core layer 21.

[0047] Specifically, the flux-gathering coating layer 22 refers to a thin layer made of a high-permeability material that wraps around the conductive core layer 21. The conductive core layer 21 is the main body that carries the current, and an auxiliary current I is passed through the conductive core layer 21. Oe To generate the Oersted field B Oe The flux-concentrating coating layer 22, as a high-permeability material, can guide and concentrate magnetic field lines, optimizing the spatial distribution of the magnetic field. The flux-concentrating coating layer 22 can concentrate more magnetic flux onto the plane of the free layer 12, enhancing the magnetic field strength at the location of the free layer 12. Simultaneously, the flux-concentrating coating layer 22 can confine the magnetic field, reducing diffusion into other unwanted directions, thereby achieving the same auxiliary current I... Oe To obtain a stronger effective in-plane magnetic field, or to achieve the required magnetic field strength with a smaller current.

[0048] Therefore, by providing a magnetic flux gathering coating layer 22 to cover at least part of the sidewalls and / or at least part of the bottom wall of the conductive core layer 21, and preferably by providing a magnetic flux gathering coating layer 22 to cover all the sidewalls and all the bottom wall of the conductive core layer 21, the auxiliary current I is significantly improved. Oe Generates Oersted field B Oe This improved efficiency helps to further reduce write power consumption. Simultaneously, the enhanced local magnetic field makes switching more reliable, increasing the device's operating margin. Preferably, a flux-converging coating layer 22 can be provided to cover two sidewalls and one bottom wall of the conductive core layer 21, exposing only the top surface of the conductive core layer 21.

[0049] In some embodiments, the integrated auxiliary magnetic field generating structure 2 is a metal interconnect; the cross-sectional shape of the integrated auxiliary magnetic field generating structure 2 is rectangular or trapezoidal; the width of the integrated auxiliary magnetic field generating structure 2 is 10 nanometers to 100 nanometers; the thickness of the integrated auxiliary magnetic field generating structure 2 is 50 nanometers to 200 nanometers; and the spacing between the integrated auxiliary magnetic field generating structure 2 and the free layer 12 in the stacking direction is 50 nanometers to 150 nanometers.

[0050] Specifically, the integrated auxiliary magnetic field generating structure 2 can be implemented using metal interconnects compatible with integrated circuit back-end processes, such as copper, aluminum, or other alloy wires with low resistivity. The cross-sectional shape of the integrated auxiliary magnetic field generating structure 2 is preferably rectangular or trapezoidal. A rectangular cross-section is easier to process control, and the magnetic field distribution calculation is relatively simple; a trapezoidal cross-section better conforms to the morphology of certain practical etching processes, and its sloping sidewalls are beneficial for creating a certain converging effect on the magnetic field distribution. The width of the integrated auxiliary magnetic field generating structure 2 is preferably in the range of 100 nanometers to 200 nanometers, and the thickness is preferably in the range of 50 nanometers to 200 nanometers. This size range matches modern nanoscale semiconductor process nodes. The width and thickness directly affect the resistance and current density of the wires, and thus affect the Oersted field B generated under a given current. Oe Strength. Too small a size may result in excessive resistance, increased power consumption, and higher manufacturing difficulty; too large a size may unnecessarily occupy chip area.

[0051] The spacing between the integrated auxiliary magnetic field generating structure 2 and the free layer 12 in the stacking direction is preferably 50 nanometers to 150 nanometers. This spacing refers to the vertical distance from the top surface of the integrated auxiliary magnetic field generating structure 2 to the bottom surface of the free layer 12. The magnetic field strength generated by the current decreases rapidly with increasing distance; this size range ensures that a reasonable auxiliary current I is generated. Oe Below, a sufficiently strong in-plane magnetic field component is generated at position 12 of the free layer to effectively assist in magnetic moment reversal. Too small a spacing may pose integration challenges and increase parasitic capacitance; too large a spacing requires an auxiliary current I... Oe The increase is proportional, leading to a sharp rise in power consumption.

[0052] Figure 4 This is a three-dimensional structural diagram of a magnetic random access memory (MRM) cell provided in an embodiment of the present invention. Figure 5 This is a cross-sectional structural schematic diagram of another magnetic random access memory cell provided in an embodiment of the present invention. (Combined with...) Figure 4 and Figure 5 The integrated auxiliary magnetic field generating structure 2 includes at least one first auxiliary conductive part disposed on the side of the magnetic tunnel junction stacked structure 1, and at least one second auxiliary conductive part disposed on the side of the spin-orbit torque layer 11 away from the free layer 12. The integrated auxiliary magnetic field generating structure 2 is electrically isolated from the spin-orbit torque layer 11. The first auxiliary conductive part is... Figure 4 and Figure 5 The portion of the integrated auxiliary magnetic field generating structure 2 arranged vertically, namely the second auxiliary conductive part. Figure 4 and Figure 5 The integrated auxiliary magnetic field generating structure 2 is a portion arranged horizontally. The integrated auxiliary magnetic field generating structure 2 is not limited to a single location; it can include multiple parts, such as at least one first auxiliary conductive portion disposed on the side of the magnetic tunnel junction stack structure 1, and at least one second auxiliary conductive portion disposed on the side of the spin-orbit torque layer 11 away from the free layer 12. It is important to emphasize that both the first and second auxiliary conductive portions must be electrically isolated from the spin-orbit torque layer 11 to ensure the write current I... SOT Path independence.

[0053] When the integrated auxiliary magnetic field generating structure 2 includes both a first auxiliary conductive part on the side and a second auxiliary conductive part below, the integrated auxiliary magnetic field generating structure 2 forms a three-dimensional covering of the free layer 12, and the first and second auxiliary conductive parts can work together. For example, when the same auxiliary current is passed through the first and second auxiliary conductive parts, the magnetic fields generated by the two are vector-superimposed in the region of the free layer 12, forming a more uniform or stronger composite in-plane magnetic field. The direction and distribution of the composite magnetic field can be optimized through design. Thus, the embodiments of the present invention provide higher design flexibility and magnetic field control capability. By setting auxiliary conductive parts at multiple locations, the problem of magnetic field inhomogeneity or insufficient strength that may exist at a single location can be overcome, which is especially suitable for smaller devices or applications with extremely high requirements for flip-flop consistency.

[0054] Figure 6 This is a flowchart illustrating an information operation control method for a magnetic random access memory (MRMemory) cell according to an embodiment of the present invention. The information operation control method for the MRMemory cell is used to control the MRMemory cell as described in the above embodiment. Figure 6 As shown, the information operation control method for a magnetic random access memory (MRM) cell includes the following steps: S101. Control the supply of auxiliary current to the integrated auxiliary magnetic field generating structure to generate an in-plane magnetic field in the plane where the free layer is located.

[0055] S102. Control the flow of write current into the spin-orbit torque layer to generate a spin-orbit torque effect on the free layer. The effective pulse of the auxiliary current overlaps the effective pulse of the write current in time, and the direction of the in-plane magnetic field is parallel to the flow direction of the write current in the spin-orbit torque layer.

[0056] First, an auxiliary current I is applied to the integrated auxiliary magnetic field generating structure 2. OeTo establish a stable in-plane magnetic field within the plane of the free layer 12; subsequently, a writing current I is applied to the spin-orbit torque layer 11. SOT Writing current I SOT The spin-orbit torque exerted on free layer 12 causes the magnetic moment of free layer 12 to precess. During the writing current I... SOT During the entire duration, the auxiliary current I Oe Maintain this state at all times to ensure the in-plane magnetic field remains constant. After writing is complete, first remove the write current I. SOT Then remove the auxiliary current I Oe Crucially, the direction of the in-plane magnetic field must be controlled to be aligned with the writing current I. SOT The flow direction in the spin orbit torque layer 11 is parallel. This parallel relationship ensures that the in-plane magnetic field can break the symmetry of the flip, thereby assisting the spin orbit torque to flip the magnetic moment of the free layer 12 to a certain state, such as upward or downward, to realize information writing, and correspondingly set the resistance state of the magnetic tunnel junction to a high resistance state or a low resistance state.

[0057] Figure 7 This is a current timing diagram of an information writing operation on a magnetic random access memory cell provided by an embodiment of the present invention. Figure 7 This illustrates the write current I during an information write operation to a magnetic random access memory cell. SOT and auxiliary current I Oe The duration and phase relationship between them. Specifically, the auxiliary current I can be set. Oe The effective pulse width is greater than or equal to the write current I. SOT Effective pulse width to ensure auxiliary current I Oe In the write current I SOT A magnetic field is provided during the application, thereby providing a write current I SOT The writing of the magnetic tunnel junction stack structure 1 is completed within the effective pulse width. Specifically, Figure 7 The time t1 in the equation is the auxiliary current I. Oe Prior to the write current I SOT The time of generation, time t2 is the auxiliary current I Oe Following the write current I SOT The removal time, t1 and t2, are both greater than or equal to 0 to ensure that at least the written current I is maintained. SOT The auxiliary magnetic field exists for a continuous period of time.

[0058] correspond Figure 7 The timing diagram shows that the write operation of the magnetic random access memory cell follows the timing control flow as follows: First, an auxiliary current I is supplied to the integrated auxiliary magnetic field generating structure 2. OeTo establish a stable in-plane auxiliary magnetic field along a predetermined direction within the plane of the free layer 12; subsequently, a writing current I is introduced into the spin-orbit torque layer 11. SOT Its direction is parallel to the direction of the in-plane magnetic field, and the combined effect of the two drives the magnetic moment of the free layer 12 to complete a deterministic flip; after writing is completed, the writing current I is first removed. SOT Then remove the auxiliary current I Oe In this process, the auxiliary current I Oe The effective pulse width is greater than or equal to the write current I. SOT The effective pulse width ensures that the auxiliary magnetic field remains effective throughout the writing process, thereby guaranteeing the reliability and consistency of the flipping process.

[0059] Therefore, this embodiment of the invention achieves the state reversal of the magnetic tunnel junction stacked structure 1 by introducing currents with the same effective pulse width and phase into the spin-orbit torque layer 11 and the integrated auxiliary magnetic field generating structure 2. Simultaneously, by precisely controlling the timing and direction of the two currents, deterministic magnetization reversal control without an external magnetic field can be achieved, providing a fundamental electrical interface for writing and logically operating the magnetic random access memory (MRAM) cell states.

[0060] In some embodiments, a write current I is controlled to be supplied to the spin-orbit torque layer 11. SOT Control the supply of auxiliary current I to the integrated auxiliary magnetic field generating structure 2 Oe This includes: controlling the write current I SOT polarity and auxiliary current I Oe The polarity of the polarity combination ensures that the correspondence between the polarity combination and the final resistance state of the magnetic tunnel junction stack structure 1 conforms to the XOR logic; where the polarity combination is the write current I. SOT The polarity and auxiliary current I Oe The polar combination.

[0061] Specifically, the XOR logic means that the output is 1 when the two input logic values ​​are the same, and 0 when they are different. Write current I SOT and auxiliary current I Oe Each can be independently set to positive or negative polarity, with one polarity direction defined as logic 1 and the opposite direction as logic 0. Table 1 is the truth table of the XOR logic function implemented by the magnetic random access memory (MRRAM) unit.

[0062] Table 1 Figure 8 This is a schematic diagram illustrating the high and low resistance states of a magnetic tunnel junction stacked structure corresponding to different polarity combinations, provided in an embodiment of the present invention. (Combined with...) Figure 8 And Table 1, for example, defines Figure 8 Right-hand flow writing current ISOT The corresponding logic is 1, indicating a left-flowing write current I. SOT , Figure 8 The diagram in the middle is represented as -I SOT The corresponding logic value is 0. Definition Figure 8 Internal flow of auxiliary current I Oe The corresponding logic value is 1, indicating an external flow of auxiliary current I. Oe , Figure 8 The diagram in the middle is represented as -I Oe The corresponding logic is 0. In the magnetic tunnel junction stack structure 1, the high-resistivity state AP corresponds to logic 1, and the low-resistivity state P corresponds to logic 0. Additionally, Figure 8 The vertical arrows in the free layer 12 and reference layer 14 shown in the figure indicate the magnetization state of the corresponding film layers.

[0063] Changing the combination of the polarities of the two currents can alter the corresponding Oersted field B. Oe The polarity changes, and the Oersted field B of different polarities Oe Corresponding to different write polarities of magnetic random access memory cells, the high and low resistance states of the magnetic tunnel junction stack structure 1 can be changed. Write current I SOT and auxiliary current I Oe When both are positive, the magnetic tunnel junction stack structure 1 is in a high-resistivity state (AP); when the write current I... SOT The auxiliary current I is negative. Oe When positive, the magnetic tunnel junction stack structure 1 is in a low-resistivity state P; when the write current I... SOT If positive, the auxiliary current I Oe When the value is negative, the magnetic tunnel junction stack structure 1 is in a low-resistivity state P; when the write current I... SOT The auxiliary current I is negative. Oe When the value is negative, the magnetic tunnel junction stack structure 1 is in the high-resistance state AP. This ensures that the mapping relationship between the polarity combination of the two currents and the final resistance state of the magnetic tunnel junction stack structure 1 strictly conforms to the XOR gate logic shown in Table 1, and the result of the XOR operation is stored as the resistance state of the magnetic tunnel junction stack structure 1.

[0064] Therefore, this embodiment of the invention changes the write current I. SOT and auxiliary current I Oe The polarity of the magnetic tunnel junction stack structure 1 enables writing to both high-resistivity and low-resistivity states. Only one magnetic random access memory (MRAM) cell is needed to complete the XOR logic operation within a single write cycle, achieving computation-storage or in-memory computing integration. This greatly simplifies the hardware and operational steps required for logical operations, laying the foundation for building high-energy-efficiency in-memory computing systems. Furthermore, the result of the XOR logic operation is stored in the magnetic tunnel junction stack structure 1, and array-level XOR operations can be achieved by expanding the MRAM cells.

[0065] In some embodiments, a write current I is controlled to be supplied to the spin-orbit torque layer 11. SOT Control the supply of auxiliary current I to the integrated auxiliary magnetic field generating structure 2 Oe Then, it also includes: controlling the application of a read signal to the magnetic tunnel junction stack 1 to read the resistance state of the magnetic tunnel junction stack 1 and obtain the operation result of the XOR logic.

[0066] Specifically, the read signal refers to a voltage or current with a small amplitude and short duration, insufficient to change the direction of the magnetic moment of the free layer 12. After the write operation is completed, the resistance state of the magnetic tunnel junction stack 1 has stored the result of the XOR operation. To read this result, a read signal needs to be applied to the magnetic tunnel junction stack 1. This signal can be applied across the magnetic tunnel junction stack 1 via the top electrode 7 connected to the reference layer 14 and the bottom electrode 3 connected to the spin-orbit torque layer 11. The top electrode 7 can be connected to the second metal interconnect 9 via the second metal via 8. Since the strength of the read signal is designed to be below the threshold that would cause a magnetic moment reversal, it is non-destructive. The read current flowing through the magnetic tunnel junction stack 1 or the voltage drop across the magnetic tunnel junction stack 1 will reflect its resistance value. By converting this resistance state to a logic level of 1 or 0 through an external sense amplifier, the result of the previous XOR logic operation can be obtained.

[0067] Therefore, by controlling the application of a read signal to the magnetic tunnel junction stack 1 to read the resistance state of the magnetic tunnel junction stack 1 and obtain the operation result of the XOR logic, this embodiment of the invention provides a standard method for non-destructively reading the stored result, and completes the entire information processing flow from input, calculation, storage to reading.

[0068] This invention also provides a magnetic random access memory array. Figure 9 This is a three-dimensional structural diagram of a magnetic random access memory array provided in an embodiment of the present invention. Figure 10 This is a cross-sectional structural diagram of a magnetic random access memory array provided in an embodiment of the present invention. Combined with... Figure 9 and Figure 10 The magnetic random access memory array includes multiple magnetic random access memory cells arranged in an array as described in the above embodiments, and therefore possesses the beneficial effects described in the above embodiments, which will not be repeated here. Multiple magnetic random access memory cells located in the same row share the integrated auxiliary magnetic field generating structure 2, and multiple magnetic random access memory cells located in the same column share the spin-orbit torque layer 11.

[0069] Specifically, a magnetic random access memory (MRM) array refers to a collection of multiple MRM cells arranged in rows and columns on a two-dimensional plane, and it is the core component of a memory chip. All MRM cells in each row share the same integrated auxiliary magnetic field generating structure 2. When it is necessary to operate on a particular row of MRM cells, an auxiliary current I is applied through the shared integrated auxiliary magnetic field generating structure 2 of that row. Oe This generates an in-plane magnetic field at the corresponding location of all magnetic random access memory (MRM) cells in that row. All MRM cells in each column share the same spin-orbit torque layer 11. When it is necessary to operate on a column of MRM cells, a write current I is applied through the shared spin-orbit torque layer 11 of that column. SOT By combining row and column selection circuits, a single magnetic random access memory (MRM) cell in the MRM array can be uniquely selected for independent operation; or, by activating multiple rows and columns simultaneously, a sub-MRM array or multiple MRM cells can be operated in parallel.

[0070] Therefore, by setting multiple magnetic random access memory cells located in the same row to share the integrated auxiliary magnetic field generating structure 2, and multiple magnetic random access memory cells located in the same column to share the spin-orbit torque layer 11, the row-column shared structure greatly simplifies the interconnection layout, reduces the number of independent control lines, and is conducive to improving array integration and scalability, providing a feasible layout scheme for large-scale storage or computing arrays.

[0071] In some embodiments, the magnetic random access memory array is used to perform XOR logic operations in parallel on multiple rows and columns of magnetic random access memory cells.

[0072] Specifically, the auxiliary current I corresponding to multiple rows can be... Oe Polarity is used as a set of input vectors to represent multiple columns of corresponding write current I. SOT Polarity serves as another set of input vectors. When these currents are applied simultaneously, each selected magnetic random access memory cell in the magnetic random access memory array will be affected by the auxiliary current I of its row. Oe Polarity and the write current I of the column SOT The XOR operations are performed independently and in parallel, with the results stored in the resistive state of their respective magnetic tunnel junction stack 1. For an m×n magnetic random access memory array, where m is the number of spin-orbit torque layers 11 and n is the number of integrated auxiliary magnetic field generating structures 2, m×n XOR logic operations can be completed within one write operation cycle, and the result of each XOR logic operation is stored in the corresponding magnetic tunnel junction stack 1. This achieves large-scale parallel logic operations at the magnetic random access memory array level, significantly improving computational throughput and energy efficiency.

[0073] This invention also provides an in-memory computing device, including a magnetic random access memory (MRM) array as described in the above embodiments, and therefore possesses the beneficial effects described in the above embodiments, which will not be repeated here. The MRM array is used to perform computational tasks according to an XOR logic operation while storing data.

[0074] Specifically, an in-memory computing device refers to a hardware device or system module that physically integrates data storage and computing functions. The in-memory computing device uses the aforementioned magnetic random access memory (MRM) array as its core computing and storage resource. The MRM array can serve as non-volatile memory for storing weights, input data, or intermediate results, and can also perform basic logical operations or more complex operations based on this during data read / write access, according to the information operation control methods described in the above embodiments. Peripheral control circuitry is responsible for generating and scheduling the required write current, auxiliary current, and read signals, and managing data input and output. Therefore, the in-memory computing device effectively alleviates the data transfer bottleneck between the processor and memory in the traditional von Neumann architecture, making it particularly suitable for applications requiring a large number of parallel multiply-accumulate operations or pattern matching, such as artificial intelligence, the Internet of Things, and signal processing, providing high-energy-efficiency, low-latency computing services.

[0075] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A magnetic random access memory (MRM) cell, characterized in that, include: A magnetic tunnel junction stacked structure includes at least a spin-orbit torque layer, a free layer, a barrier layer and a reference layer stacked sequentially, wherein the free layer and the reference layer have perpendicular magnetic anisotropy; An integrated auxiliary magnetic field generating structure is used to introduce an auxiliary current to generate an in-plane magnetic field in the plane where the free layer is located.

2. The magnetic random access memory unit according to claim 1, characterized in that, The integrated auxiliary magnetic field generating structure is disposed on the side of the spin-orbit torque layer away from the free layer and is electrically isolated from the spin-orbit torque layer. The extension direction of the integrated auxiliary magnetic field generating structure is perpendicular to the stacking direction of the magnetic tunnel junction stack structure.

3. The magnetic random access memory unit according to claim 2, characterized in that, In the projection along the stacking direction, at least a portion of the integrated auxiliary magnetic field generating structure overlaps with the magnetic tunnel junction stack structure.

4. The magnetic random access memory unit according to claim 2, characterized in that, Also includes: The bottom electrode is electrically connected to the spin-orbit torque layer. The integrated auxiliary magnetic field generating structure is fabricated in the same layer as the first metal interconnect and is electrically isolated. The bottom electrode is connected to an external circuit through the first metal interconnect.

5. The magnetic random access memory unit according to claim 2, characterized in that, The integrated auxiliary magnetic field generating structure reuses the word lines or bit lines in the array where the magnetic random access memory cell is located.

6. The magnetic random access memory unit according to claim 1 or 2, characterized in that, The integrated auxiliary magnetic field generating structure includes: A conductive core layer and a magnetic flux gathering coating layer, wherein the magnetic flux gathering coating layer covers at least a portion of the sidewalls and / or at least a portion of the bottom wall of the conductive core layer.

7. A magnetic random access memory array, characterized in that, It includes a plurality of magnetic random access memory cells as described in any one of claims 1-6, arranged in an array; Multiple magnetic random access memory (MRM) cells located in the same row share the integrated auxiliary magnetic field generating structure, and multiple MRM cells located in the same column share the spin-orbit torque layer.

8. A method for controlling information operation of a magnetic random access memory cell, characterized in that, The information operation control method for controlling a magnetic random access memory cell as described in any one of claims 1-6 includes: An auxiliary current is supplied to the integrated auxiliary magnetic field generating structure to generate the in-plane magnetic field in the plane where the free layer is located; A write current is controlled to be supplied to the spin-orbit torque layer to generate a spin-orbit torque on the free layer; The effective pulse of the auxiliary current overlaps the effective pulse of the write current in time, and the direction of the in-plane magnetic field is parallel to the flow direction of the write current in the spin-orbit torque layer.

9. The information operation control method for a magnetic random access memory cell according to claim 8, characterized in that, Controlling the flow of write current into the spin-orbit torque layer and controlling the flow of auxiliary current into the integrated auxiliary magnetic field generating structure, including: The polarity of the write current and the polarity of the auxiliary current are controlled such that the polarity combination corresponds to the final resistance state of the magnetic tunnel junction stack structure in an XOR logic manner; wherein, the polarity combination is the combination of the polarity of the write current and the polarity of the auxiliary current.

10. The information operation control method for a magnetic random access memory cell according to claim 9, characterized in that, After controlling the flow of a write current into the spin-orbit torque layer and controlling the flow of an auxiliary current into the integrated auxiliary magnetic field generating structure, the method further includes: A read signal is applied to the magnetic tunnel junction stack structure to read the resistance state of the magnetic tunnel junction stack structure and obtain the operation result of the XOR logic.

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