A method for detecting defects in component mounting in a chip stack package

Abstract

This invention discloses a defect detection method for component mounting in chip stacking packaging, comprising the following steps: before mounting, performing grid scanning and bilinear surface fitting on the substrate to achieve active warpage correction of the mounting head; after mounting, extracting stacking features such as planar offset, tilt angle, adhesive overflow width, and rotation angle of the chip through visual and laser height measurement; during vacuum release, monitoring the springback amount and springback rate through gradient release and continuous height sampling, and determining asymmetric springback; performing closed-loop compensation for the mounting torque and nozzle posture of the next chip based on the springback features; integrating substrate warpage, stacking features, springback monitoring, and compensation process data to calculate a comprehensive defect risk score, classifying the chips into four grades and performing corresponding treatments; finally, generating a full-process data package using the chip's unique identifier as the primary key. This invention achieves full-process perception, closed-loop compensation, and intelligent judgment in the mounting process, significantly improving the yield and reliability of stacked packaging.

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