A multi-core package structure and a method for manufacturing the same

Abstract

This invention discloses a multi-chip stacked packaging structure and its fabrication method, comprising the following steps: chip A is mounted on a substrate with its front side facing up; chip B is stacked on the back side of chip A with its front side facing up; chip A and chip B are encapsulated; the top surface of the encapsulation is ground down to expose the back side of chip B; wiring layer one and wiring layer two are electroplated on the encapsulation surface of the exposed back side of chip B, with wiring layer one electrically connected to the back side of chip B; after disassembly, the chip is flipped over and remounted on the substrate; holes are drilled in the encapsulation surface to expose wiring layer two; pillars are electroplated to fill the holes and electrically connect them to wiring layer two; wiring layer three is electroplated to electrically connect the exposed front side of chip A to the pillars; wiring layer three is encapsulated; and the chip is cut into package units. This invention features a simple structure, efficient process, reduced chip stacking height, reduced overall product thickness, reduced on-resistance, shortened chip connection length, reduced signal delay, meets the ultra-thin requirements of terminal products, and improves heat dissipation.

Description

Technical Field

[0001] This invention belongs to the field of chip packaging technology, and particularly relates to a multi-core stacked packaging structure and its preparation method. Background Technology

[0002] As semiconductor packaging technology develops towards high density, miniaturization, high speed and low power consumption, multi-chip stacking packaging has become an important technical path to improve chip integration and system performance. In a multi-chip packaging system, multiple chips are connected in series, so that electrical signals, control signals or data can flow through each chip in sequence, realizing the step-by-step transmission and collaborative work of functions such as signal amplification and logic operation.

[0003] Traditional multi-chip stacking methods involve first packaging each chip into a package with electrical interconnection structures, then connecting the packages in series and laying them flat on a printed circuit board to achieve the series connection, or directly stacking them in series during the packaging process and then electrically leading them out to form a series connection. This limits the potential of end products to develop towards miniaturization and high density, and makes it difficult to meet the urgent needs of today's electronic devices for compact packaging. The complex structure and numerous wirings lead to signal delay, severe signal interference, and affect heat dissipation. Summary of the Invention

[0004] To address the problems in the prior art, the present invention provides a multi-core stacked packaging structure and its fabrication method.

[0005] To achieve the above objectives, the present invention proposes a method for fabricating a multi-core stacked packaging structure, comprising the following steps: Chip mounting: Chip A is mounted on the substrate with its front side facing up. Chip B is stacked on the back side of Chip A with its front side facing up. Chip A and Chip B are encapsulated. The top surface of the encapsulation is ground until the back side of Chip B is exposed. Electroplating of wiring: Electroplating wiring layer one and wiring layer two on the packaging cover on the back of exposed chip B. Wiring layer one is electrically connected to the back of chip B, and wiring layer two is laid flat on one side of wiring layer one and is not electrically connected to chip B. Drilling and electroplating: After disassembling the board, flip it over. At this time, the front of chip A is exposed on the packaging cover. Reattach it to the substrate. Drill holes in the packaging cover to expose the second wiring layer. Electroplat the pillars to fill and electrically connect them to the second wiring layer. Wiring plating: The wiring layer three is electroplated on the package cover to electrically connect the exposed front of chip A to the pillar. The wiring layer three is then encapsulated and cut into package units.

[0006] Furthermore, in the chip mounting step, chip A and chip B are stacked together using conductive and thermally conductive adhesive.

[0007] Furthermore, in the chip mounting step, chip A and chip B may contain the same or different numbers of chips, and the size of each chip may be the same or different. When chips of different sizes are stacked, they are mounted and stacked with each chip aligned on one side.

[0008] Furthermore, in the chip mounting step, electrodes are provided on both the front and opposite back sides of chip A and chip B, and the back side of chip A and the front side of chip B are electrically connected in series through the electrodes.

[0009] Furthermore, in the wiring electroplating step, pins are electroplated on wiring layer one and wiring layer two respectively, and in the chip mounting step, the back cover of exposed chip B is further encapsulated and the pin surfaces are exposed.

[0010] A multi-core stacked package structure includes a package body, which encapsulates: Chip A and chip B have opposite front and back sides, with chip B's front side mounted and stacked on the back side of chip A. Wiring layer 1 and wiring layer 2. Wiring layer 1 electrically lays out the back of chip B, and wiring layer 2 is laid out on one side of wiring layer 1 and has no electrical connection with chip B. The third wiring layer lays out the front side of chip A electrically and is electrically connected to the second wiring layer through pillars.

[0011] Furthermore, chip A and chip B are stacked together using conductive and thermally conductive adhesive.

[0012] Furthermore, the number of chips contained in chip A and chip B may be the same or different, and the size of each chip may be the same or different. When chips of different sizes are stacked, they are mounted and stacked with each chip aligned on one side.

[0013] Furthermore, electrodes are provided on both the front and opposite back sides of chip A and chip B, and the back side of chip A and the front side of chip B are electrically connected in series through the electrodes.

[0014] Furthermore, pins are electroplated on wiring layer one and wiring layer two respectively, with the pins flush with and exposed on the surface of the package.

[0015] Beneficial effects of this invention: 1. Chip A and chip B are stacked in series using conductive and thermally conductive adhesive, then encapsulated and electrically led out. They are directly connected in series by conductive materials, eliminating the need for solder pads or other connections. This results in a simple structure, efficient process, shorter chip stacking height, reduced overall product thickness, and reduced on-resistance.

[0016] 2. Direct chip stacking eliminates the need for separate encapsulation before stacking and electrical connection on the circuit board, shortening chip connection length, reducing signal delay, and meeting the ultra-thin requirements of terminal products.

[0017] 3. After the chip stacking structure is completed, the two ends of the series electrical connection on the front and back of the stacking structure are covered by electroplated wiring layers. The metal wiring layers directly transfer and dissipate the chip heat, improve heat dissipation, and ensure chip performance. Attached Figure Description

[0018] Figures 1-2 This is a schematic diagram of the chip mounting steps in an embodiment of a method for fabricating a multi-core stacked packaging structure according to the present invention. Figures 3-6 This is a schematic diagram of the wiring electroplating steps in an embodiment of a method for fabricating a multi-core stacked packaging structure according to the present invention. Figures 7-9 This is a schematic diagram of the drilling and electroplating steps in an embodiment of a method for fabricating a multi-core stacked packaging structure according to the present invention. Figures 10-12 This is a schematic diagram of the wiring electroplating steps in an embodiment of a method for fabricating a multi-core stacked packaging structure according to the present invention. Figure 13 This is a cross-sectional view of a first embodiment of a multi-core stacked packaging structure of the present invention; Figure 14 This is a cross-sectional view of a second embodiment of a method for fabricating a multi-core stacked packaging structure according to the present invention.

[0019] In the diagram: 1. Chip A; 2. Chip B; 3. Wiring layer 1; 4. Wiring layer 2; 5. Pillar; 6. Wiring layer 3; 7. Package. Detailed Implementation

[0020] The present invention will now be described in conjunction with specific embodiments, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar components or components having the same or similar functions throughout.

[0021] The directional terms used in this invention, such as up, down, left, right, front, back, inside, outside, front, back, side, etc., are merely for reference to the accompanying drawings. The embodiments and directional terms used in the following description with reference to the accompanying drawings are exemplary and are only used to explain this invention, and should not be construed as limiting this invention. Furthermore, the various specific processes and materials provided in this invention are examples that those skilled in the art will recognize for the application of other processes and / or the use of other materials. Example 1

[0022] To better understand the purpose, structure, and function of this invention, the following detailed description, in conjunction with the accompanying drawings, provides an explanation of a multi-core stacked packaging structure and its fabrication method.

[0023] The fabrication method of the multi-core stacked packaging structure specifically includes the following steps: Chip mounting steps: First, a commonly used substrate in the art is provided as a support for the chips and subsequent processes. Based on the surface area of ​​the substrate, multiple chips A1 are mounted evenly and at reasonable intervals on the substrate. Chip A1 has a front and a back side. Electrical input and output ports of chip A1 are respectively provided on the front and back sides, serving as electrodes for external electrical connection of chip A1. There are no electrodes on the other sides of chip A1. Chip A1 is mounted with its front side facing the substrate. Chip A1 is firmly mounted with adhesive. The adhesive is a commonly used conductive and thermally conductive adhesive in the art, such as silver paste.

[0024] After chip A1 is mounted on the substrate, chip B2 is stacked on the back side of chip A1. Chip B2 can be the same size as chip A1. Like chip A1, chip B2 has opposing front and back sides. Electrical input and output ports are respectively located on the front and back sides of chip B2, serving as electrodes for external electrical connections. The other surfaces of chip B2 have no electrodes. The front side of chip B2 is electrically connected to the back side of chip A1, achieving series electrical stacking of the two chips. The two chips are firmly stacked with their sides aligned (e.g., ...). Figure 1 (As shown).

[0025] Chip B2 is stacked and mounted on each chip A1. Then, an encapsulating compound is used to completely encapsulate the stacked chips A1 and B2 on the substrate. After the encapsulating compound cures, the top surface of the encapsulation is flat. Using a mechanical polishing method commonly used in the art, the top surface of the encapsulation is polished until the back surface of each chip B2 is exposed (e.g., ...). Figure 2 As shown in the figure, the encapsulating material at this time constitutes an encapsulation unit, namely the encapsulation layer one.

[0026] Furthermore, in order to ensure that chip B2 is not damaged by mechanical stress when the back side of chip B2 is exposed during grinding, a thermally and electrically conductive adhesive is applied to the back side of chip B2 as a stress buffer layer after chip B2 is stacked and before encapsulation. Then, the back side of chip B2 is encapsulated and ground to expose the buffer layer (not shown in the figure).

[0027] Wiring plating steps: After grinding, the top surface of the encapsulation layer one is horizontal and flat. The back side of chip B2 is flush with the top surface of the encapsulation layer and exposed. On the encapsulation surface on the exposed back side of chip B2, wiring layer one 3 and wiring layer two 4 are electroplated using an electroplating process. Wiring layer one 3 is flatly electroplated on the top surface of the encapsulation layer after grinding (e.g., Figure 3 (As shown).

[0028] Wiring layer 3 covers the back of chip B2, is electrically connected to the electrodes on the back of chip B2, and is rearranged. Since wiring layer 3 is electroplated and covers the back of chip B2 and is in direct contact with the back of chip B2, the thickness of wiring layer 3 needs to be kept within a reasonable range to prevent stress compression on the chip B2 body. Taking into account factors such as the stress bearing capacity of the chip B2 body, the thickness that can be achieved by normal technical means in this field, and the normal thickness of wiring layer 3 to maintain normal electrical conduction function, the thickness of wiring layer 3 is determined.

[0029] The second wiring layer 4 is electroplated and laid flat on one side of the first wiring layer 3, extending at a suitable position on the top surface of the enclosure, and has no electrical connection with the first wiring layer 3 or the back of the chip B2; the two wiring layers can be electroplated simultaneously, and the electroplating height can be the same or different.

[0030] Using encapsulating material, further encapsulate wiring layer 3 and wiring layer 4 on top of encapsulation layer 1. The encapsulating material cures to form encapsulation layer 2, and encapsulation layer 1 and encapsulation layer 2 are cured into a single unit.

[0031] Furthermore, after electroplating wiring layer 3 and wiring layer 4, and before encapsulating wiring layer 3 and wiring layer 4, the leads (such as...) are further electroplated on wiring layer 3 and wiring layer 4 using an electroplating process. Figure 4 As shown), the pins are respectively positioned on wiring layer 3 and wiring layer 4 at appropriate locations. Appropriate locations refer to adjusting the electrical terminal positions and distances between the two wiring layers according to the specific conditions of the actual product. The pin plating heights are the same. Encapsulation layer 1 is then further encapsulated and cured to form encapsulation layer 2. Encapsulation layer 1 and encapsulation layer 2 are cured into a single unit (as shown). Figure 5 As shown), at this point, the second encapsulation layer has undergone a grinding process, and the top surface of the pins is flush with and exposed to the top surface of the second encapsulation layer after grinding (as shown). Figure 6 (As shown).

[0032] Drilling and electroplating steps: Remove the cured encapsulation layer 1 and encapsulation layer 2 from the substrate. The adhesive on the front of chip A1 is flush with the surface of encapsulation layer 1 and exposed. After removing the board, flip the entire encapsulation layer over and reattach it to the substrate (e.g., Figure 7 As shown in the figure, the surface of the exposed pins of the second encapsulation layer is mounted on the substrate, and the adhesive on the front of chip A1 is flush with and exposed on the surface of the first encapsulation layer.

[0033] A vertical hole is drilled at a suitable location on the surface of the adhesive encapsulation layer on the front side of the exposed chip A1 using an etching process. The suitable location refers to the position corresponding to wiring layer 4. The drilling continues until the bottom of the hole exposes the surface of wiring layer 4 (e.g., ...). Figure 8 As shown), the etching process can be either wet etching or dry etching, and this invention does not limit the choice between them.

[0034] Electroplated metal is used to fill the borehole, and the metal pillar 5 completely fills the internal space of the borehole (e.g., Figure 9 As shown), the drilling width can be flexibly adjusted. The drilling does not affect chip A1, chip B2, or wiring layer 3. That is, the structure of chip A1, chip B2, and wiring layer 3 has no contact with the drilling area and does not affect the structural stability. The drilling width only needs to meet the requirement that the electroplated metal can completely fill the internal space of the drilling. One end of the pillar 5 is electroplated and connected to wiring layer 4, and the other end is flush with the surface of the adhesive on the front of the exposed chip A1 of the encapsulation layer. Wiring plating step: On the surface of the encapsulation layer one, which is also exposed on the front adhesive side of the post 5 and chip A1 during the drilling plating step, the plating process continues to form wiring layer three 6 (as shown in the image). Figure 10 As shown), wiring layer 36 is electroplated and laid flat on the surface of encapsulation layer 1. Wiring layer 36 covers the adhesive on the front side of chip A1. The electrical components on the front side of chip A1 are pulled to the surface of encapsulation layer 1 by the adhesive and rearranged.

[0035] The plating thickness of wiring layer 6 is controlled within a reasonable range. Since wiring layer 6 is not in direct contact with the front of chip A1, but has an adhesive as an intermediate layer, the adhesive can buffer the stress impact on chip A1. Therefore, there is no limit to the plating thickness of wiring layer 6. It is sufficient to achieve the thickness that can be achieved by normal technical means in this field and the normal thickness that wiring layer 6 can maintain normal electrical conduction function.

[0036] Wiring layer 3 (6) lays out the front electrical components of chip A1 on the surface of encapsulation layer 1 and is electroplated and connected to pillar 5. Wiring layer 3 (6) electrically connects the exposed front electrical components of chip A1 to pillar 5. Since pins are electroplated on wiring layer 1 (3) and wiring layer 2 (4), and the pin surfaces are flush with the surface of encapsulation layer 2, the front electrical components of chip A1 are pulled to the horizontal plane where the back electrical components of chip B2 are pulled by wiring layer 1 (3) and pins through wiring layer 3 (6), pillar 5, wiring layer 2 (4), and pins. After the chips are stacked in series, some pins serve as the electrical input terminals of the structure, and other pins serve as the electrical output terminals of the structure. For example, the back electrical components of chip B2 are pulled to the pins by wiring layer 1 (3), and this pin serves as the electrical input port of the entire structure. Then, the front electrical components of chip A1 are pulled to the pins by wiring layer 3 (6), pillar 5, and wiring layer 2 (4), and this pin serves as the electrical output port of the entire structure. The polarity of the electrodes on the front and opposite back of the chip is set according to the actual situation to meet the requirements of chip series stacking.

[0037] On the surface of the encapsulation layer of the adhesive on the front side of the exposed chip A1, the encapsulation process is continued using encapsulation material to completely encapsulate the wiring layer 3 (e.g., Figure 11 As shown), the encapsulating material cures into encapsulation layer three, and encapsulation layer three, encapsulation layer one, and encapsulation layer two cure into a complete whole.

[0038] Finally, since multiple chips A1 are mounted on the substrate, and chips B2 are stacked on each chip A1, and the same process flow is performed to obtain the same structure, the encapsulation material between each structural unit constitutes the cutting area. The corresponding size design is completed in the actual product packaging design stage, and the corresponding position size can be reserved in subsequent process flows. The encapsulation material is cut vertically from the cutting area, and the encapsulation is separated into multiple structural units. The encapsulation body of each structural unit is a package body 7. The package body 7 encapsulates the chip and wiring layer. After the cutting and separation is completed, the substrate is removed to obtain multiple package body 7 product units (e.g., Figure 12 (As shown).

[0039] In this invention, chip A1 and chip B2 do not refer to a single chip. Chip A1 and chip B2 can refer to chips containing the same or different numbers of chips, but the types of chips contained in chip A1 and chip B2 are the same, and the types of chips in chip A1 and chip B2 can be the same or different. At the same time, the chips contained in chip A1 and chip B2 are also stacked in series by connecting the front and back sides. For example, chip A1 contains two chips of the same type, and chip B2 contains one chip. These three chips are stacked in series by connecting the front of the chip to the back of another chip in turn through conductive and thermally conductive adhesive, and finally forming a three-chip stacked structure. This invention does not limit this. In this embodiment, chip A1 and chip B2 are chips with the same length and width on the front and back sides, so they are stacked neatly.

[0040] In this invention, chips A1 and B2 are stacked in series using a conductive and thermally conductive adhesive, then encapsulated and electrically led out. They are directly connected in series by conductive materials, eliminating the need for solder pads or other connections. This results in a simple structure, efficient process, reduced chip stacking height, decreased overall product thickness, and reduced on-resistance. Direct chip stacking eliminates the need for separate encapsulation before stacking and electrical connection on a circuit board, shortening chip connection length, reducing signal delay, and meeting the ultra-thin requirements of end products. After the chip stacking structure is completed, the series electrical terminals on the front and back sides of the stacked structure are covered by electroplated wiring layers. The metal wiring layers directly transfer and dissipate heat from the chips, improving heat dissipation and ensuring chip performance. Example 2

[0041] Chip A1 and chip B2 contain chips of different sizes. For example, if the front and back lengths of chip A1 and chip B2 are different, multiple chips are stacked in series, and each chip is mounted together with one side aligned (as shown in the attached diagram). Figure 14As shown in the figure, the stacked structure is aligned and stacked on the same side, while the other side can be misaligned. The misaligned sides form a step difference, which, after the encapsulation material is encapsulated and cured, forms an encapsulation seal with the step of the stacked structure, preventing the risk of encapsulation delamination and warping, and making the structure more stable. Moreover, the single-sided alignment of the stacked structure allows for the stacking and mounting of small-sized chips on large-sized chips, with the small-sized chips completely falling within the range of the large-sized chips, avoiding the risk of small-sized chips hanging over the edge. At the same time, the wiring of wiring layer 3, wiring layer 4, and wiring layer 6 of this invention are distributed at both ends of the stacked structure, the wiring structure is symmetrical, and the pins leading out the series electrical terminals are spaced sufficiently apart, so they are not crowded to one side, resulting in low signal interference.

[0042] The above-described packaging method can be flexibly adjusted according to actual conditions. This invention is not limited to the above-described process steps, and adjustments to the order of other steps are also within the scope of protection of this invention.

[0043] All encapsulation steps involved in the process of this invention use molding compounds, such as epoxy resin, cyanate ester, and polyimide. These materials are low in cost, have good curing performance, and are commonly used encapsulation methods in the field. Encapsulation technology plays an important role in the semiconductor manufacturing field, mainly in protecting chips, connecting the whole, supporting structures, improving reliability, and promoting technological progress. The encapsulation method in this invention is the commonly used molding and injection molding methods in the field, but other suitable encapsulation methods and materials are also acceptable.

[0044] In all process steps of this invention involving the grinding of encapsulating material, a three-stage progressive grinding method of coarse grinding, fine grinding, and polishing can be used. First, coarse grinding is performed using low-grit diamond grinding discs or wheels to quickly remove most of the encapsulating material. Then, fine grinding is performed using high-grit diamond abrasive belts or sandpaper to remove scratches from the coarse grinding, gradually grinding down to the surface of the metal structure. In each process step of this invention, grinding is performed until the back side of chip B2 and the pin surface are exposed. Finally, polishing is performed using a polishing cloth. After grinding, the exposed metal structure is free of burrs, the chip is free of microcracks, and the surface is smooth. The degree of grinding can be selected according to the actual requirements of the product, and the above grinding process can be reasonably modified.

[0045] In all process steps of this invention involving electroplating of structures, a photoresist film is first adhered, followed by photolithography techniques such as exposure and development to form an electroplating protection layer on the surface of the area to be electroplated. Areas not requiring electroplating are protected by the photoresist film, exposing the areas to be electroplated. Then, a metal seed layer is formed on the exposed areas to be electroplated using suitable methods such as sputtering or copper deposition. The metal seed layer is made of copper or other metals. The metal seed layer ensures the bonding strength between subsequent metal-to-metal and metal-to-encapsulating materials, while also providing a surface for conductive ion adhesion, ensuring the electroplating effect. The entire electroplating process and the materials used are common knowledge in the field. Wiring layer 1 (3), wiring layer 2 (4), pillars (5), wiring layer 3 (6), and leads in each process flow of this invention are all formed by electroplating. The metal electroplated in the electroplating process can be copper, and the protective layer can be a nickel-gold layer, but this invention does not limit this.

[0046] Based on the above method for fabricating a multi-core stacked packaging structure, a multi-core stacked packaging structure (such as...) is obtained. Figure 13 As shown, this packaging structure is not only obtainable through the aforementioned packaging methods; other packaging methods, processes, and techniques also fall within the scope of protection of this invention. The packaging structure includes a packaging body 7, which encapsulates: Chip A1 and chip B2 have opposite front and back sides. Chip B2 is mounted on the front side and stacked on the back side of chip A1. Chip A1 and chip B2 are stacked together by conductive and thermally conductive adhesive.

[0047] Chip A1 and chip B2 may contain the same or different numbers of chips, and the size of each chip may be the same or different. When stacking chips of different sizes, they are mounted and stacked with each chip aligned on the same side.

[0048] Electrodes are provided on the front and opposite back sides of both chip A1 and chip B2. The back side of chip A1 and the front side of chip B2 are electrically connected in series through the electrodes.

[0049] Wiring layer 3 and wiring layer 4. Wiring layer 3 electrically lays out the back of chip B2, and wiring layer 4 is laid out on one side of wiring layer 3 and has no electrical connection with chip B2. Wiring layer 3, 6, lays out the front side of chip A1 electrically and connects it to wiring layer 2, 4 through pillar 5.

[0050] Pins are plated on wiring layer 3 and wiring layer 4 respectively, and the pins are flush with and exposed on the surface of package 7.

[0051] In the packaging structure of this invention, chips A1 and B2 are stacked in series using conductive and thermally conductive adhesive, then encapsulated and electrically led out. They are directly connected in series by conductive materials, eliminating the need for solder pads or other connections. This results in a simple structure, efficient process, reduced chip stacking height, decreased overall product thickness, and reduced on-resistance, meeting the ultra-thin requirements of end products. After the chip stacking structure is completed, wiring layers are electroplated on both the front and back ends of the series electrical connection. The metal wiring layers directly transfer and dissipate heat from the chips, improving heat dissipation and ensuring chip performance.

[0052] It is understood that this invention has been described through some embodiments, and those skilled in the art will recognize that various changes or equivalent substitutions can be made to these features and embodiments without departing from the spirit and scope of this invention. Furthermore, under the teachings of this invention, these features and embodiments can be modified to adapt to specific situations and materials without departing from the spirit and scope of this invention. Therefore, this invention is not limited to the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this invention are within the protection scope of this invention.

Claims

1. A method for fabricating a multi-core stacked packaging structure, characterized in that, Includes the following steps: Chip mounting: Chip A is mounted on the substrate with its front side facing up. Chip B is stacked on the back side of Chip A with its front side facing up. Chip A and Chip B are encapsulated. The top surface of the encapsulation is ground until the back side of Chip B is exposed. Electroplating of wiring: Electroplating wiring layer 1 and wiring layer 2 on the encapsulation cover on the back of exposed chip B. Wiring layer 1 is electrically connected to the back of chip B, and wiring layer 2 is laid flat on one side of wiring layer 1 and is not electrically connected to chip B. Continue to encapsulate wiring layer 1 and wiring layer 2. Drilling and electroplating: After disassembling the board, flip it over. At this time, the front of chip A is exposed on the packaging cover. Reattach it to the substrate. Drill holes in the packaging cover to expose the second wiring layer. Electroplat the pillars to fill and electrically connect them to the second wiring layer. Wiring plating: The wiring layer three is electroplated on the package cover to electrically connect the exposed front of chip A to the pillar. The wiring layer three is then encapsulated and cut into package units.

2. The method for fabricating a multi-core stacked packaging structure according to claim 1, characterized in that, In the chip mounting step, chip A and chip B are stacked together using conductive and thermally conductive adhesive.

3. The method for fabricating a multi-core stacked packaging structure according to claim 2, characterized in that, In the chip mounting step, chip A and chip B may contain the same or different numbers of chips, and the size of each chip may be the same or different. When chips of different sizes are stacked, they are mounted and stacked with each chip aligned on one side.

4. The method for fabricating a multi-core stacked packaging structure according to claim 3, characterized in that, In the chip mounting step, electrodes are provided on the front and opposite back sides of both chip A and chip B, and the back side of chip A and the front side of chip B are electrically connected in series through the electrodes.

5. The method for fabricating a multi-core stacked packaging structure according to claim 1, characterized in that, In the wiring electroplating step, pins are electroplated on wiring layer one and wiring layer two respectively. In the chip mounting step, the chip B is further encapsulated on the cover exposing the back of the chip and the pin surface is exposed.

6. A multi-core stacked package structure, comprising a package body, characterized in that, The package contains: Chip A and chip B have opposite front and back sides, with chip B's front side mounted and stacked on the back side of chip A. Wiring layer 1 and wiring layer 2. Wiring layer 1 electrically lays out the back of chip B, and wiring layer 2 is laid out on one side of wiring layer 1 and has no electrical connection with chip B. The third wiring layer lays out the front side of chip A electrically and is electrically connected to the second wiring layer through pillars.

7. The multi-core stacked packaging structure according to claim 6, characterized in that, Chip A and chip B are stacked together using conductive and thermally conductive adhesive.

8. The multi-core stacked packaging structure according to claim 7, characterized in that, Chip A and chip B may contain the same or different numbers of chips, and the size of each chip may be the same or different. When chips of different sizes are stacked, they are mounted and stacked with each chip aligned on one side.

9. The multi-core stacked packaging structure according to claim 8, characterized in that, Electrodes are provided on the front and opposite back sides of both chip A and chip B, and the back side of chip A and the front side of chip B are electrically connected in series through the electrodes.

10. The multi-core stacked packaging structure according to claim 6, characterized in that, The wiring layer one and wiring layer two are respectively plated with pins, and the pins are flush with and exposed on the surface of the package.

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