Multi-device structure and packaging process thereof
By uniform thickness processing of incoming chips in multi-chip packaging technology, the problem of inconsistent chip thickness is solved, and efficient electrical connection and low-cost production of multi-chip are achieved.
Patent Information
- Application Number
- CN202510005844.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-03
- Publication Date
- 2025-05-09
AI Technical Summary
In multi-chip packaging technology, the prior art is difficult to match the thickness consistency of different incoming chips, which affects the normal progress of the packaging.
By testing the thickness of the incoming chip, the chip with the largest thickness is screened out and the adhesive is brushed on the back of it as the standard thickness. Other chips brush adhesive on the back of the chip to make up according to the difference between their own thickness and the standard thickness, so that the chip thickness is the same. Then, through substrate bonding and use of encapsulation materials, the electrical connection and lead-out of the chip are realized.
The thickness of multi-chip is achieved, the subsequent electrical connection process is simplified, and the process difficulty and production cost are reduced.
Smart Images
Figure CN119965095A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of multi-chip packaging, and in particular relates to a multi-device structure and a packaging process thereof. Background Art
[0002] Multi-Chip Package (MCP) is an integrated circuit packaging technology that integrates multiple chips into one package structure, realizes the integration of multiple functional modules in one package, improves integration and performance, and reduces package size and power consumption. The mobile phone field is the main driving force for accelerating the development of multi-chip packaging. Mobile phones have developed from low-end functions such as making calls and sending and receiving short messages to high-end functions such as taking pictures, TV, and games, and require mobile phones to be small in size, light in weight, and multi-functional. To this end, high-end mobile phone chips must have a strong memory capacity, that is, the circuit integration is required to be higher.
[0003] In multi-chip packaging technology, diodes or MOS tubes are often required to be interconnected and packaged. The thickness of existing diode or MOS tube chips varies according to different applications and requirements. The thickness of incoming materials varies greatly. When packaging multiple chips, it is difficult to match the requirements for chip thickness consistency in the process, which affects the normal packaging process. Summary of the invention
[0004] In order to solve the above problems in the prior art, the present invention provides a multi-device structure and a packaging process thereof.
[0005] To achieve the above object, the present invention provides a multi-device packaging process, comprising the following steps: Chip thickness standardization: Test the thickness of incoming chips, select the thickest chip, and apply adhesive on the back of the chip. The total thickness of the chip after applying adhesive is used as the standard thickness. For other chips, apply adhesive on the back of the chip to make up the difference between their own thickness and the standard thickness, so that the thickness of the incoming chips is the same; Chip mounting: Provide a substrate, and fix the back of the chip with the same thickness to the corresponding area on the substrate by bonding with adhesive. After bonding, the front output port of the chip is flush with the same height. Use encapsulation material on the substrate to completely encapsulate the chip. The encapsulation material is cured, and the top surface of the encapsulation is horizontally ground to expose the front output port of the chip. Electrical connection: Electroplating a wiring layer on the ground package surface, the wiring layer is electrically connected to the chip front output port to achieve electrical connection between the chips, and the wiring layer is completely encapsulated with encapsulation material on the package surface, and the top surface of the package is ground until it is horizontal and flat; Electrical lead-out: Peel off the substrate and flip the package upside down. The back of the chip is electrically exposed outside the encapsulation material. External pins are electroplated in the exposed electrical area to electrically lead the chip out of the package.
[0006] Furthermore, in the chip mounting step, the adhesive applied on the back side of the chip is conductive adhesive.
[0007] Furthermore, in the chip mounting step, bumps A and B of equal height are electroplated on the substrate according to the product design, and bumps A and bumps B are arranged at intervals, and the backs of multiple chips with the same thickness are bonded and fixed toward bumps A respectively.
[0008] Furthermore, in the electrical connection step, a vertical hole is drilled on the package surface of the chip front output port exposed by grinding, the corresponding encapsulation material above the bump B is removed until the top surface of the bump B is exposed, and a conductive column is electroplated and filled in the drill hole.
[0009] Furthermore, in the electrical connection step, the lower end of the conductive column is electrically connected to the bump B, and the upper end of the conductive column is electrically connected to the wiring layer.
[0010] Furthermore, in the electrical lead-out step, the middle pillar is electroplated on the surface of the bump A bonded to the exposed back side of the chip, and the surface of the middle pillar is exposed by further encapsulation and grinding, and the outer pin is electrically connected to the middle pillar.
[0011] A multi-device packaging structure includes a packaging body and further includes: For chips, the total thickness of the thickest chip after applying glue on the back is taken as the standard thickness. The difference between the thickness of each chip and the standard thickness is supplemented by applying adhesive on the back of the chip to make up the difference so that the thickness of the chips is the same; Wiring layer: After the chip is mounted, the front output port is flush with the front output port of the chip, and the wiring layer is electrically connected to the front output port of the chip to achieve electrical connection between the chips. The chip and the wiring layer are both encapsulated in the package; External pins: The external pins are arranged in the electrical connection area of the adhesive on the back of the chip, and the external pins electrically lead the chip out of the package.
[0012] Furthermore, the adhesive applied on the back side of the chip is conductive adhesive.
[0013] Furthermore, the package body also encapsulates bumps A and bumps B that are spaced apart and have the same height, and the back surfaces of multiple chips with the same thickness are bonded and fixed toward the bumps A respectively.
[0014] Furthermore, the bump B is electrically connected to a vertically arranged conductive column, and the upper end of the conductive column is electrically connected to the wiring layer.
[0015] Furthermore, a middle pillar is electroplated on the surface of the bump A away from the back side of the chip, and the middle pillar is also encapsulated in the package body.
[0016] Furthermore, the external pins are electrically connected to the surface of the middle column away from the bump A, and the external pins are arranged outside the package body to electrically lead the chip out of the package body.
[0017] The present invention measures the thickness of the chip with the largest thickness after applying glue on its back side as the standard thickness, and applies adhesive glue on the back sides of other chips to make up the difference between their own thickness and the standard thickness, so that the thickness of the chips that need to be packaged together in the end are the same, which is convenient for subsequent electrical connection between the chips, has low process requirements, reduces process difficulty, and reduces production costs. BRIEF DESCRIPTION OF THE DRAWINGS
[0018] Figure 1-Figure 2 A cross-sectional view of a chip thickness unification step in a multi-device packaging process of the present invention; Figure 3-Figure 6 A cross-sectional view of a chip mounting step of a multi-device packaging process of the present invention; Figure 7-Figure 10 A cross-sectional view of an electrical connection step of a multi-device packaging process of the present invention; Figure 11-Figure 15 A cross-sectional view of an electrical lead-out step of a multi-device packaging process of the present invention; Fig.16 This is a product cross-sectional view of a multi-device packaging structure of the present invention.
[0019] In the figure: 1. Package; 2. Chip; 3. Wiring layer; 4. Conductive column; 5. External pin; 6. Bump A; 7. Bump B; 8. Middle column; 9. Adhesive. DETAILED DESCRIPTION
[0020] The content of the present invention will be explained below in conjunction with specific embodiments, examples of which are shown in the accompanying drawings, wherein the same or similar numbers throughout represent the same or similar components or components with the same or similar functions.
[0021] The directional terms mentioned in the present invention, such as: up, down, left, right, front, back, inside, outside, front, back, side, etc., are only reference directions of the drawings. The embodiments described below with reference to the drawings and the directional terms used are exemplary and are only used to explain the present invention, and cannot be understood as limiting the present invention. In addition, the various specific process and material examples provided in the present invention are all those skilled in the art who can recognize the application of other processes and / or the use of other materials.
[0022] In order to better understand the purpose, structure and function of the present invention, the following is a further detailed description of a multi-device packaging process proposed by the present invention in conjunction with the accompanying drawings. The process includes the following steps: Chip 2 thickness homogenization: Test the thickness of incoming chips 2, select the thickest chip 2, and apply adhesive 9 on the back of the chip 2. The total thickness of the chip 2 after applying adhesive is used as the standard thickness. The difference between the thickness of other chips 2 and the standard thickness is made up by applying adhesive on the back of the chip 2, so that the thickness of the incoming chips 2 is the same; Chip 2 mounting: provide a substrate, and fix the back of chip 2 with the same thickness to the corresponding area on the substrate by bonding with adhesive. After bonding, the front output port of chip 2 is flush with the same height, and the chip 2 is completely encapsulated with encapsulation material on the substrate. The encapsulation material is cured, and the top surface of the encapsulation is horizontally ground to expose the front output port of chip 2; Electrical connection: electroplating the wiring layer 3 on the ground package surface, the wiring layer 3 is electrically connected to the front output port of the chip 2 to achieve electrical connection between the chips 2, and the wiring layer 3 is completely encapsulated with encapsulation material on the package surface, and the top surface of the package is ground until it is horizontal and flat; Electrical lead-out: The substrate is peeled off and the package is turned upside down. The back of the chip 2 is electrically exposed outside the encapsulation material, and external pins 5 are electroplated in the exposed electrical area to electrically lead the chip 2 out of the package body 1.
[0023] Among them, Figure 1-Figure 2 As shown, in the chip 2 thickness homogenization step, the chip 2 can be one or more of a variety of semiconductor devices, such as a transistor, a memory, a diode, a triode or a MOS, etc. When multiple chips 2 are integrated in a packaging structure, the multiple chips 2 need to realize electrical connection function. The incoming chips 2 have different thicknesses due to the different types of chips 2, the functions of chips 2, etc. It is difficult to match the thickness consistency requirements of the chips 2 in the packaging process, resulting in difficulty in realizing electrical connection function between the multiple chips 2; therefore, it is necessary to keep the thickness of the chips 2 with different thicknesses the same through the thickness homogenization step. The chips 2 are evenly distributed on the entire wafer. Each chip 2 unit is provided with an output port on the chip 2 through a ball implantation process, and then the wafer is diced and cut into chip units, namely, chips 2, and tested and screened out. The chip 2 of the standard will be tested for thickness of each incoming chip 2 that needs to be encapsulated in a packaging structure, and the chip 2 with the largest thickness will be screened out, and a layer of adhesive glue 9 will be brushed on the back of the chip 2. The adhesive glue 9 is a glue material commonly used in this field and is a conductive glue. After brushing the glue, the thickness of the chip 2 is measured again, and the thickness is used as the standard thickness. The thickness of other chips 2 is measured, and the difference between the thickness of other chips 2 and the standard thickness is also brushed with adhesive glue 9 on the back of the chip 2 to make up for it, so that the thickness of the chips 2 that need to be packaged together in the end is the same; the packaging structure of the present invention is to package multiple chips 2 flatly. When the chip 2 is flatly mounted, the back of the chip 2 is flush and at an equal height, and the front of the chip 2 is also flush and at an equal height, which is convenient for the subsequent electrical connection between the chips 2, has low process requirements, reduces process difficulty, and reduces production costs.
[0024] Among them, Figure 3-Figure 6 As shown, in the chip 2 mounting step, after the chip 2 is glued on the back to eliminate the thickness difference, the chip 2 needs to be encapsulated and electrically connected; first, a substrate is used, which is a silicon, metal or other suitable material substrate commonly used in the art as a support platform for each step in the packaging process, and bumps A6 and bumps B7 are pre-arranged at corresponding positions on the substrate by electroplating or mounting process 2. The bumps A6 and bumps B7 are of the same height and are arranged flatly and spaced apart on the left and right. The distribution of multiple groups of bumps A6 and bumps B7 can be arranged according to the area of the substrate. The present invention takes the arrangement of one group as an example. Bump A6 is used to carry chip 2. The backs of chips 2 to be encapsulated in the same packaging structure are facing bump A6 and fixed by adhesive 9. Since the thickness difference is eliminated by brushing glue on the back of chip 2, the front of chip 2 is flush after mounting. After mounting, chip 2 and bump A6 and bump B7 are completely encapsulated by encapsulation material on the substrate. The encapsulation material is removed by horizontal mechanical grinding on the top surface of the encapsulation until the output port on the front of chip 2 is exposed. The front of chip 2 is flush and the output port on the front of chip 2 is exposed at the same time after grinding.
[0025] Among them, Figure 7-Figure 10 As shown, in the electrical connection step, wiring is required at the simultaneously exposed and equal-height front output ports of the chips 2 to realize electrical connection between the chips 2. Before wiring, firstly, vertical holes are drilled in the corresponding areas on the package surface ground in the chip 2 mounting step to remove the corresponding encapsulation material on the bump B7. The top surface of the bump B7 is exposed in the drilled hole. Then, the conductive column 4 is electroplated in the drilled hole to completely fill the hole. The lower end of the conductive column 4 is electrically connected to the bump B7. Then, the wiring layer 3 is plated flat on the package surface. The wiring layer 3 electrically connects the conductive column 4 and the output port of the chip 2. After the electroplating is completed, the package surface is further encapsulated to completely encapsulate the wiring layer 3 in the encapsulation material. To ensure that the new package surface is level and flat, the package surface is continuously ground by mechanical horizontal grinding until the package surface is level and flat.
[0026] Among them, Figure 11-Figure 15As shown, in the electrical lead-out step, after the encapsulation material is solidified, the encapsulation as a whole is peeled off from the substrate, that is, the bottom surfaces of the bumps A6 and the bumps B7 are flush with the encapsulation as a whole and exposed, and the encapsulation as a whole is turned upside down and mounted on the substrate. The colloid for bonding and fixing is not shown in the figure. At this time, the bottom surfaces of the bumps A6 and the bumps B7 are exposed, and the middle column 8 is electroplated on the exposed bump A6. The top surface of the middle column 8 is exposed by encapsulation and grinding, and the external pin 5 is continuously electroplated on the top surface of the middle column 8. The encapsulation process is completed, and the encapsulation as a whole constitutes a package body 1, and the external lead 5 is formed. Pin 5 serves as the external connection structure of the package 1, and the package 1 is welded to the working area through the external pin 5; by electroplating the intermediate column 8, the distance between the external pin 5 and the bump A6 is increased, which increases the structural stability while preventing the large-area bump A6 from short-circuiting with other circuit contact assemblies in the working area, thereby enhancing electrical stability. The electrical properties of the chip 2 are transferred from the conductive adhesive 9 through the bump A6 and the intermediate column 8 to the external pin 5, and the electrical layout and electrical connection of each chip 2 are realized through the wiring layer 3, the conductive column 4 and the bump B7.
[0027] Finally, the substrate is peeled off. According to the bonding colloid material, a suitable peeling method can be selected, such as chemical etching, mechanical peeling, etc. For example, a plurality of groups of bumps A6 and bumps B7 are arranged on the substrate, and the package as a whole contains a plurality of groups of multi-chip 2 packaging structures. After the encapsulation process is completed, it is still necessary to use a cutting process to cut and separate each product unit in the cutting path reserved in the product design stage. In the present invention, a group of bumps A6 and bumps B7 are arranged on the substrate, so only one group of multi-chip 2 packaging structure is encapsulated, and the multi-chip 2 packaging structure product unit can be obtained after the substrate is peeled off.
[0028] A multi-device packaging structure can be obtained through the above-mentioned multi-device packaging process. Fig.16 As shown, the packaging structure includes a packaging body 1, and also includes: Chip 2, the total thickness of the thickest chip 2 after brushing glue on the back is taken as the standard thickness, and the difference between the thickness of each chip 2 and the standard thickness is brushed with adhesive glue 9 on the back of the chip 2 to make up the difference, so that the thickness of the chips 2 is the same, and the adhesive glue 9 brushed on the back of the chip 2 is conductive glue, and the package body 1 also encapsulates bumps A6 and bumps B7 that are spaced and equal in height, and the backs of multiple chips 2 with the same thickness are respectively bonded and fixed toward the bump A6; Wiring layer 3: After chip 2 is mounted, the front output port is flush with the same height, and the wiring layer 3 is electrically connected to the front output port of chip 2 to achieve electrical connection between the chips 2. The chip 2 and the wiring layer 3 are both encapsulated in the package 1. The bump B7 is electrically connected to a vertically arranged conductive column 4, and the upper end of the conductive column 4 is electrically connected to the wiring layer 3; External pin 5: The external pin 5 is arranged in the electrical connection area of the adhesive 9 on the back side of the chip 2, and the external pin 5 electrically leads the chip 2 to the outside of the package 1. The surface of the bump A6 away from the back side of the chip 2 is electroplated with an intermediate column 8, and the intermediate column 8 is also encapsulated in the package 1. The surface of the bump A6 away from the back side of the chip 2 is electroplated with an intermediate column 8, and the intermediate column 8 is also encapsulated in the package 1. The external pin 5 is electrically connected to the surface of the intermediate column 8 away from the bump A6, and the external pin 5 is arranged outside the package 1 to electrically lead the chip 2 to the outside of the package 1.
[0029] The encapsulation material used in the present invention is a plastic encapsulation material, and the specific material may be epoxy resin, cyanate, polyimide, etc., which has low cost and good curing performance. The encapsulation process plays an important role in the field of semiconductor manufacturing, mainly in terms of protection, connection, support, reliability and promotion of technological progress. The encapsulation method is the compression molding method commonly used in this field.
[0030] All the steps of the electroplating process of the present invention are to first form electroplating protection on the surface through exposure and development photolithography technology, protect the places that do not need electroplating, expose the areas that need electroplating, and then form a metal seed layer in the area to be electroplated by sputtering or copper deposition or other appropriate methods. The metal seed layer is copper or other metal materials. The metal seed layer is to ensure the bonding force between the metals and metals and between the metals and the encapsulation materials in the subsequent electroplating, and at the same time provide a surface for the electroplating to attach conductive ions, thereby ensuring the electroplating effect. The entire steps in the electroplating process and the materials used are also common technical knowledge in this field. The metals electroplated in all the electroplating processes of the present invention are all made of metallic copper.
[0031] The present invention uses the thickness of the chip 2 with the largest thickness measured after brushing glue on the back side as the standard thickness. The other chips 2 are also brushed with adhesive glue 9 on the back side to make up for the difference between their own thickness and the standard thickness, so that the thickness of the chips 2 that need to be encapsulated together in the end are the same, which is convenient for the subsequent electrical connection between the chips 2, has low process requirements, reduces process difficulty, and reduces production costs. By electroplating the middle column 8, the distance between the outer pin 5 and the bump A6 is increased, which increases the structural stability while preventing the large-area bump A6 from short-circuiting with other circuit contact assemblies in the working area, thereby enhancing electrical stability.
[0032] It is to be understood that the present invention is described by some embodiments, and it is known to those skilled in the art that various changes or equivalent substitutions may be made to these features and embodiments without departing from the spirit and scope of the present invention. In addition, under the teachings of the present invention, these features and embodiments may be modified to adapt to specific circumstances and materials without departing from the spirit and scope of the present invention. Therefore, the present invention is not limited by the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of the present invention are within the scope of protection of the present invention.
Claims
1. A multi-device packaging process, characterized in that: The following steps are involved: Chip thickness standardization: Test the thickness of incoming chips, select the thickest chip, and apply adhesive on the back of the chip. The total thickness of the chip after applying adhesive is used as the standard thickness. For other chips, apply adhesive on the back of the chip to make up the difference between their own thickness and the standard thickness, so that the thickness of the incoming chips is the same; Chip mounting: Provide a substrate, and fix the back of the chip with the same thickness to the corresponding area on the substrate by bonding with adhesive. After bonding, the front output port of the chip is flush with the same height. Use encapsulation material on the substrate to completely encapsulate the chip. The encapsulation material is cured, and the top surface of the encapsulation is horizontally ground to expose the front output port of the chip. Electrical connection: Electroplating a wiring layer on the ground package surface, the wiring layer is electrically connected to the chip front output port to achieve electrical connection between the chips, and the wiring layer is completely encapsulated with encapsulation material on the package surface, and the top surface of the package is ground until it is horizontal and flat; Electrical lead-out: Peel off the substrate and flip the package upside down. The back of the chip is electrically exposed outside the encapsulation material. External pins are electroplated in the exposed electrical area to electrically lead the chip out of the package.
2. The multi-device packaging process according to claim 1, characterized in that: In the chip mounting step, the adhesive brushed on the back side of the chip is conductive adhesive.
3. The multi-device packaging process according to claim 1, characterized in that: In the chip mounting step, bumps A and B of equal height are electroplated on the substrate according to the product design, and bumps A and B are arranged at intervals. The backs of multiple chips with the same thickness are bonded and fixed toward bumps A respectively.
4. The multi-device packaging process according to claim 3, characterized in that: In the electrical connection step, a hole is vertically drilled on the package surface of the chip front output port exposed by grinding, the corresponding encapsulation material above the bump B is removed until the top surface of the bump B is exposed, and a conductive column is electroplated and filled in the drill hole.
5. The multi-device packaging process according to claim 4, characterized in that: In the electrical connection step, the lower end of the conductive column is electrically connected to the bump B, and the upper end of the conductive column is electrically connected to the wiring layer.
6. The multi-device packaging process according to claim 5, characterized in that: In the electrical lead-out step, the middle pillar is electroplated on the surface of the bump A bonded to the exposed back side of the chip, and the surface of the middle pillar exposed by encapsulation and grinding is continued, and the outer pin is electrically connected to the middle pillar.
7. A multi-device packaging structure, comprising a packaging body, characterized in that: Also included are: For chips, the total thickness of the thickest chip after applying glue on the back is taken as the standard thickness. The difference between the thickness of each chip and the standard thickness is supplemented by applying adhesive on the back of the chip to make up the difference so that the thickness of the chips is the same; Wiring layer: After the chip is mounted, the front output port is flush with the front output port of the chip, and the wiring layer is electrically connected to the front output port of the chip to achieve electrical connection between the chips. The chip and the wiring layer are both encapsulated in the package; External pins: The external pins are arranged in the electrical connection area of the adhesive on the back of the chip, and the external pins electrically lead the chip out of the package.
8. The multi-device packaging structure according to claim 7, characterized in that: The adhesive brushed on the back of the chip is conductive adhesive.
9. The multi-device packaging structure according to claim 7, characterized in that: The package body also encapsulates bumps A and bumps B that are spaced apart and have the same height. The backs of multiple chips with the same thickness are bonded and fixed toward the bumps A.
10. The multi-device packaging structure according to claim 9, characterized in that: The bump B is electrically connected to a vertically arranged conductive column, and the upper end of the conductive column is electrically connected to the wiring layer.
11. The multi-device packaging structure according to claim 10, characterized in that: The surface of the bump A away from the back side of the chip is electroplated with a middle pillar, which is also encapsulated in the package.
12. The multi-device packaging structure according to claim 11, characterized in that: The external pins are electrically connected to the surface of the middle column away from the bump A, and the external pins are arranged outside the package body to electrically lead the chip out of the package body.