Packaging structure and packaging process of high-voltage diode

Abstract

The invention discloses a packaging structure and a packaging process of a high-voltage diode, and the process comprises the following steps: chip packaging: placing a chip, the front surface of which is brushed with an adhesive layer A, on a substrate, packaging the chip on the substrate by using a packaging material, grinding a packaging surface until the top surface of the adhesive layer A is exposed, and vertically drilling a hole in a corresponding position of the grinding surface; and electrically connecting: electroplating and filling a vertical column A in the drill hole, horizontally laying and electroplating a wiring layer A on the grinding surface, enabling the wiring layer A to be in contact with the top surface of the chip front adhesive layer A, electrically connecting one end of the wiring layer A with the vertical column A, and continuously encapsulating the vertical column A and the wiring layer A by using an encapsulating material on the grinding surface, after the encapsulation material is cured, stripping the whole body from the substrate, turning over up and down and placing on the substrate again, wherein the back surface of the chip is exposed; and electrical leading-out: vertically drilling a hole at the corresponding position of the overturned packaging surface until the top of the upright column A. According to the invention, the stress directly acting on the chip is uniform, and the service life of the chip is prolonged.

Description

Technical Field

[0001] The present invention belongs to the technical field of diode packaging, and in particular relates to a packaging structure of a high-voltage diode and a packaging process thereof. Background Art

[0002] A high-voltage diode usually contains a PN junction with two terminals, an anode and a cathode. It uses the unidirectional conductive characteristics of the PN junction to convert alternating current into pulsating direct current. It is a semiconductor device used to convert alternating current into direct current. It is mainly used in industrial frequency conversion, digital generators and other fields, and can be expanded to other fields.

[0003] Existing high-voltage diodes have large currents and are large in size. Traditional wire bonding and clip bonding (ClipBonding) packaging methods each have their own disadvantages. The wire bonding process requires bonding metal wires between the device and the circuit to achieve electrical connection. The metal wires are thin and the package size is large, resulting in poor thermal conductivity, electrical conductivity, and heat dissipation performance of the entire structure. The copper bridge bonding process requires the development of complex jigs or the pre-production of copper strips, which is not universal and increases costs. Summary of the invention

[0004] In order to solve the above problems in the prior art, the present invention provides a packaging structure of a high voltage diode and a packaging process thereof.

[0005] To achieve the above object, the present invention provides a packaging process for a high voltage diode, comprising the following steps: Chip encapsulation: Place the chip with glue layer A on the front side on the substrate, encapsulate the chip with encapsulation material on the substrate, grind the encapsulation surface until the top surface of glue layer A is exposed, and drill vertical holes at the corresponding positions on the grinded surface; Electrical connection: Electroplating fills the column A in the drilled hole, and horizontally electroplating sets the wiring layer A on the polished surface. The wiring layer A contacts the top surface of the chip front glue layer A. One end of the wiring layer A is electrically connected to the column A. The encapsulation material is continued to be used on the polished surface to encapsulate the column A and the wiring layer A. After the encapsulation material is cured, it is peeled off from the substrate and turned upside down and placed back on the substrate, exposing the back of the chip; Electrical lead-out: Drill vertically at the corresponding position of the flipped package cover until the top of column A is exposed, continue to electroplating column B in the drilled hole, apply glue layer B on the back of the exposed chip, and electroplating wiring layer B in contact with the top surface of glue layer B and pads electrically connected to column B on the package cover to electrically lead out the chip.

[0006] Furthermore, in the chip encapsulation step, a glue layer A is applied to the entire front side of the wafer, and after the wafer is cut into chip units, the tested chips are mounted on the substrate with the glue-coated side facing upwards.

[0007] Furthermore, in the chip encapsulation step, electrodes are provided on the front and back sides of the chip, and glass is provided at the edge of the chip.

[0008] Furthermore, in the electrical lead-out step, the adhesive layer A on the front side of the chip and the adhesive layer B on the back side of the chip are located opposite to each other on both sides of the chip, have the same size and thickness, and are both conductive adhesives.

[0009] Furthermore, in the electrical lead-out step, the distribution of the adhesive layer A and the adhesive layer B on the chip surface does not exceed the chip edge glass.

[0010] Furthermore, the electrical lead-out step also includes a solder foot electroplating step, in which solder feet are respectively electroplated on the electroplated wiring layer B and the solder pad, and the encapsulation is continued to encapsulate the wiring layer B, the solder pad and the solder foot in the encapsulation material to form a product unit of the package.

[0011] Furthermore, in the solder foot electroplating step, the package surface is horizontally ground until the top surface of the solder foot is exposed, and a protective layer is electroplated on the exposed top surface of the solder foot.

[0012] A packaging structure of a high-voltage diode, comprising a packaging body, wherein the packaging body encapsulates: A chip, wherein a glue layer A is applied to the front side of the chip and a glue layer B is applied to the back side of the chip; Wiring layer: Wiring layer A and wiring layer B are horizontally plated on the front and back of the chip respectively, with wiring layer A in contact with glue layer A and wiring layer B in contact with glue layer B; Pillar: Pillar A and pillar B are vertically electroplated in the package body and are stacked and connected up and down, and one end of the pillar A away from the pillar B is connected to the wiring layer A; The pad is connected to one end of the column B away from the column A. The electrical properties of the front side of the chip are transferred from the wiring layer A through the columns A and B to the pad, and the electrical properties of the back side of the chip are transferred from the wiring layer B.

[0013] Furthermore, the chip is formed by applying glue layer A on the entire front side of the wafer, cutting it, and testing and screening for qualified ones.

[0014] Furthermore, electrodes are arranged on the front and back sides of the chip, and glass is arranged at the edge of the chip.

[0015] Furthermore, the adhesive layer A on the front side of the chip and the adhesive layer B on the back side of the chip are located opposite to each other on both sides of the chip, have the same size and thickness, and are both conductive adhesives.

[0016] Furthermore, the distribution of the adhesive layer A and the adhesive layer B on the chip surface does not exceed the chip edge glass.

[0017] Furthermore, solder feet are plated on the electroplated wiring layer B and the solder pads respectively, and the solder feet are also encapsulated in the encapsulation material to form a product unit of the package.

[0018] Furthermore, the soldering feet are exposed flush with the surface of the package body, and a protective layer is electroplated on the top surface of the exposed soldering feet.

[0019] The present invention: 1. The adhesive layer is applied to both opposite sides of the chip and the wiring layer is electroplated. The distribution position of the adhesive layer on the chip is corresponding, and the size, thickness and material are the same. The wiring layer is made of the same material and is covered with the adhesive layer, so that the stress on the front and back sides of the chip is symmetrical, the stress directly acting on the chip is uniform, and the chip life is extended; 2. The electroplated wiring layer replaces wire bonding or copper bridge bonding, making the structure more stable, with better conductivity and surge resistance, better thermal conductivity of the entire structure, simpler process, smaller overall package size, and no need to prepare complex jigs or copper bridge strips. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1-Figure 4 A cross-sectional view of a chip thickness unification step in a packaging process for a high-voltage diode of the present invention; Figure 5-Figure 6 A cross-sectional view of an electrical connection step in a packaging process of a high-voltage diode of the present invention; Figure 7-Figure 10 A cross-sectional view of an electrical lead-out step in a packaging process for a high-voltage diode of the present invention; Figure 11-Figure 15 A cross-sectional view of a solder foot electroplating step in a packaging process for a high-voltage diode of the present invention; Fig.16 A product cross-sectional view of a packaging structure of a high-voltage diode of the present invention; Fig.17 The product perspective view is a packaging structure of a high-voltage diode of the present invention.

[0021] In the figure: 1. Package; 2. Chip; 3. Wiring layer A; 4. Wiring layer B; 5. Pillar A; 6. Pillar B; 7. Pad; 8. Solder foot; 9. Glue layer A; 10. Glue layer B. DETAILED DESCRIPTION

[0022] The content of the present invention will be explained below in conjunction with specific embodiments, examples of which are shown in the accompanying drawings, wherein the same or similar numbers throughout represent the same or similar components or components with the same or similar functions.

[0023] The directional terms mentioned in the present invention, such as: up, down, left, right, front, back, inside, outside, front, back, side, etc., are only reference directions of the drawings. The embodiments described below with reference to the drawings and the directional terms used are exemplary and are only used to explain the present invention, and cannot be understood as limiting the present invention. In addition, the various specific process and material examples provided in the present invention are all those skilled in the art who can recognize the application of other processes and / or the use of other materials.

[0024] In order to better understand the purpose, structure and function of the present invention, the packaging process of a high-voltage diode proposed by the present invention is further described in detail below in conjunction with the accompanying drawings. The process includes the following steps: Chip 2 encapsulation: Place chip 2 with adhesive layer A9 on the front side on the substrate, encapsulate chip 2 with encapsulation material on the substrate, grind the encapsulation surface until the top surface of adhesive layer A9 is exposed, and vertically drill holes at the corresponding positions of the grinded surface; Electrical connection: electroplating fills the column A5 in the drilled hole, and horizontally electroplating the wiring layer A3 on the polished surface, the wiring layer A3 contacts the top surface of the front adhesive layer A9 of the chip 2, one end of the wiring layer A3 is electrically connected to the column A5, and the encapsulation material is continued to be used on the polished surface to encapsulate the column A2 and the wiring layer A3. After the encapsulation material is cured, it is peeled off from the substrate and turned upside down and placed back on the substrate, and the back of the chip 2 is exposed; Electrical lead-out: Drill vertically at the corresponding position of the flipped package cover until the top of the column A5 is exposed, continue to electroplating the column B6 in the drilled hole, brush the glue layer B10 on the back of the exposed chip 2, and electroplating the wiring layer B4 in contact with the top surface of the glue layer B10 and the pad 7 electrically connected to the column B6 on the package cover to electrically lead out the chip 2.

[0025] Among them, Figure 1-Figure 4 As shown, in the chip 2 encapsulation step, chip 2 can be one of a variety of semiconductor devices, such as transistors, memories, diodes, triodes or MOS, etc. In the present application, chip 2 is a high-voltage diode, and chip 2 units are all obtained by wafer dicing. After the wafer is mounted as a whole, the glue brushing process of the prior art is used to brush glue on the front side of the wafer, and a glue layer A9 of a certain thickness is brushed. After the wafer is cut to form chip 2 units, qualified chips 2 are screened out through testing. The chip 2 of this existing high-voltage diode includes a front side and a back side, and electrodes are provided on both the front side and the back side. The edge position of chip 2 is made of glass material, and the glue layer A9 adheres to the front side of chip 2, covering the front electrode but not exceeding the edge glass of chip 2. The glue layer A9 is a conductive glue. If it exceeds the glass material, it will cause glue overflow. The overflow of the conductive glue layer A9 is likely to cause a short circuit in the internal circuit of the packaging structure, resulting in defective products.

[0026] The chip 2 is mounted with the back side of the chip 2 facing the substrate, and the front adhesive layer A9 of the chip 2 is away from the substrate. The substrate is a commonly used substrate type in the field of packaging, such as a resin board, etc., which provides support for the entire packaging process. According to the substrate area and process capabilities, multiple chips 2 are mounted on the substrate at even intervals. This application takes the mounting of a chip 2 as an example. After mounting, the chip 2 and the adhesive layer A9 are encapsulated with an encapsulation material on the substrate. After the encapsulation material is solidified and stabilized, the top surface of the encapsulation is horizontally ground by mechanical grinding until the top surface of the adhesive layer A9 is exposed, and vertical holes are drilled at the corresponding positions of the ground encapsulation surface. There is no requirement for the drilling depth, but some encapsulation material is reserved from the bottom to the substrate.

[0027] Among them, Figure 5-Figure 6 As shown, in the electrical connection step, the metal-plated column A5 is filled in the above-mentioned drilled hole, and the wiring layer A3 is plated on the package surface through the electroplating process. The wiring layer A3 is horizontally laid and extended along the package surface. One end of the wiring layer A3 is in contact with and covers the glue layer A9, and the other end is connected to the column A5 to achieve electrical connection with the glue layer A9 and the column A5. The encapsulation material is continued to be used to encapsulate the column A5 and the wiring layer A3 on the package surface after electroplating. The column A5 and the wiring layer A3 are completely encapsulated in the encapsulation material. After the encapsulation material is cured, the processing process of the front side of the chip 2 is completed, the package as a whole is peeled off from the substrate, and the upper and lower surfaces of the package as a whole are turned over and placed on the substrate again. At this time, the back side of the chip 2 faces up and is exposed flush with the encapsulation material.

[0028] Among them, Figure 7-Figure 10 As shown, in the electrical lead-out step, a vertical hole is drilled at a corresponding position on the flipped package surface, i.e., the position corresponding to the pillar A5, until the top surface of the pillar A5 is exposed. Similarly, a pillar B6 filled with metal is electroplated in the drilled hole. The pillars A5 and B6 can be electroplated to different sizes and shapes to increase the contact area with the encapsulation material. A glue layer B10 of a certain thickness is brushed on the back of the exposed chip 2 using a glue brushing process. The glue layer B10 is also a conductive glue, which covers the back electrode of the chip 2 but does not exceed the edge glass of the chip 2.

[0029] Then, the wiring layer B4 is electroplated on the adhesive layer B10. The wiring layer B4 is horizontally laid and extended along the package surface after flipping. The wiring layer B4 covers the adhesive layer B10 and is in direct contact with it. While the wiring layer B4 is electroplated, a larger pad 7 is electroplated on the plated column B6; that is, the adhesive layer is applied to both opposite sides of the chip 2 and the wiring layer is electroplated. The distribution positions of the adhesive layer A9 and the adhesive layer B10 on the chip 2 correspond, and the size, thickness and material are the same. The same adhesive layer is applied to both sides of the chip 2. The wiring layers are made of the same material and are covered with a glue layer, so that the stress on the front and back sides of the chip 2 is symmetrical. The glue is applied on both sides to reduce the stress symmetrically. The stress directly acting on the chip 2 is uniform, and the life of the chip 2 is extended. The electroplated wiring layer replaces wire bonding or copper bridge bonding, and the structure is more stable, and the conductive performance and surge resistance are better. By electroplating a large area wiring layer and a large area pad 7, the pad 7 is directly connected to the column, and the thermal conductivity of the entire structure is better. The process is simple and there is no need to prepare complex jigs or copper bridge belts.

[0030] Among them, Figure 11-Figure 15 As shown, in the electroplating step of the solder foot 8, the solder foot 8 is further electroplated on the wiring layer B4 and the pad 9 after the electroplating is completed. After the solder foot 8 is electroplated, the encapsulation is continued, and the wiring layer B4, the pad 7 and the solder foot 8 are all encapsulated in the encapsulation material. The top surface of the solder foot 8 is exposed by horizontal grinding on the newly formed encapsulation surface. Further, a protective layer, such as a tin-plated layer, is electroplated on the exposed top surface of the solder foot 8, and the substrate is peeled off. At this time, the back side of the chip 2 is also processed. Since the present application takes the encapsulation of one chip 2 at a time as an example, the encapsulation material is solidified to form a product unit of the package 1. For the packaging process of encapsulating multiple chips 2 at a time, it is finally necessary to perform product cutting on the entire package in the cutting area to separate it into product units of the package 1.

[0031] A packaging structure of a high-voltage diode can be obtained by the above-mentioned packaging process of the high-voltage diode. Figure 16-Figure 17 As shown, the packaging structure includes a packaging body 1, and the packaging body 1 encapsulates: Chip 2, chip 2 is formed by brushing a glue layer A9 on the entire front side of the wafer, cutting it, and testing and screening it to be qualified. Electrodes are arranged on the front and back sides of chip 2, and glass is arranged at the edge of chip 2. The front side of chip 2 is brushed with a glue layer A9, and the back side of chip 2 is brushed with a glue layer B10; Wiring layer: wiring layer A3 and wiring layer B4 are plated horizontally on the front and back of chip 2 respectively, wiring layer A3 is in contact with glue layer A9, and wiring layer B4 is in contact with glue layer B10. Glue layer A9 on the front of chip 2 and glue layer B10 on the back of chip 2 are opposite to each other, have the same size and thickness, and are both conductive glues. The distribution of glue layer A9 and glue layer B10 on the surface of chip 2 does not exceed the edge glass of chip 2. Pillars: Pillars A5 and B6 are vertically electroplated in the package 1 and are stacked and connected up and down. One end of the pillar A5 away from the pillar B6 is connected to the wiring layer A3; Pad 7, pad 7 is connected to the end of column B6 away from column A5, the front side electrical property of chip 2 is transferred from wiring layer A3 through column A5 and column B6 to pad 7, and the back side electrical property of chip 2 is transferred from wiring layer B4; Solder pin 8 is plated on the electroplated wiring layer B4 and pad 7 respectively, and solder pin 8 is also encapsulated in the encapsulation material to form a product unit of package 1. Solder pin 8 is exposed flush with the surface of package 1, and a protective layer is plated on the top surface of the exposed solder pin 8.

[0032] The encapsulation material used in the present invention is a plastic encapsulation material, and the specific material may be epoxy resin, cyanate, polyimide, etc., which has low cost and good curing performance. The encapsulation process plays an important role in the field of semiconductor manufacturing, mainly in terms of protection, connection, support, reliability and promotion of technological progress. The encapsulation method is the compression molding method commonly used in this field.

[0033] All the steps of the electroplating process of the present invention are to first form electroplating protection on the surface through exposure and development photolithography technology, protect the places that do not need electroplating, expose the areas that need electroplating, and then form a metal seed layer in the area to be electroplated by sputtering or copper deposition or other appropriate methods. The metal seed layer is copper or other metal materials. The metal seed layer is to ensure the bonding force between the metals and metals and between the metals and the encapsulation materials in the subsequent electroplating, and at the same time provide a surface for the electroplating to attach conductive ions, thereby ensuring the electroplating effect. The entire steps in the electroplating process and the materials used are also common technical knowledge in this field. The metals electroplated in all the electroplating processes of the present invention are all made of metallic copper.

[0034] The present invention applies glue layer and electroplates wiring layer on both opposite sides of chip 2, and the distribution positions of glue layer A9 and glue layer B10 on chip 2 correspond, and the size, thickness and material are the same. The same glue layer is applied on both sides of chip 2, and the wiring layer is made of the same material and is covered with glue layer, so that the stress on the front and back sides of chip 2 is symmetrical, the stress directly acting on chip 2 is uniform, the life of chip 2 is extended, and the electroplated wiring layer replaces wire bonding or copper bridge bonding, so that the structure is more stable, and the conductive performance and surge resistance are better. By electroplating a large-area wiring layer and a large-area pad 7, the pad 7 is directly connected to the column, the thermal conductivity of the whole structure is better, the process is simple, the whole package size is smaller, and there is no need to prepare complex jigs or copper bridge belts.

[0035] It is to be understood that the present invention is described by some embodiments, and it is known to those skilled in the art that various changes or equivalent substitutions may be made to these features and embodiments without departing from the spirit and scope of the present invention. In addition, under the teachings of the present invention, these features and embodiments may be modified to adapt to specific circumstances and materials without departing from the spirit and scope of the present invention. Therefore, the present invention is not limited by the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of the present invention are within the scope of protection of the present invention.

Claims

1. A packaging process for a high voltage diode, characterized in that: The following steps are involved: Chip encapsulation: Place the chip with glue layer A on the front side on the substrate, encapsulate the chip with encapsulation material on the substrate, grind the encapsulation surface until the top surface of glue layer A is exposed, and drill vertical holes at the corresponding positions on the grinded surface; Electrical connection: Electroplating fills the column A in the drilled hole, and horizontally electroplating sets the wiring layer A on the polished surface. The wiring layer A contacts the top surface of the chip front glue layer A. One end of the wiring layer A is electrically connected to the column A. The encapsulation material is continued to be used on the polished surface to encapsulate the column A and the wiring layer A. After the encapsulation material is cured, it is peeled off from the substrate and turned upside down and placed back on the substrate, exposing the back of the chip; Electrical lead-out: Drill vertically at the corresponding position of the flipped package cover until the top of column A is exposed, continue to electroplating column B in the drilled hole, apply glue layer B on the back of the exposed chip, and electroplating wiring layer B in contact with the top surface of glue layer B and pads electrically connected to column B on the package cover to electrically lead out the chip.

2. The packaging process of the high voltage diode according to claim 1, characterized in that: In the chip encapsulation step, a glue layer A is applied to the entire front side of the wafer, and after the wafer is cut into chip units, the chips that have passed the test are mounted on the substrate with the glue-coated side facing upward.

3. The packaging process of the high voltage diode according to claim 1, characterized in that: In the chip encapsulation step, electrodes are arranged on the front and back sides of the chip, and glass is arranged at the edge of the chip.

4. The packaging process of the high voltage diode according to claim 3, characterized in that: In the electrical lead-out step, the adhesive layer A on the front side of the chip and the adhesive layer B on the back side of the chip are opposite to each other on both sides of the chip, have the same size and thickness, and are both conductive adhesives.

5. The packaging process of the high voltage diode according to claim 4, characterized in that: In the electrical lead-out step, the distribution of the adhesive layer A and the adhesive layer B on the chip surface does not exceed the chip edge glass.

6. The packaging process of the high voltage diode according to claim 1, characterized in that: The electrical lead-out step also includes a solder foot electroplating step, in which solder feet are respectively electroplated on the electroplated wiring layer B and the solder pad, and the encapsulation is continued to encapsulate the wiring layer B, the solder pad and the solder foot in the encapsulation material to form a product unit of the package.

7. The packaging process of the high voltage diode according to claim 6, characterized in that: In the solder foot electroplating step, the package surface is horizontally ground until the top surface of the solder foot is exposed, and a protective layer is electroplated on the exposed top surface of the solder foot.

8. A packaging structure of a high voltage diode, comprising a packaging body, characterized in that: The package contains: A chip, wherein a glue layer A is applied to the front side of the chip and a glue layer B is applied to the back side of the chip; Wiring layer: Wiring layer A and wiring layer B are plated horizontally on the front and back of the chip respectively, with wiring layer A in contact with glue layer A and wiring layer B in contact with glue layer B; Pillar: Pillar A and pillar B are vertically electroplated in the package body and are stacked and connected up and down, and one end of the pillar A away from the pillar B is connected to the wiring layer A; The pad is connected to one end of the column B away from the column A. The electrical properties of the front side of the chip are transferred from the wiring layer A through the columns A and B to the pad, and the electrical properties of the back side of the chip are transferred from the wiring layer B.

9. The packaging structure of the high voltage diode according to claim 8, characterized in that: The chip is formed by applying a glue layer A on the entire front side of the wafer, cutting it, and testing and screening for qualified ones.

10. The packaging structure of the high voltage diode according to claim 8, characterized in that: Electrodes are arranged on the front and back of the chip, and glass is arranged at the edge of the chip.

11. The packaging structure of the high voltage diode according to claim 10, characterized in that: The adhesive layer A on the front side of the chip and the adhesive layer B on the back side of the chip are located opposite to each other on both sides of the chip, have the same size and thickness, and are both conductive adhesives.

12. The packaging structure of the high voltage diode according to claim 11, characterized in that: The distribution of the adhesive layer A and the adhesive layer B on the chip surface does not exceed the chip edge glass.

13. The packaging structure of the high voltage diode according to claim 8, characterized in that: Solder feet are plated on the electroplated wiring layer B and the pads respectively, and the solder feet are also encapsulated in the encapsulation material to form a product unit of the package.

14. The packaging structure of the high voltage diode according to claim 13, characterized in that: The soldering feet are flush with the surface of the package body and exposed, and a protective layer is electroplated on the top surface of the exposed soldering feet.

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