Radio frequency device packaging structure and packaging process thereof
By etching grooves in the RF chip packaging structure and welding the transformer pins horizontally, combining layer-layer encapsulation processes to form a compact chip and transformer stacking structure, the problem of bending welding of transformer pins in the prior art is solved, the welding quality and electrical performance are improved, and the cost and volume are reduced.
Patent Information
- Application Number
- CN202411839162.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-13
- Publication Date
- 2025-04-04
AI Technical Summary
In the existing RF chip packaging structure, the transformer pins need to be bent and solder, resulting in poor welding quality, degraded electrical performance, shortened service life and affecting the appearance and cost of the product.
Design a RF device packaging structure and process to ensure that the transformer pins can be soldered horizontally and avoid bending welding by etching grooves on the top surface of the package. At the same time, a layered encapsulation process is used to form a stacked structure between the chip and the transformer, which is compactly packaged and reduces the volume.
It improves welding quality, enhances the electrical performance of the transformer, extends service life, improves product appearance and reduces production costs, and meets the needs of miniaturized mounting.
Smart Images
Figure CN119764188A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of chip packaging, and in particular relates to a radio frequency device packaging structure and a packaging process thereof. Background Art
[0002] With the development of the global mobile communication market, wireless communication systems have increasingly strong requirements for reducing chip size, reducing production costs and shortening R&D cycles. Manufacturers try their best to integrate digital, analog and some RF on a whole circuit. RF IC (RFIC) is the core component of modern wireless communication systems. The main function of RF chip is to convert low-frequency signals into high-frequency signals to achieve wireless communication. RF chips usually include key components such as RF front-end, RF transceiver, power amplifier, low-noise amplifier, etc. The performance of RF chip directly affects the performance of wireless communication system, such as transmission rate, coverage, power consumption, etc.
[0003] The transformer in the RF chip plays an important role: first, it is used for impedance conversion; second, it is used for positive or negative power synthesis, and plays the role of power distribution or power merging, etc. In the existing RF chip packaging process, the transformer is stacked on the chip packaging structure. After the chip packaging is completed, an external solder foot with electrical connection is provided on the packaging surface. The pins of the transformer are welded to the external solder foot as a whole, thereby realizing the electrical connection between the transformer and the chip. However, in this packaging structure, since the transformer has a certain size and the size of the external solder foot is limited, when the transformer pin is connected to the external solder foot, the transformer pin needs to be bent to ensure stable welding with the external solder foot. There are many problems with bending welding: 1. It affects the welding quality, uneven heat conduction leads to changes in internal stress of the metal, resulting in welding deformation, and causing the welding point to break and fail; 2. Bending welding will affect the electrical performance of the transformer and shorten its service life; 3. It affects the product appearance and production cost, etc.; Therefore, it is urgent to design a RF device packaging structure and its packaging process to solve the above problems. Summary of the invention
[0004] In order to solve the above problems in the prior art, the present invention provides a radio frequency device packaging structure and a packaging process thereof.
[0005] To achieve the above object, the present invention provides a radio frequency device packaging process, comprising the following steps: Chip encapsulation step: mount the chip in the center of the base island, and after encapsulation, grind to expose the output end of the chip, and electroplate an electrically connected redistribution layer on part of the output end to electrically wire the chip, and then electrically connect one end of the redistribution layer to the solder pin next to the base island through electroplating conductive pillars, and the solder pin leads the chip electrically; Output terminal electroplating step: electroplating a metal block on the other part of the output terminal exposed by grinding, increasing the height of the output terminal, and the top surface of the metal block is higher than the top surface of the redistribution layer, and the encapsulation operation is continued on the grinding surface to encapsulate the redistribution layer. At this time, the conductive column and the metal block are also completely encapsulated, and grinding is continued on the encapsulation surface until the top surface of the metal block is exposed; Circuit electroplating step: electroplating an electrically connected circuit layer on the top surface of the polished exposed metal block, and electroplating a connection column A at one end of the circuit layer, and continuing to encapsulate the circuit layer and the connection column A completely; Drilling and electroplating step: drilling a hole at a corresponding position of the package surface until the top surface of the connection column A is exposed, and electroplating a connection column B whose bottom surface is electrically connected to the connection column A in the drilled hole, and the top surface of the connection column B is flush with the package surface; Steps for installing the transformer: etch a groove in the middle of the package surface, and mount the transformer in the groove. The pins of the transformer are horizontally welded to the top surface of the connecting column B.
[0006] Furthermore, in the chip encapsulation step, a substrate is provided, on which a lead frame is placed, the lead frame including a base island and solder pins located next to the base island, and the back side of the chip opposite to the output end is mounted toward the base island for encapsulation.
[0007] Furthermore, in the circuit electroplating step, the top surface of the metal block is exposed by horizontal grinding on the package surface, and the circuit layer is horizontally laid and extended along the ground top surface of the package.
[0008] Furthermore, in the circuit electroplating step, the connection column A is electroplated and arranged at one end of the circuit layer away from the metal block, and the connection column A serves as an electrical connection end of the circuit layer.
[0009] Furthermore, in the transformer installation step, the depth of the etched groove matches the height of the transformer, and the bottom of the transformer is mounted in the groove. At this time, the pins of the transformer are horizontal and contact the connecting column B at the ends of the pins.
[0010] A radio frequency device packaging structure, comprising a packaging body, wherein the packaging body encapsulates: A chip, wherein the chip is electrically connected to a part of the output terminals of the chip through the electroplated redistribution layer and the conductive pillars at the ends of the redistribution layer, so that the electrical properties of the chip are led out of the package; Circuit layer, another part of the output end of the chip is electrically connected to the circuit layer stacked on the redistribution layer by electroplating, and the end of the circuit layer is electrically connected to the connection column B; The transformer has a groove etched in the middle of the top surface of the package body, the connecting column B is encapsulated in the encapsulation material around the groove, the transformer is mounted in the groove, and the pins of the transformer are horizontally welded on the top surface of the connecting column B.
[0011] Furthermore, the package body encapsulates a lead frame, which includes a base island and solder pins located next to the base island. The back of the chip is mounted toward the base island for encapsulation, and one end of the conductive column is electrically connected to the solder pin.
[0012] Furthermore, a metal block is electroplated on the output end of the chip, the circuit layer is electrically connected to the chip through the metal block, and the circuit layer extends horizontally in the package.
[0013] Furthermore, a connection column A is plated at the end of the circuit layer, and a connection column B is plated and connected above the connection column A. The connection column B is formed by drilling a hole through the top surface of the package body and then electroplating in the hole, and the top surface of the connection column B is flush with the top surface of the package body.
[0014] Furthermore, the etching depth of the groove matches the height of the transformer, and the bottom of the transformer is mounted in the groove. At this time, the pins of the transformer are in a horizontal state and contact the connecting column B at the ends of the pins.
[0015] The present invention: 1. After etching the groove on the top surface of the package, mount the transformer to ensure that the pins of the transformer can be horizontally welded to the circuit, avoid bending the pins during welding, and ensure welding quality; 2. The stacking structure of the chip and the transformer is formed through the layer-by-layer encapsulation process, which has a compact structure and a reduced package volume to meet the needs of miniaturized mounting. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] Figure 1-Figure 5 A cross-sectional view of a chip encapsulation step of a radio frequency device packaging process of the present invention; Figure 6-Figure 7 A cross-sectional view of an output end electroplating step of a radio frequency device packaging process of the present invention; Figure 8-Figure 10 A cross-sectional view of a circuit electroplating step of a radio frequency device packaging process of the present invention; Figure 11-Figure 12 A cross-sectional view of a drilling and electroplating step of a radio frequency device packaging process of the present invention; Figure 13-Figure 15 A cross-sectional view of a transformer installation step in a radio frequency device packaging process of the present invention; Fig.16 This is a product cross-sectional view of the radio frequency device packaging structure of the present invention.
[0017] In the figure: 1. Package body; 2. Chip; 3. Rewiring layer; 4. Solder pin; 5. Base island; 6. Circuit layer; 7. Connection column A; 8. Connection column B; 9. Transformer; 10. Groove. DETAILED DESCRIPTION
[0018] The content of the present invention will be explained below in conjunction with specific embodiments, examples of which are shown in the accompanying drawings, wherein the same or similar numbers throughout represent the same or similar components or components with the same or similar functions.
[0019] The directional terms mentioned in the present invention, such as: up, down, left, right, front, back, inside, outside, front, back, side, etc., are only reference directions of the drawings. The embodiments described below with reference to the drawings and the directional terms used are exemplary and are only used to explain the present invention, and cannot be understood as limiting the present invention. In addition, the various specific process and material examples provided in the present invention are all those skilled in the art who can recognize the application of other processes and / or the use of other materials.
[0020] In order to better understand the purpose, structure and function of the present invention, the following Figure 1 -Attached Fig.15 , the RF device packaging structure and packaging process proposed by the present invention are further described in detail. The process includes the following steps: Chip 2 encapsulation step: mount the chip 2 in the center of the base island 5, and after encapsulation, grind to expose the output end of the chip 2, and electroplate the electrically connected redistribution layer 3 on part of the output end to electrically wire the chip 2, and then electrically connect one end of the redistribution layer 3 to the solder pin 4 next to the base island 5 by electroplating the conductive column, and the solder pin 4 leads the electrical property of the chip 2 out; Output terminal electroplating step: electroplating a metal block on the other part of the output terminal exposed by grinding, increasing the height of the output terminal, and the top surface of the metal block is higher than the top surface of the redistribution layer 3, and continuing the encapsulation operation on the grinding surface to encapsulate the redistribution layer 3. At this time, the conductive column and the metal block are also completely encapsulated, and grinding is continued on the encapsulation surface until the top surface of the metal block is exposed; Circuit plating step: electroplating the electrically connected circuit layer 6 on the top surface of the polished exposed metal block, and electroplating the connecting post A7 at one end of the circuit layer 6, and continuing to encapsulate the circuit layer 6 and the connecting post A7 completely; Drilling and electroplating step: drilling holes at corresponding positions of the package surface until the top surface of the connection column A7 is exposed, and electroplating the connection column B8 whose bottom surface is electrically connected to the connection column A7 in the drilled hole, so that the top surface of the connection column B8 is flush with the package surface; Steps for installing transformer 9: a groove 10 is etched in the middle of the package surface, and transformer 9 is mounted in the groove 10, and the pins of transformer 9 are horizontally welded to the top surface of connecting column B8.
[0021] Among them, Figure 1-Figure 5As shown, in the chip 2 encapsulation step, a substrate is provided. The substrate is made of a material commonly used in the art, and may be a resin board, etc. A lead frame is placed on the substrate. The lead frame includes a base island 5 and a solder foot 4 located next to the base island 5. The back side of the chip 2 opposite to the output end is mounted toward the base island 5 for encapsulation. The base island 5 supports the mounting of the chip 2. After encapsulation, the surface of the base island 5 is exposed outside the package body 1 to dissipate the heat of the chip 2. The solder foot 4 serves as a medium for electrically leading the chip 2 out of the package body 1. The number of chips 2 placed on the substrate is set according to the actual product situation and the size of the substrate. After the chip 2 is placed, the output end is away from the base island 5. Through the first encapsulation process, the chip 2 and its output end are completely encapsulated. After encapsulation, the encapsulation material is ground on the top surface of the encapsulation by horizontal mechanical grinding, so that the output end of the chip 2 is exposed, while the other parts of the chip 2 are encapsulated.
[0022] A hole is drilled vertically downward in the corresponding area of the ground package top surface until the solder foot 4 is exposed, and a conductive column is electroplated in the drilled hole. A redistribution layer 3 is electroplated on the ground package top surface. The redistribution layer 3 extends horizontally along the package surface, and one end of the redistribution layer 3 is electrically connected to part of the output terminals of the chip 2. The redistribution layer 3 leads out the output terminals of the chip and then readjusts the layout to improve the output terminal spacing; the top of the conductive column is electrically connected to the end of the redistribution layer 3, and then the chip 2 is electrically transmitted through the output terminal, the redistribution layer 3, and the solder foot 4, to achieve electrical connection between the inside and outside of the package 1.
[0023] Among them, Figure 6-Figure 7 As shown, in the output end electroplating step, a part of the chip 2 needs to electrically lead out to the package body 1 for the application connection end of the entire package body 1, and the other part needs to electrically connect to the transformer 9 to play the role of the transformer 9 and realize the function of the RF circuit. Specifically, a metal block is electroplated on the other part of the output end exposed by the above grinding, and the top surface of the metal block is higher than the top surface of the redistribution layer 3. Therefore, when it is encapsulated again, the redistribution layer 3 is completely encapsulated, and the top surface of the metal block is exposed by mechanical grinding at the level of the encapsulation surface. The metal block separates the different output ends of the chip 2 to avoid contact short circuits between circuits.
[0024] Among them, Figure 8-Figure 10 As shown, in the circuit plating step, the circuit layer 6 is continuously plated on the top surface of the package where the metal block is exposed after grinding. The metal block is electrically connected to the circuit layer 6. The function of the circuit layer 6 is the same as that of the redistribution layer 3. The circuit layer 6 leads out the output end of the chip 2 and then readjusts the layout to improve the output end spacing. The circuit layer 6 is also horizontally flattened and extended on the top surface of the package after grinding. Therefore, in order to better connect the circuit layer 6, it is necessary to plate the connecting column A7 at the end of the circuit layer 6. At this time, the circuit layer 6 is also completely encapsulated by the encapsulated connecting column A7.
[0025] Among them, Figure 11-Figure 12As shown, in the drilling and electroplating step, a hole is drilled in the area corresponding to the connecting column A7 on the top surface of the package until the top surface of the connecting column A7 is exposed, and a connecting column B8 is electroplated in the hole to fill the drilled hole. The connecting column B8 is electroplated and connected to the connecting column A7 as a whole, and the top surface of the connecting column B8 is flush with the package surface. At this point, the encapsulation process is completed.
[0026] Among them, Figure 13-Figure 15 As shown, in the step of installing the transformer 9, since the transformer 9 needs efficient heat dissipation and the thermal resistance of the encapsulation material is relatively large, it is not suitable to be encapsulated in the package body 1. In the middle position of the package surface, that is, the corresponding position of the chip 2 encapsulation, the encapsulation material is etched to form a groove 10, and the transformer 9 is mounted in the groove 10. The depth of the etched groove 10 matches the height of the transformer 9. The bottom of the transformer 9 is mounted in the groove 10. At this time, the pins of the transformer 9 are in a horizontal state and contact with the connecting column B8 at the end of the pin. The pins of the transformer 9 and the connecting column B8 are welded as a whole through a welding process. Each chip 2 is electrically connected to a transformer 9. After completion, the substrate If multiple chips 2 are placed on it, they will eventually need to go through a cutting process to separate the chip 2 units to form product units. After peeling off the substrate, the solder feet 4 and the base island 5 of the lead frame are exposed outside the package 1. The solder feet 4 serve as connectors for electrical welding of the package 1, and the base island 5 dissipates the heat of the chip 2 to the outside of the package 1. Through the layer-by-layer encapsulation process, a stacking structure of the chip 2 and the transformer 9 is formed. The structure is compact, and the area of the package 1 is reduced to meet the requirements of miniaturized mounting. Moreover, after etching a groove 10 on the top surface of the package 1, the transformer 9 is mounted to ensure that the pins of the transformer 9 can be horizontally welded to the circuit, avoiding pin bending during welding, and ensuring welding quality.
[0027] A radio frequency device packaging structure can be obtained through the above radio frequency device packaging process, such as Fig.16 As shown, the structure includes a package body 1, and the package body 1 encapsulates: Chip 2, chip 2 is electrically connected to part of the output ends of chip 2 through the electroplated redistribution layer 3 and the conductive pillars at the end of the redistribution layer 3, so that the electrical properties of chip 2 are led out of the package 1; Circuit layer 6, another part of the output end of the chip 2 is electrically connected to the circuit layer 6 stacked on the redistribution layer 3 by electroplating, and the end of the circuit layer 6 is electrically connected to the connection column B8; Transformer 9, a groove 10 is etched in the middle of the top surface of the package body 1, the connecting column B8 is encapsulated in the encapsulation material around the groove 10, the transformer 9 is mounted in the groove 10, and the pins of the transformer 9 are horizontally welded to the top surface of the connecting column B8.
[0028] A lead frame is encapsulated in the package body 1, and the lead frame includes a base island 5 and a solder pin 4 located next to the base island 5. The back of the chip 2 is mounted toward the base island 5 for encapsulation, one end of the conductive column is electrically connected to the solder pin 4, a metal block is electroplated on the output end of the chip 2, and the circuit layer 6 is electrically connected to the chip 2 through the metal block. The circuit layer 6 extends horizontally in the package body 1, and a connecting column A7 is electroplated on the end of the circuit layer 6. The connecting column B8 is electroplated and connected above the connecting column A7. The connecting column B8 is formed by drilling a hole on the top surface of the package body 1 and then electroplating in the hole, and the top surface of the connecting column B8 is flush with the top surface of the package body 1. The etching depth of the groove 10 matches the height of the transformer 9. The bottom of the transformer 9 is mounted in the groove 10. At this time, the pins of the transformer 9 are in a horizontal state and contact with the connecting column B8 at the ends of the pins.
[0029] The packaging material used in the present invention can be epoxy resin, cyanate, polyimide, etc., which has low cost and good curing performance. The packaging process plays an important role in the field of semiconductor manufacturing, mainly in protection, connection, support, reliability and promotion of technological progress. The protection function refers to the chip 2 packaging can protect the chip 2 from mechanical damage, moisture, dust and other external environmental factors, ensuring the normal operation of the chip 2 in extreme environments; the connection function refers to the packaging provides a way to connect the chip 2 with other electronic components, so that the chip 2 can be installed and used on the circuit board; the support function refers to the packaging while supporting the chip 2, it can fix the chip 2 to prevent it from being damaged; reliability refers to the increasingly high reliability requirements for packaging materials and processes to ensure that the chip 2 can operate normally in various extreme environments.
[0030] All the steps of the electroplating process of the present invention are to first form electroplating protection on the surface through exposure and development photolithography technology, and then form a metal seed layer in the area to be electroplated by sputtering or copper deposition or other appropriate methods. The metal seed layer is made of copper or other metal materials. The metal seed layer is to ensure the bonding force between the subsequent electroplated metal and the encapsulation material, and at the same time provide a surface for the electroplating to attach conductive ions to ensure the electroplating effect. The entire steps in the electroplating process and the materials used are also technical common sense in this field.
[0031] The present invention forms a stacked structure of the chip 2 and the transformer 9 through a layer-by-layer encapsulation process, which has a compact structure and a reduced packaging volume, thereby meeting the requirements of miniaturized mounting. Moreover, after a groove 10 is etched on the top surface of the package body 1 and the transformer 9 is mounted, it is ensured that the pins of the transformer 9 can be horizontally welded to the circuit, avoiding pin bending during welding, thereby ensuring welding quality.
[0032] It is to be understood that the present invention is described by some embodiments, and it is known to those skilled in the art that various changes or equivalent substitutions may be made to these features and embodiments without departing from the spirit and scope of the present invention. In addition, under the teachings of the present invention, these features and embodiments may be modified to adapt to specific circumstances and materials without departing from the spirit and scope of the present invention. Therefore, the present invention is not limited by the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of the present invention are within the scope of protection of the present invention.
Claims
1. A radio frequency device packaging process, characterized in that: The following steps are involved: Chip encapsulation step: mount the chip in the center of the base island, and after encapsulation, grind to expose the output end of the chip, and electroplate an electrically connected redistribution layer on part of the output end to electrically wire the chip, and then electrically connect one end of the redistribution layer to the solder pin next to the base island through electroplating conductive pillars, and the solder pin leads the chip electrically; Output terminal electroplating step: electroplating a metal block on the other part of the output terminal exposed by grinding, increasing the height of the output terminal, and the top surface of the metal block is higher than the top surface of the redistribution layer, and the encapsulation operation is continued on the grinding surface to encapsulate the redistribution layer. At this time, the conductive column and the metal block are also completely encapsulated, and grinding is continued on the encapsulation surface until the top surface of the metal block is exposed; Circuit electroplating step: electroplating an electrically connected circuit layer on the top surface of the polished exposed metal block, and electroplating a connection column A at one end of the circuit layer, and continuing to encapsulate the circuit layer and the connection column A completely; Drilling and electroplating step: drilling a hole at a corresponding position of the package surface until the top surface of the connection column A is exposed, and electroplating a connection column B whose bottom surface is electrically connected to the connection column A in the drilled hole, and the top surface of the connection column B is flush with the package surface; Steps for installing the transformer: etch a groove in the middle of the package surface, and mount the transformer in the groove. The pins of the transformer are horizontally welded to the top surface of the connecting column B.
2. The RF device packaging process according to claim 1, characterized in that: In the chip encapsulation step, a substrate is provided, on which a lead frame is placed, the lead frame including a base island and solder pins located next to the base island, and the back side of the chip opposite to the output end is mounted toward the base island for encapsulation.
3. The RF device packaging process according to claim 1, characterized in that: In the circuit electroplating step, the top surface of the metal block is exposed by horizontal grinding on the package surface, and the circuit layer is horizontally laid and extended along the ground package top surface.
4. The RF device packaging process according to claim 3, characterized in that: In the circuit electroplating step, the connection column A is electroplated and arranged at one end of the circuit layer away from the metal block, and the connection column A serves as an electrical connection end of the circuit layer.
5. The radio frequency device packaging process according to claim 4, characterized in that: In the transformer installation step, the depth of the etched groove matches the height of the transformer, and the bottom of the transformer is mounted in the groove. At this time, the pins of the transformer are horizontal and contact the connecting column B at the ends of the pins.
6. A radio frequency device packaging structure, comprising a packaging body, characterized in that: The package contains: A chip, wherein the chip is electrically connected to a part of the output terminals of the chip through the electroplated redistribution layer and the conductive pillars at the ends of the redistribution layer, so that the electrical properties of the chip are led out of the package; Circuit layer, another part of the output end of the chip is electrically connected to the circuit layer stacked on the redistribution layer by electroplating, and the end of the circuit layer is electrically connected to the connection column B; The transformer has a groove etched in the middle of the top surface of the package body, the connecting column B is encapsulated in the encapsulation material around the groove, the transformer is mounted in the groove, and the pins of the transformer are horizontally welded on the top surface of the connecting column B.
7. The radio frequency device packaging structure according to claim 6, characterized in that: The package body encapsulates a lead frame, which includes a base island and solder pins located next to the base island. The back of the chip is mounted toward the base island for encapsulation, and one end of the conductive column is electrically connected to the solder pin.
8. The radio frequency device packaging structure according to claim 6, characterized in that: A metal block is electroplated on the output end of the chip, the circuit layer is electrically connected to the chip through the metal block, and the circuit layer is horizontally spread and extended in the package body.
9. The radio frequency device packaging structure according to claim 8, characterized in that: The end of the circuit layer is electroplated with a connection column A, and a connection column B is electroplated and connected above the connection column A. The connection column B is formed by drilling a hole on the top surface of the package body and then electroplating in the hole, and the top surface of the connection column B is flush with the top surface of the package body.
10. The radio frequency device packaging structure according to claim 9, characterized in that: The etching depth of the groove matches the height of the transformer, and the bottom of the transformer is mounted in the groove. At this time, the pins of the transformer are in a horizontal state and contact with the connecting column B at the ends of the pins.