Display panel and display device

Abstract

A display panel and a display device are disclosed. The display panel includes: a substrate, a plurality of pixel driving circuit groups, a plurality of row-direction initial signal lines, and a plurality of column-direction initial signal lines. The plurality of pixel driving circuit groups are arrayed along row and column directions, each pixel driving circuit group including one or more adjacent pixel driving circuits in the row direction. The orthographic projections of the row-direction initial signal lines on the substrate extend along the row direction and are spaced apart along the column direction. The orthographic projections of the plurality of column-direction initial signal lines on the substrate extend along the column direction and are spaced apart along the row direction. The column-direction initial signal lines and pixel driving circuit groups are correspondingly arranged, and the column-direction initial signal lines provide initial signals to their corresponding pixel driving circuit groups. Each pixel driving circuit group includes an x-region located at the same position. The plurality of column-direction initial signal lines include an x-th column-direction initial signal line and a y-th column-direction initial signal line. The x-th column-direction initial signal line includes an x1-th via connection portion, and the x-th column-direction initial signal line is connected to at least a portion of the pixel driving circuit group via the x1-th via connection portion. The row-direction initial signal line intersecting with it, and the y-th column-direction initial signal line are connected at least partially to the row-direction initial signal line through vias; in the region where the x-th column-direction initial signal line and its corresponding pixel driving circuit group are located, the x1-th via connection portion is located within region x; in the region where the pixel driving circuit group corresponding to the x-th column-direction initial signal line is located, the area of ​​the orthogonal projection of all light-shielding structures in region x onto the substrate is S1; in the region where the pixel driving circuit group corresponding to the y-th column-direction initial signal line is located, the area of ​​the orthogonal projection of all light-shielding structures in region x onto the substrate is S2, and S1 and S2 are the same or approximately the same; the distance between the orthogonal projection of the x-th column-direction initial signal line on the substrate and the orthogonal projection of its nearest y-th column-direction initial signal line on the substrate is less than 270 μm or greater than 700 μm. This display panel has a high fingerprint detection accuracy.

Description

Display panel and display device Technical Field

[0001] This disclosure relates to the field of display technology, and more particularly to a display panel and a display device. Background Technology

[0002] In related technologies, the fingerprint sensor located on the back of the display panel detects vertical lines on the display panel itself, and these vertical lines interfere with the fingerprint sensor's fingerprint detection.

[0003] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art.

[0004] Summary of the Invention

[0005] According to one aspect of this disclosure, a display panel is provided, wherein the display panel includes:

[0006] Substrate;

[0007] Multiple pixel driving circuit groups are arranged in an array along the row and column directions, and each pixel driving circuit group includes one or more pixel driving circuits that are adjacent in the row direction.

[0008] Multiple row-direction initial signal lines, wherein the orthographic projection of the row-direction initial signal lines on the substrate extends along the row direction and is spaced apart along the column direction;

[0009] Multiple column-oriented initial signal lines, wherein the orthographic projection of the multiple column-oriented initial signal lines on the substrate extends along the column direction and is spaced apart along the row direction;

[0010] The column-directed initial signal line and the pixel driving circuit group are respectively arranged. The column-directed initial signal line is used to provide an initial signal to the pixel driving circuit group corresponding to it. The area where each pixel driving circuit group is located includes an x-region located at the same position, and the area of ​​the x-region in the area where each pixel driving circuit group is located is the same.

[0011] The plurality of column-directed initial signal lines include an xth column-directed initial signal line and a yth column-directed initial signal line. The xth column-directed initial signal line includes an x1th via-connection portion. The xth column-directed initial signal line is connected to at least partially intersecting with the row-directed initial signal line through the x1th via-connection portion. The yth column-directed initial signal line is connected to at least partially intersecting with the row-directed initial signal line through a via.

[0012] In the region where the xth column initial signal line and the corresponding pixel driving circuit group are located, the x1th via connection is located within the x region;

[0013] In the region where the pixel driving circuit group corresponding to the x-th column initial signal line is located, the area of ​​the orthogonal projection of all light-shielding structures in the x-region onto the substrate is S1;

[0014] In the region where the pixel driving circuit group corresponding to the initial signal line in column y is located, the area of ​​the orthogonal projection of all light-shielding structures in region x onto the substrate is S2, and S1 and S2 are the same or approximately the same.

[0015] The distance between the orthographic projection of the x-th column initial signal line on the substrate and the orthographic projection of the nearest y-th column initial signal line on the substrate is less than 270 μm or greater than 700 μm.

[0016] In an exemplary embodiment of this disclosure, the y-th column-directed initial signal line includes a y-th via connection portion, and the y-th column-directed initial signal line is connected to at least partially intersecting the row-directed initial signal line through the y-th via connection portion via a via.

[0017] At least a portion of the orthographic projection of the x1th via connection on the substrate and the orthographic projection of the yth via connection on the substrate are misaligned in the column direction.

[0018] In an exemplary embodiment of this disclosure, the xth column initial signal line further includes an xth main body extension connected to the x1th via connection portion, and the size of the orthogonal projection of the x1th via connection portion on the substrate in the row direction is greater than the size of the orthogonal projection of the xth main body extension portion on the substrate in the row direction.

[0019] The x1th via connection portion includes an xth column extension portion and a protrusion portion. The orthogonal projection of the protrusion portion on the substrate is provided in the row direction on one or both sides of the orthogonal projection of the xth column extension portion on the substrate.

[0020] Wherein, the orthographic projection of the protrusion on the substrate and the orthographic projection of the other light-shielding structure on the substrate do not overlap at least partially;

[0021] The yth column initial signal line includes a yth column extension, and the orth projection of the yth column extension on the substrate and the orth projection of the x1 via connection on the substrate are arranged opposite to each other in the row direction.

[0022] The display panel also includes:

[0023] The light-shielding portion is provided on one or both sides of the orthogonal projection of the y-th column extension portion on the substrate in the row direction.

[0024] In one exemplary embodiment of this disclosure, the light-shielding portion includes:

[0025] A first light-shielding portion is connected to the same layer as the y-th column initial signal line. The orthogonal projection of the first light-shielding portion on the substrate protrudes in the row direction and is disposed on one or both sides of the orthogonal projection of the y-th column extension portion on the substrate.

[0026] In one exemplary embodiment of this disclosure, the plurality of row-direction initial signal lines include an x-th row-direction initial signal line and a y-th row-direction initial signal line, the x-th column-direction initial signal line is connected to the x-th row-direction initial signal line that intersects with it, and the y-th column-direction initial signal line is connected to the y-th row-direction initial signal line that intersects with it.

[0027] The display panel further includes a first source / drain layer, which is located on one side of the substrate. The first source / drain layer includes:

[0028] The xth bridging section is connected to the pixel driving circuit and the xth row initial signal line respectively;

[0029] The x2 via connection part is connected to the xth bridge part, and the x1 via connection part is connected to the x2 via connection part through a via;

[0030] The orthographic projection of the yth virtual via connection portion on the substrate and the orthographic projection of the yth column extension portion on the substrate at least partially overlap;

[0031] The light-shielding part includes:

[0032] The second light-shielding part is provided on one or both sides of the orthogonal projection of the second light-shielding part on the substrate in the row direction.

[0033] The structure of the yth virtual via connection portion forms the second light-shielding portion.

[0034] In one exemplary embodiment of this disclosure, the display panel further includes:

[0035] The y-th bridging section is connected to the y-th column-directed initial signal line and the y-th row-directed initial signal line respectively;

[0036] In the same group of pixel driving circuits:

[0037] Furthermore, the yth virtual via connection and the xth bridging connection are connected on the same layer;

[0038] Alternatively, the yth virtual via connection and the yth bridge connection are connected on the same layer.

[0039] In one exemplary embodiment of this disclosure, the pixel driving circuit includes a driving transistor, which is used to provide a driving current to the light-emitting unit according to its gate voltage;

[0040] The display panel also includes:

[0041] An active layer is located on one side of the substrate, and a portion of the structure of the active layer is used to form the channel region of the driving transistor.

[0042] A shielding layer is located between the substrate and the active layer, and a portion of the structure of the shielding layer forms the light-shielding portion.

[0043] In one exemplary embodiment of this disclosure, the display panel further includes:

[0044] A touch layer is located on one side of the substrate. A portion of the structure of the touch layer is used to form a touch electrode, and a portion of the structure of the touch layer forms the light-shielding portion.

[0045] In one exemplary embodiment of this disclosure, the pixel driving circuit includes a driving transistor and a capacitor. The driving transistor is used to provide a driving current to the light-emitting unit according to its gate voltage. The first electrode of the capacitor is connected to the gate of the driving transistor, and the second electrode of the capacitor is connected to a power supply line.

[0046] The display panel also includes:

[0047] The second gate layer is located on one side of the substrate. The second gate layer includes a second conductive portion and a first connecting portion. The second conductive portion is used to form the second electrode of the capacitor. The first connecting portion is connected between two adjacent second conductive portions in the same pixel driving circuit group.

[0048] The second gate layer further includes an epitaxial portion connected to the first connection portion, and the orthographic projection of the epitaxial portion on the substrate is located on one side of the orthographic projection of the first connection portion on the substrate in the column direction, and at least a portion of the structure of the epitaxial portion forms the light-shielding portion.

[0049] In an exemplary embodiment of this disclosure, the xth column initial signal line further includes an xth main body extension connected to the x1th via connection portion, wherein the size of the orthogonal projection of the x1th via connection portion on the substrate in the row direction is equal to the size of the orthogonal projection of the xth main body extension portion on the substrate in the row direction.

[0050] In one exemplary embodiment of this disclosure, the display panel further includes:

[0051] The x2 via connection part is connected to the x1 via connection part through a via;

[0052] The orthographic projection of the x2th via connection on the substrate is located within the orthographic projection of the x1th via connection on the substrate.

[0053] In an exemplary embodiment of this disclosure, the yth via connection portion is connected to the row initial signal line through a first via, and the x1th via connection portion is connected to the row initial signal line through a second via.

[0054] The area of ​​the orthogonal projection of the opening of the first via facing the y-th via connection portion on the substrate is greater than the area of ​​the orthogonal projection of the opening of the second via facing the x1-th via connection portion on the substrate.

[0055] In one exemplary embodiment of this disclosure, the pixel driving circuit includes:

[0056] Drive transistors;

[0057] The first transistor has a first terminal connected to the first column initial signal line and a second terminal connected to the gate of the driving transistor.

[0058] The seventh transistor has its first electrode connected to the second column initial signal line and its second electrode connected to the first electrode of the light-emitting unit.

[0059] The eighth transistor has its first terminal connected to the third column initial signal line and its second terminal connected to the first terminal of the driving transistor.

[0060] Wherein, the xth column-directed initial signal line forms the first column-directed initial signal line, and the yth column-directed initial signal line forms the second column-directed initial signal line or the third column-directed initial signal line.

[0061] In one exemplary embodiment of this disclosure, the orthographic projections of the first column-directed initial signal line, the second column-directed initial signal line, the third column-directed initial signal line, and the second column-directed initial signal line on the substrate are sequentially and cyclically distributed in the row direction.

[0062] In one exemplary embodiment of this disclosure, the pixel driving circuit includes:

[0063] Drive transistors;

[0064] The first transistor has a first terminal connected to the first column initial signal line and a second terminal connected to the gate of the driving transistor.

[0065] The seventh transistor has its first electrode connected to the second column initial signal line and its second electrode connected to the first electrode of the light-emitting unit.

[0066] The eighth transistor has its first terminal connected to the third column initial signal line and its second terminal connected to the first terminal of the driving transistor.

[0067] Wherein, the xth column-oriented initial signal line forms the first column-oriented initial signal line corresponding to a pixel driving circuit group, and the yth column-oriented initial signal line forms the first column-oriented initial signal line corresponding to another pixel driving circuit group;

[0068] The orthographic projections of the first column initial signal line, the second column initial signal line, and the third column initial signal line on the substrate are sequentially and cyclically distributed in the row direction.

[0069] In one exemplary embodiment of this disclosure, the pixel driving circuit further includes:

[0070] The second transistor has a first terminal connected to the gate of the driving transistor and a second terminal connected to the second terminal of the driving transistor;

[0071] The capacitor has its first electrode connected to the gate of the driving transistor and its second electrode connected to the power supply line.

[0072] The display panel also includes:

[0073] A first gate layer is located on one side of the substrate. The first gate layer includes a first gate line. The orthographic projection of the first gate line on the substrate extends in a row direction. A portion of the structure of the first gate line is used to form the gate of the second transistor.

[0074] The second gate layer is located on the side of the first gate layer away from the substrate. The second gate layer includes a second conductive portion and a first connecting portion. The second conductive portion is used to form the second electrode of the capacitor. The first connecting portion is connected between two adjacent second conductive portions in the same pixel driving circuit group.

[0075] Wherein, the orthographic projection of the x1th via connection portion on the substrate is at least partially located between the orthographic projection of the first connection portion on the substrate and the orthographic projection of the first gate line on the substrate.

[0076] In one exemplary embodiment of this disclosure, the pixel driving circuit group includes two pixel driving circuits distributed in the row direction, and the two pixel driving circuits in the same pixel driving circuit group are arranged at least partially mirror-symmetrically on the substrate.

[0077] In one exemplary embodiment of this disclosure, the pixel driving circuit includes:

[0078] Drive transistors;

[0079] The first transistor has a first terminal connected to the first row initial signal line and a second terminal connected to the gate of the driving transistor.

[0080] The second transistor has a first terminal connected to the gate of the driving transistor and a second terminal connected to the second terminal of the driving transistor;

[0081] The fourth transistor has its first terminal connected to the data line and its second terminal connected to the first terminal of the driving transistor.

[0082] The fifth transistor has its first terminal connected to the power supply line and its second terminal connected to the first terminal of the driving transistor.

[0083] The sixth transistor has its first electrode connected to the second electrode of the driving transistor, and the second electrode connected to the first electrode of the light-emitting unit.

[0084] The seventh transistor has its first electrode connected to the second row initial signal line and its second electrode connected to the first electrode of the light-emitting unit.

[0085] The eighth transistor has its first terminal connected to the third row of the initial signal line, and its second terminal connected to the first terminal of the driving transistor.

[0086] The capacitor has its first electrode connected to the gate of the driving transistor and its second electrode connected to the power supply line.

[0087] In one exemplary embodiment of this disclosure, the pixel driving circuit includes:

[0088] Drive transistors;

[0089] The first transistor has a first terminal connected to the first row initial signal line and a second terminal connected to the gate of the driving transistor.

[0090] The fourth transistor has its first terminal connected to the data line and its second terminal connected to the first terminal of the driving transistor.

[0091] The display panel also includes:

[0092] The second bridging portion is connected to the gate of the driving transistor via a via;

[0093] The sixth bridging portion is connected to the first electrode of the fourth transistor via a via;

[0094] The sixth conductive part is connected to one side of the first row initial signal line in the column direction, and the orthographic projection of the sixth conductive part on the substrate is located between the orthographic projection of the second bridging part on the substrate and the orthographic projection of the sixth bridging part on the substrate.

[0095] In one exemplary embodiment of this disclosure, the y-th column extension and the light-shielding portion are located in the x region.

[0096] According to one aspect of this disclosure, a display device is provided, wherein the display device includes the display panel described above.

[0097] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0098] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0099] Figure 1 is a schematic diagram of the structure of a display panel in the related art;

[0100] Figure 2 is a schematic diagram of the structure of an exemplary embodiment of the display panel of this disclosure;

[0101] Figure 3 is a partial structural layout of a display panel in an exemplary embodiment of the present disclosure;

[0102] Figure 4 is a structural layout of the row initial signal line and bridging section in the display panel shown in Figure 3;

[0103] Figure 5 is a structural layout of the column initial signal lines in the display panel shown in Figure 3;

[0104] Figure 6 is a partial structural layout of a display panel in an exemplary embodiment of the present disclosure;

[0105] Figure 7 is a partial structural layout of a display panel in an exemplary embodiment of the present disclosure;

[0106] Figure 8 is a structural layout of the second gate layer in the display panel shown in Figure 7;

[0107] Figure 9 is a partial structural layout of another exemplary embodiment of the display panel of this disclosure;

[0108] Figure 10 is a structural layout of the row initial signal line and bridging section in the display panel shown in Figure 9;

[0109] Figure 11 is a partial structural layout of another exemplary embodiment of the display panel of this disclosure;

[0110] Figure 12 is a schematic diagram of the pixel driving circuit in an exemplary embodiment of the display panel of this disclosure;

[0111] Figure 13 is a structural layout diagram of an exemplary embodiment of the display panel of this disclosure;

[0112] Figure 14 is a structural layout of the shielding layer in the display panel shown in Figure 13;

[0113] Figure 15 is a structural layout of the active layer in the display panel shown in Figure 13;

[0114] Figure 16 is a structural layout of the first gate layer in the display panel shown in Figure 13;

[0115] Figure 17 is a structural layout of the second gate layer in the display panel shown in Figure 13;

[0116] Figure 18 is a structural layout of the first source / drain layer in the display panel shown in Figure 13;

[0117] Figure 19 is a structural layout of the second source / drain layer in the display panel shown in Figure 13;

[0118] Figure 20 is a structural layout of the electrode layer in the display panel shown in Figure 13;

[0119] Figure 21 is a structural layout of the shielding layer and active layer in the display panel shown in Figure 13;

[0120] Figure 22 is a structural layout of the shielding layer, active layer, and first gate layer in the display panel shown in Figure 13;

[0121] Figure 23 is a structural layout of the shielding layer, active layer, first gate layer and second gate layer in the display panel shown in Figure 13;

[0122] Figure 24 is a structural layout of the shielding layer, active layer, first gate layer, second gate layer, and first source / drain layer in the display panel shown in Figure 13;

[0123] Figure 25 is a structural layout of the shielding layer, active layer, first gate layer, second gate layer, first source / drain layer, and second source / drain layer in the display panel shown in Figure 13.

[0124] Figure 26 is a partial cross-sectional view of the display panel shown in Figure 13, cut along the dashed line AA. Detailed Implementation

[0125] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that this disclosure will be more comprehensive and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore their detailed description will be omitted.

[0126] The terms “a,” “one,” and “the” are used to indicate the existence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended meaning of inclusion and that there may be other elements / components / etc. in addition to the listed elements / components / etc.

[0127] In the description of this disclosure, unless otherwise expressly specified and limited, the terms “first” and “second” are used for descriptive purposes only and should not be construed as indicating or implying relative importance; the term “multiple” refers to two or more; and the term “and / or” includes any and all combinations of one or more associated listed items. In particular, references to “the / described” object or “a” object are also intended to indicate one of a possible plurality of such objects.

[0128] Unless otherwise specified or stated, the terms "connection," "fixed," etc., should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, an integral connection, an electrical connection, or a signal connection; "connection" can be a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in this disclosure according to the specific circumstances.

[0129] Furthermore, it should be understood that the directional terms such as "upper," "lower," "inner," and "outer" described in the exemplary embodiments of this disclosure are used to describe the angles shown in the accompanying drawings and should not be construed as limiting the exemplary embodiments of this disclosure. It should also be understood that, in the context of an element or feature being connected to one or more "upper," "lower," "inner," or "outer" elements, it can be directly connected to one or more "upper," "lower," "inner," or "outer" elements, or indirectly connected to one or more "upper," "lower," "inner," or "outer" elements through intermediate elements.

[0130] In related technologies, the display panel includes row-oriented initial signal lines and column-oriented initial signal lines. The row-oriented initial signal lines and their corresponding column-oriented initial signal lines are connected by vias to form a grid structure. The grid structure of the initial signal lines can reduce the voltage difference of the initial signals at different positions on the display panel, thereby improving the display uniformity of the display panel. However, the column-oriented initial signal lines may generate column stripes. When the distance between the column stripes is similar to the width of the fingerprint, the column stripes can interfere with the fingerprint sensor's fingerprint detection.

[0131] For example, as shown in Figure 1, this is a schematic diagram of a display panel in the related art. The display panel includes multiple pixel driving circuit groups Pz, which are arrayed along the row direction X and column direction Y. Each pixel driving circuit group Pz includes two pixel driving circuits Pix distributed along the row direction X. The display panel also includes multiple row-direction initial signal lines and multiple column-direction initial signal lines. The column-direction initial signal lines are correspondingly configured with each column of pixel driving circuit group Pz, and the row-direction initial signal lines are correspondingly configured with each row of pixel driving circuit groups. The multiple row-direction initial signal lines include: a first row-direction initial signal line Vinit1H, a second row-direction initial signal line Vinit2H, and a third row-direction initial signal line Vinit2H. The multiple column-direction initial signal lines include: a first column-direction initial signal line Vinit1V, a second column-direction initial signal line Vinit2V, and a third column-direction initial signal line Vinit3V. The first column-oriented initial signal line Vinit1V, the second column-oriented initial signal line Vinit2V, the third column-oriented initial signal line Vinit3V, and the second column-oriented initial signal line Vinit2V are distributed alternately and cyclically in the row direction X. That is, after the first column-oriented initial signal line Vinit1V, the second column-oriented initial signal line Vinit2V, the third column-oriented initial signal line Vinit3V, and the second column-oriented initial signal line Vinit2V are distributed in the row direction X, the first column-oriented initial signal line Vinit1V, the second column-oriented initial signal line Vinit2V, the third column-oriented initial signal line Vinit3V, and the second column-oriented initial signal line Vinit2V are distributed in the row direction X again. Among them, the first column-oriented initial signal line Vinit1V is connected to the first row-oriented initial signal line Vinit1H that intersects with it through a via; the second column-oriented initial signal line Vinit2V is connected to the second row-oriented initial signal line Vinit2H that intersects with it through a via; and the third column-oriented initial signal line Vinit3V is connected to the third row-oriented initial signal line Vinit3H that intersects with it through a via. As shown in Figure 1, the area where the pixel driving circuit group Pz is located includes a via connection area HQ. The first column initial signal line Vinit1V is connected to the first row initial signal line Vinit1H, which intersects it, through a first via connection part VB located within the via connection area HQ. Since the first via connection part VB blocks part of the light-transmitting area of ​​the display panel, the light transmittance of the via connection area HQ corresponding to the first column initial signal line Vinit1V is less than the light transmittance of the via connection area HQ corresponding to the second column initial signal line Vinit2V / the third column initial signal line Vinit3V. Consequently, the fingerprint sensor detects the column pattern at the distribution position of the first column initial signal line Vinit1V.

[0132] Based on this, this exemplary embodiment provides a display panel, as shown in FIG2, which is a structural schematic diagram of an exemplary embodiment of the display panel disclosed herein. The display panel includes a substrate, multiple pixel driving circuit groups Pz, multiple row initial signal lines VinitH, and multiple column initial signal lines VinitV. The multiple pixel driving circuit groups Pz are arrayed along the row direction X and the column direction Y. Each pixel driving circuit group Pz includes two adjacent pixel driving circuits Pix in the row direction X. The orthographic projection of the row initial signal lines VinitH on the substrate extends along the row direction X and is spaced apart along the column direction Y. The orthographic projection of the multiple column initial signal lines VinitV on the substrate extends along the column direction Y. Furthermore, they are spaced at intervals along the row direction X; among them, the column-directed initial signal line VinitV and the pixel driving circuit group are correspondingly arranged. The column-directed initial signal line VinitV is used to provide an initial signal to its corresponding pixel driving circuit group. The area where each pixel driving circuit group Pz is located includes the x-region HQx located at the same position; among the multiple column-directed initial signal lines, there are the x-th column-directed initial signal line VinitVx and the y-th column-directed initial signal line VinitVy. The x-th column-directed initial signal line VinitVx includes the x1-th via connection portion VBx1, and the x-th column-directed... The initial signal line VinitVx is connected to the row-direction initial signal line VinitH, which intersects with it, via the x1st via connection portion VBx1. The yth column-direction initial signal line VinitVy is connected to the row-direction initial signal line VinitH, which intersects with it, via a via. In the region where the xth column-direction initial signal line VinitVx and its corresponding pixel driving circuit group are located, the x1st via connection portion VBx1 is located within region x HQx. In the region where the pixel driving circuit group Pz corresponding to the xth column-direction initial signal line VinitVx is located... In the x-region HQx, the area of ​​the orthogonal projection of all light-shielding structures on the substrate is S1; in the region where the pixel driving circuit group Pz corresponding to the y-th column initial signal line VinitVy is located, the area of ​​the orthogonal projection of all light-shielding structures in the x-region HQx on the substrate is S2, and S1 and S2 are the same or approximately the same; the distance between the orthogonal projection of the x-th column initial signal line VinitVx on the substrate and the orthogonal projection of its nearest y-th column initial signal line VinitVy on the substrate is less than 270 μm or greater than 700 μm.

[0133] The sensitive area of ​​the fingerprint width is between 270μm and 700μm. In this exemplary embodiment, the minimum distance between the initial signal lines of the column that can form column dark patterns is set to less than 270μm or greater than 700μm. This setting can prevent column dark patterns from interfering with the fingerprint sensor's detection of fingerprints.

[0134] It should be noted that due to process errors, S1 and S2 may not be exactly equal; that is, S1 and S2 are approximately equal. The x-region HQx within the region where each pixel driving circuit group Pz is located can be defined as a region of equal area located within the same area of ​​each pixel driving circuit group Pz. The distance between the orthographic projection of the x-th column initial signal line VinitVx on the substrate and the orthographic projection of its nearest y-th column initial signal line VinitVy on the substrate can be equal to 30μm, 40μm, 50μm, 60μm, 70μm, 80μm, 90μm, 100μm, 120μm, 140μm, 160μm, 180μm, 200μm, 220μm, 240μm, 260μm, 710μm, 720μm, 730μm, 740μm, 750μm, 760μm, 770μm, 780μm, 790μm, 800μm, etc. In this exemplary embodiment, the light-shielding structure is a layer with light-shielding function. For example, the light-shielding structure can be formed by structural layers such as the active layer, first gate layer, second gate layer, first source / drain layer, second source / drain layer, electrode layer, and touch electrode layer in the display panel. In this exemplary embodiment, the distance between the orthographic projection of any x-th column initial signal line VinitVx on the substrate and the orthographic projection of its nearest y-th column initial signal line VinitVy on the substrate is less than 270 μm or greater than 700 μm.

[0135] The x-th column-directed initial signal line VinitVx and the y-th column-directed initial signal line VinitVy can be set adjacently or at intervals.

[0136] In this exemplary embodiment, as shown in FIG2, the orthographic projections of the two pixel driving circuits Pix in the same pixel driving circuit group Pz on the substrate are at least partially mirror-symmetrical. Specifically, the orthographic projections of the channel regions of the same type of transistor in the two mirror-symmetrical pixel driving circuits on the substrate are mirror-symmetrical. For example, the pixel driving circuit may include a first transistor, and the orthographic projections of the channel regions of the first transistor in the two mirror-symmetrical pixel driving circuits are mirror-symmetrical.

[0137] It should be understood that in other exemplary embodiments, the pixel driving circuit group Pz may also include other numbers of pixel driving circuits Pix. For example, the pixel driving circuit group Pz may include one pixel driving circuit, or the pixel driving circuit group Pz may include multiple pixel driving circuits that are adjacent in the row direction X.

[0138] In this exemplary embodiment, as shown in FIG2, the multiple row-direction initial signal lines include the x-th row-direction initial signal line VinitHx and the y-th row-direction initial signal line VinitHy. The x-th column-direction initial signal line VinitVx is connected to the x-th row-direction initial signal line VinitHx, which intersects with it, via a via, and the y-th column-direction initial signal line VinitVy is connected to the y-th row-direction initial signal line VinitHy, which intersects with it, via a via.

[0139] In this exemplary embodiment, the x-th column-oriented initial signal line VinitVx can form the first column-oriented initial signal line Vinit1V in the related art, and the y-th column-oriented initial signal line VinitVy can form the second column-oriented initial signal line Vinit2V or the third column-oriented initial signal line Vinit3V in the related art. The x-th row-oriented initial signal line VinitHx can form the first row-oriented initial signal line Vinit1H in the related art, and the y-th row-oriented initial signal line VinitHy can form the second row-oriented initial signal line Vinit2H or the third row-oriented initial signal line Vinit3H in the related art. That is, this exemplary embodiment adjusts the transmittance of the x-region HQx corresponding to the first column-oriented initial signal line Vinit1V and the x-region HQx corresponding to the second column-oriented initial signal line Vinit2V / third column-oriented initial signal line Vinit3V to be the same or approximately the same, thereby reducing the distance between the columns and improving the problem of column interference with fingerprint sensor detection.

[0140] As shown in Figure 2, the area where the pixel driving circuit group Pz is located also includes a second via connection area HQ2 and a third via connection area HQ3. The second column-oriented initial signal line Vinit2V is connected to the second row-oriented initial signal line Vinit2H through a via connection portion located in the second via connection area HQ2, and the third column-oriented initial signal line Vinit3V is connected to the third row-oriented initial signal line Vinit3H through a via connection portion located in the third via connection area HQ3. In other exemplary embodiments, when the display panel has different transmittance in different second via connection areas HQ2, the display panel can also improve the problem of column pattern interference fingerprint sensor detection through the above solution. Accordingly, the x-th column-oriented initial signal line VinitVx can form the second column-oriented initial signal line Vinit2V, and the y-th column-oriented initial signal line VinitVy can form the first column-oriented initial signal line Vinit1V or the third column-oriented initial signal line Vinit3V. The x-th row-oriented initial signal line VinitHx can form the second row-oriented initial signal line Vinit2H, and the y-th row-oriented initial signal line VinitHy can form the first row-oriented initial signal line Vinit1H or the third row-oriented initial signal line Vinit3H. When the display panel has differences in light transmittance in different third via connection areas HQ3, the display panel can also improve the problem of column pattern interference fingerprint sensor detection through the above scheme. Accordingly, the x-th column-oriented initial signal line VinitVx forms the third column-oriented initial signal line Vinit3V, and the y-th column-oriented initial signal line VinitVy forms the first column-oriented initial signal line Vinit1V or the second column-oriented initial signal line Vinit2V. The x-th row-oriented initial signal line VinitHx forms the third row-oriented initial signal line Vinit3H, and the y-th row-oriented initial signal line VinitHy forms the first row-oriented initial signal line Vinit1H or the second row-oriented initial signal line Vinit2H.

[0141] As shown in Figures 3-5, Figure 3 is a partial structural layout diagram of an exemplary embodiment of the display panel of this disclosure, Figure 4 is a structural layout diagram of the row initial signal lines and bridging portions in the display panel shown in Figure 3, and Figure 5 is a structural layout diagram of the column initial signal lines in the display panel shown in Figure 3. The multiple row initial signal lines include an x-th row initial signal line VinitHx and a y-th row initial signal line VinitHy. The x-th column initial signal line VinitVx is connected via a via to the intersecting x-th row initial signal line VinitHx, and the y-th column initial signal line VinitVy is connected via a via to the intersecting y-th row initial signal line VinitHy. The y-th column-direction initial signal line VinitVy includes a y-th via connection portion Vby1. The y-th column-direction initial signal line VinitVy is connected to the y-th row-direction initial signal line VinitHy, which intersects with it at least partially, through the y-th via connection portion Vby1. At least a portion of the orthographic projection of the x1-th via connection portion VBx1 on the substrate and the orthographic projection of the y-th via connection portion on the substrate are offset in the column direction Y.

[0142] In this exemplary embodiment, as shown in Figures 3-5, the x-th column-direction initial signal line VinitVx further includes an x-th main body extension Vzx connected to the x-th via connection portion VBx1. The orthographic projection of the x-th via connection portion VBx1 on the substrate in the row direction X is larger than the orthographic projection of the x-th main body extension portion Vzx on the substrate in the row direction. The x-th via connection portion VBx1 includes an x-th column-direction extension portion VBxv and a protrusion portion VBxt. The orthographic projection of the protrusion portion VBxt on the substrate in the row direction X is protruding and disposed on one or both sides of the orthographic projection of the x-th column-direction extension portion VBxv on the substrate. The protrusion portion VBxt is located on the substrate... The orthographic projection on the board and the orthographic projections of all other light-shielding structures on the substrate do not overlap at least partially; the y-th column initial signal line VinitVy includes a y-th column extension VByv, the orthographic projection of the y-th column extension VByv on the substrate and the orthographic projection of the x1 via connection VBx1 on the substrate are disposed opposite each other in the row direction X; the display panel also includes: a light-shielding part ZB, the orthographic projection of the light-shielding part ZB on the substrate is protruding in the row direction X and disposed on one or both sides of the orthographic projection of the y-th column extension VByv on the substrate, and the orthographic projection of the light-shielding part ZB on the substrate and the orthographic projections of all other light-shielding structures on the substrate do not overlap at least partially.

[0143] This exemplary embodiment adds a light-shielding portion ZB to ensure that the x-region HQx corresponding to the y-th column-directed initial signal line VinitVy and the x-region HQx corresponding to the x-th column-directed initial signal line VinitVx have the same or approximately the same light transmittance. Specifically, the x-th column-directed initial signal line VinitVx can form a first column-directed initial signal line Vinit1V, and the y-th column-directed initial signal line VinitVy can form a second column-directed initial signal line Vinit2V or a third column-directed initial signal line Vinit3V.

[0144] It should be noted that structures A and D are set relative to each other in the row direction X. This can be understood as the area that structure A moves infinitely along the row direction X and the area that structure D moves infinitely along the row direction X overlap.

[0145] In this exemplary embodiment, as shown in Figures 3-5, the orthogonal projection of the x-th column extension Vbxv onto the substrate in the row direction X can be equal to the orthogonal projection of the x-th main extension Vzx onto the substrate in the row direction. The orthogonal projection of the x-th column extension Vbxv onto the substrate in the row direction X can also be equal to the orthogonal projection of the y-th column extension VByv onto the substrate in the row direction X.

[0146] In this exemplary embodiment, as shown in FIG3-5, the light-shielding portion may include: a first light-shielding portion ZB1, the first light-shielding portion ZB1 and the initial signal line VinitVy in the y-th column direction are connected in the same layer, the orth projection of the first light-shielding portion ZB1 on the substrate is protruding in the row direction X and is disposed on one or both sides of the orth projection of the y-th column extension VByv on the substrate, and the orth projection of the first light-shielding portion ZB1 on the substrate and the orth projections of all other light-shielding structures other than the light-shielding portion on the substrate do not overlap at least partially.

[0147] In this exemplary embodiment, as shown in Figures 3-5, the display panel further includes a first source / drain layer located on one side of the substrate. The first source / drain layer includes: an xth bridging portion Qx, an x2th via connection portion VBx2, and a yth virtual via connection portion VBy2. The xth bridging portion Qx is connected to the pixel driving circuit and the xth row initial signal line VinitHx, respectively. The x2th via connection portion VBx2 is connected to the xth bridging portion Qx, and the x1th via connection portion VBx1 is connected to the x2th via connection portion VBx2. The yth virtual via connection portion VBy2 is located on... The orthographic projection on the substrate and the orthographic projection of the y-th column extension VByv on the substrate at least partially overlap; the light-shielding portion may further include: a second light-shielding portion ZB2, the orthographic projection of the second light-shielding portion ZB2 on the substrate being raised in the row direction above the orthographic projection of the y-th column extension VByv on the substrate, and the orthographic projection of the second light-shielding portion ZB2 on the substrate and the orthographic projections of all other light-shielding structures other than the light-shielding portion on the substrate at least partially do not overlap; wherein, a portion of the structure of the y-th virtual via connection portion VBy2 forms the second light-shielding portion ZB2.

[0148] In this exemplary embodiment, as shown in Figures 3-5, the display panel further includes a y-th bridging portion Qy, which connects to the y-th column-directed initial signal line VinitVy and the y-th row-directed initial signal line VinitHy, respectively. In the same pixel driving circuit group, the y-th virtual via connection portion VBy2 can be connected to the y-th bridging portion Qy on the same layer.

[0149] It should be understood that, in other exemplary embodiments, the yth virtual via connection portion VBy2 and the yth via connection portion Vby1 are insulated from each other, and the yth virtual via connection portion VBy2 can be connected to the xth bridging portion Qx on the same layer.

[0150] It should be understood that in other exemplary embodiments, the light-shielding portion may also be located in one or more other light-shielding structural layers. For example, the light-shielding portion may be located in one or more of the following: a shielding layer, an active layer, a first gate layer, a second gate layer, a first source / drain layer, a second source / drain layer, an electrode layer, and a touch electrode layer. Figure 6 shows a partial structural layout of a display panel in an exemplary embodiment of the present disclosure. The display panel further includes: a shielding layer and an active layer. A portion of the active layer is used to form the channel region of the driving transistor in the pixel driving circuit. The shielding layer is located between the substrate and the active layer, and a portion of the shielding layer can form a light-shielding portion. Furthermore, in other exemplary embodiments, the display panel may also include: a touch layer. The touch layer is located on one side of the substrate. A portion of the touch layer is used to form a touch electrode, and a portion of the touch layer can form a light-shielding portion.

[0151] As shown in Figures 7 and 8, Figure 7 is a partial structural layout diagram of an exemplary embodiment of the display panel of this disclosure, and Figure 8 is a structural layout diagram of the second gate layer in the display panel shown in Figure 7. The pixel driving circuit includes a driving transistor and a capacitor. The driving transistor is used to provide driving current to the light-emitting unit according to its gate voltage. The first electrode of the capacitor is connected to the gate of the driving transistor, and the second electrode of the capacitor is connected to the power supply line. The display panel also includes a second gate layer located on one side of the substrate. The second gate layer includes a second conductive portion 22 and a first connecting portion 23. The second conductive portion 22 is used to form the second electrode of the capacitor. The first connecting portion 23 is connected between two adjacent second conductive portions 22 in the same pixel driving circuit group. The second gate layer also includes an epitaxial portion 24. The epitaxial portion 24 is connected to the first connecting portion 23, and the orthographic projection of the epitaxial portion 24 on the substrate is located on the side where the orthographic projection of the first connecting portion 23 on the substrate is in the column direction Y. At least a portion of the structure of the epitaxial portion 24 can be used to form a light-shielding portion.

[0152] As shown in Figures 9 and 10, Figure 9 is a partial structural layout diagram of another exemplary embodiment of the display panel of this disclosure, and Figure 10 is a structural layout diagram of the row initial signal line and bridging portion in the display panel shown in Figure 9. The xth column initial signal line VinitVx also includes an xth main body extension Vzx connected to the x1th via connection portion VBx1. The size of the orthogonal projection of the x1th via connection portion VBx1 on the substrate in the row direction X can be equal to the size of the orthogonal projection of the xth main body extension Vzx on the substrate in the row direction. That is, this exemplary embodiment reduces the width of the x1th via connection portion VBx1 so that the transmittance of the x-region HQx corresponding to the xth column initial signal line VinitVx is the same or approximately the same as the transmittance of the x-region HQx corresponding to the yth column initial signal line VinitVy.

[0153] In this exemplary embodiment, as shown in FIG9 and 10, the display panel further includes: a second via connection portion VBx2, wherein the first via connection portion VBx1 is connected to the second via connection portion VBx2 through a via; the orthogonal projection of the second via connection portion VBx2 on the substrate is located within the orthogonal projection of the first via connection portion VBx1 on the substrate.

[0154] In this exemplary embodiment, as shown in Figures 9 and 10, the y-th via connection portion VBy1 is connected to its corresponding y-th row-direction initial signal line VinitHy via the first via H1, and the x1-th via connection portion VBx1 is connected to its corresponding x-th row-direction initial signal line VinitHx via the second via H2. The area of ​​the orthographic projection of the opening of the first via H1 facing the y-th via connection portion VBy1 onto the substrate is greater than the area of ​​the orthographic projection of the opening of the second via H2 facing the x1-th via connection portion VBx1 onto the substrate. That is, in addition to reducing the width of the x1-th via connection portion VBx1, this exemplary embodiment also needs to correspondingly reduce the opening size of the second via H2.

[0155] In the embodiments shown in Figures 3-10, the first column-oriented initial signal line Vinit1V, the second column-oriented initial signal line Vinit2V, the third column-oriented initial signal line Vinit3V, and the second column-oriented initial signal line Vinit2V can be sequentially and cyclically distributed in the row direction X. That is, after the first column-oriented initial signal line Vinit1V, the second column-oriented initial signal line Vinit2V, the third column-oriented initial signal line Vinit3V, and the second column-oriented initial signal line Vinit2V are sequentially distributed in the row direction X, the first column-oriented initial signal line Vinit1V, the second column-oriented initial signal line Vinit2V, the third column-oriented initial signal line Vinit3V, and the second column-oriented initial signal line Vinit2V are sequentially distributed again. The column-oriented initial signal lines are correspondingly set with each column pixel driving circuit group Pz, and the row-oriented initial signal lines are correspondingly set with each row pixel driving circuit group.

[0156] It should be understood that, in other exemplary embodiments, the first column-oriented initial signal line Vinit1V, the second column-oriented initial signal line Vinit2V, and the third column-oriented initial signal line Vinit3V may be distributed in other ways. The column-oriented initial signal lines may also be configured corresponding to the multi-column pixel driving circuit group Pz, and the row-oriented initial signal lines may also be configured corresponding to the multi-row pixel driving circuit group.

[0157] Figure 11 shows a partial structural layout of another exemplary embodiment of the display panel of this disclosure. The x-th column-directed initial signal line VinitVx can form the first column-directed initial signal line Vinit1V corresponding to a pixel driving circuit group, and the y-th column-directed initial signal line VinitVy forms the first column-directed initial signal line Vinit1V corresponding to another pixel driving circuit group; the orthographic projections of the first column-directed initial signal line Vinit1V, the second column-directed initial signal line Vinit2V, and the third column-directed initial signal line Vinit3V on the substrate are alternately distributed in the row direction. This exemplary embodiment reduces the distance between two adjacent first column-directed initial signal lines Vinit1V so that the distance between the column patterns is less than 200μm, so that even if the via connection area HQ corresponding to the first column-directed initial signal line Vinit1V and the via connection area HQ corresponding to the second / third column-directed initial signal lines Vinit2V and Vinit3V have different light transmittance, the column patterns formed by the first column-directed initial signal line Vinit1V will not interfere with the fingerprint sensor's fingerprint detection.

[0158] It should be noted that the light transmittance of a local area of ​​the display panel is equal to the ratio of the area without light-blocking structure to the total area of ​​that area.

[0159] Figure 12 shows a schematic diagram of the pixel driving circuit in an exemplary embodiment of the display panel of this disclosure. The pixel driving circuit may include: a driving transistor T3, a first transistor T1, a second transistor T2, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a capacitor C. In this configuration, the first electrode of the fourth transistor T4 is connected to the data signal terminal Da, the second electrode is connected to the first electrode of the driving transistor T3, and the gate is connected to the first gate drive signal terminal G1; the first electrode of the fifth transistor T5 is connected to the first power supply terminal VDD, the second electrode is connected to the first electrode of the driving transistor T3, and the gate is connected to the enable signal terminal EM; the gate of the driving transistor T3 is connected to node N; the first electrode of the second transistor T2 is connected to node N, the second electrode is connected to the second electrode of the driving transistor T3, and the gate is connected to the first gate drive signal terminal G1; the first electrode of the sixth transistor T6 is connected to the second electrode of the driving transistor T3, the second electrode is connected to the second electrode of the seventh transistor T7, and the gate is connected to the enable signal terminal EM; the first electrode of the seventh transistor T7 is connected to the second initial signal terminal Vinit2, and the gate is connected to the second reset signal terminal Re2; the second electrode of the first transistor T1 is connected to node N, the first electrode is connected to the first initial signal terminal Vinit1, and the gate is connected to the first reset signal terminal Re1; the first electrode of the capacitor C is connected to node N, and the second electrode is connected to the first power supply terminal VDD; the first electrode of the eighth transistor T8 is connected to the third initial signal terminal Vinit3, the second electrode is connected to the first electrode of the driving transistor, and the gate is connected to the second reset signal terminal Re2. The pixel driving circuit can be connected to an OLED light-emitting unit. The pixel driving circuit is used to drive the OLED to emit light. The OLED can be connected between the second terminal and the second power supply terminal VSS of the sixth transistor T6. Among them, the first transistor T1, the second transistor T2, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 can be P-type transistors.

[0160] The pixel driving circuit driving method can include a reset stage, a data writing stage, and a light-emitting stage. In the reset stage, the first reset signal terminal Re1 outputs a low-level signal, the second reset signal terminal Re2 outputs a low-level signal, the first transistor T1, the seventh transistor T7, and the eighth transistor T8 are turned on, the first initial signal terminal Vinit1 inputs a first initial signal to node N, the second initial signal terminal Vinit2 inputs a second initial signal to the first electrode of the light-emitting unit, and the third initial signal terminal Vinit3 inputs a third initial signal to the first electrode of the driving transistor T3. In the data writing stage, the first gate driving signal terminal G1 outputs a low-level signal, the second transistor T2 and the fourth transistor T4 are turned on, and simultaneously the data signal terminal Da outputs a data signal to write a compensation voltage Vdata+Vth to node N, where Vdata is the voltage of the data signal and Vth is the threshold voltage of the driving transistor T3. In the light-emitting stage: the enable signal terminal EM outputs a low-level signal, the sixth transistor T6 and the fifth transistor T5 are turned on, and the driving transistor T3 drives the light-emitting unit to emit light under the action of the compensation voltage Vdata+Vth stored in capacitor C. In this pixel driving circuit, the output current of the driving transistor is I = (μWCox / 2L)(Vdata + Vth - Vdd - Vth). 2 This pixel driving circuit can avoid the influence of the driving transistor threshold on its output current. Where I is the driving transistor output current; μ is the carrier mobility; Cox is the gate capacitance per unit area; W is the width of the driving transistor channel; L is the length of the driving transistor channel; Vgs is the gate-source voltage difference of the driving transistor; and Vth is the driving transistor threshold voltage.

[0161] This exemplary embodiment also provides a display panel, which may include a substrate, a shielding layer, an active layer, a first gate layer, a second gate layer, a first source / drain layer, a second source / drain layer, and an electrode layer stacked sequentially. An insulating layer may be disposed between adjacent layers. As shown in Figures 13-25, Figure 13 is a structural layout diagram of an exemplary embodiment of the display panel of this disclosure; Figure 14 is a structural layout diagram of the shielding layer in the display panel shown in Figure 13; Figure 15 is a structural layout diagram of the active layer in the display panel shown in Figure 13; Figure 16 is a structural layout diagram of the first gate layer in the display panel shown in Figure 13; Figure 17 is a structural layout diagram of the second gate layer in the display panel shown in Figure 13; Figure 18 is a structural layout diagram of the first source / drain layer in the display panel shown in Figure 13; Figure 19 is a structural layout diagram of the second source / drain layer in the display panel shown in Figure 13; and Figure 20 is a structural layout diagram of the electrode layer in the display panel shown in Figure 13. The structural layouts are as follows: Figure 21 is a structural layout of the shielding layer and active layer in the display panel shown in Figure 13; Figure 22 is a structural layout of the shielding layer, active layer, and first gate layer in the display panel shown in Figure 13; Figure 23 is a structural layout of the shielding layer, active layer, first gate layer, and second gate layer in the display panel shown in Figure 13; Figure 24 is a structural layout of the shielding layer, active layer, first gate layer, second gate layer, and first source / drain layer in the display panel shown in Figure 13; and Figure 25 is a structural layout of the shielding layer, active layer, first gate layer, second gate layer, first source / drain layer, and second source / drain layer in the display panel shown in Figure 13. Figure 13 shows a more detailed structural layout of the display panel shown in Figure 3. The display panel shown in Figure 13 includes multiple pixel driving circuit groups Pz distributed along the row and column directions. Each pixel driving circuit group Pz includes two pixel driving circuits Pix distributed in the row direction. The two pixel driving circuits Pix in the same pixel driving circuit group Pz are at least partially mirror-symmetrically arranged on the substrate. The structure of the pixel driving circuit Pix can be as shown in Figure 12.

[0162] As shown in Figures 13, 14, and 21, the shading layer includes multiple shading parts 81 distributed in an array along the row direction X and the column direction Y, and the shading parts 81 are interconnected.

[0163] As shown in Figures 13, 15, and 22, the active layer may include: a first active section 71, a second active section 72, a third active section 73, a fourth active section 74, a fifth active section 75, a sixth active section 76, a seventh active section 77, an eighth active section 78, a ninth active section 79, a tenth active section 710, an eleventh active section 711, a twelfth active section 712, a thirteenth active section 713, a fourteenth active section 714, a fifteenth active section 715, a sixteenth active section 716, a seventeenth active section 717, an eighteenth active section 718, and a nineteenth active section 719. The first active portion 71 is used to form the channel region of the first transistor T1, wherein the first active portion 71 includes a first sub-active portion 731 and a second sub-active portion 732; the second active portion 72 is used to form the channel region of the second transistor T2, wherein the second active portion 72 includes a third sub-active portion 723 and a fourth sub-active portion 724; the third active portion 73 can be used to form the channel region of the driving transistor T3; the fourth active portion 74 can be used to form the channel region of the fourth transistor T4; the fifth active portion 75 can be used to form the channel region of the fifth transistor T5; the sixth active portion 76 can be used to form the channel region of the sixth transistor T6; the seventh active portion 77 can be used to form the channel region of the seventh transistor T7; the eighth active portion 78 can be used to form the channel region of the eighth transistor T8; and the ninth active portion 79 is connected between the first active portion 71 and the second active portion 72. The tenth active part 710 and the eleventh active part 711 are connected to the two ends of the eighth active part 78; the twelfth active part 712 is connected to the end of the seventh active part 77 away from the sixth active part 76; the thirteenth active part 713 is connected between the seventh active part 77 and the sixth active part 76; the fourteenth active part 714 is connected to the end of the fifth active part 75 away from the third active part 73; the fifteenth active part 715 is connected between the fifth active part 75 and the third active part 73; the sixteenth active part 716 is connected to the end of the fourth active part 74 away from the third active part 73; the seventeenth active part 717 is connected between the third sub-active part 723 and the fourth sub-active part 724; the eighteenth active part 718 is connected between the first sub-active part 731 and the second sub-active part 732; and the nineteenth active part 719 is connected to the end of the first active part 71 away from the second active part 72. The active layer can be formed of polycrystalline silicon material. Correspondingly, the first transistor T1, the second transistor T2, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 can be P-type low-temperature polycrystalline silicon thin-film transistors.In this exemplary embodiment, both the first transistor and the second transistor have two channel regions spaced apart. Correspondingly, both the first transistor T1 and the second transistor T2 have two gates, i.e., the first transistor T1 and the second transistor T2 are dual-gate structures. The transistor with the dual-gate structure has a smaller turn-off leakage current. This arrangement can reduce the leakage current through the gate of the driving transistor through the first transistor T1 and the second transistor T2, thereby improving the voltage stability of the gate of the driving transistor.

[0164] As shown in Figures 13 and 21, the orthographic projection of the shielding portion 81 on the substrate can at least partially overlap with the orthographic projection of the third active portion 73 on the substrate. The shielding portion 81 can block light from the third active portion 73 to improve the stability of the output characteristics of the driving transistor. The shielding layer can be a conductive structure, and the shielding layer can be connected to a stable voltage source. The shielding layer can shield the pixel driving circuit from signals, and the shielding layer can be connected to stable voltage sources such as the first initial signal terminal, the second initial signal terminal, the third initial signal terminal, the first power supply terminal, and the second power supply terminal in Figure 12.

[0165] As shown in Figures 13, 16, and 22, the first gate layer may include: a first conductive portion 11, a first gate line G1, an enable signal line EM, a first reset signal line Re1, and a second reset signal line Re2. The first gate line G1 can be used to provide the first gate drive signal terminal in Figure 12; the enable signal line EM can be used to provide the enable signal terminal in Figure 12; the first reset signal line Re1 can be used to provide the first reset signal terminal in Figure 12; and the second reset signal line Re2 can be used to provide the second reset signal terminal in Figure 12. The orthographic projections of the first gate line G1, the enable signal line EM, the first reset signal line Re1, and the second reset signal line Re2 on the substrate can all extend along the row direction X. The orthographic projection of the first gate line G1 on the substrate covers the orthographic projections of the fourth active portion 74 and the second active portion 72 on the substrate. A portion of the structure of the first gate line G1 is used to form the gate of the fourth transistor T4, and a portion of the structure of the first gate line G1 is used to form the gate of the second transistor T2. The orthographic projection of the enable signal line EM onto the substrate covers the orthographic projections of the fifth active portion 75 and the sixth active portion 76 onto the substrate. A portion of the structure of the enable signal line EM can be used to form the gates of the fifth transistor T5 and the sixth transistor T6, respectively. The orthographic projection of the first reset signal line Re1 onto the substrate covers the orthographic projection of the first active portion 71 onto the substrate. A portion of the structure of the first reset signal line Re1 is used to form the gate of the first transistor T1. The orthographic projection of the second reset signal line Re2 onto the substrate covers the orthographic projections of the seventh active portion 77 and the eighth active portion 78 onto the substrate. A portion of the structure of the first reset signal line Re1 can be used to form the gates of the seventh transistor T7 and the eighth transistor T8, respectively. The orthographic projection of the first conductive portion 11 onto the substrate covers the orthographic projection of the third active portion 73 onto the substrate. The first conductive portion 11 can be used to form the gate of the driving transistor T3 and the first electrode of the capacitor C. The display panel can use the first gate layer as a mask to conduct the active layer, that is, the area of ​​the active layer covered by the first gate layer can form the channel region of the transistor, and the area of ​​the active layer not covered by the first gate layer forms a conductor structure.

[0166] As shown in Figures 13, 17, and 23, the second gate layer may include: a second conductive portion 22, a first connecting portion 23, a fifth conductive portion 25, a sixth conductive portion 26, a first row-direction initial signal line Vinit1H, and a third row-direction initial signal line Vinit3H. The orthographic projections of the first row-direction initial signal line Vinit1H and the third row-direction initial signal line Vinit3H on the substrate can extend along the row direction X. The first row-direction initial signal line Vinit1H provides the first initial signal terminal in Figure 12, and the third row-direction initial signal line Vinit3H provides the third initial signal terminal in Figure 12. The orthographic projection of the second conductive portion 22 on the substrate can at least partially overlap with the orthographic projection of the first conductive portion 11 on the substrate. The second conductive portion 22 forms the second electrode of the capacitor C. The first connecting portion 23 connects between two adjacent second conductive portions 22 in the same pixel driving circuit group Pz. The fifth conductive part 25 is connected to one side of the first row-oriented initial signal line Vinit1H in the column direction Y, and the sixth conductive part 26 is connected to one side of the first row-oriented initial signal line Vinit1H in the column direction Y. The orthographic projection of the fifth conductive part 25 on the substrate and the orthographic projection of the seventeenth active part 717 on the substrate at least partially overlap. The fifth conductive part 25 can regulate the voltage of the seventeenth active part 717 to improve the problem of leakage current to the source / drain of the second transistor T2 caused by voltage fluctuations of the seventeenth active part 717. The orthographic projection of the sixth conductive part 26 on the substrate is located between the orthographic projections of the ninth active part 79 and the sixteenth active part 716 on the substrate. The sixth conductive part 26 can shield the interference of fluctuation signals from the data signal terminal to the gate of the driving transistor T3.

[0167] As shown in Figures 13, 18, and 24, the first source / drain layer may include a first bridging portion 41, a second bridging portion 42, a third bridging portion 43, a fourth bridging portion 44, a fifth bridging portion 45, a sixth bridging portion 46, a seventh bridging portion 47, an eighth bridging portion 48, a ninth bridging portion 49, a second row initial signal line Vinit2H, and a first fan-out line FIPH. The first bridging portion 41 connects to the third row initial signal line Vinit3H and the tenth active portion 710 via vias, connecting the first terminal of the eighth transistor T8 and the third initial signal terminal. The second bridging portion 42 connects to the first conductive portion 11 and the ninth active portion 79 via vias, connecting the gate of the driving transistor T3 and the second terminal of the first transistor T1 and the first terminal of the second transistor T2. A through-hole 221 is formed on the second conductive portion 22, and the through-hole connecting the first conductive portion 11 and the second bridging portion 42 can be disposed through the through-hole 221. The third bridging section 43 connects to the second conductive section 22 and the fourteenth active section 714 via vias to connect the second electrode of capacitor C and the first electrode of the fifth transistor. Two adjacent pixel driving circuit groups located in the row direction X can share the same third bridging section 43. The fourth bridging section 44 connects to the thirteenth active section 713 via vias to connect the second electrodes of the sixth and seventh transistors. The fifth bridging section 45 connects to the nineteenth active section 719 and the first row initial signal line Vinit1H via vias to connect the first electrode of the first transistor T1 and the first initial signal terminal. The fifth bridging section 45 can form the aforementioned xth bridging section Qx. The sixth bridging section 46 connects to the sixteenth active section 716 via vias to connect the first electrode of the fourth transistor T4. The eighth bridging section 48 connects to the fifteenth active section 715 and the eleventh active section 711 via vias to connect the second electrode of the eighth transistor T8 and the first electrode of the driving transistor T3. The ninth bridging portion 49 can be connected to the second row-direction initial signal line Vinit2H on the same layer, and the ninth bridging portion 49 can form the aforementioned y-th bridging portion Qy. The orthographic projection of the second row-direction initial signal line Vinit2H on the substrate can extend along the row direction X, and the second row-direction initial signal line Vinit2H can be used to provide the second initial signal terminal in FIG12. The orthographic projection of the first fan-out line FIPH on the substrate can extend along the row direction X, and the first fan-out line FIPH can be used as a row-direction fan-out line connecting data lines in the FIP (Fanout In Pixel).

[0168] As shown in Figures 13, 18, and 24, the orthographic projection of the sixth conductive part 26 on the substrate is located between the orthographic projection of the second bridging part 42 on the substrate and the orthographic projection of the sixth bridging part 46 on the substrate.

[0169] As shown in Figures 13, 18, and 24, the first source / drain layer further includes a first via connection portion 411, a second virtual via connection portion 412, and a third virtual via connection portion 413. The first via connection portion 411 and the fifth bridging portion 45 are connected on the same layer, and the first via connection portion 411 can form the aforementioned x2-th via connection portion. The second virtual via connection portion 412 and the ninth bridging portion 49 are connected on the same layer, and the second virtual via connection portion 412 can form the y-th virtual via connection portion corresponding to the second column-directed initial signal line Vinit2V. A portion of the structure of the second virtual via connection portion 412 is used to form the aforementioned light-shielding portion. The third virtual via connection portion 413 and the fifth bridging portion 45 are connected on the same layer, and the third virtual via connection portion 413 can form the y-th virtual via connection portion corresponding to the third column-directed initial signal line Vinit3V. A portion of the structure of the third virtual via connection portion 413 is used to form the aforementioned light-shielding portion.

[0170] As shown in Figures 13, 19, and 25, the second source / drain layer may include a data line Da, a power line VDD, a second fan-out line FIPV, a first column-directed initial signal line Vinit1V, a second column-directed initial signal line Vinit2V, a third column-directed initial signal line Vinit3V, and a tenth bridge section 510. The orthogonal projections of the data line Da, power line VDD, second fan-out line FIPV, first column-directed initial signal line Vinit1V, second column-directed initial signal line Vinit2V, and third column-directed initial signal line Vinit3V onto the substrate all extend along the column direction Y. The data line Da provides the data signal terminal shown in Figure 12. The data line Da can be connected to the sixth bridge section 46 via a via to connect the data signal terminal and the first terminal of the fourth transistor T4. The power line VDD provides the first power terminal shown in Figure 12. The power line VDD can be connected to the third bridge section 43 via a via to connect the first power terminal and the first terminal of the fifth transistor T5 and the second terminal of the capacitor C. The first column-oriented initial signal line Vinit1V can be connected via a via to the first via connection part 411 to connect to the intersecting first row-oriented initial signal line Vinit1H. The first column-oriented initial signal line Vinit1V and the first row-oriented initial signal line Vinit1H can form a grid structure. The second column-oriented initial signal line Vinit2V can be connected via a via to the ninth bridging part 49 to connect to the intersecting second row-oriented initial signal line Vinit2H. The second column-oriented initial signal line Vinit2V and the second row-oriented initial signal line Vinit2H can form a grid structure. The third column-oriented initial signal line Vinit3V can be connected via a via to the first bridging part 41 to connect to the intersecting third row-oriented initial signal line Vinit3H. The third column-oriented initial signal line Vinit3V and the third row-oriented initial signal line Vinit3H can form a grid structure. The grid structure of the initial signal lines can reduce the voltage difference on the initial signal lines at different positions on the display panel, thereby providing display uniformity of the display panel. Each column of pixel driving circuit groups can be provided with one corresponding column-oriented initial signal connection line. The first column-direction initial signal line Vinit1V, the second column-direction initial signal line Vinit2V, the third column-direction initial signal line Vinit3V, and the second column-direction initial signal line Vinit2V can be alternately and cyclically distributed in the row direction X. The second fan-out line FIPV can be used as a column-direction fan-out line connecting data lines in the FIP (Fanout In Pixel). The second fan-out line FIPV can include multiple fan-out line segments spaced apart in the column direction, and adjacent fan-out line segments can be bridged through the seventh bridging part 47. The tenth bridging part 510 can be connected to the fourth bridging part 44 through a via.

[0171] As shown in Figures 13, 19, and 25, the first column-oriented initial signal line Vinit1V includes a fourth via connection portion VB1, the second column-oriented initial signal line Vinit2V includes a fifth via connection portion VB2, and the third column-oriented initial signal line Vinit3V includes a sixth via connection portion VB3. The first column-oriented initial signal line Vinit1V is connected to the first row-oriented initial signal line Vinit1H through the fourth via connection portion VB1. The fourth via connection portion VB1 can form the aforementioned x1th via connection portion, the fifth via connection portion VB2 can form the yth via connection portion corresponding to the second column-oriented initial signal line Vinit2V, and the sixth via connection portion VB3 can form the yth via connection portion corresponding to the third column-oriented initial signal line Vinit3V.

[0172] It should be noted that, in other exemplary embodiments, the first row-directed initial signal line Vinit1H, the second row-directed initial signal line Vinit2H, and the third row-directed initial signal line Vinit3H may also be located in other conductive layers. For example, any one of the first row-directed initial signal line Vinit1H, the second row-directed initial signal line Vinit2H, and the third row-directed initial signal line Vinit3H may also be located in any one of the active layer, the second gate layer, the first source / drain layer, and the second source / drain layer.

[0173] As shown in Figures 13 and 20, the electrode layer may include multiple electrode sections: these multiple electrode sections include a first electrode section R, a second electrode section B, and a third electrode section G. Each electrode section can be connected to the tenth bridge section 510 via vias to connect to the second electrode of the sixth transistor. Among the multiple electrode sections connected to the same row of pixel driving circuits, the first electrode section R, the third electrode section G, the second electrode section B, and the third electrode section G are alternately distributed in the row direction. In two adjacent columns of pixel driving circuits, multiple first electrode sections R and multiple second electrode sections B are connected to the same column of pixel driving circuits, and the first electrode sections R and second electrode sections B connected to the same column of pixel driving circuits are alternately distributed in the column direction. Multiple third electrode sections G are connected to another column of pixel driving circuits. The third electrode section G can serve as the first electrode of a green light-emitting unit, the first electrode section R can serve as the first electrode of a red light-emitting unit, and the second electrode section B can serve as the first electrode of a blue light-emitting unit.

[0174] As shown in Figures 13-25, the orthographic projection of the fourth via connection portion VB1 on the substrate is at least partially located between the orthographic projection of the first connection portion 23 on the substrate and the orthographic projection of the first gate line G1 on the substrate.

[0175] Figure 26 shows a partial cross-sectional view of the display panel shown in Figure 13, cut along the dashed line AA. The display panel may further include a buffer layer 101, a first insulating layer 102, a second insulating layer 103, a dielectric layer 104, a passivation layer 105, a first planarization layer 106, and a second planarization layer 107. The substrate 100, shielding layer, buffer layer 101, active layer, first insulating layer 102, first gate layer, second insulating layer 103, second gate layer, dielectric layer 104, first source / drain layer, passivation layer 105, first planarization layer 106, second source / drain layer, second planarization layer 107, and electrode layer are sequentially stacked. The buffer layer 101, the first insulating layer 102, and the second insulating layer 103 can be single-layer or multi-layer structures, and the materials of the buffer layer 101, the first insulating layer 102, and the second insulating layer 103 can be at least one of silicon nitride, silicon oxide, and silicon oxynitride; the dielectric layer 104 can be a silicon nitride layer; the materials of the first planarization layer 106 and the second planarization layer 107 can be organic materials, such as polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), silicon-glass bonded structure (SOG), etc. The passivation layer 105 can be a silicon oxide layer. The substrate 100 can include a glass substrate, a barrier layer, and a polyimide layer stacked sequentially, and the barrier layer can be an inorganic material. The materials of the first gate layer and the second gate layer can be one of molybdenum, aluminum, copper, titanium, niobium, or an alloy thereof, or a molybdenum / titanium alloy or a stacked conductive layer. The materials of the first and second source / drain layers can include metallic materials, such as molybdenum, aluminum, copper, titanium, niobium, or alloys thereof, or molybdenum / titanium alloys or stacks, or conductive layers such as titanium / aluminum / titanium stacks. The sheet resistance of either the first or second source / drain layer can be less than the sheet resistance of either the first or second gate layer.

[0176] It should be noted that, as shown in Figure 3-25, the black squares drawn on the side of the first source / drain layer away from the substrate represent vias connecting the first source / drain layer to other layers facing the substrate; the black rectangles with chamfers drawn on the side of the second source / drain layer away from the substrate represent vias connecting the second source / drain layer to other layers facing the substrate; and the black circles drawn on the side of the electrode layer away from the substrate represent vias connecting the electrode layer to other layers facing the substrate. Vias at different positions can penetrate different insulating layers.

[0177] The scale of the accompanying drawings in this disclosure can be used as a reference in actual processes, but is not limited thereto. For example, the aspect ratio of the channels, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display panel and the number of sub-pixels in each pixel are not limited to the quantities shown in the figures. The drawings described in this disclosure are only schematic diagrams of the structure. In addition, the terms "first," "second," etc., are only used to define different structural names and do not have a specific order meaning. The same structural layer can be formed by the same patterning process. In this exemplary embodiment, the orthographic projection of a certain structure on the substrate extends along a certain direction, which can be understood as the orthographic projection of the structure on the substrate extending in a straight line or bending along that direction.

[0178] This exemplary embodiment also provides a display device, which includes the display panel described above. The display device can be a mobile phone, tablet computer, television, or other display device.

[0179] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the disclosure herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the claims.

[0180] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is defined only by the appended claims.

Claims

1. A display panel, wherein, The display panel includes: Substrate; Multiple pixel driving circuit groups are arranged in an array along the row and column directions, and each pixel driving circuit group includes one or more pixel driving circuits that are adjacent in the row direction. Multiple row-direction initial signal lines, wherein the orthographic projection of the row-direction initial signal lines on the substrate extends along the row direction and is spaced apart along the column direction; Multiple column-oriented initial signal lines, wherein the orthographic projection of the multiple column-oriented initial signal lines on the substrate extends along the column direction and is spaced apart along the row direction; The column-directed initial signal line and the pixel driving circuit group are respectively arranged. The column-directed initial signal line is used to provide an initial signal to the pixel driving circuit group corresponding to it. The area where each pixel driving circuit group is located includes the x area located at the same position. The plurality of column-directed initial signal lines include an xth column-directed initial signal line and a yth column-directed initial signal line. The xth column-directed initial signal line includes an x1th via connection portion. The xth column-directed initial signal line is connected to at least partially intersecting with the row-directed initial signal line through the x1th via connection portion. The yth column-directed initial signal line is connected to at least partially intersecting with the row-directed initial signal line through a via. In the region where the xth column initial signal line and the corresponding pixel driving circuit group are located, the x1th via connection is located within the x region; In the region where the pixel driving circuit group corresponding to the x-th column initial signal line is located, the area of ​​the orthogonal projection of all light-shielding structures in the x-region onto the substrate is S1; In the region where the pixel driving circuit group corresponding to the initial signal line in column y is located, the area of ​​the orthogonal projection of all light-shielding structures in region x onto the substrate is S2, and S1 and S2 are the same or approximately the same. The distance between the orthographic projection of the x-th column initial signal line on the substrate and the orthographic projection of the nearest y-th column initial signal line on the substrate is less than 270 μm or greater than 700 μm.

2. The display panel according to claim 1, wherein, The y-th column initial signal line includes a y-th via connection portion, and the y-th column initial signal line is connected to the row initial signal line that intersects with it at least partially through the y-th via connection portion. At least a portion of the orthographic projection of the x1th via connection on the substrate and the orthographic projection of the yth via connection on the substrate are misaligned in the column direction.

3. The display panel according to claim 2, wherein, The xth column initial signal line also includes an xth main body extension connected to the x1th via connection portion, wherein the orthographic projection of the x1th via connection portion on the substrate in the row direction is larger than the orthographic projection of the xth main body extension portion on the substrate in the row direction; The x1th via connection portion includes an xth column extension portion and a protrusion portion. The orthogonal projection of the protrusion portion on the substrate is provided in the row direction on one or both sides of the orthogonal projection of the xth column extension portion on the substrate. Wherein, the orthographic projection of the protrusion on the substrate and the orthographic projection of the other light-shielding structure on the substrate do not overlap at least partially; The yth column initial signal line includes a yth column extension, and the orth projection of the yth column extension on the substrate and the orth projection of the x1 via connection on the substrate are arranged opposite to each other in the row direction. The display panel also includes: The light-shielding portion is provided on one or both sides of the orthogonal projection of the y-th column extension portion on the substrate in the row direction.

4. The display panel according to claim 3, wherein, The light-shielding part includes: A first light-shielding portion is connected to the same layer as the y-th column initial signal line. The orthogonal projection of the first light-shielding portion on the substrate protrudes in the row direction and is disposed on one or both sides of the orthogonal projection of the y-th column extension portion on the substrate.

5. The display panel according to claim 3 or 4, wherein, The plurality of row-direction initial signal lines include an x-th row-direction initial signal line and a y-th row-direction initial signal line. The x-th column-direction initial signal line is connected to the x-th row-direction initial signal line that intersects with it, and the y-th column-direction initial signal line is connected to the y-th row-direction initial signal line that intersects with it. The display panel further includes a first source / drain layer, which is located on one side of the substrate. The first source / drain layer includes: The xth bridging section is connected to the pixel driving circuit and the xth row initial signal line respectively; The x2 via connection portion is connected to the xth bridging portion, and the x1 via connection portion is connected through... The x2th through-hole connection is connected via the through-hole; The orthographic projection of the yth virtual via connection portion on the substrate and the orthographic projection of the yth column extension portion on the substrate at least partially overlap; The light-shielding part includes: The second light-shielding part is provided on one or both sides of the orthogonal projection of the second light-shielding part on the substrate in the row direction. The structure of the yth virtual via connection portion forms the second light-shielding portion.

6. The display panel according to claim 5, wherein, The display panel also includes: The y-th bridging section is connected to the y-th column-directed initial signal line and the y-th row-directed initial signal line respectively; In the same group of pixel driving circuits: The yth virtual via connection and the xth bridging connection are connected on the same layer; Alternatively, the yth virtual via connection and the yth bridge connection are connected on the same layer.

7. The display panel according to claim 3, wherein, The pixel driving circuit includes a driving transistor, which is used to provide driving current to the light-emitting unit according to its gate voltage; The display panel also includes: An active layer is located on one side of the substrate, and a portion of the structure of the active layer is used to form the channel region of the driving transistor. A shielding layer is located between the substrate and the active layer, and a portion of the structure of the shielding layer forms the light-shielding portion.

8. The display panel according to claim 3, wherein, The display panel also includes: A touch layer is located on one side of the substrate. A portion of the structure of the touch layer is used to form a touch electrode, and a portion of the structure of the touch layer forms the light-shielding portion.

9. The display panel according to claim 3, wherein, The pixel driving circuit includes a driving transistor and a capacitor. The driving transistor is used to provide driving current to the light-emitting unit according to its gate voltage. The first electrode of the capacitor is connected to the gate of the driving transistor, and the second electrode of the capacitor is connected to the power supply line. The display panel also includes: The second gate layer is located on one side of the substrate. The second gate layer includes a second conductive portion and a first connecting portion. The second conductive portion is used to form the second electrode of the capacitor. The first connecting portion is connected between two adjacent second conductive portions in the same pixel driving circuit group. The second gate layer further includes an epitaxial portion connected to the first connection portion, and the orthographic projection of the epitaxial portion on the substrate is located on one side of the orthographic projection of the first connection portion on the substrate in the column direction, and at least a portion of the structure of the epitaxial portion forms the light-shielding portion.

10. The display panel according to claim 2, wherein, The xth column initial signal line also includes an xth main body extension connected to the x1th via connection portion, and the size of the orthogonal projection of the x1th via connection portion on the substrate in the row direction is equal to the size of the orthogonal projection of the xth main body extension portion on the substrate in the row direction.

11. The display panel according to claim 10, wherein, The display panel also includes: The x2 via connection part is connected to the x1 via connection part through a via; The orthographic projection of the x2th via connection on the substrate is located within the orthographic projection of the x1th via connection on the substrate.

12. The display panel according to claim 10, wherein, The yth via connection portion is connected to the row initial signal line through the first via, and the x1th via connection portion is connected to the row initial signal line through the second via; The area of ​​the orthogonal projection of the opening of the first via facing the y-th via connection portion on the substrate is greater than the area of ​​the orthogonal projection of the opening of the second via facing the x1-th via connection portion on the substrate.

13. The display panel according to any one of claims 2-12, wherein, The pixel driving circuit includes: Drive transistors; The first transistor has a first terminal connected to the first column initial signal line and a second terminal connected to the gate of the driving transistor. The seventh transistor has its first electrode connected to the second column initial signal line and its second electrode connected to the first electrode of the light-emitting unit. The eighth transistor has its first terminal connected to the third column initial signal line and its second terminal connected to the first terminal of the driving transistor. Wherein, the xth column-directed initial signal line forms the first column-directed initial signal line, and the yth column-directed initial signal line forms the second column-directed initial signal line or the third column-directed initial signal line.

14. The display panel according to claim 13, wherein, The orthographic projections of the first column initial signal line, the second column initial signal line, the third column initial signal line, and the second column initial signal line on the substrate are sequentially and cyclically distributed in the row direction.

15. The display panel according to claim 1, wherein, The pixel driving circuit includes: Drive transistors; The first transistor has a first terminal connected to the first column initial signal line and a second terminal connected to the gate of the driving transistor. The seventh transistor has its first electrode connected to the second column initial signal line and its second electrode connected to the first electrode of the light-emitting unit. The eighth transistor has its first terminal connected to the third column initial signal line and its second terminal connected to the first terminal of the driving transistor. Wherein, the xth column-oriented initial signal line forms the first column-oriented initial signal line corresponding to a pixel driving circuit group, and the yth column-oriented initial signal line forms the first column-oriented initial signal line corresponding to another pixel driving circuit group; The orthographic projections of the first column initial signal line, the second column initial signal line, and the third column initial signal line on the substrate are sequentially and cyclically distributed in the row direction.

16. The display panel according to any one of claims 13-15, wherein, The pixel driving circuit also includes: The second transistor has a first terminal connected to the gate of the driving transistor and a second terminal connected to the second terminal of the driving transistor; The capacitor has its first electrode connected to the gate of the driving transistor and its second electrode connected to the power supply line. The display panel also includes: A first gate layer is located on one side of the substrate. The first gate layer includes a first gate line. The orthographic projection of the first gate line on the substrate extends in a row direction. A portion of the structure of the first gate line is used to form the gate of the second transistor. The second gate layer is located on the side of the first gate layer away from the substrate. The second gate layer includes a second conductive portion and a first connecting portion. The second conductive portion is used to form the second electrode of the capacitor. The first connecting portion is connected between two adjacent second conductive portions in the same pixel driving circuit group. Wherein, the orthographic projection of the x1th via connection portion on the substrate is at least partially located between the orthographic projection of the first connection portion on the substrate and the orthographic projection of the first gate line on the substrate.

17. The display panel according to any one of claims 1-16, wherein, The pixel driving circuit group includes two pixel driving circuits distributed in the row direction, and the two pixel driving circuits in the same pixel driving circuit group are arranged at least partially mirror-symmetrically on the substrate.

18. The display panel according to any one of claims 1-17, wherein, The pixel driving circuit includes: Drive transistors; The first transistor has a first terminal connected to the first row initial signal line and a second terminal connected to the gate of the driving transistor. The second transistor has a first terminal connected to the gate of the driving transistor and a second terminal connected to the second terminal of the driving transistor; The fourth transistor has its first terminal connected to the data line and its second terminal connected to the first terminal of the driving transistor. The fifth transistor has its first terminal connected to the power supply line and its second terminal connected to the first terminal of the driving transistor. The sixth transistor has its first electrode connected to the second electrode of the driving transistor, and the second electrode connected to the first electrode of the light-emitting unit. The seventh transistor has its first electrode connected to the second row initial signal line and its second electrode connected to the first electrode of the light-emitting unit. The eighth transistor has its first terminal connected to the third row of the initial signal line, and its second terminal connected to the drive. The first electrode of the moving transistor; The capacitor has its first electrode connected to the gate of the driving transistor and its second electrode connected to the power supply line.

19. The display panel according to claim 1, wherein, The pixel driving circuit includes: Drive transistors; The first transistor has a first terminal connected to the first row initial signal line and a second terminal connected to the gate of the driving transistor. The fourth transistor has its first terminal connected to the data line and its second terminal connected to the first terminal of the driving transistor. The display panel also includes: The second bridging portion is connected to the gate of the driving transistor via a via; The sixth bridging portion is connected to the first electrode of the fourth transistor via a via; The sixth conductive part is connected to one side of the first row-direction initial signal line in the column direction, and the orthographic projection of the sixth conductive part on the substrate is located between the orthographic projection of the second bridging part on the substrate and the orthographic projection of the sixth bridging part on the substrate.

20. The display panel according to claim 3, wherein, The y-th column extension and the light-shielding portion are located in region x.

21. A display device, wherein, The display device includes the display panel as described in any one of claims 1-20.

Images