Multilayer ceramic capacitor

Abstract

A multilayer ceramic capacitor (10) is provided that can suppress the decline in reliability. The multilayer ceramic capacitor (10) comprises: a multilayer body (12) including an effective portion (21) in which multiple ceramic layers (14) and multiple internal electrode layers (16) are alternately stacked, and an ineffective portion (24) in which one or more ceramic layers (14) are stacked and cover at least a portion of the effective portion (21); and an external electrode (30) formed on the outer surface of the multilayer body (12) and connected to the internal electrode layers (16). The ineffective portion (24) includes an interface region (42) including an interface (41) between the effective portion (21) and the ineffective portion (24), and an outer interface region (44) located in the direction outside the multilayer body (12) relative to the interface region (42). The continuity of Si present in the interface region (42) in the direction along the interface (41) is greater than the continuity of (Si) present in the outer interface region (44) in the direction along the interface (41).

Description

Technical Field

[0001] This invention relates to multilayer ceramic capacitors. Background Technology

[0002] In recent years, with the trend towards miniaturization of electronic devices, there has been a demand for miniaturization and larger capacitance in multilayer ceramic capacitors used in electronic devices. A typical multilayer ceramic capacitor comprises a laminate having an effective portion and an ineffective portion, and external electrodes disposed on the outer surface of the laminate. The effective portion accumulates capacitance by stacking multiple ceramic layers and multiple internal electrode layers. The ineffective portion covers the effective portion and is formed by stacking multiple ceramic layers. The internal electrode layers and external electrode layers of the effective portion are connected.

[0003] In the multilayer ceramic capacitor described in Patent Document 1, the effective portion before firing is formed by stacking components in which internal electrode paste is applied to ceramic sheets for the effective portion. Furthermore, a multilayer chip before firing is prepared by integrating multiple ceramic sheets for the ineffective portion with the effective portion. Here, the ceramic sheets for the effective and ineffective portions contain ceramic particles, a binder, and a solvent. The binder and solvent contain resin components. Then, the multilayer chip undergoes a degreasing process and a firing process, thereby forming the multilayer.

[0004] Prior art literature

[0005] Patent documents

[0006] Patent Document 1: Japanese Patent Application Publication No. 2014-7187 Summary of the Invention

[0007] The problem the invention aims to solve

[0008] The inventors discovered that in various laminates, including the one described in Patent Document 1, problems sometimes arise with the tightness of the contact between the ineffective and effective portions. When such problems exist with the tightness of the contact between the ineffective and effective portions, the reliability of the laminated ceramic capacitor sometimes decreases. Therefore, there is room for improvement in order to stably produce reliable laminated ceramic capacitors.

[0009] Therefore, the main objective of this invention is to provide a multilayer ceramic capacitor capable of suppressing a decrease in reliability.

[0010] Technical solutions for solving the problem

[0011] The multilayer ceramic capacitor of the present invention comprises: a multilayer body, including an effective portion having multiple ceramic layers and multiple internal electrode layers alternately stacked, and an ineffective portion having one or more ceramic layers stacked and covering at least a portion of the effective portion; and an external electrode formed on the outer surface of the multilayer body and connected to the internal electrode layers.

[0012] The invalid part includes: an interface region comprising the interface between the valid part and the invalid part, and an outer interface region located on the outer side of the laminate relative to the interface region.

[0013] The continuity of Si in the interface region along the interface direction is greater than the continuity of Si in the outer region along the interface direction.

[0014] According to the multilayer ceramic capacitor of the present invention, the continuity of Si in the interface region is greater than the continuity of Si in the region outside the interface. That is, Si is more continuously present in the interface region between the effective part and the ineffective part. By having Si more continuously present in the interface region, the adhesion between the effective part and the ineffective part can be improved. Therefore, the peeling of the ineffective part from the effective part can be suppressed, thus providing a multilayer ceramic capacitor that can suppress the decline in reliability.

[0015] Invention Effects

[0016] According to the present invention, a multilayer ceramic capacitor capable of suppressing a decrease in reliability can be provided.

[0017] The above-mentioned objects, other objects, features, and advantages of the present invention will become more apparent from the following detailed description of specific embodiments with reference to the accompanying drawings. Attached Figure Description

[0018] Figure 1 This is a perspective view showing an example of a multilayer ceramic capacitor according to an embodiment of the present invention.

[0019] Figure 2 yes Figure 1 A sectional view at line II-II.

[0020] Figure 3 yes Figure 1 A cross-sectional view at line III-III.

[0021] Figure 4 yes Figure 2 A cross-sectional view at line IV-IV.

[0022] Figure 5 yes Figure 2 A cross-sectional view at line V-V.

[0023] Figure 6 (a) is Figure 3 (a) is a magnified view of part α, and (b) is an analysis using a wavelength dispersive X-ray analyzer (WDX). Figure 3 The α portion was photographed to produce a cross-sectional photograph corresponding to (a).

[0024] Figure 7 This is a schematic diagram illustrating the method for determining the continuity of SiO2 (or Si).

[0025] Figure 8 (a) is Figure 3 (b) is a magnified view of the β portion, obtained using a wavelength dispersive X-ray analyzer (WDX). Figure 3 The β portion was photographed to produce a cross-sectional photograph corresponding to (a).

[0026] Figure 9 Figures (a) to (e) are used to illustrate the manufacturing method of the multilayer ceramic capacitor according to this embodiment.

[0027] Figure 10 This is a schematic diagram showing the stacking of ceramic sheets for the effective part, which are coated with conductive paste for internal electrode layers. Detailed Implementation

[0028] <Implementation Method>

[0029] 1. Multilayer ceramic capacitor

[0030] The multilayer ceramic capacitor according to embodiments of the present invention will be described. In this embodiment, a two-terminal multilayer ceramic capacitor will be used as an example for explanation.

[0031] Figure 1 This is a perspective view showing an example of a multilayer ceramic capacitor according to an embodiment of the present invention. Figure 2 yes Figure 1 A sectional view at line II-II. Figure 3 yes Figure 1 A cross-sectional view at line III-III. Figure 4 yes Figure 2 A cross-sectional view at line IV-IV. Figure 5 yes Figure 2 A cross-sectional view at line V-V.

[0032] like Figures 1 to 3 As shown, the multilayer ceramic capacitor 10 includes a cuboid multilayer 12 and external electrodes 30 disposed at both ends of the multilayer 12.

[0033] (1) Layered body

[0034] like Figure 1As shown, the laminate 12 has a first main surface 12a and a second main surface 12b facing each other in the height direction (lamination direction) x, a first side surface 12c and a second side surface 12d facing each other in the width direction y orthogonal to the height direction x, and a first end surface 12e and a second end surface 12f facing each other in the length direction z orthogonal to the height direction x and the width direction y. The laminate 12 has rounded corners and edges. A corner is the portion where three adjacent surfaces of the laminate intersect, and an edge is the portion where two adjacent surfaces of the laminate 12 intersect. Furthermore, some or all of the first main surface 12a and the second main surface 12b, the first side surface 12c and the second side surface 12d, and the first end surface 12e and the second end surface 12f may be formed with irregularities or protrusions.

[0035] like Figures 2-5 As shown, the laminate 12 has an effective portion 21 and an ineffective portion 24. The ineffective portion 24 includes an outer layer portion 22 and a side edge portion 23. The effective portion 21 and the ineffective portion 24 will be described below.

[0036] (1-1) Effective part

[0037] The effective portion 21 is formed by alternately stacking multiple ceramic layers 14 and multiple internal electrode layers 16. In the effective portion 21, the internal electrode layers 16 are opposed to each other across the ceramic layers 14, thereby forming an electrostatic capacitance. The effective portion 21 is the portion in which the internal electrode layers 16 are present. Specifically, in the height direction x, the effective portion 21 is the portion between the outermost surface of the effective portion 21 on the first main surface 12a side and the outermost surface of the effective portion 21 on the second main surface 12b side. The outermost surface of the effective portion 21 on the first main surface 12a side is the inner electrode layer 16 located on the outermost surface of the multiple internal electrode layers 16 on the first main surface 12a side (in... Figure 2 , 3 In the example, the internal electrode surface on the first main surface 12a side of the first internal electrode layer 16a is the internal electrode surface on the second main surface 12b side. Furthermore, the outermost surface of the effective portion 21 on the second main surface 12b side is the inner electrode layer 16 located on the outermost surface of the second main surface 12b side among the plurality of internal electrode layers 16. Figure 2 , 3 In the example, the internal electrode surface is on the second main surface 12b side of the second internal electrode layer 16b. Furthermore, in the width direction y, the effective portion 21 is the portion between the outermost surface of the effective portion 21 on the first side surface 12c and the outermost surface of the effective portion 21 on the second side surface 12d. The outermost surface of the effective portion 21 on the first side surface 12c is located at the internal electrode end on the first side surface 12c side of the first and second internal electrode layers 16a and 16b. The outermost surface of the effective portion 21 on the second side surface 12d is located at the internal electrode end on the second side surface 12d side of the first and second internal electrode layers 16a and 16b.

[0038] The ceramic layer 14 can be formed from a dielectric material, for example, as a ceramic material. As such a dielectric material, for example, a dielectric ceramic having a perovskite structure and being primarily composed of a perovskite-type compound containing BaTiO3, CaTiO3, SrTiO3, or CaZrO3 can be used. When the above-mentioned dielectric material is used as the main component, a Si compound can be added as an additive according to the desired characteristics of the laminate 12. In addition to Si compounds, for example, additives such as Mg compounds, Ba compounds, Mn compounds, Fe compounds, Cr compounds, Co compounds, and Ni compounds, which are present in smaller amounts than the main component, can also be added. Furthermore, the compound can be an oxide or a carbonate.

[0039] The thickness of the fired ceramic layer 14 in the effective portion 21 is preferably, for example, 0.3 μm or more and 1.0 μm or less, but is not limited thereto. The number of ceramic layers 14 stacked in the effective portion 21 is preferably, for example, 15 or more and 1000 or less, but is not limited thereto. More preferably, the thickness of the fired ceramic layer 14 in the effective portion 21 is preferably, for example, 0.3 μm or more and 0.6 μm or less, but is not limited thereto. As a result, the number of stacked layers can be increased, which can help to achieve high capacitance.

[0040] The internal electrode layer 16 has, for example, a plurality of first internal electrode layers 16a and a plurality of second internal electrode layers 16b having a generally rectangular shape. The plurality of first internal electrode layers 16a and the plurality of second internal electrode layers 16b are embedded in a configuration that alternates at equal intervals with respect to the ceramic layer 14 along the height direction x of the laminate 12.

[0041] like Figure 4 As shown, the first internal electrode layer 16a is disposed on a plurality of ceramic layers 14 and is located inside the laminate 12. The first internal electrode layer 16a has a first opposing electrode portion 26a opposite to the second internal electrode layer 16b, and a first lead-out electrode portion 28a located at one end of the first internal electrode layer 16a and extending from the first opposing electrode portion 26a to the first end face 12e of the laminate 12. The end of the first lead-out electrode portion 28a is led out to the surface of the first end face 12e and exposed from the laminate 12.

[0042] like Figure 5 As shown, the second internal electrode layer 16b is disposed on a plurality of ceramic layers 14 and is located inside the laminate 12. The second internal electrode layer 16b has a second opposing electrode portion 26b opposite to the first internal electrode layer 16a, and a second lead-out electrode portion 28b located at one end of the second internal electrode layer 16b and extending from the second opposing electrode portion 26b to the second end face 12f of the laminate 12. The end of the second lead-out electrode portion 28b is led out to the surface of the second end face 12f and exposed from the laminate 12.

[0043] While the shapes of the first opposing electrode portion 26a of the first inner electrode layer 16a and the second opposing electrode portion 26b of the second inner electrode layer 16b are not particularly limited, they are preferably rectangular in plan view. However, the corner portions may be rounded in plan view or formed into a cone shape in plan view. Alternatively, it may be a cone shape in plan view that is inclined in a certain direction.

[0044] While the shapes of the first lead-out electrode portion 28a of the first internal electrode layer 16a and the second lead-out electrode portion 28b of the second internal electrode layer 16b are not particularly limited, they are preferably rectangular in plan view. However, the corner portions may be rounded in plan view, or the corner portions may be formed as tilted (conical) in plan view. Alternatively, they may be tilted as they face a certain direction and have a conical shape in plan view.

[0045] The width of the first counter electrode portion 26a and the width of the first lead-out electrode portion 28a can be formed with the same width, or one of them can be formed with a narrower width. Similarly, the width of the second counter electrode portion 26b and the width of the second lead-out electrode portion 28b can be formed with the same width, or one of them can be formed with a narrower width.

[0046] The first internal electrode layer 16a and the second internal electrode layer 16b can be made of suitable conductive materials, such as metals like Ni, Cu, Ag, Pd, Au, or alloys containing at least one of these metals, such as Ag-Pd alloys.

[0047] The thickness of each of the internal electrode layers 16, namely the first internal electrode layer 16a and the second internal electrode layer 16b, is preferably 0.2 μm or more and 2.0 μm or less, but is not limited thereto. Furthermore, it is more preferably 0.2 μm or more and 0.5 μm or less, but is not limited thereto.

[0048] Furthermore, the total number of the first internal electrode layer 16a and the second internal electrode layer 16b is preferably 15 or more and 1000 or less.

[0049] Within the laminate 12, the first opposing electrode portion 26a of the first inner electrode layer 16a and the second opposing electrode portion 26b of the second inner electrode layer 16b are opposed to each other across the ceramic layer 14, thereby forming an electrostatic capacitor. Therefore, an electrostatic capacitor can be obtained between the first outer electrode 30a connected to the first inner electrode layer 16a and the second outer electrode 30b connected to the second inner electrode layer 16b, exhibiting the characteristics of a capacitor.

[0050] (1-2) Invalid part

[0051] The ineffective portion 24 is formed by stacking one or more ceramic layers 14. The dielectric material, additives, and other material composition of the ceramic layer 14 of the ineffective portion 24 may be the same as that of the ceramic layer 14 of the effective portion 21. The ineffective portion 24 covers at least a portion of the effective portion 21. The ineffective portion 24 has an outer layer portion 22 and a side edge portion 23.

[0052] exist Figure 6 In the middle, (a) is Figure 3 (a) is a magnified view of part α, and (b) is an analysis using a wavelength dispersive X-ray analyzer (WDX). Figure 3 The α portion was photographed to produce a cross-sectional photograph corresponding to (a). Figure 7 This is a schematic diagram illustrating the method for determining the continuity of SiO2 (or Si). Figure 8 In the middle, (a) is Figure 3 (b) is a magnified view of the β portion, obtained using a wavelength dispersive X-ray analyzer (WDX). Figure 3 The β portion was photographed to produce a cross-sectional photograph corresponding to (a).

[0053] (a) Outer layer

[0054] like Figure 2 , Figure 3As shown, the outer layer 22 (part of the ineffective part 24) has a first outer layer 22a and a second outer layer 22b. The first and second outer layers 22a and 22b are formed by stacking multiple ceramic layers 14. The effective part 21 is sandwiched between the first outer layer 22a and the second outer layer 22b in the height direction (stack direction) x. The first outer layer 22a is adjacent to the inner electrode surface of the outermost first inner electrode layer 16a of the effective part 21. The inner electrode surface is along the planar direction (LW planar direction). That is, the first outer layer 22a is located on the side of the first main surface 12a and is formed by multiple ceramic layers 14 located between the outermost surface of the effective part 21 on the side of the first main surface 12a and a straight line (extension line) in the length direction z of the outermost surface. The second outer layer 22b is adjacent to the inner electrode surface of the outermost second inner electrode layer 16b of the effective portion 21. That is, the second outer layer 22b is located on the second main surface 12b side and is formed by a plurality of ceramic layers 14 located between the outermost surface of the effective portion 21 on the second main surface 12b side and a straight line along the length direction z of that outermost surface. The thickness of the fired ceramic layers 14 in the first and second outer layers 22a and 22b is preferably, for example, 10 μm or more and 100 μm or less, but is not limited thereto. The number of ceramic layers 14 stacked in the first and second outer layers 22a and 22b is preferably, for example, 1 or more and 50 or less, but is not limited thereto. Alternatively, the first and second outer layers 22a and 22b may also be formed by a single layer of ceramic layer 14.

[0055] In the first and second outer layers 22a and 22b, Si is continuously present at the interface 41 with the effective portion 21. The first and second outer layers 22a and 22b include an interface region 42 and an outer interface region 44. The interface region 42 includes the interface 41 between the effective portion 21 and the first and second outer layers 22a and 22b. The outer interface region 44 is located in the outer direction of the laminate 12 relative to the interface region 42. The continuity of Si present in the interface region 42 along the direction of the interface 41 is greater than the continuity of Si present in the outer interface region 44 along the direction of the interface 41. Using... Figure 6 The outer layer 22 in this embodiment will be further described. However, the structures of the first and second outer layers 22a and 22b are the same, so the first outer layer 22a will be described below.

[0056] exist Figure 6In the example, the first outer layer 22a includes an interface region 42, an interface adjacent region 43, and an interface outer region 44. The interface region 42 includes an interface 41 where the effective portion 21 and the first outer layer 22a contact. The interface adjacent region 43 is adjacent to the interface region 42 in the outer direction of the laminate 12. The interface outer region 44 is adjacent to the interface adjacent region 43 in the outer direction of the laminate 12. That is, in the first outer layer 22a, the interface region 42, the interface adjacent region 43, and the interface outer region 44 are sequentially arranged adjacent to each other in the outer direction of the laminate 12. Furthermore, the interface outer region 44 includes a central portion 47 in the first outer layer 22a in the direction from the effective portion 21 side toward the first outer layer 22a side. In other words, the central portion 47 is the center of the first outer layer 22a in a direction orthogonal to the direction along the interface 41. Furthermore, the interface outer region 44 includes an outer surface region 45 and an outer main region 46. The outer surface region 45 includes the outer surface of the laminate 12 and is located on the outer surface side of the laminate 12. The outer interface main region 46 is the region outside the outer surface region 45 in the outer interface region 44, and is located in the direction inward of the laminate 12 than the outer surface region 45. The outer interface main region 46 includes a central portion 47. The average thickness of the interface region 42 of the first outer layer 22a is, for example, 1.20 μm or more and 1.25 μm or less. Furthermore, the average thickness of the interface adjacent region 43 of the first outer layer 22a is, for example, 3 μm or more and 5 μm or less.

[0057] The positions, extents, and continuity of Si in regions 42, 43, 45, 46, etc., can be determined visually and using scales (as reference dimensions, rulers, etc.) based on results measured by a wavelength dispersive X-ray analyzer (WDX). For example, in Figure 6 In (b), the continuity of regions 42, 43, 45, 46, etc., and Si are determined using visual inspection and scales as follows. Figure 6 In (b), the portion adjacent to the effective portion 21 in the outer direction of the laminate 12 and containing a continuous white region of Si is defined as interface region 42. Furthermore, the portion adjacent to interface region 42 in the outer direction of the laminate 12, containing fewer and less continuous white regions of Si compared to interface region 42, is defined as interface adjacent region 43. Furthermore, the portion where white regions of Si are scattered and the continuity of Si is small is defined as outer main region 46. Furthermore, the portion adjacent to outer main region 46 in the outer direction of the laminate 12 and containing more continuous white regions of Si compared to outer main region 46 is defined as outer surface region 45.

[0058] Here, the position, extent, and continuity of Si in each region 42, 43, 45, 43, etc., can also be determined by the intensity of Si. For example, the interface region 42 and the adjacent interface region 43 can be determined as follows: First, the intensity of Si in the portion of the interface region 42 that can be considered as the first outer layer 22a within a given field of view is measured using WDX, for example, the ratio of the intensity of Si to the intensity of Ba (intensity of Si / intensity of Ba). As described later, the intensity of Si in multiple sub-segmented regions (e.g., one pixel) within the portion that can be considered as the interface region 42 is obtained, and their average is obtained. Based on this average, it is determined whether Si segregation occurs in the portion of the interface region 42 that can be considered as the first outer layer 22a. In other words, the average ratio of the intensity of Si to the intensity of Ba (intensity of Si / intensity of Ba) in the portion of the interface region 42 that can be considered as the first outer layer 22a within a given field of view is calculated. In this embodiment, if the average value of the intensity of Si / intensity of Ba is, for example, 0.1 or higher, it is determined that Si segregation occurs. The average value is, for example, 0.1 or higher and 0.2 or lower. In this way, the portion determined to be Si segregated can be identified as interface region 42. Similarly, the Si intensity / Ba intensity is obtained in at least one sub-segmented region within the portion that can be considered the interface adjacent region 43 of the first outer layer 22a, and their average is obtained. Based on this result, it can be determined whether Si segregation has occurred, and the interface adjacent region 43 can be identified. Furthermore, if the average value of the Si intensity / Ba intensity in the interface adjacent region 43 is, for example, 0.05 or higher and less than 0.10, it is considered as Si not segregated in the definition of this invention.

[0059] The location, extent, and continuity of Si of other outer surface regions 45 and main interface regions 46 can also be determined by the strength of Si / strength of Ba, just as described above.

[0060] In the first outer layer 22a, Si is added as an additive to the ceramic material. Si exists in the first outer layer 22a as SiO2. Alternatively, Si can be in the form of SiO2 or a low-viscosity liquid phase containing SiO2. The same applies below. Furthermore, below, Si may sometimes be referred to as SiO2, and sometimes as SiO2. Moreover, Si is generally continuously present in the interface region 42 along the direction of the interface 41. Furthermore, the continuity of Si present in the interface region 42 along the direction of the interface 41 is greater than the continuity of Si present in the outer interface region 44 along the direction of the interface 41. In other words, the continuity of Si present in the interface region 42 along the direction of the interface 41 is greater than the continuity of Si present in the central portion 47 along the direction of the interface 41. Further, in other words, the continuity of Si present in the interface region 42 along the direction of the interface 41 is greater than the continuity of Si present in the outer interface main region 46 along the direction of the interface 41.

[0061] exist Figure 6 In (b), the white area represents the region where Si exists. Figure 6 As shown in (b), Si exists continuously in the interface region 42. In contrast, Si exists dispersedly and has low continuity in the main region 46 outside the interface (the region outside the interface 44 excluding the outer surface region 45).

[0062] To improve the adhesion between the effective portion 21 and the outer layer 22, the continuity of Si in the interface region 42 is preferably 50% or more. To further improve the adhesion between the effective portion 21 and the outer layer 22, the continuity of Si in the interface region 42 is more preferably 80% or more.

[0063] Furthermore, the Si content in the adjacent region 43 is sometimes lower than the Si content in the interface region 42. According to... Figure 6 As shown in (b), the white area in the interface-adjacent region 43 is smaller and contains less Si compared to the interface region 42. Furthermore, the Si content in the interface-adjacent region 43 can also be less than the Si content in the outer interface region 44.

[0064] Here, the content of metal elements containing compounds such as Ni and NiO in the outer interface region 44 is less than the content of metal elements containing compounds such as Ni and NiO in the interface region 42. In particular, when the main component of the inner electrode layer 16 is Ni, the Ni content in the outer interface region 44 is less than the Ni content in the interface region 42. This can be attributed to the fact that the first inner electrode layer 16a of the effective part 21 is further away from the outer interface region 44 compared to the interface region 42. Similarly, the content of metal elements containing compounds such as Ni and NiO in the interface adjacent region 43 is less than the content of metal elements containing compounds such as Ni and NiO in the interface region 42. In particular, when the main component of the inner electrode layer 16 is Ni, the Ni content in the interface adjacent region 43 is less than the Ni content in the interface region 42. This can be attributed to the fact that the first inner electrode layer 16a of the effective part 21 is further away from the interface region 43 compared to the interface region 42.

[0065] The continuity of Si in the first outer layer 22a can be determined, for example, as follows. In the laminate 12, for example, Figure 3 The WT profile is exposed as shown. For the WT profile, the presence of Si is analyzed using, for example, a wavelength dispersive X-ray analysis (WDX) device. By using WDX analysis, the intensity of various components is detected in each of the multiple segmented regions in the WT profile. Specifically, intensity analysis is performed by dividing a given field of view (here referred to as one field of view portion) into multiple segmented regions using WDX. These multiple segmented regions are, for example, regions where the first outer layer 22a is divided in a direction orthogonal to the interface 41. In this embodiment, the first outer layer 22a includes multiple segmented regions divided in a direction orthogonal to the interface 41 and arranged along the direction of the interface 41. The presence of Si in the interface region 42 is determined based on the intensity of Si in each segmented region. Then, the continuity of Si is determined by the proportion of segmented regions in the interface region 42 where Si is present in the interface region 42 among all segmented regions. Each segmented region is, for example, a given region of an image obtained using WDX with multiple pixels.

[0066] use Figure 7 An example of a method for determining the continuity of Si will be further explained. Figure 7 It is to Figure 6 (a) and the following Figure 8 (a) A diagram showing the same field of view in a rough outline. Figure 7 In this example, the main component of the ceramic layer 14 is assumed to be BaTiO3, and Si is included as an additive. Furthermore, the main component of the internal electrode layer 16 is assumed to be Ni.

[0067] In the first outer layer 22a, for example, Figure 7The WT cross-section is thus exposed. Using a wavelength dispersive X-ray diffraction (WDX) analyzer, various components in multiple segmented regions of the WT cross-section are analyzed. These multiple segmented regions are areas where the first outer layer 22a is divided in a direction orthogonal to the interface 41. Figure 7 In the example, the first outer layer 22a is divided into segmented regions C1, C2, C3, C4...Cn. Furthermore, each segmented region C1 to Cn is further divided into, for example, 12 sub-segmented regions R1 to R12, from the effective portion 21 side toward the ineffective portion 24 side. Here, the interface region 42 and the adjacent interface region 43, etc., can be determined visually or using a scale, as described above. For example, in... Figure 7 In the example, groups G1 to G4 are defined as interface region 42. Group G1 contains sub-segmented regions R1 to R5 within segmented region C1, group G2 contains sub-segmented regions R2 to R6 within segmented region C2, group G3 contains sub-segmented regions R1 to R5 within segmented region C3, and group G4 contains sub-segmented regions R1 to R5 within segmented region C4. Here, in the context of... Figure 6 (b) and the following Figure 8 (b) Under visual inspection, there is a continuous white area of ​​Si, which is identified as a region of Si segregation. Figure 7 The locations of each group G1 to G4, which contains a given number of sub-segments, are generally consistent. Furthermore, the adjacent interface region 43, the outer surface region 45, and the main outer interface region 46 can also be determined using the same method.

[0068] Here, the interface 41 between the outermost surface of the first main surface 12a side of the effective portion 21, namely the first inner electrode layer 16a, and the first outer layer 22a (ineffective portion 24), can be determined, for example, as follows. For each sub-divided region R1 to R12, the ratio of Ni intensity to Ba intensity (Ni intensity / Ba intensity) is determined using a wavelength dispersive X-ray analysis apparatus (WDX) as an indicator of Ni content. Next, from the effective portion 21 side toward the ineffective portion 24 side, sub-divided regions are determined where the ratio of Ni intensity to Ba intensity is initially, for example, 0.2 or less. In this embodiment, a Ni intensity / Ba intensity ≤ 0.2 is used as a reference for regions that are not internal electrode layer 16. Therefore, when the Ni intensity / Ba intensity is, for example, 0.3, a region is determined to contain internal electrode layer 16. Figure 7In the case where the condition of Ni strength / Ba strength ≤ 0.2 is initially met, sub-segmentation regions are defined as follows: sub-segmentation region R1 is defined in segmentation region C1, sub-segmentation region R2 is defined in segmentation region C2, sub-segmentation region R1 is defined in segmentation region C3, and sub-segmentation region R1 is defined in segmentation region C4. Furthermore, the Ni content index can also be expressed by the ratio of Ni content to Ba content (Ni content / Ba content). By using the Ni content index in this way, the interface 41 between the outermost surface of the first main surface 12a side of the effective part 21, namely the first inner electrode layer 16a, and the first outer layer 22a (ineffective part 24) can be deduced.

[0069] Then, in Figure 7 In this case, the continuity of interface region 42 can be determined as follows. First, for each group G1 to G4, the ratio of Si intensity to Ba intensity (Si intensity / Ba intensity) is determined using a wavelength dispersive X-ray analyzer (WDX). In group G1 of interface region 42, the ratio of Si intensity / Ba intensity in sub-divided regions R1 to R5 is as follows: Figure 7 As shown, the average Si intensity / Ba intensity ratio is 0.066. Therefore, the average Si intensity / Ba intensity ratio in group G1 is less than 0.1. Therefore, the amount of Si present in group G1 is low, indicating a break in the continuity of Si. On the other hand, the Si intensity / Ba intensity ratios in groups G2 (sub-segmentation regions R2-R6), G3 (sub-segmentation regions R1-R5), and G4 (sub-segmentation regions R1-R5) are as follows... Figure 7 As shown, the average Si intensity / Ba intensity ratios for groups G2 to G4 are 0.196, 0.19, and 0.188, respectively. Therefore, the average Si intensity / Ba intensity ratio for groups G2 to G4 is above 0.1 and below 0.2. Thus, the amount of Si present in each of groups G2 to G4 is high, indicating that Si is continuously present throughout groups G2 to G4. Based on this result, when observing the interface region 42 (groups G1 to G4) as a whole, it is determined that Si is continuously present and segregated in this interface region 42.

[0070] Then, in Figure 7 In the example, the proportion of groups (groups G2 to G4) where the Si intensity / Ba intensity is 0.1 or higher is determined among the multiple groups G1 to G4. From this, the continuity of Si in the interface region 42 can be determined.

[0071] Furthermore, the continuity of Si in the outer region 44 can be determined in the same manner as described above. That is, the outer region 44 is determined visually, etc. Then, for each segmented region C1, C2, etc., of the outer region 44, the average of the Si intensity / Ba intensity of the sub-segmented regions is calculated. Then, the proportion of segmented regions in the outer region 44 whose Si intensity / Ba intensity is 0.05 or higher and less than 0.10 is calculated. Thus, the continuity of Si in the outer region 44 can be determined.

[0072] Furthermore, the continuity of Si can also be determined using the same method for the outer surface region 45 and the main interface region 46.

[0073] In addition, the continuity of Si can also be determined not by the strength of Si / strength of Ba, but by the ratio of Si content to Ba content.

[0074] (b) Side edge

[0075] like Figures 3-5 As shown, the side edge portion 23 (part of the ineffective portion 24) has a first side edge portion 23a and a second side edge portion 23b. The first and second side edge portions 23a and 23b are formed by stacking multiple ceramic layers 14. A stacked portion 20 is sandwiched between the first side edge portion 23a and the second side edge portion 23b in the width direction y. Here, the stacked portion 20 is obtained by stacking an effective portion 21 and an outer pair of outer layers 22 in the height direction x of the effective portion 21. The first and second side edge portions 23a and 23b are adjacent to the internal electrode ends of the first and second internal electrode layers 16a and 16b. The internal electrode ends are located at the two ends in the W direction of the planar direction (LW planar direction) of the first and second internal electrode layers 16a and 16b. In particular, the internal electrode ends are the ends of the first and second side surfaces 12c and 12d sides of the first and second internal electrode layers 16a and 16b. Furthermore, the first and second side edge portions 23a and 23b are as follows: Figure 4 , Figure 5 The cross-section shown, viewed from the height direction (stack direction) x, does not contain areas of the first and second internal electrode layers 16a and 16b. The thickness of the fired ceramic layer 14 in the first and second side edge portions 23a and 23b is preferably, for example, 10 μm or more and 100 μm or less, but is not limited thereto. The number of ceramic layer 14 sheets stacked in the first and second side edge portions 23a and 23b is preferably, for example, 1 or more and 50 or less, but is not limited thereto. Alternatively, the first and second side edge portions 23a and 23b may also be formed from a single layer of ceramic layer 14.

[0076] In the first and second side edge portions 23a and 23b, Si is continuously present at the interface 41 with the effective portion 21. The first and second side edge portions 23a and 23b include an interface region 42 and an outer interface region 44. The interface region 42 includes the interface 41 between the effective portion 21 and the first and second side edge portions 23a and 23b. The outer interface region 44 is located in the outer direction of the laminate 12 relative to the interface region 42. The continuity of Si present in the interface region 42 along the direction of the interface 41 is greater than the continuity of Si present in the outer interface region 44 along the direction of the interface 41. Utilizing... Figure 8 The side edge portion 23 in this embodiment will be further described. However, the structures of the first and second side edge portions 23a and 23b are the same, so the first side edge portion 23a will be described below.

[0077] exist Figure 8 In this example, the first side edge portion 23a includes an interface region 42, an interface adjacent region 43, and an interface outer region 44. The interface region 42 includes an interface 41 that contacts the effective portion 21 and the first side edge portion 23a. The interface adjacent region 43 is adjacent to the interface region 42 in the outer direction of the laminate 12. The interface outer region 44 is adjacent to the interface adjacent region 43 in the outer direction of the laminate 12. That is, in the first side edge portion 23a, the interface region 42, the interface adjacent region 43, and the interface outer region 44 are arranged sequentially adjacent to each other in the outer direction of the laminate 12. Furthermore, the interface outer region 44 includes a central portion 47 in the first side edge portion 23a in the direction from the effective portion 21 towards the first side edge portion 23a. In other words, the central portion 47 is the center of the first side edge portion 23a in a direction orthogonal to the direction along the interface 41. Furthermore, the interface outer region 44 includes an outer surface region 45 and an outer main region 46. The outer surface region 45 includes the outer surface of the laminate 12 and is located on the outer surface side of the laminate 12. The outer interface main region 46 is the region outside the outer surface region 45 in the outer interface regions 44, and is located in the direction inward of the laminate 12 than the outer surface region 45. The outer interface main region 46 includes a center portion 47. The average thickness of the interface region 42 of the first side edge portion 23a is, for example, 1.06 μm or more and 1.12 μm or less. Furthermore, the average thickness of the interface adjacent region 43 of the first side edge portion 23a is, for example, 3 μm or more and 5 μm or less.

[0078] The positions, extents, and continuity of Si in regions 42, 43, 45, 46, etc., as described above, can be determined visually or by using a scale (a reference dimension, ruler, etc.) based on the results measured by a wavelength dispersive X-ray analyzer (WDX). For example, in Figure 8In (b), the continuity of regions 42, 43, 45, 46, etc., and Si are determined using visual inspection and scales as follows. Figure 8 In (b), the portion adjacent to the effective portion 21 in the outer direction of the laminate 12 and containing a continuous white region of Si is defined as interface region 42. Furthermore, the portion adjacent to interface region 42 in the outer direction of the laminate 12, containing fewer and less continuous white regions of Si compared to interface region 42, is defined as interface adjacent region 43. Furthermore, the portion where white regions of Si are scattered and the continuity of Si is small is defined as outer main region 46. Furthermore, the portion adjacent to outer main region 46 in the outer direction of the laminate 12 and containing more continuous white regions of Si compared to outer main region 46 is defined as outer surface region 45.

[0079] Here, the position, extent, and continuity of Si in each region 42, 43, 45, 43, etc., can also be determined by the intensity of Si. For example, the interface region 42 and the adjacent interface region 43 can be determined as follows: First, the intensity of Si in a portion of the interface region 42 that can be considered as the first side edge 23a within a given field of view is measured using WDX, for example, the ratio of the intensity of Si to the intensity of Ba (intensity of Si / intensity of Ba). The intensity of Si in multiple sub-segmented regions (e.g., 1 pixel) within the portion that can be considered as the interface region 42 is obtained, and their average is obtained. Based on this average, it is determined whether Si segregation occurs in the portion of the interface region 42 that can be considered as the first side edge 23a. In other words, the average ratio of the intensity of Si to the intensity of Ba (intensity of Si / intensity of Ba) in the portion of the interface region 42 that can be considered as the first side edge 23a within a given field of view is calculated. In this embodiment, if the average value of the intensity of Si / intensity of Ba is, for example, 0.1 or higher, it is determined that Si segregation occurs. The average value is, for example, 0.1 or higher and 0.2 or lower. In this way, the portion determined to be Si segregated can be identified as interface region 42. Similarly, the Si intensity / Ba intensity is obtained in at least one sub-segmented region within the portion of the interface adjacent region 43 that can be considered as the first side edge 23a, and their average is obtained. Based on this result, it can be determined whether Si segregation has occurred, and the interface adjacent region 43 can be identified. Furthermore, if the average value of the Si intensity / Ba intensity in the interface adjacent region 43 is, for example, 0.05 or higher and less than 0.10, it is considered as Si not segregated in the definition of this invention.

[0080] The location, extent, and continuity of Si of other outer surface regions 45 and main interface regions 46 can also be determined by the strength of Si / strength of Ba, just as described above.

[0081] In the first side edge portion 23a, Si is added as an additive to the ceramic material. Si exists in the first side edge portion 23a as SiO2. Alternatively, Si can also be in the form of SiO2 or a low-viscosity liquid phase containing SiO2. The same applies below. Furthermore, sometimes Si is referred to as SiO2, and sometimes SiO2 is referred to as Si. Moreover, Si is generally continuously present in the interface region 42 along the direction of the interface 41. Furthermore, the continuity of Si present in the interface region 42 along the direction of the interface 41 is greater than the continuity of Si present in the outer interface region 44 along the direction of the interface 41. In other words, the continuity of Si present in the interface region 42 along the direction of the interface 41 is greater than the continuity of Si present in the central portion 47 along the direction of the interface 41. Further, in other words, the continuity of Si present in the interface region 42 along the direction of the interface 41 is greater than the continuity of Si present in the outer interface main region 46 along the direction of the interface 41.

[0082] exist Figure 8 In (b), the white area represents the region where Si exists. Figure 8 As shown in (b), Si exists continuously in the interface region 42. In contrast, Si exists dispersedly and has low continuity in the main region 46 outside the interface (the region outside the interface 44 excluding the outer surface region 45).

[0083] To improve the tightness of the contact between the effective portion 21 and the side edge portion 23, the continuity of Si in the interface region 42 is preferably 50% or more. To further improve the tightness of the contact between the effective portion 21 and the side edge portion 23, the continuity of Si in the interface region 42 is more preferably 80% or more.

[0084] Furthermore, the Si content in the adjacent region 43 is sometimes lower than the Si content in the interface region 42. According to... Figure 8 As shown in (b), the white area in the interface-adjacent region 43 is smaller and contains less Si compared to the interface region 42. Furthermore, the Si content in the interface-adjacent region 43 can also be less than the Si content in the outer interface region 44.

[0085] Here, the content of metal elements containing compounds such as Ni and NiO in the outer interface region 44 is less than the content of metal elements containing compounds such as Ni and NiO in the interface region 42. In particular, when the main component of the inner electrode layer 16 is Ni, the Ni content in the outer interface region 44 is less than the Ni content in the interface region 42. This can be attributed to the fact that the first inner electrode layer 16a of the effective part 21 is further away from the outer interface region 44 compared to the interface region 42. Similarly, the content of metal elements containing compounds such as Ni and NiO in the interface adjacent region 43 is less than the content of metal elements containing compounds such as Ni and NiO in the interface region 42. In particular, when the main component of the inner electrode layer 16 is Ni, the Ni content in the interface adjacent region 43 is less than the Ni content in the interface region 42. This can be attributed to the fact that the first inner electrode layer 16a of the effective part 21 is further away from the interface region 43 compared to the interface region 42.

[0086] The continuity of Si in the first side edge portion 23a can be determined, for example, as described above, in the following manner. For the WT profile, the presence of Si is analyzed using WDX, for example. By performing analysis using WDX, the intensity of various components is detected for each of the multiple segmented regions in the WT profile. Specifically, an intensity analysis is performed by dividing a given field of view (here referred to as one field of view portion) into multiple segmented regions using WDX. These multiple segmented regions are, for example, regions in which the first side edge portion 23a is divided in a direction orthogonal to the interface 41. In this embodiment, the first side edge portion 23a includes multiple segmented regions divided in a direction orthogonal to the interface 41 and arranged along the direction of the interface 41. The presence of Si in the interface region 42 is determined for each segmented region based on the intensity of Si. Then, the continuity of Si is determined by the proportion of segmented regions in the interface region 42 where Si is present in the interface region 42 among all segmented regions. Each segmented region is, for example, a given region of an image obtained using WDX with multiple pixels.

[0087] The continuity of Si in the first side edge portion 23a can be consistent with the above. Figure 7 Similarly, find the answer.

[0088] (2) External electrode

[0089] like Figures 1-5 As shown, external electrodes 30 are disposed on the first end face 12e side and the second end face 12f side of the laminate 12.

[0090] The external electrode 30 has a first external electrode 30a and a second external electrode 30b.

[0091] The first external electrode 30a is connected to the first internal electrode layer 16a and is disposed at least on the surface of the first end face 12e. Furthermore, in this embodiment, the first external electrode 30a extends from the first end face 12e of the laminate 12 and is also disposed on a portion of the first main surface 12a, a portion of the second main surface 12b, a portion of the first side surface 12c, and a portion of the second side surface 12d. In this case, the first external electrode 30a is electrically connected to the first lead-out electrode portion 28a of the first internal electrode layer 16a.

[0092] The second external electrode 30b is connected to the second internal electrode layer 16b and is disposed at least on the surface of the second end face 12f. Furthermore, in this embodiment, the second external electrode 30b extends from the second end face 12f and is also disposed on a portion of the first main surface 12a, a portion of the second main surface 12b, a portion of the first side surface 12c, and a portion of the second side surface 12d. In this case, the second external electrode 30b is electrically connected to the second lead-out electrode portion 28b of the second internal electrode layer 16b.

[0093] The external electrode 30 includes a base electrode layer 32 containing a metallic component and a plating layer 34 disposed on the base electrode layer 32.

[0094] The first external electrode 30a has a first base electrode layer 32a containing a metal component and a first plating layer 34a disposed on the first base electrode layer 32a.

[0095] The second external electrode 30b includes a second base electrode layer 32b containing a metallic component and a second plating layer 34b disposed on the second base electrode layer 32b.

[0096] (2-1) Substrate electrode layer

[0097] The first base electrode layer 32a is connected to the first inner electrode layer 16a and disposed on the surface of the first end face 12e. Furthermore, the first base electrode layer 32a extends from the first end face 12e and is also disposed on a portion of the first main surface 12a, a portion of the second main surface 12b, a portion of the first side surface 12c, and a portion of the second side surface 12d. In this case, the first base electrode layer 32a is electrically connected to the first lead-out electrode portion 28a of the first inner electrode layer 16a. Alternatively, the first base electrode layer 32a may be disposed only on the surface of the first end face 12e.

[0098] The second base electrode layer 32b is connected to the second inner electrode layer 16b and disposed on the surface of the second end face 12f. Furthermore, the second base electrode layer 32b extends from the second end face 12f and is also disposed on a portion of the first main surface 12a, a portion of the second main surface 12b, a portion of the first side surface 12c, and a portion of the second side surface 12d. In this case, the second base electrode layer 32b is electrically connected to the second lead-out electrode portion 28b of the second inner electrode layer 16b. Alternatively, the second base electrode layer 32b may be disposed only on the surface of the second end face 12f.

[0099] (2-2) Coating

[0100] Next, refer to Figures 2-5 The plating layers 34 disposed on the substrate electrode layer 32, namely the first plating layer 34a and the second plating layer 34b, will be described.

[0101] The first plating layer 34a is configured to cover the first base electrode layer 32a on the first end face 12e side. Furthermore, the first plating layer 34a may also be configured to cover the first base electrode layer 32a on the first main face 12a, the second main face 12b, the first side face 12c, and the second side face 12d side. However, the first plating layer 34a may also be configured only on the first base electrode layer 32a on the first end face 12e side.

[0102] The second plating layer 34b is configured to cover the second base electrode layer 32b on the second end face 12f side. Furthermore, the second plating layer 34b may also be configured to cover the second base electrode layer 32b on the first main face 12a, the second main face 12b, the first side face 12c, and the second side face 12d side. However, the second plating layer 34b may also be configured only on the second base electrode layer 32b on the second end face 12f side.

[0103] The first plating layer 34a and the second plating layer 34b may, for example, include at least one selected from Cu, Ni, Sn, Ag, Pd, Ag-Pd alloy, Au, etc.

[0104] The plating layer 34 can also be formed of multiple layers. For example, the first plating layer 34a is a two-layer structure comprising a first lower plating layer and a first upper plating layer covering the first lower plating layer, and the second plating layer 34b is a two-layer structure comprising a second lower plating layer and a second upper plating layer covering the second lower plating layer. Preferably, the first lower plating layer and the second lower plating layer are Ni plating layers, and the first upper plating layer and the second upper plating layer are Sn plating layers.

[0105] The first and second lower plating layers formed by the Ni plating layer are used to prevent the base electrode layer 32 from being eroded by the solder when mounting the multilayer ceramic capacitor 10. In addition, the first and second upper plating layers formed by the Sn plating layer are used to improve the wettability of the solder when mounting the multilayer ceramic capacitor 10, so that it can be easily mounted.

[0106] The first and second lower plating layers formed by the Ni plating layer are preferably 1 μm or more and 15 μm or less. The first and second upper plating layers formed by the Sn plating layer are preferably 1 μm or more and 15 μm or less.

[0107] The first and second external electrodes 30a and 30b may each be formed with a plating layer 34 directly on the surface of the laminate 12 without the base electrode layer 32. That is, the laminated ceramic capacitor 10 may also be constructed by plating the first end face 12e and the second end face 12f to form a plating layer 34 that is electrically connected to the first internal electrode layer 16a or the second internal electrode layer 16b. In this case, the plating layer 34 may also be formed by plating after a catalyst has been disposed on the surface of the laminate 12 as a pretreatment.

[0108] Furthermore, when the plating layer 34 is formed directly on the laminate 12 without setting the base electrode layer 32, the portion where the thickness of the base electrode layer 32 is reduced can be made thinner or converted into the thickness of the laminate, i.e., the thickness of the effective portion 21, thus increasing the design freedom of the thickness of the laminate 12.

[0109] (3) Dimensions of multilayer ceramic capacitors

[0110] The dimensions of the multilayer ceramic capacitor 10 in the length direction z (L dimension), height direction x (T dimension), and width direction y (W dimension) are not particularly limited.

[0111] 2. Manufacturing method of multilayer ceramic capacitors

[0112] Next, the manufacturing method of multilayer ceramic capacitors will be explained. Figure 9 In the figure, (a) to (e) are diagrams illustrating the manufacturing method of the multilayer ceramic capacitor according to this embodiment. Figure 10 This is a schematic diagram showing the stacking of ceramic sheets for effective parts coated with conductive paste for internal electrode layers.

[0113] (1) Formation of stacked small pieces (unfired stacked small pieces)

[0114] First, a perovskite-type compound containing Ba and Ti is prepared as a dielectric ceramic material. In a dielectric powder obtained from this dielectric ceramic material, Si, an organic binder, an organic solvent, a plasticizer, and a dispersant are mixed in a given proportion as additives to prepare a ceramic paste for the effective part. In the ceramic paste for the effective part, for example, 0.8 mol to 2.0 mol of Si is contained relative to 100 mol of Ti.

[0115] The same ceramic paste for the ineffective part (ceramic paste for the outer layer, ceramic paste for the side edges, and ceramic paste for the interface) is made in the same way as the ceramic paste for the effective part.

[0116] The ceramic paste used for the outer layer and the ceramic paste used for the side edges contain, for example, 1.0 mol or more but less than 4.0 mol of Si relative to 100 mol of Ti. The ceramic paste used for the interface between the effective part 21 and the ineffective part 24 is adjusted to contain more Si than the ceramic paste used for the effective part, the ceramic paste used for the outer layer, and the ceramic paste used for the side edges. The ceramic paste used for the interface contains, for example, 5.0 mol or more but less than 10.0 mol of Si relative to 100 mol of Ti.

[0117] In addition, conductive metals, organic binders, organic solvents, and additives for the internal electrode layer are mixed in a given ratio to produce a conductive paste for the internal electrode layer.

[0118] Various ceramic pastes are applied to the surfaces of multiple resin films (not shown) to form ceramic sheets 50 (50a, 50b). Specifically, a ceramic paste for the effective part is applied to the surface of the resin film and dried to form a ceramic sheet 50a for the effective part. The thickness of the ceramic sheet 50a for the effective part is, for example, 0.5 μm or more and 2.0 μm or less. Furthermore, a ceramic paste for the ineffective part is applied to the surface of the resin film and dried to form a ceramic sheet 50b for the ineffective part (an outer layer ceramic sheet 50b1, a side edge ceramic sheet 50b2, and an interface ceramic sheet 50b3). The thickness of the outer layer ceramic sheet 50b1 and the side edge ceramic sheet 50b2 is, for example, 20 μm or more and 30 μm or less. The thickness of the interface ceramic sheet 50b3 is, for example, 5.0 μm or more and 8.0 μm or less.

[0119] Next, as Figure 9 As shown in (a), a given number of outer ceramic sheets 50b1 are stacked in a state where they are peeled off from the resin film. Then, as... Figure 9 As shown in (b), ceramic sheets 50b3 for the interface are stacked on top of it in a state of being peeled off from the resin film. By stacking these multiple outer layer ceramic sheets 50b1 and interface ceramic sheets 50b3 and firing them, a second outer layer 22b can be formed.

[0120] Next, as Figure 9 As shown in (c), an effective portion ceramic sheet 50a is laminated onto the outer layer ceramic sheets 50b1 and 50b3, which form the second outer layer 22b and the interface, in a state of being peeled off from the resin film. A conductive paste 51 for an internal electrode layer is applied (printed) onto the effective portion ceramic sheet 50a. The conductive paste 51 for the internal electrode layer on the effective portion ceramic sheet 50a is dried to form a conductive film. At this time, as... Figure 10 As shown, adjacent ceramic sheets 50a, on which conductive films are formed, are stacked in a staggered manner. This produces an effective portion 21 before firing, having ceramic sheets 50a on which conductive films forming the first and second internal electrode layers 16a and 16b are formed. Various printing methods can be used, such as screen printing, inkjet printing, and gravure printing.

[0121] Next, as Figure 9 As shown in (d), an interface ceramic sheet 50b3 is stacked on the uppermost effective portion ceramic sheet 50a, where a conductive film is formed, in a state of being peeled off from the resin film. Then, a given number of outer layer ceramic sheets 50b1 are stacked on top of it. This results in a laminated sheet. By stacking multiple outer layer ceramic sheets 50b1 and interface ceramic sheets 50b3 and then firing them, the first outer layer portion 22a can be formed.

[0122] Next, laminated sheets are pressed in the lamination direction using methods such as isostatic pressing to produce laminated blocks.

[0123] Then, by cutting the laminated block to a given size, the unfired laminated portion 20 (a component formed by laminating the unfired effective portion 21 and the unfired outer layer portion 22) is cut out. At this time, the corners and edges of the unfired laminated portion 20 can also be rounded by tumbling or the like.

[0124] The unfired laminate 20 obtained through the above processes exposes only the conductive film that forms the first internal electrode layer 16a on one end face. Furthermore, only the conductive film that forms the second internal electrode layer 16b is exposed on the other end face.

[0125] Furthermore, on both sides of the unfired laminated portion 20, conductive films that form the first and second internal electrode layers 16a and 16b are exposed respectively.

[0126] (2) Formation of the side edge

[0127] Next, the steps for making the first and second side edge portions 23a and 23b will be explained.

[0128] As described above, an interface ceramic paste is applied to the surface of the resin film and dried to form an interface ceramic sheet 50b3. Furthermore, an edge ceramic paste is applied to the surface of the resin film and dried to form an edge ceramic sheet 50b2.

[0129] Next, ceramic sheet 50b3 for peeling off the interface of the resin film and ceramic sheet 50b2 for multiple side edges are used.

[0130] Next, as Figure 9 As shown in (e), a ceramic sheet 50b3 for the interface is laminated onto the side of the unfired laminate 20 where the conductive film is exposed, and then multiple ceramic sheets 50b2 for the side edges are laminated on top of it. Pressing and punching are performed with the ceramic sheets 50b3 and 50b2 facing the side of the unfired laminate 20 where the conductive film is exposed. By laminating these interface ceramic sheets 50b3 and multiple ceramic sheets 50b2 for the side edges and firing them, the first side edge portion 23a can be formed. Furthermore, interface ceramic sheets 50b3 are also laminated onto the side of the unfired laminate 20 where the layer that does not form the first side edge portion 23a is not formed, and then multiple ceramic sheets 50b2 for the side edges are laminated on top of it. Pressing and punching are performed with the ceramic sheets 50b3 and 50b2 facing the side of the unfired laminate 20 where the conductive film is exposed. By stacking ceramic sheets 50b3 for the interface and multiple ceramic sheets 50b2 for the side edges and firing them, a second side edge portion 23b can be formed. At this time, it is preferable to pre-apply an organic solvent, which serves as an adhesive, to the side surface of the unfired stacked portion 20.

[0131] Next, the laminated sheet 55, which forms the first and second side edges 23a and 23b, is fed into a degreasing process (a degreasing process for laminated sheets) and degreased under given conditions. The degreasing process is preferably performed, for example, in a N2 / H2 / H2O mixed atmosphere. The degreasing process is performed, for example, sequentially at low temperature and high temperature. Low-temperature degreasing is performed, for example, at 250°C or higher and 300°C or lower, at a heating rate of 0.15°C / min or higher and 0.25°C / min or lower, for a low-temperature time of 300 min, but is not limited thereto. High-temperature degreasing is performed, for example, at 800°C, at a heating rate of 3.0°C / min or higher and 3.5°C / min or lower, for a high-temperature time of 200 min, but is not limited thereto.

[0132] Then, the stacked small pieces 55 are fed into the firing process (firing process for stacked small pieces) and fired at a given temperature to obtain the sintered stacked body 12. Although the firing temperature also depends on the materials of the ceramic layer and the internal electrode layer, it is preferably above 1200°C and below 1250°C.

[0133] Alternatively, the portions that can become the first and second side edge portions 23a and 23b can also be formed by applying ceramic paste for the interface and ceramic paste for the side edges to both exposed sides of the conductive film of the stacked small piece 55.

[0134] That is, a ceramic paste for the interface is applied to both exposed sides of the conductive film of the stacked small sheet 55 and dried to form a ceramic sheet 50b3 for the interface. Then, a ceramic paste for the side edges is applied to the surface of the ceramic sheet 50b3 for the interface and dried to form a ceramic sheet 50b2 for the side edges.

[0135] Furthermore, the portions that could become the first and second side edge portions 23a and 23b can be formed by, after covering the two end faces of the laminated portion 20 with resin or the like, immersing the entire laminated portion 20 in an interface ceramic paste and drying it, and then immersing it in a side edge ceramic paste and drying it. In this case, an interface ceramic sheet 50b3 and a side edge ceramic sheet 50b2 are also formed sequentially on both sides of the laminated portion 20.

[0136] (3) Formation of external electrodes

[0137] Next, an external electrode 30, comprising a base electrode layer 32 and a plating layer 34, is formed on the laminate 12. First, a conductive paste for external electrodes, such as one with Cu as the main component, is applied to the two end faces 12e, 12f, etc. of the laminate 12. The base electrode layer 32 is formed by firing the laminate 12 in a firing process for external electrodes.

[0138] Next, a plating layer 34 is formed. The plating layer 34 can be formed on the surface of the substrate electrode layer 32 or directly on the laminate 12. In this embodiment, the plating layer 34 is formed on the surface of the substrate electrode layer 32. In this case, the plating layer 34 is formed on the surface of the substrate electrode layer 32 after the substrate electrode layer 32 is formed. More specifically, a Ni plating layer and a Sn plating layer are formed on the substrate electrode layer 32. During the plating process, either electrolytic plating or electroless plating can be used, but electroless plating requires pretreatment with catalysts or the like to increase the plating deposition rate, which complicates the process. Therefore, electrolytic plating is generally preferred. As the plating method, barrel plating is preferred.

[0139] As described above, manufacturing Figure 1 The stacked ceramic capacitor 10 shown.

[0140] 3. Effects

[0141] According to the multilayer ceramic capacitor 10 described above, the continuity of Si (SiO2) in the interface region 42 is greater than the continuity of Si in the outer interface region 44. That is, Si is more continuously present in the interface region 42 between the effective portion 21 and the ineffective portion 24. In this way, by having more continuously present Si in the interface region 42, the adhesion between the effective portion 21 and the ineffective portion 24 can be improved. Therefore, the peeling of the ineffective portion 24 from the effective portion 21 can be suppressed, thus providing a multilayer ceramic capacitor 10 that can suppress the decrease in reliability. Furthermore, in this embodiment, Si is mainly present as SiO2.

[0142] Furthermore, the reason for the improved adhesion between the effective portion 21 and the ineffective portion 24 will be explained. The improved adhesion may be due to phenomena such as those described below, but is not limited to these. The effective portion 21 before firing is formed by laminating a component made by coating an internal electrode layer conductive paste 51 onto a ceramic sheet 50a used in the effective portion. Furthermore, the ineffective portion 24 before firing is formed by laminating a ceramic sheet 50b used in the ineffective portion. A laminated piece 55 (the laminated body 12 before firing) is formed by integrating the ineffective portion 24 before firing (the ceramic sheet 50b for the ineffective portion: the outer layer ceramic sheet 50b1, the side edge ceramic sheet 50b2, and the interface ceramic sheet 50b3) with the effective portion 21 before firing, such that at least a portion of the effective portion 21 before firing is covered. This laminated piece 55 undergoes a degreasing process and a firing process to become the laminated body 12 (the laminated body 12 after firing). In at least one of the degreasing and firing processes, the resin component is removed from the ceramic sheet 50b used in the inactive portion, leaving behind BaTiO3 powder and the like, which is the main component. Therefore, gaps may form between the BaTiO3 powder and the like due to the removal of the resin component. Consequently, gaps may also form at the interface 41 between the effective portion 21 and the inactive portion 24. In the multilayer ceramic capacitor 10 of this embodiment, such gaps are generally not generated in the interface region 42; instead, Si is continuously present along the interface 41 in the interface region 42. That is, there is generally no continuous gap along the interface 41 in the interface region 42 between the inner electrode layer 16 at the outermost surface (or outermost end) of the effective portion 21 and the inactive portion 24; instead, Si is continuously present along the interface 41. It can be considered that the Si substantially fills the gap, and the adhesion between the effective portion 21 and the inactive portion 24 is considered improved compared to the case where there is a continuous gap in the interface region 42. Therefore, it is possible to suppress the invalid part 24 from peeling off from the effective part 21, and as a result, it is possible to suppress the decrease in the reliability of the multilayer ceramic capacitor 10.

[0143] Furthermore, regarding the generation of gaps and the presence of Si within those gaps, if the degreasing and firing processes are studied separately, for example, the following actions may occur during the manufacturing process of the multilayer ceramic capacitor 10, but this is not a limitation. In the multilayer 12 before firing, the resin component is removed through the degreasing process, thereby potentially creating gaps continuously along the interface 41 between the effective portion 21 and the ineffective portion 24. Specifically, by removing the resin component from the ceramic sheet 50b used in the ineffective portion (the ceramic sheet 50 for the ineffective portion includes the outer layer ceramic sheet 50b1, the side edge ceramic sheet 50b2, and the interface ceramic sheet 50b3) through the degreasing process, gaps may be continuously created at the interface 41 between the conductive layer of the inner electrode layer on the outermost surface (or the outermost end) of the effective portion 21 and the ceramic sheet 50b used in the ineffective portion. By firing the laminate 12 before firing in the firing process, the metal powder of the conductive paste 51 for the internal electrode layer, and the ceramic powder of the ceramic sheets 50a and 50b for the effective and ineffective parts are sintered into metal particles and ceramic particles. Furthermore, it can be considered that the Si of the ceramic sheet 50b for the ineffective part melts and flows during the firing process, moving to the gap in the interface region 42. In this embodiment, it can be considered that mainly the Si of the ceramic sheet 50b3 for the interface melts and flows, moving to the gap in the interface region 42. Therefore, it can be considered that by passing through the firing process, the gap in the interface region 42 is substantially filled with Si, improving the adhesion between the effective part 21 and the ineffective part 24. In addition, it can be considered that at least a portion of the Si present in the interface adjacent region 43 moves to the gap in the interface region 42 during the firing process, so the Si content in the interface adjacent region 43 is less than that in the interface region 42.

[0144] Furthermore, in the above embodiment, the interface region 42 is located closer to the effective portion 21 than the center portion 47 of the ineffective portion 24. The continuity of Si is high in this interface region 42 near the effective portion 21, thus improving the tightness of the connection between the effective portion 21 and the ineffective portion 24.

[0145] Furthermore, the outer surface region 45 is located on the outer surface side of the laminate 12, and sometimes Si is also continuously present in this outer surface region 45. Even in this case, the continuity of Si in the interface region 42 is greater than the continuity of Si in the main interface region 46 outside the interface region 44, excluding the outer surface region 45. That is, Si is more continuously present in the interface region 42 between the effective part 21 and the ineffective part 24. Therefore, it is possible to suppress the peeling of the ineffective part 24 from the effective part 21.

[0146] 4. Experimental Example

[0147] As a multilayer ceramic capacitor 10, multilayer ceramic capacitors of the embodiments and comparative examples were manufactured. Then, the interface peeling rate of the ineffective part 24 from the effective part 21 was evaluated.

[0148] A. Sample preparation

[0149] As an example, a laminate 12 was fabricated using the manufacturing method described above. In this example, particularly during the formation of the first and second outer layer portions 22a and 22b, for the effective portion 21 before firing, an outer layer ceramic sheet 50b1 was stacked while an interface ceramic sheet 50b3 was stacked. Furthermore, during the formation of the first and second side edge portions 23a and 23b, for the laminated portion 20 (effective portion 21 and outer layer portion 22), a side edge ceramic sheet 50b2 was stacked while an interface ceramic sheet 50b3 was stacked.

[0150] As a comparative example, the laminate 12 was manufactured using the above-described manufacturing method, except for the ceramic sheet 50b3 used for the interface. That is, the ceramic sheet 50b3 for the interface was not used in the comparative example. When forming the first and second outer layers 22a and 22b, the outer layer ceramic sheet 50b1 was stacked on the effective portion 21 before firing. Furthermore, when forming the first and second side edge portions 23a and 23b, the side edge ceramic sheet 50b2 was stacked on the laminate 20.

[0151] B. Evaluation of the sample

[0152] As an example, 100 multilayer ceramic capacitors were prepared, and as a comparative example, 100 multilayer ceramic capacitors were prepared. By observing the appearance of the samples, it was determined whether cracks, peeling, etc., occurred at the interface 41 between the effective part 21 and the ineffective part 24. The multilayer ceramic capacitors that had cracks, peeling, etc., were counted as peeling occurrences, and the interface peeling rate relative to 100 was calculated.

[0153] Table 1 shows the results of the interface peeling rate for the embodiments and comparative examples.

[0154] [Table 1]

[0155]

[0156] C. Experimental Results

[0157] In the embodiment, the interface peeling rate between the effective and ineffective parts was 0%, meaning no peeling occurred. When the sample of the embodiment was observed using WDX, Si in the interface region showed continuous segregation. The continuity of Si was approximately 80%.

[0158] On the other hand, in the comparative example, the interface peeling rate between the effective and ineffective parts was 20%, indicating peeling. When the comparative example sample was observed using WDX, no segregation of Si continuity in the interface region was observed.

[0159] As can be seen from the above, by continuously segregating Si in the interface region, it is possible to suppress the stripping of the ineffective part from the effective part.

[0160] Furthermore, as described above, the embodiments of the present invention have been disclosed through the foregoing description, but the present invention is not limited thereto.

[0161] That is, various changes can be made to the above-described embodiments regarding the mechanism, shape, material, quantity, position or configuration without departing from the technical concept and purpose of the present invention, and these changes are included in the present invention.

[0162] <Variation Example> (1)

[0164] In the above embodiment, the invalid part 24 includes the interface adjacent region 43. However, as long as the adhesion between the effective part 21 and the invalid part 24 can be improved by the continuous presence of Si in the interface region 42, the invalid part 24 may not include the interface adjacent region 43. Similarly, in the above embodiment, the interface outer region 44 includes the outer surface region 45. However, as long as the adhesion between the effective part 21 and the invalid part 24 can be improved by the continuous presence of Si in the interface region 42, the interface outer region 44 may not include the outer surface region 45. (2)

[0166] In the above embodiment, Si is continuously present in the interface region 42 in both the outer layer portion 22 and the side edge portion 23. However, it is also possible that Si is continuously present in the interface region 42 of either the outer layer portion 22 or the side edge portion 23.

[0167] For example, the continuity of Si in the interface region 42 of the outer layer 22 is sometimes greater than the continuity of Si in the interface region 44 of the outer layer 22. As a result, the tightness of the contact between the effective part 21 and the outer layer 22 can be improved.

[0168] Furthermore, for example, the continuity of Si in the interface region 42 of the side edge portion 23 is sometimes greater than the continuity of Si in the outer interface region 44 of the side edge portion 23. As a result, the tightness of the contact between the effective portion 21 and the side edge portion 23 can be improved. (3)

[0170] In the above embodiment, in order to improve the continuity of Si in the interface region 42, an interface ceramic sheet 50b3, which has a higher Si content than the outer layer and side edge ceramic sheets 50b1 and 50b2, is disposed in or near the interface region 42 to form a multilayer ceramic capacitor 10. However, a multilayer ceramic capacitor 10 with high Si continuity in the interface region 42 can also be formed, for example, by adjusting the atmosphere in at least one of the degreasing process and the firing process for the multilayer sheet. In this case, the process of preparing the interface ceramic paste and disposing of the interface ceramic sheet 50b3 can be omitted in the manufacturing method of the multilayer ceramic capacitor in the above embodiment. In addition, the Si content in the ceramic paste for the effective part, the outer layer and the side edge ceramic paste, and the thickness of the ceramic sheet 50a for the effective part, and the outer layer and the side edge ceramic sheets 50b1 and 50b2 can be the same as in the above embodiment.

[0171] Furthermore, in the manufacturing method of the above-described embodiment, a laminated portion 20 having an effective portion 21 and an outer layer portion 22 is first formed, and then a side edge portion 23 is formed on the unfired laminated portion 20 to form a laminated body 12. The manufacturing process is not limited as long as Si is continuously present in the interface region 42. For example, an unfired laminated piece 55 can also be generated by simultaneously configuring the unfired effective portion 21 with the unfired outer layer portion 22 and the unfired side edge portion 23. (4)

[0173] In the above embodiments, a two-terminal type multilayer ceramic capacitor having two terminals, a first external electrode 30a and a second external electrode 30b, was described as a multilayer ceramic capacitor. However, the scope of application of the present invention is not limited to two-terminal type multilayer ceramic capacitors. The present invention is applicable to multilayer ceramic capacitors having a multilayer body with effective and ineffective portions and external electrodes. Therefore, the present invention can also be applied, for example, to three-terminal type multilayer ceramic capacitors. The three-terminal type multilayer ceramic capacitor has the same multilayer body 12 and first to fourth external electrodes as in the above embodiments. The internal electrode layer 16 has a first internal electrode layer led to a first end face 12e and a second end face 12f, and a second internal electrode layer led to a first side face 12c and a second side face 12d. The first external electrode is disposed on the first end face 12e of the multilayer body 12. The first external electrode is electrically connected to the first internal electrode layer exposed on the first end face 12e of the multilayer body 12. The second external electrode is disposed on the second end face 12f of the multilayer body 12. The second external electrode is electrically connected to the first internal electrode layer exposed on the second end face 12f of the laminate 12. A third external electrode is disposed on the first side face 12c of the laminate 12. The third external electrode is electrically connected to the second internal electrode layer exposed on the first side face 12c of the laminate 12. A fourth external electrode is disposed on the second side face 12d of the laminate 12. The fourth external electrode is electrically connected to the second internal electrode layer exposed on the second side face 12d of the laminate 12. (5)

[0175] In the above embodiments, a multilayer ceramic capacitor 10 in which Si is continuously present in the interface region 42 between the effective portion 21 and the ineffective portion 24 has been described as an example. The present invention can also be applied to the following electronic components.

[0176] When a piezoelectric ceramic material is used in ceramic layer 14, the multilayer ceramic capacitor functions as a piezoelectric component. Specific examples of piezoelectric ceramic materials include, for instance, PZT (lead zirconate titanate) based ceramic materials.

[0177] Furthermore, when a semiconductor ceramic material is used in the ceramic layer 14, the multilayer ceramic capacitor functions as a thermistor. Specific examples of semiconductor ceramic materials include, for instance, spinel-based ceramic materials.

[0178] Furthermore, when a magnetic ceramic material is used in the ceramic layer 14, the multilayer ceramic capacitor functions as an inductor. Additionally, when functioning as an inductor, the internal electrode layer 16 becomes a coil-shaped conductor. Specific examples of magnetic ceramic materials include, for instance, ferrite ceramic materials.

[0179] <1>

[0180] A multilayer ceramic capacitor, comprising:

[0181] A laminate comprising an effective portion consisting of alternating layers of ceramic layers and internal electrode layers, and an ineffective portion consisting of one or more ceramic layers covering at least a portion of the effective portion; and

[0182] External electrodes are formed on the outer surface of the laminate and are connected to the inner electrode layer.

[0183] in,

[0184] The invalid portion includes: an interface region comprising the interface between the valid portion and the invalid portion, and an outer interface region located on the outer side of the laminate relative to the interface region.

[0185] The continuity of Si in the interface region along the direction of the interface is greater than the continuity of Si in the region outside the interface along the direction of the interface.

[0186] <2>

[0187] According to the multilayer ceramic capacitor described in <1>, among which,

[0188] The area outside the interface includes the central portion of the invalid portion in the direction from the valid portion side toward the invalid portion side.

[0189] The continuity of Si in the interface region along the direction of the interface is greater than the continuity of Si in the center portion along the direction of the interface.

[0190] <3>

[0191] According to the multilayer ceramic capacitor described in <1> or <2>, wherein,

[0192] The invalid portion further includes an interface adjacent region that is adjacent to the interface region in the outer direction of the laminate, wherein the Si content in the interface adjacent region is less than the Si content in the interface region.

[0193] <4>

[0194] According to any one of <1> to <3>, the multilayer ceramic capacitor, wherein,

[0195] The outer interface region includes: an outer surface region, comprising the outer surface of the laminate and located on the outer surface side of the laminate; and an outer interface main region, which is the region outside the outer surface region and located on the laminate side.

[0196] The continuity of Si in the interface region along the direction of the interface is greater than the continuity of Si in the main region outside the interface along the direction of the interface.

[0197] <5>

[0198] According to any one of <1> to <4>, the multilayer ceramic capacitor described therein,

[0199] The amount of Ni-containing metal elements in the region outside the interface is less than the amount of Ni-containing metal elements in the interface region.

[0200] <6>

[0201] According to any one of <1> to <5>, the multilayer ceramic capacitor, wherein,

[0202] The invalid part comprises multiple segmented regions that are divided in a direction orthogonal to the interface and arranged along the direction of the interface.

[0203] The continuity of Si in the interface region is represented by the proportion of the multiple segmented regions in which Si exists in the interface region, and the continuity of Si in the outer region is represented by the proportion of the multiple segmented regions in which Si exists in the outer region.

[0204] <7>

[0205] According to the multilayer ceramic capacitor described in <6>, among which,

[0206] Among the plurality of segmented regions, the segmented region containing Si in the interface region includes the portion with a Si content index of 0.1 or higher. The Si content index is expressed by the ratio of the strength of Si to the strength of Ba, or the ratio of the Si content to the Ba content.

[0207] <8>

[0208] According to the multilayer ceramic capacitor described in <6> or <7>, among which,

[0209] Among the plurality of segmented regions, the segmented region containing Si in the interface region includes a portion in which the Ni content index initially becomes 0.2 or less from the effective part side toward the ineffective part side. The Ni content index is expressed by the ratio of Ni strength to Ba strength, or the ratio of Ni content to Ba content.

[0210] <9>

[0211] According to any one of <1> to <8>, the multilayer ceramic capacitor described therein,

[0212] The continuity of Si in the interface region is over 80%.

[0213] <10>

[0214] According to any one of <1> to <9>, the multilayer ceramic capacitor, wherein,

[0215] The internal electrode layer has an internal electrode surface along the planar direction and an end along the planar direction, namely the internal electrode end.

[0216] The ineffective portion includes an outer layer portion adjacent to the inner electrode surface of the outermost inner electrode layer of the effective portion, and a side edge portion adjacent to the end of the inner electrode.

[0217] In at least one of the outer layer and the side edge, the continuity of Si in the interface region along the direction of the interface is greater than the continuity of Si in the outer region along the direction of the interface.

[0218] Explanation of reference numerals in the attached figures

[0219] 10: Multilayer ceramic capacitors

[0220] 12: Layered bodies

[0221] 12a, 12b: 1st and 2nd main surface

[0222] 12c, 12d: First and second side views

[0223] 12e, 12f: First and second end faces

[0224] 14: Ceramic layer

[0225] 16: Internal electrode layer

[0226] 16a, 16b: First and second internal electrode layers

[0227] 20: Stacked Part

[0228] 21: Effective part

[0229] 22: Outer layer

[0230] 22a, 22b: First and second outer layers

[0231] 23: Side edge

[0232] 23a, 23b: The first and second side edges

[0233] 24: Invalid part

[0234] 26a, 26b: First and second opposing electrode sections

[0235] 28a, 28b: First and second lead-out electrode sections

[0236] 30: External electrode

[0237] 30a, 30b: First and second external electrodes

[0238] 32: Substrate electrode layer

[0239] 32a, 32b: First and second base electrode layers

[0240] 34: Plating layer

[0241] 34a, 34b: First and second plating layers

[0242] 41: Interface

[0243] 42: Interface Area

[0244] 43: Adjacent areas on the interface

[0245] 44: Area outside the interface

[0246] 45: Outer surface area

[0247] 46: Main area outside the interface

[0248] 47: Central Section

[0249] 50: Ceramic slab

[0250] 50a: Ceramic plate used in the effective part

[0251] 50b: Ceramic plate for inactive part

[0252] 50b1: Ceramic sheet for outer layer

[0253] 50b2: Ceramic sheet for side edges

[0254] 50b3: Ceramic sheet for interface

[0255] 51: Conductive paste used for the internal electrode layer

[0256] 55: Layered small pieces

[0257] C1~Cn: Segmentation Region

[0258] G1, G2, G3, G4...: Group

[0259] R1~R12: Sub-segmentation regions

[0260] x: height direction

[0261] y: width direction

[0262] z: Length direction.

Claims

1. A multilayer ceramic capacitor, comprising: A laminate comprising an effective portion consisting of alternating layers of ceramic layers and internal electrode layers, and an ineffective portion consisting of one or more ceramic layers covering at least a portion of the effective portion; and External electrodes are formed on the outer surface of the laminate and are connected to the inner electrode layer. in, The invalid portion includes: an interface region comprising the interface between the valid portion and the invalid portion, and an outer interface region located on the outer side of the laminate relative to the interface region. The continuity of Si in the interface region along the direction of the interface is greater than the continuity of Si in the region outside the interface along the direction of the interface.

2. The multilayer ceramic capacitor according to claim 1, wherein, The area outside the interface includes the central portion of the invalid portion in the direction from the valid portion side toward the invalid portion side. The continuity of Si in the interface region along the direction of the interface is greater than the continuity of Si in the center portion along the direction of the interface.

3. The multilayer ceramic capacitor according to claim 1 or claim 2, wherein, The invalid portion further includes an interface adjacent region that is adjacent to the interface region in the outer direction of the laminate, wherein the Si content in the interface adjacent region is less than the Si content in the interface region.

4. The multilayer ceramic capacitor according to any one of claims 1 to 3, wherein, The outer interface region includes: an outer surface region, comprising the outer surface of the laminate and located on the outer surface side of the laminate; and an outer interface main region, which is the region outside the outer surface region and located on the laminate side. The continuity of Si in the interface region along the direction of the interface is greater than the continuity of Si in the main region outside the interface along the direction of the interface.

5. The multilayer ceramic capacitor according to any one of claims 1 to 4, wherein, The amount of Ni-containing metal elements in the region outside the interface is less than the amount of Ni-containing metal elements in the interface region.

6. The multilayer ceramic capacitor according to any one of claims 1 to 5, wherein, The invalid part comprises multiple segmented regions that are divided in a direction orthogonal to the interface and arranged along the direction of the interface. The continuity of Si in the interface region is represented by the proportion of the multiple segmented regions in which Si exists in the interface region, and the continuity of Si in the outer region is represented by the proportion of the multiple segmented regions in which Si exists in the outer region.

7. The multilayer ceramic capacitor according to claim 6, wherein, Among the plurality of segmented regions, the segmented region containing Si in the interface region includes the portion with a Si content index of 0.1 or higher. The Si content index is expressed by the ratio of the strength of Si to the strength of Ba, or the ratio of the Si content to the Ba content.

8. The multilayer ceramic capacitor according to claim 6 or claim 7, wherein, Among the plurality of segmented regions, the segmented region containing Si in the interface region includes a portion in which the Ni content index initially becomes 0.2 or less from the effective part side toward the ineffective part side. The Ni content index is expressed by the ratio of Ni strength to Ba strength, or the ratio of Ni content to Ba content.

9. The multilayer ceramic capacitor according to any one of claims 1 to 8, wherein, The continuity of Si in the interface region is over 80%.

10. The multilayer ceramic capacitor according to any one of claims 1 to 9, wherein, The internal electrode layer has an internal electrode surface along the planar direction and an end along the planar direction, namely the internal electrode end. The ineffective portion includes an outer layer portion adjacent to the inner electrode surface of the outermost inner electrode layer of the effective portion, and a side edge portion adjacent to the end of the inner electrode. In at least one of the outer layer and the side edge, the continuity of Si in the interface region along the direction of the interface is greater than the continuity of Si in the outer region along the direction of the interface.

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