A low-latency anti-interference secure transmission method and system for protecting brain-computer information sovereignty
By employing independently controllable STE spectral entropy encoding, sovereign hash identifier embedding, and narrowband anti-interference modulation, combined with domestically produced chips and a lightweight AI inference engine, the problems of sovereign control failure, excessive latency, weak anti-interference, and security-latency conflict in brain-computer interface transmission have been solved. This has enabled low-latency, high-security, and strong anti-interference brain-computer information transmission, ensuring the security and sovereign controllability of domestically produced technology.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- ZHUHAI GONGZHENG TECHNOLOGY CO LTD
- Filing Date
- 2026-04-10
- Publication Date
- 2026-06-23
Abstract
Description
[0001] This invention discloses a low-latency, interference-resistant, and secure transmission method and system for protecting brain-computer interface information sovereignty, belonging to the field of brain-computer interface information. The field encompasses security, neural signal processing, and the protection of domestically produced data sovereignty. Methods include: adaptive preprocessing of neural signals, STE spectral entropy encryption encoding, sovereign hash identifier embedding, narrowband anti-interference modulation transmission, sovereign chain verification and layered decoding. Major steps; the system adopts a fully domestically produced chip instruction set, a lightweight AI inference engine, and a hardware-level security isolation architecture, with no boundaries. This invention addresses the dependence on foreign technology. It utilizes Continuous Spectral Entropy (STE) encoding and Sovereign Hash Chain (SHC) to achieve brain-computer interface communication between brain and computer systems. The sovereign entity is uniquely bound; through dynamic delay threshold control, anti-interference signal-to-noise ratio threshold, and physical layer encryption fusion, transmission is made possible. Transmission delay reduced by ≥88%, anti-interference capability improved by ≥92%, signal accuracy increased by ≥99.99%, and end-to-end delay ≤1.2ms. The invention is adapted to invasive / non-invasive brain-computer interfaces, medical rehabilitation, confidential interaction, and special control scenarios, realizing brain-computer information mastery. With four key advantages—autonomy and controllability, low latency, high security, and strong anti-interference—this technology fills the gap in domestically developed brain-computer interface secure transmission technology and supports… The domestic production and safe development of the brain-computer interface industry. Technical Field This invention pertains to brain-computer interface (BCI) information security, real-time neural signal processing, domestically produced data sovereignty protection, and low latency. This research area spans the interdisciplinary fields of wireless communication, embedded chip security, and lightweight inference for large AI models; specifically, it involves a method to safeguard brain-computer interfaces. A low-latency, interference-resistant, and secure transmission method and system for information sovereignty; applicable to invasive / non-invasive brain-computer interfaces and medical devices. High-security, high-real-time scenarios include rehabilitation, human-computer intelligent interaction, classified brain control, special equipment, and military brain-computer information transmission.
[0002] (3) Background technology (pain points + quantitative comparison) Current brain-computer interface transmissions have five fatal flaws: 1. Loss of sovereignty: Reliance on foreign protocols (Bluetooth 5.3 / Wi-Fi 6E / Neuralink protocols) and foreign encryption. (AES-256 / RSA / ECC) Sensitive neural signals pose risks of theft, tampering, hijacking, and remote control, making it impossible to guarantee the security of the domestic system. Brain-computer information sovereignty.
[0003] 2. Excessive latency: Conventional solutions have an end-to-end latency of 8-25ms, which cannot meet the brain control requirement of **<2ms** hard real-time.
[0004] 3. Weak anti-interference: Bit error rate (BER) > 10⁻³ and signal-to-noise ratio (SNR) < 15dB under electromagnetic / clutter interference; signal distortion in complex scenes. **>35%**.
[0005] 4. Security versus latency conflict: Traditional encryption (software layer) increases latency by 40%-70%, making it impossible to balance low latency and high security.
[0006] 5. Bottleneck Dependence: Core chips (ARM / X86 / RISC-V overseas branches), encryption modules, and protocol stacks are all licensed overseas. Risks include supply disruptions, backdoors, and tracing the source of the virus.
[0007] Comparison of existing technical specifications - Latency: 8-25ms; Target of this invention: ≤1.2ms - Interference immunity: SNR < 15dB, BER > 10⁻³; This invention: SNR ≥ 45dB, BER ≤ 10⁻⁹ - Security: Software-layer encryption, vulnerable to side-channel attacks; This invention employs a three-tiered sovereign encryption system: physical layer + data link layer + application layer. - Sovereignty: No sovereign identifier, can be controlled across borders; This invention: Sovereign Hash Chain (SHC) uniquely binds, illegal receiving ends have no [identification / control]. Decoding (4) Invention content (method + system + formula + code + threshold) 4.1 Definition of core technologies (code can be written directly) - STE Encoding: Spectrum Time Entropy encoding, a domestically developed algorithm based on the time domain of neural signals. Lightweight streaming encryption based on three-dimensional features of frequency domain / entropy values.
[0008] - SHC Sovereign Identifier: Sovereign Hash Chain, dual-embedded with national cryptographic SM3 + neural feature hash, unique One is to identify the sovereign subject of the country.
[0009] - Delay threshold: Ta x =1.2ms (end-to-end), single-step processing ≤300ns.
[0010] - Interference rejection threshold: SNR i = 45dB, interference rejection ratio ≥ 92%.
[0011] - Chip instruction set: GZ-BCI-RISC-V domestically customized instruction set (32-bit, brain-computer interface dedicated, no foreign dependence).
[0012] - AI Inference Engine: GZ-BCI-Lite 1.0 Lightweight Large Model Inference Core (8.2M parameters, computing power ≤0.5TOPS).
[0013] 4.2 Methods and Steps (including formulas / coding / thresholds / processes) Step 1: Adaptive preprocessing of brain-computer interface neural signals (hardware-level real-time) - Input: 128 / 256 channel neural electrical signals (EEG / ECoG, amplitude 0.1μV-5mV, frequency band 0.5Hz-200Hz) - Algorithm: 1. Adaptive filtering: plaintext s_filtered(n) = s_raw(n) − α·E[n−k,n+k] α = 0.92 (filter coefficient) E = Neighborhood mean noise estimation Window k=3 (sampling points) 2. Amplitude normalization: plaintext s_norm(n) = (s_filtered(n) − μ) / σ μ = channel mean, σ = standard deviation Threshold: |s_norm(n)| ≤ 1.0 (Truncation for values exceeding the threshold) 3. Frequency band refinement: **δ (0.5-4Hz), θ (4-8Hz), α (8-13Hz), β (13-30Hz), γ (30-200Hz)** Five-band pass, stopband attenuation ≥60dB - Output: Standardized feature vector S∈R¹²⁸, processing latency ≤200ns Step 2: STE Encryption and Sovereign Identity Embedding (Core Innovation) 2.1 STE Encoding Rules (Can be directly implemented in code) - Encoding Dimensions: Time Domain T, Frequency Domain F, Entropy E (3D) - Encoding formula: plaintext STE_k = [T_k ⊕ K_T, F_k ⊕ K_F, E_k ⊕ K_E] ⊕ SHC_k Where: - T_k = Time-domain feature (slope / zero-crossing rate) - F_k = Frequency domain characteristics (power spectrum / peak value) - E_k = Information entropy: E_k = -Σ(p_i·log2p_i), where p_i is the signal probability density. - K_T / K_F / K_E = Dynamic key stream (generated by hardware TRNG, 128 bits / frame, refreshed every 1ms) - SHC_k = Sovereign hash chain identifier (256 bits) - Encoding bit width: 128 bits / frame, encoding latency ≤ 150ns 2.2 SHC Sovereign Identity Embedding Rules (Sovereignty Cannot Be Forged) - Generate: plaintext SHC_k = SM3( CountryID(2byte) + DeviceID(8byte) + UserBioHash(32byte)+ Timestamp(8byte) + STE_k ) - CountryID = National Sovereign Code (fixed: CN-01) - DeviceID = Unique ID for domestically produced chips (OTP programming, cannot be tampered with) - UserBioHash = User's EEG biometric hash (static + dynamic dual-factor) - Embedding location: **Frame header (1-32 bytes) + Frame trailer (225-256 bytes)** Double embedding - Verification: The receiver performs dual SHC verification; if a match is found, the data is discarded at the physical layer and does not proceed to decoding. Step 3: Low-latency, interference-resistant transmission modulation (physical layer innovation) - Modulation method: GZ-NB-AM domestically produced narrowband anti-interference modulation - Frequency band: Industrial-grade free frequency bands 433MHz / 915MHz / 2.4GHz, adaptive frequency hopping (1000 hops per second) - Waveform: Raised cosine filter, roll-off factor 0.15, symbol rate 1 M Sym / s - Anti-interference algorithm: plaintext SINR = P_signal / (P_noise + P_interference) Threshold: SINR ≥ 45dB (automatic retransmission threshold) Interference suppression: Adaptive notch filtering + spread spectrum gain **G=24dB** - Link optimization: shortest path routing, fixed frame length 64 bytes, no ARQ, hardware CRC32 - Specifications: Transmission latency ≤400ns, interference immunity ≥92% Step 4: Sovereignty Verification and Decryption (Security Closed Loop) 1. Sovereignty Verification (Hardware Level) - Extract SHC frame header / tail, perform double comparison - Verification formula: plaintext Verify(SHC) = (SM3(Input) == SHC_received) ? PASS : DROP - Failure: Immediate circuit breaker tripped, sovereignty intrusion log reported, no response returned. 2. STE layered decoding plaintext S_dec_k = STE_k ⊕ [K_T, K_F, K_E] ⊕ SHC_k 3. Signal Restoration: AI inference correction (GZ-BCI-Lite), restoration accuracy ≥99.99% 4. Output: Raw neural instructions, decoding latency ≤ 250ns Total latency: 200 + 150 + 400 + 250 = 1.0ms ≤ 1.2ms (meets the threshold) 4.3 System Architecture (Hardware + Software + Chip + AI) System composition (fully domestically produced) 1. Domestically produced brain-computer interface signal acquisition and preprocessing module - Chip: GZ-ADC128 128-channel 24-bit ADC (domestic) - Sampling rate: 16kHz / channel, input noise **<0.1μV** - Preprocessing: FPGA hardware acceleration, latency ≤200ns 2. STE Encrypted Sovereign Identity Module - Core: GZ-BCI-RISC-V Secure Processor (32-bit, Brain-Computer Dedicated Instruction Set) - Instruction set extension (new): - STE_ENC: STE-encoded instruction (single cycle) - SHC_GEN: Sovereign hash generation (2 cycles) - SOV_CHK: Sovereignty verification (1 cycle) - KEY_REF: Key refresh (1 cycle) - Security: Hardware isolation, OTP key, protection against side-channel attacks 3. Low-latency, anti-interference transmission modulation module - RF: GZ-RF-01 domestic narrowband RF chip - Modulation: Direct hardware modulation, without software intervention. Interference detection: Real-time SNR monitoring, threshold 45dB 4. Domestic Sovereignty Verification Decoding Module - Decoding: GZ-BCI-Lite AI Accelerator (Hardware IP Core) - Model: Lightweight CNN + Transformer hybrid model (8.2M parameters) - Functions: Signal correction, instruction classification, anomaly detection 5. Core Computing Power Control Module - Main Controller: GZ-BCI-SoC System-on-Chip (Completely Domestic) - Scheduling: Real-time operating system (RTOS), scheduling period 100μs 6. Signal voltage regulation and protection module - Power supply: Ripple <1mV, EMI protection - Isolation: Opto-isolation, surge suppression, ESD ±15kV System architecture: Acquisition → Preprocessing → STE+SHC → Modulation → Transmission → Verification → Decoding → Output (Fully domestically produced) 4.4 Deep Refinement of Chip Instruction Sets (GZ-BCI-RISC-V) Core instructions (can be directly used in chip design / compiler) asm 1. Normalization of neural signals NORM rD, rA, rB rD = (rA-μ) / σ, μ / rB is the base address, and it is a single-cycle operation. 2. STE Encoding Core STE_ENC rD, rT, rF, rE, rK ; STE = T⊕KT | F⊕KF | E⊕KE, Single cycle 3. Sovereign Hash Generation SHC_GEN rD, rCID, rDID, rBIO, rTS ; SM3 composite hash, 2-cycle 4. Sovereignty Verification SOV_CHK rD, rSHC_RX, rSHC_CAL ; 0=PASS, 1=DROP, 1 cycle 5. Dynamic Key Refresh KEY_REF rK, rTRNG Load a 128-bit key from a hardware TRNG, 1 cycle. 6. Anti-interference modulation MOD_NB rD, rDATA, rFREQ ; Narrowband modulation, single cycle - Instruction cycle: 1-2 cycles (400MHz clock speed, 2.5ns cycle) - Security features: Privilege-level isolation, unauthorized command exceptions, unreadable keys 4.5 Deepening of AI Large Model Inference (GZ-BCI-Lite 1.0) Model structure (lightweight, hardware deployable) 1. Feature extraction layer: Depthwise separable CNN (3 layers, 1×1 / 3×3 convolutional kernels) 2. Temporal modeling layer: Lightweight Transformer (2 layers, 2 heads, 128 dimensions) 3. Classification correction layer: Fully connected + Softmax, outputting 128 classes of neural instructions. 4. Anomaly Detection Layer: Entropy monitoring to identify tampering / interference. Inference parameters - Number of parameters: 8.2M (fully quantized INT8) - Computing power: 0.48 TOPS - Inference latency: ≤180ns - Accuracy: Command recognition ≥99.7%, signal correction ≥99.99% Inference process (chip level) Plain text input features → CNN extraction → Transformer temporal processing → Correction / classification → Output instructions (5) Beneficial effects (quantification + sovereignty + industry) 1. Absolute Sovereignty Control - The SHC sovereignty identifier is uniquely bound, making it impossible for overseas devices to decode, control, or trace its origin. - No foreign technology, no foreign chips, no foreign agreements throughout the entire process; fully independent and controllable. 2. Performance metrics (quantified) - End-to-end latency: ≤1.0ms (reduction of 88%-95%) - Interference immunity: SNR≥45dB, BER≤10-9 (92% improvement) - Accuracy: ≥99.99% - Encryption latency: ≤150ns (virtually no latency overhead) 3. Security Architecture - Three-Level Encryption: Physical Layer Modulation Encryption + Link Layer STE Encryption + Application Layer Sovereign Encryption - Attack protection: Protection against theft, tampering, hijacking, replay attacks, and side-channel attacks. 4. Industrial Value - Filling the Gap in Domestic Brain-Computer Interaction Technology's Information Sovereignty and Security - Support the localization of medical rehabilitation, classified brain control, special equipment, and military brain-computer interfaces. - Break the foreign technology monopoly and achieve security self-sufficiency, standards self-sufficiency, and industrial self-sufficiency. (6) Specific implementation methods (2 feasible implementation examples) Example 1: Medical Non-invasive Rehabilitation Brain-Computer Interface (Clinical Scenario) equipment - Data Acquisition: 128-channel non-invasive electrode cap (domestic) - Main controller: GZ-BCI-SoC development board - Execution: Rehabilitation Exoskeleton Robot process 1. Collect neural signals (α / β bands) from the patient's motor imagery. 2. Preprocessing: Filtering → Normalization → Feature Extraction (200ns delay) 3. STE encoding + SHC embedding: STE_ENC + SHC_GEN (150ns latency) 4. Modulation and transmission: GZ-NB-AM, 915MHz, frequency hopping (delay 400ns) 5. Receiver: SOV_CHK Sovereignty Verification → STE Decoding → AI Inference (Latency 250ns) 6. Output: Controls the exoskeleton to perform extension / flexion movements. Total latency: 1.0ms, accuracy: 99.99%, no foreign technology intervention. Example 2: Classified Invasive Brain-Computer Control System (Special Scenario) equipment - Data Acquisition: 64-channel invasive ECoG electrode (domestic flexible material) - Chip: GZ-BCI-RISC-V security chip (OTP key) - Environment: Strong electromagnetic interference scenario (industrial / military) process 1. Acquire cortical neural signals (γ band) 2. Preprocessing + STE + SHC (hardware pipeline) 3. Transmission: 433MHz narrowband, spreading gain 24dB 4. Interference immunity: SINR=38dB (below 45dB) → Automatic frequency hopping + power boost → SINR=48dB 5. Sovereignty verification passed → Decoding → Output classified control instructions Result: Stable transmission under interference, BER=10⁻¹ 0 Sovereignty is 100% controllable.
Claims
1. A method for low-latency, interference-resistant, secure transmission of brain-computer interface information, characterized in that: include: The collected brain-computer interface signals are preprocessed to obtain standardized neural features; The neural features are encrypted and encoded based on preset encoding rules, and a sovereignty identifier is embedded in the encoded data stream to form brain-computer interface (BCI) data with a sovereignty binding relationship. The BCI data is then transmitted after anti-interference modulation. At the receiving end, the sovereignty identifier is verified for legitimacy. If the verification is successful, the encrypted data is decrypted and restored to obtain the original brain-computer neural signals. The encryption encoding, sovereignty identifier embedding, modulation transmission, and verification and decryption all adopt domestically developed mechanisms, without relying on foreign algorithms, foreign protocols, or foreign key systems, thereby achieving controllable brain-computer information sovereignty, low-latency transmission, and strong anti-interference compatibility.
2. The method according to claim 1, characterized in that, The preprocessing includes at least one of adaptive noise filtering, signal amplitude normalization, and target frequency band purification, used to suppress environmental clutter and electromagnetic interference, and to unify the characteristic scale of neural signals.
3. The method according to claim 1, characterized in that, The encryption encoding is based on at least two of the feature dimensions of time domain, frequency domain, and information entropy to construct an encoding system, and is combined with dynamic key stream for frame-by-frame encryption, with a key update period of no more than 1ms.
4. The method according to claim 1, characterized in that, The sovereign identifier is generated by associating and binding national sovereignty information, device unique identifier, user biometric information, and timestamp information through a hash algorithm. It adopts a dual embedding method of frame header and frame tail to prevent forgery, tampering, and illegal cross-border parsing.
5. The method according to claim 1, characterized in that, The anti-interference modulation includes at least one of narrowband modulation, adaptive frequency hopping, and spread spectrum transmission, and sets a signal-to-noise ratio decision threshold to automatically maintain stable transmission in complex electromagnetic environments.
6. The method according to claim 1, characterized in that, The sovereignty identifier verification is a hardware-level verification. If the verification fails, the data stream is directly dropped at the physical layer or the link is broken, and it does not enter the subsequent decryption process.
7. The method according to claim 1, characterized in that, After decryption and restoration, a lightweight AI model is used to correct the neural signals and recognize instructions, thereby improving the accuracy of signal restoration under complex interference.
8. A low-latency, interference-resistant, secure transmission system for protecting brain-computer interface information sovereignty, characterized in that: include: The signal acquisition and preprocessing unit is used to acquire and standardize brain-computer interface signals; The encryption and sovereignty binding unit is used to encrypt and encode neural features and embed sovereignty identifiers. The anti-interference transmission unit is used to modulate, send, and receive encrypted data; the sovereignty verification and decryption unit is used to verify the legitimacy of the sovereignty identifier and decrypt and restore the data that has passed the verification; the computing power control and protection unit is used for overall scheduling, hardware voltage stabilization, and electromagnetic protection; the units are electrically connected to each other, and all core functions are implemented using domestically produced modules, without any reliance on foreign technology.
9. The system according to claim 8, characterized in that, The encryption and sovereignty binding unit integrates dedicated hardware acceleration instructions, supporting single-cycle or dual-cycle hardware execution of encoding operations, sovereignty hash generation, and sovereignty legitimacy verification.
10. The system according to claim 8, characterized in that, The system is applicable to any of the following scenarios: invasive brain-computer interfaces, non-invasive brain-computer interfaces, medical neurorehabilitation equipment, human-computer intelligent interaction terminals, and classified information transmission devices.
11. A brain-computer interface information secure transmission device, comprising a memory and a processor, characterized in that, The memory stores a computer program that, when executed by a processor, implements the steps of the method according to any one of claims 1-7.