A semiconductor device, a manufacturing method thereof, and an electronic apparatus

Abstract

A semiconductor device and a manufacturing method thereof, and an electronic device, the manufacturing method comprising: providing a semiconductor substrate, the semiconductor substrate having a fin structure formed thereon, the fin structure comprising first semiconductor material layers and second semiconductor material layers which are alternately stacked; forming a dummy gate structure across the fin structure; forming a first sacrificial layer covering the dummy gate structure and the fin structure; etching the fin structure to expose a first surface thereof; etching an end portion of the first semiconductor material layers to form an inner spacer recess; forming a second sacrificial layer in the inner spacer recess; removing the dummy gate structure to form a gate recess, the gate recess exposing a second surface of the fin structure; removing the first semiconductor material layers through the second surface; forming a metal gate structure surrounding the second semiconductor material layers; and removing the first sacrificial layer and the second sacrificial layer to form an inner spacer air gap. The inner spacer air gap can reduce the parasitic capacitance of the semiconductor device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically to a semiconductor device and its manufacturing method, and an electronic device. Background Technology

[0002] As logic devices have evolved, transistor structures have transformed from three-dimensional transistors to multi-channel field-effect transistors (FETs). In a multi-channel FET structure, the inner spacer is located around the channel region to isolate the gate from the channel and optimize the transistor's electrical performance.

[0003] As device dimensions shrink, the parasitic capacitance of transistors increases accordingly, while the inner spacer region can reduce the gate-to-source-drain parasitic capacitance. The k-value of the material in the inner spacer region plays a crucial role in the device's parasitic capacitance. Air has the smallest k-value, but the complex fabrication and manufacturing processes of multi-channel field-effect transistors make it extremely difficult to fabricate the air gap inner spacer structure. Summary of the Invention

[0004] The summary section introduces a series of simplified concepts, which will be further explained in detail in the detailed description section. The summary section of this invention is not intended to limit the key features and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0005] To address the existing problems, one embodiment of the present invention provides a method for manufacturing a semiconductor device, comprising:

[0006] A semiconductor substrate is provided, on which a fin structure extending along a first direction is formed, the fin structure comprising alternating layers of a first semiconductor material and a second semiconductor material;

[0007] A pseudo-gate structure is formed across the fin structure, the pseudo-gate structure extending along a second direction;

[0008] A first sacrificial layer is formed covering the pseudo-gate structure and the fin structure exposed by the pseudo-gate structure;

[0009] Gate sidewalls are formed on the first sacrificial layers on both sides of the dummy gate structure;

[0010] The fin structure is etched using the gate sidewall as a mask to expose the first surface of the fin structure perpendicular to the first direction;

[0011] The end of the first semiconductor material layer exposed on the first surface is etched to form an inner spacer groove;

[0012] A second sacrificial layer is formed in the inner spacer groove;

[0013] An interlayer dielectric layer is formed between adjacent pseudo-gate structures;

[0014] The dummy gate structure is removed to form a gate recess, which exposes the second surface of the fin structure perpendicular to the second direction;

[0015] The first semiconductor material layer is removed by the second surface to obtain a plurality of second semiconductor material layers arranged at intervals;

[0016] A metal gate structure surrounding the second semiconductor material layer is formed in the gate recess;

[0017] The first sacrificial layer is removed to form a gap between the gate sidewall and the metal gate structure, and the second sacrificial layer is removed through the gap to form an inner spacer air gap.

[0018] In one embodiment, after forming the fin structure and before forming the pseudo-gate structure, the method further includes:

[0019] A third sacrificial layer is formed covering the fin structure;

[0020] The method further includes removing the third sacrificial layer through the gap.

[0021] In one embodiment, after removing the dummy gate structure to form a gate trench and before removing the first semiconductor material layer through the gate trench, the method further includes:

[0022] Remove the third sacrificial layer exposed by the gate recess.

[0023] In one embodiment, after forming the inner spacer air gap, the method further includes:

[0024] A medium-filled layer is formed in the gap.

[0025] In one embodiment, forming a dielectric filling layer in the gap includes:

[0026] Deposit a dielectric material to fill the gaps;

[0027] A planarization process is performed to remove the dielectric material outside the gap to form the dielectric filling layer.

[0028] In one embodiment, depositing a dielectric material to fill the gap includes: depositing the dielectric material to fill the gap using a low conformality thin film deposition process, a directional thin film deposition process, or a thin film deposition process with pinch-off characteristics.

[0029] In one embodiment, forming a second sacrificial layer in the inner spacer groove includes:

[0030] A second sacrificial layer is formed covering the first surface of the pseudo-gate structure and the fin structure, and the second sacrificial layer fills the inner spacer groove;

[0031] Remove the second sacrificial layer outside the inner spacer groove.

[0032] In one embodiment, etching the fin structure using the gate sidewall as a mask to expose a first surface of the fin structure perpendicular to the first direction includes:

[0033] The fin structure is etched using the gate sidewall as a mask to form source-drain grooves between adjacent pseudo-gate structures, the source-drain grooves exposing the first surface of the fin structure;

[0034] After forming the second sacrificial layer and before forming the interlayer dielectric layer, the method further includes forming an epitaxial source-drain structure in the source-drain groove.

[0035] A second aspect of the present invention provides a semiconductor device, which is manufactured using the method described above.

[0036] A third aspect of the present invention provides an electronic device, the electronic device comprising the semiconductor device described above.

[0037] According to the semiconductor device and its manufacturing method and electronic device provided by the present invention, a second sacrificial layer is formed at the end of a first semiconductor material layer, and a longitudinally extending first sacrificial layer is formed connected to the second sacrificial layer. After forming a metal gate structure, the second sacrificial layer is removed by removing the gap formed by the first sacrificial layer, thereby forming an internal spacer air gap between the second semiconductor material layers, which can reduce the parasitic capacitance of the semiconductor device and improve the performance of the semiconductor device. Attached Figure Description

[0038] The following drawings, which are incorporated herein by reference as part of this invention, are provided for understanding the invention. The drawings illustrate embodiments of the invention and their descriptions, serving to explain the principles of the invention.

[0039] In the attached image:

[0040] Figure 1 A schematic flowchart illustrating a method for manufacturing a semiconductor device according to a specific embodiment of the present invention is shown.

[0041] Figures 2A to 19B A schematic cross-sectional view of a semiconductor device obtained by sequentially performing each step of a method for manufacturing a semiconductor device according to an embodiment of the present invention is shown. Detailed Implementation

[0042] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention can be practiced without one or more of these details. In other instances, certain technical features well-known in the art have not been described in order to avoid obscuring the invention.

[0043] It should be understood that the invention can be embodied in various forms and should not be construed as being limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated. The same reference numerals denote the same elements throughout.

[0044] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this invention, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.

[0045] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0046] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0047] In view of the aforementioned technical problems, embodiments of the present invention propose a method for fabricating a semiconductor device. The following refers to... Figure 1 and Figures 2A to 19B The method for fabricating the semiconductor device according to embodiments of the present invention will be described in detail, wherein, Figure 1 A schematic flowchart illustrating a method for manufacturing a semiconductor device according to a specific embodiment of the present invention is shown. Figures 2A to 19B A schematic cross-sectional view of a semiconductor device obtained by sequentially performing the steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention is shown. Figure 2A , Figures 3A to 19A A cross-sectional view of the semiconductor device along the BB direction is shown. Figure 2B , Figures 3B to 19B A cross-sectional view of the semiconductor device along the AA direction is shown. Figure 8C , Figure 9C , Figure 10C and Figure 17C A cross-sectional view of the semiconductor device along the CC direction is shown.

[0048] First, execute step S101, as follows: Figure 2A , Figure 2B As shown, a semiconductor substrate 201 is provided, on which a fin structure 202 extending along a first direction is formed. The fin structure 202 includes alternating layers of first semiconductor material 2021 and second semiconductor material 2022.

[0049] The semiconductor substrate 201 is made of at least one of the following materials: silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbide (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), or other III / V compound semiconductors, or silicon on dielectric (SOI), silicon on dielectric (SSOI), silicon germanium on dielectric (S-SiGeOI), silicon germanium on dielectric (SiGeOI), and germanium on dielectric (GeOI).

[0050] Next, alternating layers of a first semiconductor material 2021 and a second semiconductor material 2022 are formed on the semiconductor substrate 201. Figure 2A and Figure 2B In the example, three alternating layers of first semiconductor material 2021 and three alternating layers of second semiconductor material 2022 are formed on the semiconductor substrate 200, but Figure 2A and Figure 2B The number of first semiconductor material layer 2021 and second semiconductor material layer 2022 shown is for illustrative purposes only and is not a limitation. The thickness of the first semiconductor material layer 2021 and the second semiconductor material layer 2022 may be equal or may be determined by those skilled in the art as appropriate, and is not limited herein.

[0051] In some embodiments, the first semiconductor material layer 2021 is made of germanium-silicon, and the second semiconductor material layer 2022 is made of silicon. The alternating layers of the first semiconductor material layer 2021 and the second semiconductor material layer 2022 can be formed by an epitaxial growth process.

[0052] Next, the first semiconductor material layer 2021, the second semiconductor material layer 2022, and the semiconductor substrate 200 are etched to form a fin structure 202 extending along a first direction. Exemplarily, a hard mask layer is first formed on the second semiconductor material layer 2022; the hard mask layer is patterned to form multiple discrete hard mask patterns for forming the fins. In one embodiment, a self-aligned dual-patterning process can be used to perform the patterning process; finally, the first semiconductor material layer 2021, the second semiconductor material layer 2022, and the semiconductor substrate 201 are etched under the mask of the hard mask layer to form multiple discrete fin structures 202 thereon.

[0053] Next, an isolation structure 203 is formed between the fin structures 202. The material of the isolation structure 203 includes insulating materials such as silicon oxide and silicon nitride, or combinations thereof. The insulating material can be deposited by processes such as high-density plasma chemical vapor deposition (HDP-CVD) and flowable chemical vapor deposition (FCVD), and the height of the insulating material can be reduced by chemical mechanical polishing and etch-back processes to form the isolation structure 203.

[0054] For example, such as Figure 3A , Figure 3B As shown, after the fin structure 202 is formed, a third sacrificial layer 204 is formed to cover the fin structure 202.

[0055] The third sacrificial layer 204 covers the fin structure and the isolation structure 203 between adjacent fin structures. The material of the third sacrificial layer 204 includes at least one of the following: silicon nitride (SiN), silicon oxide (SiO and / or SiO2), silicon carbide (SiC), carbon-containing silicon nitride (SiCN), carbon-containing silicon oxide (SiOC), oxygen-containing silicon nitride (SiON), silicon, carbon and oxygen-doped silicon nitride (SiOCN), low-k dielectric material, tetraethyl orthosilicate (TEOS), doped silicon oxide (e.g., borosilicate glass (BPSG), fluorine-doped silicate glass (FSG), phosphosilicate glass (PSG), boron-doped silicate glass (BSG)).

[0056] Next, proceed to step S102, as follows: Figure 4A , Figure 4B As shown, a pseudo-gate structure is formed across the fin structure 202, and the pseudo-gate structure extends along a second direction. Exemplarily, the second direction is perpendicular to the first direction.

[0057] Specifically, the dummy gate structure includes a dummy gate 205 and a dummy gate hard mask layer 206 above the dummy gate. The constituent material of the dummy gate 205 may include amorphous silicon, polycrystalline silicon, etc. The constituent material of the dummy gate 205 can be formed by deposition processes such as physical vapor deposition (PVD), chemical vapor deposition (CVD), sputtering deposition, etc. Subsequently, the dummy gate hard mask layer 206 can be formed on the dummy gate 205, and the dummy gate hard mask layer 206 includes a silicon nitride layer, a silicon oxide layer, or a stack of both. Next, the dummy gate hard mask layer 206 and the dummy gate 205 are etched to form a dummy gate structure spanning the fin structure 202. Exemplarily, a patterned photoresist layer can be formed above the dummy gate hard mask layer 206, and the dummy gate 205 can be etched sequentially using the photoresist layer as a mask to form a dummy gate structure spanning the fin structure 202.

[0058] It is understandable that, since the fin structure 202 is covered with a third sacrificial layer 204, a third sacrificial layer 204 is formed between the pseudo-gate structure and the fin structure 202 after the pseudo-gate structure is formed.

[0059] Next, proceed to step S103, as follows: Figure 5A , Figure 5B As shown, a first sacrificial layer 207 is formed to cover the pseudo-gate structure and the fin structure 202 exposed by the pseudo-gate structure.

[0060] Exemplarily, the material of the first sacrificial layer 207 includes at least one of the following: silicon nitride (SiN), silicon oxide (SiO and / or SiO2), silicon carbide (SiC), carbon-containing silicon nitride (SiCN), carbon-containing silicon oxide (SiOC), oxygen-containing silicon nitride (SiON), silicon, carbon, and oxygen-doped silicon nitride (SiOCN), low-k dielectric material, tetraethyl orthosilicate (TEOS), and doped silicon oxide (e.g., borosilicate glass (BPSG), fluorine-doped silicate glass (FSG), phosphosilicate glass (PSG), boron-doped silicate glass (BSG)). The material of the first sacrificial layer 207 may be the same as or different from the material of the third sacrificial layer 204. The first sacrificial layer 207 covers the dummy gate structure and the third sacrificial layer 204 on the fin structure 202 between the dummy gate structures.

[0061] Next, proceed to step S104, as follows: Figure 6A , Figure 6B As shown, gate sidewalls 208 are formed on the first sacrificial layer 207 on both sides of the pseudo-gate structure.

[0062] Specifically, first, a sidewall material layer covering the dummy gate structure is deposited; then, the sidewall material layer is etched back until the dummy gate hard mask layer 206 is exposed, thereby forming the gate sidewall 208. Exemplarily, the sidewall material layer can be deposited using atomic layer deposition, and the sidewall material layer includes, but is not limited to, a silicon nitride layer.

[0063] Next, proceed to step S105, as follows: Figure 7A , Figure 7B As shown, the fin structure 202 is etched using the gate sidewall 208 as a mask to expose the first surface of the fin structure 202 perpendicular to the first direction.

[0064] Specifically, etching is performed using the gate sidewall 208 and the dummy gate hard mask layer 206 as masks to form source / drain trenches in the fin structures 202 on both sides of the gate sidewall 208. Exemplarily, dry etching and wet etching processes are performed sequentially to form the source / drain trenches. First, using the gate sidewall 208 as a mask, an anisotropic dry etching process is used to form a bowl-shaped trench in the fin structure 202. Next, a wet etching process is used to etch the bowl-shaped trench. Taking advantage of the different etching rates of the etchant in wet etching on different crystal orientations of the constituent material of the fin structure 202, the bowl-shaped trench is extended through etching to form a Σ-shaped trench.

[0065] Next, proceed to step S106, as follows: Figure 8A , Figure 8B and Figure 8C As shown, the first surface of the fin structure 202 is etched to expose the end of the first semiconductor material layer 2021 to form an inner spacer groove.

[0066] The first semiconductor material layer 2021 can be etched using selective dry or wet etching processes to form inner spacer trenches at its ends. These inner spacer trenches are used to subsequently form an inner spacer air gap, which isolates the gate from the channel and optimizes the transistor's electrical performance. For example... Figure 8C As shown, a first sacrificial layer 207 and a third sacrificial layer 204 are formed below the gate sidewall 208, so the inner spacer groove is surrounded by the first sacrificial layer 207 and the third sacrificial layer 204 on both sides.

[0067] Next, step S107 is performed to form a second sacrificial layer 209 in the inner spacer groove.

[0068] Specifically, firstly, as Figure 9A , Figure 9B and Figure 9C As shown, a second sacrificial layer 209 is formed on the first surface covering the pseudo-gate structure and the fin structure 202, and the second sacrificial layer 209 fills the inner spacer groove; then, as Figure 10A , Figure 10B and Figure 10C As shown, the second sacrificial layer 209 outside the inner spacer groove is removed.

[0069] Exemplarily, the material of the second sacrificial layer 209 includes at least one of the following: silicon nitride (SiN), silicon oxide (SiO and / or SiO2), silicon carbide (SiC), carbon-containing silicon nitride (SiCN), carbon-containing silicon oxide (SiOC), oxygen-containing silicon nitride (SiON), silicon, carbon, and oxygen-doped silicon nitride (SiOCN), low-k dielectric materials, tetraethyl orthosilicate (TEOS), and doped silicon oxide (e.g., borosilicate glass (BPSG), fluorine-doped silicate glass (FSG), phosphosilicate glass (PSG), boron-doped silicate glass (BSG)). The material of the second sacrificial layer 209 may be the same as or different from the materials of the first sacrificial layer 207 and the third sacrificial layer 204.

[0070] like Figure 9C and Figure 10C As shown, since the inner spacer groove is surrounded by the first sacrificial layer 207 and the third sacrificial layer 204 on both sides, after the second sacrificial layer 209 is formed, the second sacrificial layer is connected to the third sacrificial layer 204 on both sides, and then the first sacrificial layer 207 is connected through the third sacrificial layer 204.

[0071] Next, as Figure 11A , Figure 11BAs shown, an epitaxial source / drain structure 210 is formed in the source / drain grooves on both sides of the dummy gate structure. Specifically, a stress layer can be grown in the source / drain grooves using selective epitaxial growth, and the stress layer can be doped to form the epitaxial source / drain structure 210. Selective epitaxial growth can be performed using one of low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), ultra-high vacuum chemical vapor deposition (UHVCVD), rapid thermal chemical vapor deposition (RTCVD), and molecular beam epitaxy (MBE). In P-type transistor devices, the stress layer has compressive stress, and its material includes, but is not limited to, SiGe. In N-type transistor devices, the stress layer has tensile stress, and its material includes SiP, SiC, or other suitable materials that can provide tensile stress. After forming the epitaxial source / drain structure 210, a second sacrificial layer 209 is filled between the first semiconductor material layer 2021 and the epitaxial source / drain structure 210.

[0072] Next, proceed to step S108, as follows: Figure 12A , Figure 12B As shown, an interlayer dielectric layer 211 is formed between adjacent dummy gate structures. The material of the interlayer dielectric layer 211 includes, but is not limited to, one or more of SiC, SiOC, SiO2, SiCN, SiOCH, SiC, SiN, and SiON. The interlayer dielectric layer 211 can be formed using chemical vapor deposition methods, such as plasma-assisted chemical vapor deposition (PECVD) or high-density plasma-assisted chemical vapor deposition (HDP-CVD). Exemplarily, after depositing the material of the interlayer dielectric layer 211, a chemical mechanical polishing (CMP) process is performed until the dummy gate 205 is exposed.

[0073] Next, step S109 is performed to remove the dummy gate structure to form a gate recess, which exposes the second surface of the fin structure 202 perpendicular to the second direction.

[0074] Among them, firstly, as Figure 13A , Figure 13B As shown, the dummy gate 205 is removed to obtain the gate recess. Figure 13A As shown, the bottom of the gate trench exposes the third sacrificial layer 204, and the sides of the gate trench expose the first sacrificial layer 207. The dummy gate 205 can be removed using either dry etching or wet etching processes. In one embodiment, a TMAH solution with high material selectivity for the dummy gate 205 can be used to remove it.

[0075] Next, as Figure 14A , Figure 14BAs shown, the third sacrificial layer 204 exposed at the bottom of the gate recess is removed, exposing the fin structure 202 beneath the third sacrificial layer 204. After etching away the third sacrificial layer 204 covering the fin structure 202, the second surface of the fin structure 202 perpendicular to the second direction is exposed. This ensures that the first semiconductor material layer 2021 can be removed and the second semiconductor material layer 2022 can be released through the exposed second surface of the fin structure 202, and that the subsequent metal gate process can proceed smoothly. For example, the third sacrificial layer 204 can be removed using a dry etching process, including free radical etching, ion beam etching, etc.

[0076] Next, proceed with step S110, as follows: Figure 15A , Figure 15B As shown, the first semiconductor material layer 2021 is removed through the second surface of the fin structure 202 to obtain a plurality of second semiconductor material layers 2022 arranged at intervals.

[0077] The method for removing the first semiconductor material layer 2021 is selective wet etching or selective dry etching. In one embodiment, selective wet etching is used to remove the first semiconductor material layer 2021. A suitable etching solution can be selected to achieve a high etching selectivity between the first semiconductor material layer 2021 and the second semiconductor material layer 2022, thereby reducing damage to the second semiconductor material layer 2022 during the removal of the first semiconductor material layer 2021. After the first semiconductor material layer 2021 is removed, the second semiconductor material layer 2022 is released and suspended, forming a nanosheet structure stacked vertically, and supported by the epitaxial source / drain structure 210 on both sides of the nanosheet structure.

[0078] Next, proceed with step S111, as follows: Figure 16A , Figure 16B As shown, a metal gate structure surrounding a second semiconductor material layer is formed in the gate recess.

[0079] Exemplarily, the metal gate structure includes at least a gate dielectric layer 212 and a metal gate 213. The gate dielectric layer 212 can be a high-k dielectric layer, where the k-value (dielectric constant) is typically 3.9 or higher. Its constituent materials include hafnium oxide, hafnium silicon oxide, hafnium oxynitride, lanthanum oxide, zirconium oxide, zirconium silicon oxide, titanium oxide, aluminum oxide, etc., and exemplarily, hafnium oxide, zirconium oxide, or aluminum oxide can be used. The gate dielectric layer 212 can be formed using suitable processes such as CVD, ALD, or PVD.

[0080] Exemplarily, after forming the gate dielectric layer 212, a capping work function layer and a diffusion barrier layer may also be formed covering the gate dielectric layer 212. The work function layer is used to adjust the work function of the device. The diffusion barrier layer is used to prevent metal (e.g., Ti) in the work function layer from diffusing into the gate dielectric layer.

[0081] Next, a metal gate 213 is formed to fill the gate trench. The material of the metal gate includes, but is not limited to, Al, W, or other suitable metal material layers. The metal gate material layer can be deposited using atomic layer deposition, physical vapor deposition, or chemical vapor deposition processes, and then a planarization process is performed to planarize the device surface until the interlayer dielectric layer 211 is exposed, thereby removing the metal gate 213 outside the gate trench. The planarization process includes chemical mechanical polishing.

[0082] Next, proceed to step S112, as follows: Figure 17A , Figure 17B , Figure 17C As shown, the first sacrificial layer 207 is removed to form a gap between the gate sidewall 208 and the metal gate structure; and the second sacrificial layer 209 is removed through the gap to form an inner spacer air gap.

[0083] Specifically, the first sacrificial layer 207 is located between the gate dielectric layer 212 and the interlayer dielectric layer 211. The etchant (etching liquid or etching gas) can start from the upper surface of the first sacrificial layer 207 and react with the first sacrificial layer 207 from top to bottom, thereby removing the first sacrificial layer 207 and forming a gap between the gate sidewall 208 and the metal gate structure.

[0084] Reference Figure 10C and Figure 17C The first sacrificial layer 207 connects to the third sacrificial layer 204 located below the gate sidewall 208. Therefore, after etching away the first sacrificial layer 207, the etchant can remove the lower third sacrificial layer 204 by removing the gap formed by the first sacrificial layer 207, and then remove the second sacrificial layer 209 connected to the third sacrificial layer 204. Thus, the first sacrificial layer 207 and the third sacrificial layer 204 form a pathway for the etchant, allowing the etchant to remove the second sacrificial layer 209 filling the space between the metal gate structure and the epitaxial source / drain structure 210, thereby forming an inner spacer air gap. Furthermore, the inner spacer air gap is formed after the metal gate process and does not affect the normal execution of the epitaxial source / drain process and the metal gate process. Thanks to the lowest k value of air (1), the parasitic capacitance of the semiconductor device is significantly reduced, improving the performance of the semiconductor device.

[0085] For example, selective etching is used for the etching of the first sacrificial layer 207, the second sacrificial layer 209, and the third sacrificial layer 204. The etchant has a high etch selectivity for the first sacrificial layer 207, the second sacrificial layer 209, and the third sacrificial layer 204, as well as the metal gate structures and gate sidewalls 208 on both sides. This ensures that the removal of the first sacrificial layer 207, the second sacrificial layer 209, and the third sacrificial layer 204 does not damage other device structures on both sides. For example, selective etching techniques include, but are not limited to, free radical etching techniques.

[0086] Next, as Figure 18A , Figure 18B As shown, dielectric material 214 is filled in the gap between the gate sidewall and the metal gate structure. The dielectric material 214 can be a low-k dielectric material to avoid affecting the k-value of the gate dielectric layer of the metal gate structure. Exemplarily, a low-conformity thin-film deposition process, a directional thin-film deposition process, or a thin-film deposition process with pinch-off characteristics can be used, such that the dielectric material 214 fills the gap left after removing the first sacrificial layer 207, but not the inner spacer air gap left after removing the second sacrificial layer 209.

[0087] Next, as Figure 19A , Figure 19B As shown, a chemical mechanical polishing process is performed to remove excess dielectric material 214 above the metal grid structure.

[0088] For example, after performing the chemical mechanical polishing process, an interconnect process can be performed, such as forming contact holes above the metal gate structure and the interlayer dielectric layer 211.

[0089] Thus, the process steps of the semiconductor device manufacturing method according to the first aspect embodiment of the present invention are completed. It is understood that the semiconductor device manufacturing method of this embodiment includes not only the above steps, but may also include other necessary steps before, during or after the above steps, all of which are included within the scope of the manufacturing method of this embodiment.

[0090] According to the semiconductor device manufacturing method provided in the embodiments of the present invention, a second sacrificial layer is formed at the end of a first semiconductor material layer, and a longitudinally extending first sacrificial layer is formed connected to the second sacrificial layer. After forming a metal gate structure, the second sacrificial layer is removed by removing the gap formed by the first sacrificial layer, thereby forming an internal spacer air gap between the second semiconductor material layers, which can reduce the parasitic capacitance of the semiconductor device and improve the performance of the semiconductor device.

[0091] This invention also provides a semiconductor device that can be prepared by the methods described in the foregoing embodiments.

[0092] Below, for reference Figure 19A , Figure 19B The semiconductor device of the present invention will be described in detail. It is worth mentioning that, in order to avoid repetition, only a brief description will be given for the same components and structures as in the foregoing embodiments. For a detailed explanation and description, please refer to the description in Embodiment 1.

[0093] Specifically, such as Figure 19A , Figure 19B As shown, the semiconductor device of this embodiment includes: a semiconductor substrate 201, on which a fin structure 202 extending along a first direction is formed, the fin structure 202 including multiple layers of second semiconductor material 2022 arranged longitudinally at intervals; a metal gate structure spanning the fin structure 202, the metal gate structure extending along a second direction and surrounding the second semiconductor material layers 2022; an internally spaced air gap located between two adjacent layers of second semiconductor material 2022 and at both ends of the metal gate structure along the first direction; an interlayer dielectric layer 211 filling the space between the metal gate structures; a gate sidewall 208 located between the metal gate structure and the interlayer dielectric layer 211; and a dielectric material 214 located between the metal gate structure and the gate sidewall 208.

[0094] For example, the metal gate structure includes a gate dielectric layer 212 and a metal gate 213, with the gate dielectric layer 212 formed on the sidewalls and bottom of the metal gate 213; and a dielectric filling layer 214 formed between the gate dielectric layer 212 and the gate sidewall 208.

[0095] For example, epitaxial source / drain structures 210 are formed on both sides of the metal gate structure, and the epitaxial source / drain structures 210 are formed at both ends of the second semiconductor material layer 2022. An internal spacer air gap is formed vertically between the two second semiconductor material layers 2022 and horizontally between the metal gate structure and the epitaxial source / drain structures 210.

[0096] The semiconductor device of this invention has an internal air gap formed between the second semiconductor material layers, which can reduce the parasitic capacitance of the semiconductor device and improve the performance of the semiconductor device.

[0097] A third aspect of the present invention also provides an electronic device including the aforementioned semiconductor device, which is prepared according to the aforementioned method.

[0098] The electronic device in this embodiment can be any electronic product or device such as a mobile phone, tablet computer, laptop computer, netbook, game console, television, VCD player, DVD player, navigator, digital photo frame, camera, camcorder, voice recorder, MP3 player, MP4 player, PSP, etc., or any intermediate product including circuitry. The electronic device in this embodiment of the invention, due to the use of the aforementioned semiconductor devices, has better performance.

[0099] The present invention has been described through the above embodiments. However, it should be understood that the above embodiments are for illustrative purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, those skilled in the art will understand that the present invention is not limited to the above embodiments, and many more variations and modifications can be made based on the teachings of the present invention, all of which fall within the scope of protection claimed by the present invention. The scope of protection of the present invention is defined by the appended claims and their equivalents.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, The manufacturing method includes: A semiconductor substrate is provided, on which a fin structure extending along a first direction is formed, the fin structure comprising alternating layers of a first semiconductor material and a second semiconductor material; A pseudo-gate structure is formed across the fin structure, the pseudo-gate structure extending along a second direction; A first sacrificial layer is formed covering the pseudo-gate structure and the fin structure exposed by the pseudo-gate structure; Gate sidewalls are formed on the first sacrificial layers on both sides of the dummy gate structure; The fin structure is etched using the gate sidewall as a mask to expose the first surface of the fin structure perpendicular to the first direction; The end of the first semiconductor material layer exposed on the first surface is etched to form an inner spacer groove; A second sacrificial layer is formed in the inner spacer groove; An interlayer dielectric layer is formed between adjacent pseudo-gate structures; The dummy gate structure is removed to form a gate recess, which exposes the second surface of the fin structure perpendicular to the second direction; The first semiconductor material layer is removed by the second surface to obtain a plurality of second semiconductor material layers arranged at intervals; A metal gate structure surrounding the second semiconductor material layer is formed in the gate recess; The first sacrificial layer is removed to form a gap between the gate sidewall and the metal gate structure, and the second sacrificial layer is removed through the gap to form an inner spacer air gap.

2. The manufacturing method as described in claim 1, characterized in that, After forming the fin structure and before forming the pseudo-gate structure, the method further includes: A third sacrificial layer is formed covering the fin structure; The method further includes removing the third sacrificial layer through the gap.

3. The manufacturing method as described in claim 2, characterized in that, After removing the dummy gate structure to form a gate trench and before removing the first semiconductor material layer through the gate trench, the method further includes: Remove the third sacrificial layer exposed by the gate recess.

4. The manufacturing method as described in claim 1, characterized in that, After forming the inner spacer air gap, the method further includes: A medium-filled layer is formed in the gap.

5. The manufacturing method as described in claim 4, characterized in that, The process of forming a dielectric filling layer in the gap includes: Deposit a dielectric material to fill the gaps; A planarization process is performed to remove the dielectric material outside the gap to form the dielectric filling layer.

6. The manufacturing method as described in claim 5, characterized in that, The dielectric material for filling the gap is deposited using a low conformity thin film deposition process, a directional thin film deposition process, or a thin film deposition process with pinch-off characteristics.

7. The manufacturing method as described in claim 1, characterized in that, The formation of the second sacrificial layer in the inner spacer groove includes: A second sacrificial layer is formed covering the first surface of the pseudo-gate structure and the fin structure, and the second sacrificial layer fills the inner spacer groove; Remove the second sacrificial layer outside the inner spacer groove.

8. The manufacturing method as described in claim 1, characterized in that, The etching of the fin structure using the gate sidewall as a mask to expose the first surface of the fin structure perpendicular to the first direction includes: The fin structure is etched using the gate sidewall as a mask to form source-drain grooves between adjacent pseudo-gate structures, the source-drain grooves exposing the first surface of the fin structure; After forming the second sacrificial layer and before forming the interlayer dielectric layer, the method further includes forming an epitaxial source-drain structure in the source-drain groove.

9. A semiconductor device, characterized in that, The semiconductor device is manufactured using the method described in any one of claims 1-8.

10. An electronic device, characterized in that, The electronic device includes the semiconductor device as described in claim 9.

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