Chip high-precision timing method, device, medium and program product

Abstract

This invention discloses a high-precision timing method, device, medium, and program product for chips, relating to the field of timing. The high-precision timing method for chips includes: creating a desired timer and a global timer on the current chip; performing start offset compensation on the global timer of the current chip based on a cold reset signal and a start compensation value, and performing periodic frequency offset compensation on the global timer of the current chip according to the period difference between the desired timer and the global timer; and aligning the compensated global timer across clock domains using Gray code cross-clock synchronization. The technical solution of this invention can improve the timing accuracy of the global timer on the chip.

Description

Technical Field

[0001] This invention relates to the field of timing technology, and in particular to a high-precision timing method, device, medium, and program product for chips. Background Technology

[0002] Global timers in a chip, if enabled through initialization configuration, will introduce timing errors due to inconsistent delays in the configuration path. If they rely on a reset signal for release or a clock signal for startup, timing errors will also be introduced due to physical wiring errors. If the chip supports partial resets, and the corresponding local timer also resets, the global timers will not maintain good consistency. Furthermore, the cross-clock design method of the chip's actual digital circuitry will itself introduce errors.

[0003] Secondly, even if the same reference clock is used on the die in the chip, the timer clock generated after passing through the phase-locked loop will still have frequency offset due to the non-ideal nature of the phase detector on the phase-locked loop on different dies, the nonlinearity of the voltage-controlled oscillator and process deviation, different temperature and power supply noise, and the path delay of the reference clock.

[0004] Since error factors and frequency offset can both affect the timing accuracy of the global timer in the chip, achieving high-precision timing of the global timer and further effectively eliminating the influence of frequency offset and timing error has become a technical challenge that urgently needs to be solved. Summary of the Invention

[0005] This invention provides a high-precision timing method, device, medium, and program product for chips to solve the problem of poor timing accuracy of existing global timers on chips.

[0006] According to one aspect of the present invention, a high-precision timing method for a chip is provided, comprising: Create the desired timer and global timer in the current chip; Based on the cold reset signal and the start compensation value, start offset compensation is performed on the global timer of the current chip, and periodic frequency offset compensation is performed on the global timer of the current chip according to the period difference between the expected timer and the global timer. The compensated global timer is aligned across clock domains using Gray code cross-clock synchronization.

[0007] According to another aspect of the present invention, a high-precision timing device for a chip is provided, comprising: The timer creation module is used to create desired timers and global timers in the current chip. The timing compensation module is used to perform start offset compensation on the current chip's global timer based on the cold reset signal and the start compensation value, and to perform periodic frequency offset compensation on the current chip's global timer based on the period difference between the desired timer and the global timer. The clock alignment module is used to perform cross-clock domain alignment of the compensated global timer using Gray code cross-clock synchronization.

[0008] According to another aspect of the present invention, an electronic device is provided, the electronic device comprising: At least one processor; and a memory communicatively connected to said at least one processor; The memory stores a computer program that can be executed by the at least one processor, and the computer program is executed by the at least one processor to enable the at least one processor to execute the high-precision timing method for chips according to any embodiment of the present invention.

[0009] According to another aspect of the present invention, a computer-readable storage medium is provided, the computer-readable storage medium storing computer instructions for causing a processor to execute and implement the high-precision timing method for chips according to any embodiment of the present invention.

[0010] According to another aspect of the present invention, a computer program product is provided, the computer program product comprising a computer program that, when executed by a processor, implements the high-precision chip timing method according to any embodiment of the present invention.

[0011] The technical solution of this invention creates a desired timer and a global timer on the current chip. Based on a cold reset signal and a start-up compensation value, it compensates for the start-up offset of the global timer on the current chip. Furthermore, based on the period difference between the desired timer and the global timer, it compensates for the periodic frequency offset of the global timer on the current chip. Finally, it uses Gray code cross-clock synchronization to align the compensated global timer across clock domains. This solution performs fine-grained start-up offset compensation on the global timer in the chip in one step, based on the cold reset signal and the start-up compensation value, unaffected by partial or full-function resets. It also compensates for the periodic frequency offset of the global timer based on the period difference to reduce timing errors caused by frequency offset. The cross-clock domain alignment of the compensated global timer using Gray code cross-clock synchronization ensures that the error introduced by the cross-clock design method remains close to the theoretical optimal value under any conditions. This solves the problem of poor timing accuracy of global timers on existing chips and improves the timing accuracy of global timers on chips.

[0012] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0013] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0014] Figure 1 This is a flowchart of a high-precision chip timing method provided in Embodiment 1 of the present invention; Figure 2 This is a flowchart of a high-precision chip timing method provided in Embodiment 2 of the present invention; Figure 3 A schematic diagram illustrating key steps of high-precision timing within a single die, as provided in Embodiment 2 of the present invention; Figure 4 A schematic diagram of a high-precision timing control structure for a chip provided in Embodiment 2 of the present invention; Figure 5 This is a schematic diagram of a high-precision timing device for a chip provided in Embodiment 3 of the present invention; Figure 6 A schematic diagram of an electronic device that can be used to implement embodiments of the present invention is shown. Detailed Implementation

[0015] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0016] It should be noted that the terms "current," "target," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0017] Example 1 Figure 1 This is a flowchart of a high-precision timing method for a chip according to Embodiment 1 of the present invention. This embodiment is applicable to situations where a distributed global timer in a chip performs high-precision timing. The method can be executed by a high-precision timing device in the chip, which can be implemented in hardware and / or software and can be configured in an electronic device. This electronic device can be a system management unit in the chip, i.e., a functional unit that manages and controls the global timer in the chip, such as alignment and error compensation. Figure 1 As shown, the method includes: Step 110: Create the desired timer and the global timer on the current chip.

[0018] The desired timer can be an ideal reference timer generated based on a high-precision fixed reference clock. The global timer can be multiple distributed timers deployed on the chip.

[0019] In this embodiment of the invention, a desired timer and a global timer can be created on the die as the deployment unit in the current chip.

[0020] Optionally, a desired timer can be created using a high-precision fixed reference clock, and the global timer can be driven by the clock of the system management unit. The creation of the desired timer and the global timer can be implemented in hardware, which is free from the latency uncertainty of path reading and provides a comparison reference for timers between dies.

[0021] For example, the frequency of the high-precision fixed reference clock can be 100MHz ± 0Hz, the frequency of the desired timer can be 100MHz, and the frequency of the global timer can be 1000MHz ± 50Hz. This embodiment of the invention does not limit the frequency values ​​of the high-precision fixed reference clock, the desired timer, and the global timer.

[0022] Step 120: Based on the cold reset signal and the start compensation value, perform start offset compensation on the global timer of the current chip, and perform periodic frequency offset compensation on the global timer of the current chip according to the period difference between the expected timer and the global timer.

[0023] The startup compensation value can be a compensation value for the startup delay of the global timer, used to characterize the physical transmission delay from the system management unit (SMU) to the global timer in the chip. The period difference can be a compensation value for frequency offset compensation of the global timer. The period difference is a signed number and can be sent to the microcontroller of the SMU via an interrupt. Periodic frequency offset compensation can be an operation that compensates for the frequency offset of the current chip's global timer according to the period difference. Periodic frequency offset compensation can be understood as periodically adding the current frequency of the timer to the period difference. Periodic frequency offset compensation calculates the timing changes caused by frequency offset by continuously tracking the difference between the global timer driven by the SMU and the desired timer driven by a high-precision fixed reference clock. It can also accept timer changes caused by frequency changes of the SMU clock due to initialization or other scenarios.

[0024] In this embodiment of the invention, based on the synchronous release strategy, after the cold reset signal is released, the global timer of the current chip is compensated for the start offset according to the start compensation value. That is, the global timer is deducted from the corresponding start compensation value at the timing point after the cold reset, and the period difference between the expected timer and the global timer is calculated according to the preset period. The period difference is then used to compensate the global timer of the current chip for periodic frequency offset.

[0025] For example, suppose the ratio of the desired timer frequency A to the global timer frequency B is K, and the current frequency of a timer in the global timer is B1, then the period difference between the desired timer and this timer is K×A-B1.

[0026] Step 130: Align the compensated global timer across clock domains using Gray code cross-clock synchronization.

[0027] Among them, Gray code cross-clock synchronization can be Gray code cross-clock domain design, which is used to achieve cross-clock domain design through binary to Gray code conversion, synchronizer, Gray code to binary conversion.

[0028] In this embodiment of the invention, the compensated global timer can be aligned across clock domains based on Gray code cross-clock synchronization. That is, the global timer after completing start-up offset compensation and periodic offset compensation can be aligned across clock domains through Gray code cross-clock domain design.

[0029] The technical solution of this invention creates a desired timer and a global timer on the current chip. Based on a cold reset signal and a start-up compensation value, it compensates for the start-up offset of the global timer on the current chip. Furthermore, based on the period difference between the desired timer and the global timer, it compensates for the periodic frequency offset of the global timer on the current chip. Finally, it uses Gray code cross-clock synchronization to align the compensated global timer across clock domains. This solution performs targeted start-up offset compensation on the global timer in the chip in one go, based on the cold reset signal and the start-up compensation value, and is unaffected by partial or full-function resets. Based on the period difference, it compensates for the periodic frequency offset of the global timer in the chip to reduce timing errors caused by frequency offset. The Gray code cross-clock synchronization method aligns the compensated global timer across clock domains, ensuring that the error introduced by the cross-clock design method always approaches the theoretical optimal value under any conditions. This solves the problem of poor timing accuracy of global timers on existing chips and improves the timing accuracy of global timers on chips.

[0030] Example 2 Figure 2 This is a flowchart of a high-precision timing method for a chip provided in Embodiment 2 of the present invention. This embodiment is a specific embodiment based on the above embodiment, and provides a specific optional implementation method for aligning the compensated global timer across clock domains using Gray code cross-clock synchronization. For example... Figure 2 As shown, the method includes: Step 210: Create the desired timer and the global timer on the current chip.

[0031] In an optional embodiment of the present invention, at least one die is packaged within the current chip; each die is deployed with at least one functional design module; the release of the cold reset signal serves as the starting point for the global timer's counting, and the counting unit of the global timer is the target duration.

[0032] The functional design module can be a reusable, verified functional module, i.e., a functional IP. The die serves as the physical implementation of the functional design module; each die has its own system management unit, and each system management unit manages the functional design modules on the same die. The cold reset signal can be a signal for a complete hardware-level reset. The target duration can be a pre-set duration. For example, the target duration can be, but is not limited to, 1 ns.

[0033] In this embodiment of the invention, at least one die can be packaged within the current chip, and at least one functional design module can be deployed on each die. Each functional design module distributes timers of the same design; that is, the timers created by all functional design modules on a die constitute the global timer for that die. The current chip uses the release of the cold reset signal as the starting point for counting the global timers in each die, and the counting unit of the global timers on each die is the target duration. This allows it to be unaffected by voltage or frequency regulation, facilitating cross-sectional comparison between functional design modules.

[0034] Step 220: Based on the cold reset signal and the start compensation value, perform start offset compensation on the global timer of the current chip, and perform periodic frequency offset compensation on the global timer of the current chip according to the period difference between the expected timer and the global timer.

[0035] In an optional embodiment of the present invention, the startup offset compensation of the global timer of the current chip based on the cold reset signal and the startup compensation value may include: after obtaining the cold reset signal, determining the startup compensation value of the functional design module of the packaged die in the current chip; and performing startup offset compensation on the global timer of the packaged die in the current chip according to the startup compensation value of the functional design module of the packaged die in the current chip.

[0036] In this embodiment of the invention, after a cold reset signal is obtained, the physical transmission delay from the system management unit to the functional design module in the current chip die, which is experimentally measured, can be used as the start-up compensation value of the corresponding functional design module in the current chip package die. Based on the start-up compensation value of the corresponding functional design module in the current chip package die, start-up offset compensation is performed on the timer of the corresponding functional design module to complete the start-up offset compensation of the global timer of the current chip package die.

[0037] In an optional embodiment of the present invention, periodic frequency offset compensation of the global timer of the current chip is performed based on the period difference between the desired timer and the global timer. This may include: calculating the period difference between the standard frequency of the desired timer and the frequency to be adjusted of the global timer based on a preset measurement interval; periodically sending the period difference to the global timer of the packaged die in the current chip; and performing periodic frequency offset compensation of the global timer of the packaged die in the current chip based on the period difference.

[0038] The preset measurement interval can be the period length of the period difference calculation period. The standard frequency can be the desired timer frequency. The frequency to be adjusted can be the frequency of the global timer.

[0039] In this embodiment of the invention, the time difference between the standard frequency of the desired timer and the frequency to be adjusted of the global timer can be calculated periodically according to a preset measurement interval, that is, the period difference between the desired timer and the global timer. Based on the period difference, periodic frequency offset compensation can be performed on the global timer of the current chip packaged die.

[0040] In an optional embodiment of the present invention, while performing periodic frequency offset compensation on the global timer of the current chip packaged die based on the period difference, it may also include: performing periodic frequency offset compensation on the system management unit of the current chip based on the period difference.

[0041] In this embodiment of the invention, periodic frequency offset compensation can also be performed based on the periodically calculated period difference and the frequency of the timer of the system management unit in the current chip, so as to ensure the high reliability of the clock in the system management unit.

[0042] Step 230: Align the compensated global timer across the management domain, control switching domain, and service domain using Gray code cross-clock synchronization.

[0043] The management domain can be a functional domain governed by the system management unit. Specifically, the management domain is the area within the chip that processes clock quality, synchronization source selection, and system management unit information. The control switching domain can be a Control Fabric domain. The service domain can be a functional domain of a functional design module.

[0044] In this embodiment of the invention, the compensated global timer can be aligned across clocks sequentially in the management domain, control switching domain, and service domain using Gray code cross-clock synchronization.

[0045] In an optional embodiment of the present invention, creating a desired timer and a global timer in the current chip may include: when multiple dies are packaged in the current chip, creating a global timer and a unified desired timer for each die; performing startup offset compensation on the global timer of the current chip based on the cold reset signal and the startup compensation value, and performing periodic frequency offset compensation on the global timer of the current chip according to the period difference between the desired timer and the global timer, which may include: performing startup offset compensation on the global timer of each die in the current chip based on the cold reset signal and the startup compensation value of the functional design module in each die; and performing periodic frequency offset compensation on the global timer of each die in the current chip according to the period difference between the unified desired timer and the global timer of each die.

[0046] In this embodiment of the invention, if the current chip contains multiple dies, a global timer can be created for each die, and a unified expected timer can be created for all dies. When a cold reset signal of the current chip is received, the global timers in each die of the current chip are compensated for corresponding start offsets according to the start compensation value of each functional design module in each die. That is, based on the start compensation value of the current functional design module in the current die, the timers deployed in the current functional design module in the global timer of the current die are compensated for start offsets. Furthermore, based on the period difference between the unified expected timer and the global timers of each die, the global timers of each die in the current chip are compensated for periodic frequency offsets, thereby achieving alignment of timers of multiple dies.

[0047] Figure 3 This is a schematic diagram illustrating key steps in high-precision timing within a single die, as provided in Embodiment 2 of the present invention. Figure 3 As shown, within a single bare chip, the system management unit creates a desired timer and a global timer based on a high-precision fixed reference clock (the desired timer and global timer belong to the system management unit's hardware). Through hardware cycle comparison, the cycle difference between the desired timer and the global timer is obtained. After recognizing a cold reset signal, the system management unit firmware sends the start-up compensation value to the global timers (timers for function IP1, function IP2, ..., function IPn) all at once, and periodically sends the cycle difference to the global timers. After the global timers complete start-up offset compensation and periodic frequency offset compensation, cross-clock domain alignment is performed in the management domain, control switching domain, and service domain using Gray code cross-clock synchronization to ensure that each function IP obtains a unified, high-precision, low-error timestamp.

[0048] Specifically, upon receiving a periodic interrupt, the system management unit firmware reads the period difference calculated by the hardware and sums the frequency of all distributed global timers on this chip with the period difference to complete the periodic frequency offset compensation.

[0049] For example, a high-precision timing control architecture for the chip can be built using four CSRs (Configuration & Status Registers), such as CSR0, CSR1, CSR2, and CSR3. CSR0, CSR1, CSR2, and CSR3 are read-write registers. CSR0 is used to set the preset measurement interval, CSR1 is used to record the period difference, CSR2 is a programming interface register within a system management unit (SMU) for clock calibration via write operations, and CSR3 is a programming interface register for functional IPs. In practice, depending on the size of the functional IPs on the die, there may be dozens or even hundreds of such registers, used for timer calibration within the functional IPs via write operations, achieving programming flexibility. The communication connection relationships between the expected timer, global timer, CSR0, CSR1, CSR2, and CSR3 are as follows: Figure 4 As shown.

[0050] When multiple dies are packaged in a chip, the desired timer for each die is created based on the same high-precision fixed reference clock. Because each die uses the same high-precision fixed reference clock, synchronization can be achieved naturally between the dies. Each die independently calibrates its desired timer based on the high-precision fixed reference clock, and the system management unit of each die adjusts the corresponding global timer (start offset compensation and periodic frequency offset compensation) according to the period difference between the desired timer and the timer of the locally managed functional IP. Finally, the overall timing error between dies is less than 20ns, and the error between functional IPs within a single die is less than 10ns.

[0051] Specifically, within each functional IP on the same die, a timer with a consistent structure is independently deployed, driven by a unified clock from the system management unit. The cold reset signal serves as the starting point for counting, supporting software clearing, assignment, and difference compensation. The timer uses Gray code for cross-clock domain synchronization, synchronizing the management domain timing to each service domain, minimizing sampling errors. The system management unit provides a globally unified high-precision fixed reference clock and cold reset signal, employing a synchronized release strategy to strictly control the physical transmission delay from the system management unit to each functional IP during cold reset. This provides a precise basis for subsequent start-up offset compensation, ensuring that the start times of the timers in each functional IP are essentially aligned. Internally, the system management unit generates a desired timer using a high-precision fixed reference clock, periodically comparing it with a global timer driven by a high-frequency operating clock. The hardware calculates the difference in real time and reports it to the firmware to track and eliminate frequency offset errors. Verification has shown that a globally counting function with simultaneous start-up, high precision, and low error within a single chip level has been achieved, ensuring that the counting units among multiple functional IPs (such as security processors and vision processing units) are identical, with an error of less than 10ns. When a chip has multiple dies, it can maintain close proximity across multiple dies. The counting error of functional IPs between dies is less than 20ns, which does not interfere with normal business operations or impose limitations on other physical designs. For example, it does not require consistent round-trip delays of communication links or calibration when the link is idle, unlike generalized precise time protocols in communication systems. Moreover, the design is simple and does not require complex calculation functions at the end nodes.

[0052] The timers in each functional IP are timers of the same design and are distributed across a single chip. All timers in all functional IPs constitute the global timer for that chip. Distributing these identically designed timers across functional IPs facilitates quick acquisition of timer counts within a localized area of ​​each functional IP, enabling timestamping for various business applications. Distributed timers allow for minimal functionality and eliminate concerns about uncertainties introduced by varying physical path lengths or arbitration backpressure in compensation information (startup compensation values ​​and period differences) sent from the system management unit.

[0053] The timers in the functional IP are driven by the system management unit's clock and use the same counting scale (1GHz high-precision clock, with a counting unit of 1ns). They are unaffected by frequency and voltage modulation, facilitating cross-comparison between functional IPs. The timers in the functional IP use the release of the cold reset signal as the counting start point, unaffected by IP local reset or global functional level reset, while also reducing the static offset between timers.

[0054] The function IP features soft reset and soft set functions, improving usability. Software-based differential compensation in the function IP provides flexibility, reduces static startup errors between timers, and minimizes errors introduced by frequency offset between bare chips. It uses the simplest Gray code cross-clock domain synchronization method to achieve cross-clock domain design across management, control, and service domains (binary to Gray code -> synchronizer -> Gray code to binary), reducing the errors of the timers actually used in the function IP and minimizing the sampling error introduced by cross-clock domains to below 4ns.

[0055] The system management unit drives the global timer clock and cold reset signal to implement a synchronous withdrawal strategy, so that the global timer start time depends only on the release time of the cold reset signal, improving the design robustness. The test results show that the single-die chip delay difference of the cold reset signal controlled by the system management unit is less than 40n.

[0056] The technical solution of this invention creates a desired timer and a global timer on the current chip. Based on a cold reset signal and a start-up compensation value, it compensates for the start-up offset of the global timer on the current chip. Furthermore, based on the period difference between the desired timer and the global timer, it compensates for the periodic frequency offset of the global timer on the current chip. Finally, it aligns the compensated global timer across management, control, and service domains using Gray code cross-clock synchronization. This solution performs fine-grained start-up offset compensation on the global timer in the chip in one step, based on the cold reset signal and the start-up compensation value, and is unaffected by partial or full-function resets. It also compensates for the periodic frequency offset of the global timer based on the period difference to reduce timing errors caused by frequency offset. The cross-clock domain alignment of the compensated global timer using Gray code cross-clock synchronization ensures that the error introduced by the cross-clock design method remains close to the theoretical optimal value under any conditions. This solves the problem of poor timing accuracy of global timers on existing chips and improves the timing accuracy of global timers on chips.

[0057] Example 3 Figure 5 This is a schematic diagram of a high-precision timing device for a chip provided in Embodiment 3 of the present invention. Figure 5 As shown, the device includes: The timer creation module 310 is used to create desired timers and global timers in the current chip. The timing compensation module 320 is used to perform start offset compensation on the global timer of the current chip based on the cold reset signal and the start compensation value, and to perform periodic frequency offset compensation on the global timer of the current chip based on the period difference between the expected timer and the global timer. The clock alignment module 330 is used to perform cross-clock domain alignment of the compensated global timer using Gray code cross-clock synchronization.

[0058] The technical solution of this invention creates a desired timer and a global timer on the current chip. Based on a cold reset signal and a start-up compensation value, it compensates for the start-up offset of the global timer on the current chip. Then, based on the period difference between the desired timer and the global timer, it performs periodic frequency offset compensation on the global timer. Finally, it uses Gray code cross-clock synchronization to align the compensated global timer across clock domains. This solution performs fine-grained start-up offset compensation on the global timer in the chip in one step based on the cold reset signal and the start-up compensation value, unaffected by partial or full-function resets. Periodic frequency offset compensation based on the period difference reduces timing errors caused by frequency offset. The cross-clock domain alignment of the compensated global timer using Gray code cross-clock synchronization ensures that the error introduced by the cross-clock design method remains close to the theoretical optimal value under any conditions. This solves the problem of poor timing accuracy of global timers on existing chips and improves the timing accuracy of global timers on chips.

[0059] Optionally, at least one die is packaged within the current chip; each die is equipped with at least one functional design module; the release of the cold reset signal serves as the starting point for the counting of the global timer, and the counting unit of the global timer is the target duration.

[0060] Optionally, the timing compensation module 320 includes a first compensation unit, used to determine the startup compensation value of the functional design module of the current in-chip packaged die after acquiring the cold reset signal; and to perform startup offset compensation on the global timer of the current in-chip packaged die according to the startup compensation value of the functional design module of the current in-chip packaged die.

[0061] Optionally, the timing compensation module 320 includes a second compensation unit, used to calculate the period difference between the standard frequency of the desired timer and the frequency to be adjusted of the global timer based on a preset measurement interval; periodically send the period difference to the global timer of the currently packaged die in the chip; and perform periodic frequency offset compensation on the global timer of the currently packaged die in the chip based on the period difference.

[0062] Optionally, the clock alignment module 330 is used to perform cross-clock domain alignment of the compensated global timer in the management domain, control switching domain, and service domain according to the Gray code cross-clock synchronization method.

[0063] Optionally, the high-precision timing device for the chip also includes a system management unit calibration module, used to perform periodic frequency offset compensation on the system management unit of the current chip based on the period difference.

[0064] Optionally, the timer creation module 310 is used to create a global timer and a unified expected timer for each die when multiple dies are packaged within the current chip. The timing compensation module 320 is used to perform start-up offset compensation on the global timers of each die in the current chip based on the cold reset signal and the start-up compensation value of the functional design modules in each die; and to perform periodic frequency offset compensation on the global timers of each die in the current chip based on the period difference between the unified expected timer and the global timers of each die.

[0065] The high-precision timing device for chips provided in the embodiments of the present invention can execute the high-precision timing method for chips provided in any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of executing the method.

[0066] Example 4 Figure 6 A schematic diagram of an electronic device that can be used to implement embodiments of the present invention is shown. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the invention described and / or claimed herein.

[0067] like Figure 6 As shown, the electronic device 10 includes at least one processor 11 and a memory, such as ROM 12, RAM 13, etc., communicatively connected to the at least one processor 11. The memory stores computer programs executable by the at least one processor. The processor 11 can perform various appropriate actions and processes based on the computer program stored in the ROM 12 or loaded into the RAM 13 from the storage unit 18. The RAM 13 can also store various programs and data required for the operation of the electronic device 10. The processor 11, ROM 12, and RAM 13 are interconnected via a bus 14. An I / O interface 15 is also connected to the bus 14. The ROM 12 is a read-only memory, the RAM 13 is a random access memory, and the I / O interface 15 is an input / output interface.

[0068] Multiple components in electronic device 10 are connected to I / O interface 15, including: input unit 16, such as keyboard, mouse, etc.; output unit 17, such as various types of displays, speakers, etc.; storage unit 18, such as disk, optical disk, etc.; and communication unit 19, such as network card, modem, wireless transceiver, etc. Communication unit 19 allows electronic device 10 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0069] Processor 11 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. Processor 11 performs the various methods and processes described above, such as chip high-precision timing methods.

[0070] In some embodiments, the high-precision chip timing method can be implemented as a computer program tangibly contained in a computer-readable storage medium, such as storage unit 18. In some embodiments, part or all of the computer program can be loaded and / or mounted on electronic device 10 via ROM 12 and / or communication unit 19. When the computer program is loaded into RAM 13 and executed by processor 11, one or more steps of the high-precision chip timing method described above can be performed. Alternatively, in other embodiments, processor 11 can be configured to execute the high-precision chip timing method by any other suitable means (e.g., by means of firmware).

[0071] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload-programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0072] Computer programs used to implement the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when executed by the processor, the computer programs cause the functions / operations specified in the flowcharts and / or block diagrams to be performed. The computer programs may be executed entirely on a machine, partially on a machine, or as a standalone software package, partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0073] In the context of this invention, a computer-readable storage medium can be a tangible medium that may contain or store a computer program for use by or in conjunction with an instruction execution system, apparatus, or device. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, RAM, ROM, erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0074] To provide interaction with a user, the systems and techniques described herein can be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the electronic device. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0075] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as data servers), or middleware components (e.g., application servers), or frontend components (e.g., user computers with graphical user interfaces or web browsers through which users can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., communication networks). Examples of communication networks include local area networks (LANs), wide area networks (WANs), blockchain networks, and the Internet.

[0076] A computing system can include clients and servers. Clients and servers are generally located far apart and typically interact through communication networks. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship with each other. The server can be a cloud server, also known as a cloud computing server or cloud host, which is a hosting product within the cloud computing service system to address the shortcomings of traditional physical hosts and VPS servers, such as high management difficulty and weak business scalability.

[0077] This application also discloses a computer program product, which includes a computer program that, when executed by a processor, implements the high-precision chip timing method provided in any embodiment of this application. This program product shares the same inventive concept as the high-precision chip timing method disclosed in the embodiments of this application, and therefore will not be described further here.

[0078] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and no limitation is imposed herein.

[0079] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A high-precision timing method for chips, characterized in that, include: Create the desired timer and global timer in the current chip; Based on the cold reset signal and the start compensation value, start offset compensation is performed on the global timer of the current chip, and periodic frequency offset compensation is performed on the global timer of the current chip according to the period difference between the expected timer and the global timer. The global timer after compensation is aligned across clock domains using Gray code cross-clock synchronization.

2. The method of claim 1, wherein, The current chip contains at least one bare die; each bare die has at least one functional design module deployed within it. The release of the cold reset signal serves as the starting point for the counting of the global timer, and the counting unit of the global timer is the target duration.

3. The method of claim 2, wherein, Based on the cold reset signal and the startup compensation value, startup offset compensation is performed on the global timer of the current chip, including: After obtaining the cold reset signal, determine the startup compensation value of the functional design module of the current chip-packaged bare die; Based on the startup compensation value of the functional design module of the current chip-packaged die, the global timer of the current chip-packaged die is compensated for startup offset.

4. The method of claim 2, wherein, Based on the period difference between the desired timer and the global timer, periodic frequency offset compensation is performed on the current chip's global timer, including: Based on a preset measurement interval, the period difference between the standard frequency of the desired timer and the frequency to be adjusted of the global timer is calculated. The period difference is periodically sent to the global timer of the currently packaged die within the chip; Based on the aforementioned period difference, periodic frequency offset compensation is performed on the global timer of the packaged die within the current chip.

5. The method of claim 1, wherein, Using Gray code cross-clock synchronization, the compensated global timer is aligned across clock domains, including: The compensated global timer is aligned across clock domains in the management domain, control switching domain, and service domain according to the Gray code cross-clock synchronization method.

6. The method of claim 4, wherein, While performing periodic frequency offset compensation on the global timer of the currently packaged die based on the aforementioned period difference, the method also includes: Based on the period difference, periodic frequency offset compensation is performed on the system management unit of the current chip.

7. The method according to claim 2, characterized in that, Create desired timers and global timers on the current chip, including: When multiple dies are packaged within the current chip, a global timer and a unified expected timer are created for each die. Based on the cold reset signal and the startup compensation value, startup offset compensation is performed on the global timer of the current chip, and periodic frequency offset compensation is performed on the global timer of the current chip according to the period difference between the desired timer and the global timer, including: Based on the cold reset signal and the start-up compensation value of the functional design module in each die, the start-up offset compensation is performed on the global timer of each die in the current chip. Based on the period difference between the unified expected timer and the global timer of each die, periodic frequency offset compensation is performed on the global timer of each die in the current chip.

8. An electronic device, characterized in that, The electronic device includes: At least one processor, and a memory communicatively connected to said at least one processor; The memory stores a computer program that can be executed by the at least one processor, which is then executed by the at least one processor to enable the at least one processor to perform the chip high-precision timing method according to any one of claims 1-7.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions that cause a processor to execute the high-precision timing method for the chip according to any one of claims 1-7.

10. A computer program product, characterized in that, The computer program product includes a computer program that, when executed by a processor, implements the chip high-precision timing method according to any one of claims 1-7.

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