Circuit board routing migration method, apparatus, and storage medium based on wiring path map

Abstract

This application discloses a circuit board routing migration method, device, and storage medium based on a routing path diagram, relating to the field of electronic manufacturing technology. The method includes: constructing a target routing path diagram for the target circuit board based on the component layout results, board outline information, layer information, and a reference routing path diagram; establishing node mapping relationships based on the connection constraints between conductors and pads in the routing space; extracting routing structure features from the reference routing path diagram, and generating routing migration guidance information by combining routing constraints and node mapping relationships; and routing according to the routing migration guidance information to obtain the routing path result. This application solves the problem of poor circuit board routing quality by constructing routing path diagrams for both the reference and target circuit boards, matching the path diagrams based on connection constraints, and generating routing migration guidance information to guide routing. This improves the robustness and success rate of routing migration while ensuring routing quality.

Description

Technical Field

[0001] This application relates to the field of electronic manufacturing technology, and in particular to a circuit board wiring migration method, device and storage medium based on wiring path diagram. Background Technology

[0002] In the printed circuit board design process, the design quality of the routing stage directly determines signal integrity, electromagnetic compatibility, and manufacturing feasibility. Getting rid of geometric coordinate dependence, accurately depicting the routing characteristics of the reference printed circuit board, and realizing routing migration under the new layout are the core foundations for improving routing efficiency and quality in layout migration scenarios.

[0003] In related technologies, methods based on geometric coordinates and cost search are commonly used. After a given component layout, routing is completed by optimizing indicators such as line length and via quantity. In layout migration scenarios, attempts are made to copy the routing path of the reference printed circuit board based on absolute coordinates. This approach is difficult to inherit the routing structure features implicit in the expert design, resulting in poor circuit board routing quality.

[0004] The above content is only used to help understand the technical solution of this application and does not represent an admission that the above content is prior art. Summary of the Invention

[0005] The main objective of this application is to provide a circuit board routing migration method, device, and storage medium based on a routing path diagram, which aims to solve the technical problem of poor circuit board routing quality.

[0006] To achieve the above objectives, this application proposes a circuit board routing migration method based on a routing path diagram, the method comprising:

[0007] Based on the component layout results, board outline information, and layer information of the target circuit board, and in conjunction with the reference routing path diagram of the corresponding reference circuit board, the target routing path diagram of the target circuit board is constructed. Based on the connection constraints between conductors and pads in the routing space, establish the node mapping relationship between the target routing path diagram and the reference routing path diagram; Extract the wiring structure features from the reference wiring path diagram, combine them with the wiring constraints of the target circuit board and the node mapping relationship, and generate wiring migration guidance information. The target circuit board is routed according to the routing migration guidance information to obtain the routing path result.

[0008] In one embodiment, node delimitation criteria and node construction rules are extracted from the reference wiring path diagram of the reference circuit board; Based on the component layout results, board outline information, and layer information of the target circuit board, a node set of the target circuit board is generated according to the node definition criteria and the node construction rules. Analyze the spatial association attributes and wiring reachability of each node in the node set within the wiring space of the target circuit board, and sort out the adjacency relationship information between each node; Based on the node connection relationship construction rules, the node set of the target circuit board is associated with the adjacency relationship information to construct and generate the target wiring path diagram of the target circuit board.

[0009] In one embodiment, the connection range of each node is determined based on the physical connection relationship of the wire nodes within the wiring space and the wiring constraints. Extract routing constraint parameters that reflect the network topology attributes, inter-layer connection attributes, local routing direction attributes, and connection topology types of the conductors; Based on the wiring constraint parameters, constraint description information is constructed to describe the consistency of the node structure; The correspondence between the nodes in the reference routing path diagram and the target routing path diagram is determined according to the routing physical constraint consistency rule, and the node mapping relationship between the nodes is constructed when the routing constraint consistency condition is met.

[0010] In one embodiment, constraint consistency correction is performed on the correspondence of candidate nodes that violate wiring physical constraints or have structural conflicts; Retain the target correspondence that satisfies the consistency threshold of the routing rules from among the multiple candidate correspondences; A stable node mapping relationship is generated between the nodes based on the corrected target correspondence.

[0011] In one embodiment, based on the node mapping relationship between the reference routing path diagram and the target routing path diagram, the routing structure features corresponding to the node mapping relationship are extracted from the reference routing path diagram; Based on the wiring constraints of the target circuit board, the wiring structure features are subjected to feasibility screening and adaptability correction to obtain a feature subset that is adapted to the wiring environment of the target circuit board. Based on the feature subset and the node mapping relationship, the routing guidance rules for the target circuit board are formulated, and the routing migration guidance information is generated.

[0012] In one embodiment, a cabling execution framework adapted to the target cabling path graph is constructed according to the cabling migration guidance information and in combination with the node connection relationship of the target cabling path graph. Based on the routing execution framework, the node connection relationships are associated with the routing structure features of the reference circuit board to obtain a routing path scheme; Verify the compatibility and feasibility of the routing path scheme, and make adaptation adjustments and optimizations for the routing conflicts and unreasonable paths after verification to generate routing path results that meet all design and process constraints of the target circuit board.

[0013] In one embodiment, the attribute information of all components in the reference circuit board, the pin association information of the pads, the routing trajectory and layer distribution information are obtained, and the core routing structure information is obtained by filtering according to the layout information filtering rules. Based on the cabling design requirements, the abstract representation rules of the nodes in the core cabling structure information are defined. The adjacency and cross-layer relationships between nodes within the wiring space are defined by the abstract representation rules of the nodes. Based on the adjacency relationship, cross-layer relationship and abstract representation rules, the core wiring structure information is subjected to node-based abstraction processing, and the resulting node set and the connection relationship between nodes are integrated to obtain the reference wiring path diagram of the reference circuit board.

[0014] In one embodiment, the signal integrity, electromagnetic compatibility, manufacturing feasibility, and conformity with the wiring migration guidance information of the wiring path result are verified, and the wiring feedback data during the verification process is recorded. The causes of various problems in the cabling feedback data are analyzed to identify the core cabling nodes, connection rules, and parameter settings that cause the problems. Unreasonable design points in the formulation of cabling migration guidance information and the matching of cabling path diagrams are also identified and integrated to obtain a feedback analysis report. Based on the optimization direction and problem location results in the feedback analysis report, the wiring parameters of the problem location results are adjusted according to the corresponding optimization direction to generate a parameter optimization strategy; Update the relevant parameters according to the parameter optimization strategy to optimize the next cabling migration process.

[0015] In addition, to achieve the above objectives, this application also proposes a circuit board routing migration device, the device comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, the computer program being configured to implement the steps of the circuit board routing migration method based on the routing path diagram described above.

[0016] In addition, to achieve the above objectives, this application also proposes a storage medium, which is a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, it implements the steps of the circuit board routing migration method based on the wiring path diagram described above.

[0017] This application provides a circuit board routing migration method based on routing path diagrams. The method includes: first, acquiring routing data of a reference printed circuit board, component layout results of the target printed circuit board, and board outline and layer information; constructing a reference routing path diagram and a target routing path diagram containing component nodes, pad nodes, and mesh nodes, respectively; then, building a cross-layer structure for the nodes of the two routing path diagrams based on the connection constraints between conductors and pads in the routing space; constructing node neighborhoods through adjacent connection traversal, generating coarse-grained and fine-grained connection constraints, and completing the structural matching of the path diagrams and establishing node mapping relationships according to the judgment results; subsequently, extracting the routing structure features of the reference routing path diagram based on the node mapping relationships, generating routing migration guidance information in combination with the routing constraints of the target printed circuit board; and finally, adapting the routing to the target printed circuit board according to this information and optimizing parameters based on feedback data of the routing results. The implementation logic addresses the shortcomings of existing automatic routing technologies for printed circuit boards (PCBs), which rely on geometric coordinates and cost search, making it difficult to inherit the implicit routing structure features of the reference PCB. Directly reusing reference routing paths when the layout changes can easily lead to path mismatch or routing failure. Furthermore, existing routing path graph matching methods rely on node labels, geometric coordinates, or global graph structure information, making it difficult to maintain stable matching results in scenarios where component positions and orientations change. Uniform scale matching strategies are also susceptible to local disturbances, thus affecting routing migration quality. This new approach improves the robustness and success rate of PCB routing migration in layout change scenarios, effectively inherits the routing structure features of the reference PCB and improves routing quality, while simultaneously enhancing the stability and accuracy of routing path graph matching. It reduces reliance on geometric coordinates and node labels, making routing path graph matching more adaptable to PCB routing migration scenarios with layout changes.

[0018] In summary, this application solves the technical problem of poor circuit board routing quality by constructing a routing path diagram of the reference and target circuit boards, matching the path diagram based on connection relationship constraints, and generating routing migration guidance information to guide routing. This improves the robustness and success rate of routing migration while ensuring routing quality. Attached Figure Description

[0019] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0020] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a flowchart illustrating the first embodiment of the circuit board routing migration method based on routing path diagram of this application. Figure 2 This is the wiring flowchart for this application; Figure 3 A flowchart illustrating the mapping relationship for the wiring path diagram in this application; Figure 4 This is a flowchart illustrating the fourth embodiment of the circuit board routing migration method based on routing path diagram of this application; Figure 5 This is a block diagram of the cabling system of this application; Figure 6 Match the wiring path diagram of this application with the system block diagram; Figure 7 This is a schematic diagram of the circuit board wiring migration device of this application.

[0022] The purpose, features, and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0023] It should be understood that the specific embodiments described herein are merely illustrative of the technical solutions of this application and are not intended to limit this application.

[0024] In related technologies, methods based on geometric coordinates and cost search are commonly used. After a given component layout, routing is completed by optimizing indicators such as line length and via quantity. In layout migration scenarios, attempts are made to copy the routing path of the reference printed circuit board based on absolute coordinates. This approach is difficult to inherit the routing structure features implicit in the expert design, resulting in poor circuit board routing quality.

[0025] This application provides a solution: First, based on the component layout results, board outline information, and layer information of the target circuit board, and combined with the reference routing path diagram of the corresponding reference circuit board, a target routing path diagram of the target circuit board is constructed. Then, according to the connection relationship constraints between conductors and pads in the routing space, a node mapping relationship between the target routing path diagram and the reference routing path diagram is established. Next, the routing structure features in the reference routing path diagram are extracted. Combined with the routing constraints of the target circuit board and the node mapping relationship, routing migration guidance information is generated. Finally, the target circuit board is routed according to the routing migration guidance information to obtain the routing path result.

[0026] It should be noted that the executing entity in this embodiment can be a computing service device with data processing, network communication, and program execution functions, such as a tablet computer, personal computer, or mobile phone, or an electronic device or circuit board routing migration device capable of performing the above functions. The following description uses a circuit board routing migration device as an example to illustrate this embodiment and the subsequent embodiments.

[0027] To better understand the technical solution of this application, a detailed description will be provided below in conjunction with the accompanying drawings and specific implementation methods.

[0028] This application provides a circuit board routing migration method based on a routing path diagram, referring to... Figure 1 , Figure 1 This is a flowchart illustrating the first embodiment of the circuit board routing migration method based on routing path diagram of this application.

[0029] In this embodiment, the circuit board routing migration method based on routing path diagram includes steps S10~S40: Step S10: Based on the component layout results, board outline information and layer information of the target circuit board, and in conjunction with the reference wiring path diagram of the corresponding reference circuit board, construct the target wiring path diagram of the target circuit board.

[0030] In this embodiment, the target circuit board is a printed circuit board that is to undergo routing migration after the component placement migration has been completed. The component placement results are the arrangement positions and placement status information of various components on the target circuit board. The board outline information is the outer contour and size range information of the target circuit board. The layer information is the number of routing layers of the target circuit board, the routing attributes of each layer, and the inter-layer connection rules. The reference circuit board is a printed circuit board with a completed high-quality routing design from which routing features can be extracted. The reference routing path diagram is a structured graph that abstracts the routing environment of the reference circuit board into a structured graph containing component nodes, pad nodes, mesh nodes, and the adjacency or reachable connections between nodes. The target routing path diagram is a structured graph with the same structure as the reference routing path diagram, used to abstractly describe the routing environment of the target circuit board.

[0031] As an optional implementation, a unified definition standard for component nodes, pad nodes, and mesh nodes is first extracted from the reference routing diagram. Simultaneously, complete construction rules for the adjacency and reachability relationships between various types of nodes are extracted to form a standardized basis for routing diagram construction. Then, based on the component layout of the target circuit board, the attribute and location information of each component, and the pin association and arrangement information of each pad are extracted one by one. Corresponding component nodes and pad nodes are generated according to the definition standard. Combining the board outline and layer information of the target circuit board, the routing space of each layer is divided according to the principle of dividing feasible routing areas, generating corresponding mesh nodes, and integrating them to form a complete set of nodes of all types for the target circuit board. Subsequently, the spatial position association and actual routing reachability of all nodes in the routing space of the target circuit board are analyzed, and adjacency or reachability connections between nodes are established according to the construction rules. Finally, the node set and the connection relationships between nodes are structurally integrated to form the target routing diagram. This method follows the construction standards of the reference routing diagram, ensuring structural comparability with the reference routing diagram and laying a unified foundation for subsequent path diagram matching.

[0032] As an alternative implementation, based on the component layout, board outline information, and layer information of the target circuit board, the routing space of each layer of the target circuit board is first divided into a whole, combined with the routing space partitioning logic. Simultaneously, basic information of components and pads is extracted, and feasible routing areas are divided, initially generating a hybrid node set containing components, pads, and meshes. Then, referring to the node attribute definitions in the reference routing path diagram, all nodes in the hybrid node set are precisely labeled with their types and assigned attributes, eliminating invalid nodes that exceed the board outline range or have no practical routing significance, forming a standardized set of all node types. Next, using the node connection relationship construction rules of the reference routing path diagram as the core, combined with the inter-layer routing constraints, board outline boundary constraints, and component layout spacing requirements of the target circuit board, the spatial relationships and actual routing accessibility between nodes are analyzed, establishing adjacency or reachable connections between nodes. Finally, the standardized node set and the connection relationships between nodes are structurally organized and hierarchically integrated to form the target routing path diagram. This method can quickly complete the node generation stage of the target routing path diagram, improve the overall construction efficiency, make the construction of the connection relationship between nodes more in line with the actual routing environment of the target circuit board, and make the abstract routing environment features more suitable for subsequent routing migration needs. At the same time, it can improve the adaptability of the routing path diagram to the actual routing scenario of the target circuit board while ensuring comparability with the reference routing path diagram structure.

[0033] Step S20: Based on the connection constraints between conductors and pads in the routing space, establish the node mapping relationship between the target routing path diagram and the reference routing path diagram.

[0034] In this embodiment, the connection constraints between conductors and pads in the routing space refer to the constraints formed by the connection method, positional association, and electrical connection requirements of conductors and pads in the routing space, which are used to standardize the connection logic between the two. The node mapping relationship is the one-to-one correspondence between nodes in the reference routing path diagram and the target routing path diagram, and it serves as a bridge connecting the structural features of the reference and target routing paths.

[0035] As an optional implementation, the target routing path diagram and the reference routing path diagram are split according to conductor type and pad type. Based on the connection relationship constraints between conductors and pads in the routing space, the connection relationships between conductors and pads of the same type are matched one by one to determine the connection logic of the corresponding nodes. Then, layer-by-layer verification is performed by routing layer to ensure that the connection relationship constraints and node mapping relationships within each layer are consistent, and matching results that do not meet the constraints are corrected. Finally, the layered matching results are integrated to form a clear layered and type-specific node mapping relationship. This method, which performs layer-by-layer matching by type, has high mapping accuracy, strong adaptability to connection relationship constraints, and can clearly distinguish the corresponding logic of different types of conductors and pads, providing reliable support for subsequent accurate extraction of routing structure features and effectively reducing mapping deviation.

[0036] As an alternative implementation, this method first integrates all nodes and connections in the target routing path diagram and the reference routing path diagram, regardless of conductor type, pad type, or routing layer. Based on the connection constraints of conductors and pads in the routing space, a global unified matching is performed on all nodes and connections to determine all correspondences at once. Then, a global consistency check is performed to ensure that all node mappings conform to the connection constraints. Finally, a globally unified node mapping relationship without hierarchical classification is formed. This method uses a global integrated matching approach, eliminating the need to split types and levels. The process is simple and efficient, enabling rapid completion of mapping relationship construction and providing efficient support for subsequent global routing migration guidance, thus improving the overall efficiency of mapping construction.

[0037] Step S30: Extract the wiring structure features from the reference wiring path diagram, and generate wiring migration guidance information by combining the wiring constraints of the target circuit board and the node mapping relationship.

[0038] In this embodiment, the routing structure features refer to the node connection logic, cross-layer routing rules, coarse-grained cross-component connection relationships, and fine-grained local routing patterns contained in the reference routing path diagram. Routing constraints are various restrictive conditions that the target circuit board routing must follow, including board outline boundary limitations, inter-layer routing rules, component spacing requirements, and manufacturing process specifications. Routing migration guidance information is a set of structured rules that can inherit the reference routing structure features and are used to guide the automatic routing of the target circuit board.

[0039] As an optional implementation, firstly, based on the node mapping relationship between the reference routing path diagram and the target routing path diagram, the routing structural features in the reference routing path diagram are precisely mapped according to the node correspondence. Coarse-grained cross-component connection features and fine-grained pad local routing features are associated with the corresponding nodes in the target routing path diagram, forming a reference routing feature set with node correspondence. Then, each feature in this reference routing feature set is individually verified for feasibility against the routing constraints of the target circuit board. Features that conflict with constraints such as board outline boundaries and inter-layer rules are eliminated, and the node connection logic of adaptable features is fine-tuned to form a feature set adapted to the target routing environment. Finally, the features in this feature set are transformed into routing connection priorities, routing path guidance rules, and inter-layer routing switching criteria for each node on the target circuit board, and integrated into structured routing migration guidance information layer by layer according to node type. This method can achieve a precise correspondence between reference routing structural features and target nodes, allowing the guidance information to highly inherit the core features of the reference routing, effectively ensuring the feature inheritance of routing migration, and improving the structural consistency between the target circuit board routing and the reference routing.

[0040] As an alternative implementation, the routing constraints of the target circuit board are first categorized and decomposed into a multi-dimensional constraint set based on board outline boundaries, inter-layer routing, and manufacturing processes. Adaptation priorities are then assigned to each constraint dimension. Based on node mapping relationships, routing structure features adaptable to each constraint dimension are extracted layer by layer from the reference routing path diagram. Features with cross-dimensional constraints undergo comprehensive adaptation and optimization, while retaining the core connection logic of the reference routing, forming an adaptation set that integrates constraints and features. Finally, based on this adaptation set, hierarchical routing migration guidance information is constructed according to the routing execution logic of the target circuit board. First, the overall guidance for global cross-component routing is determined, then the routing rules for local pads are refined, and auxiliary rules related to inter-layer routing and manufacturing processes are supplemented to generate the routing migration guidance information. This method allows for deep adaptation between routing structure features and target constraints. The hierarchical design of the guidance information better aligns with the execution logic of automatic routing, improving the smoothness of the target circuit board routing process and reducing the probability of routing conflicts.

[0041] As an alternative implementation, the reference routing path diagram is traversed layer by layer to extract the routing structure features of each layer, including routing density, line width and spacing distribution, via density, and key signal trace topology. These features are then categorized according to three dimensions: electrical performance, manufacturing process, and spatial layout, forming a hierarchical feature library. Subsequently, based on mapping relationships, the features of the reference layer are matched one by one with the routing constraints of the corresponding layer on the target circuit board. Features that do not meet the constraints are dynamically corrected; for example, the line width and spacing of high-density routing areas in the reference diagram are scaled proportionally to the minimum manufacturing process requirements of the target board, while the trace topology of key signals is adjusted according to the electromagnetic compatibility requirements of the target board. Finally, the corrected features are integrated with the mapping relationships to generate routing migration guidance information containing layered routing rules, key signal guidance strategies, and process adaptation parameters. This method, through layered extraction and dynamic correction, ensures that the guidance information retains the excellent topology of the reference design while accurately adapting to the constraints of the target board, significantly improving the relevance and executability of the guidance information and effectively avoiding manufacturing or performance problems caused by directly copying the reference design.

[0042] Step S40: According to the wiring migration guidance information, the target circuit board is wired to obtain the wiring path result.

[0043] In this embodiment, routing is a process of completing compliant routing planning based on routing migration guidance information and the routing environment of the target circuit board. The resulting routing path is a complete routing plan that meets routing constraints and design requirements, formed after routing adaptation of the target circuit board.

[0044] As an optional implementation, the routing migration guidance information is broken down into layers according to the types of component nodes, pad nodes, and mesh nodes. The routing connection priority, inter-layer routing switching criteria, and routing path guidance rules corresponding to each node type are extracted to form detailed routing guidelines for each node type. Then, based on the target routing path diagram, coarse-grained cross-component routing planning is first carried out based on component nodes, strictly following the path guidance rules for cross-component connections in the guidance information to complete the cross-component routing construction of the core network. Next, fine-grained local routing planning is carried out based on pad nodes, completing the precise connection between pads and surrounding nodes according to local routing rules. Finally, combined with the routing feasible area rules of mesh nodes, the completed routing plan is optimized, filling routing gaps and standardizing routing directions, integrating the routing plans of all networks to form a complete routing path result. This method ensures a high degree of fit between the routing process and the node structure of the routing path diagram, strictly inheriting the routing structure characteristics of the reference circuit board, guaranteeing the structural consistency of cross-component routing and local routing, and ensuring that the final routing path result is structurally highly matched with the reference circuit board. Each stage of routing has clear node type guidance rules, resulting in stronger logic and standardization in the routing planning.

[0045] As an alternative implementation, all routing rules in the routing migration guidance information are first prioritized according to network importance, and the highest priority rule corresponding to the core network routing is extracted. Then, using the routing constraints of the target circuit board as boundaries and combining the overall node connection relationships of the target routing path graph, global routing planning for the core network is carried out. The routing construction of the core network is completed first, ensuring that it meets all routing constraints and guidance rules. Then, the routing planning of ordinary networks is carried out in descending order of priority. During the routing process, the path guidance rules of the guidance information are dynamically referenced, and the routing path is flexibly adjusted using the routing feasible areas of the mesh nodes to avoid routing conflicts between different networks. Finally, the routing plans of all networks are checked and integrated as a whole, correcting unreasonable routing routes in some areas, eliminating routing overlap and gap problems, and forming a complete routing path result. This method can prioritize the routing quality of the core network, effectively reduce the probability of routing conflicts between different networks, make the routing path result more in line with the actual routing constraints of the target circuit board, and improve the efficiency of overall routing adaptation.

[0046] As an alternative implementation, the routing migration guidance information is first broken down by routing layer and signal type, forming layered routing subtasks. Then, starting from the bottom layer, routing is iteratively performed according to the layering rules and key signal priorities in the guidance information. After each layer is completed, the signal integrity, electromagnetic compatibility, and manufacturing feasibility of that layer are immediately verified. If problems are found, the process backtracks to the previous layer and adjusts according to the correction strategies in the guidance information, such as adjusting trace width and spacing or replanning via positions, until the layer meets all constraints. The process then proceeds to the next layer, ultimately completing the entire board routing and obtaining the routing path result. This method, through layered iteration and real-time verification, incorporates the constraints of the guidance information throughout the entire routing process, ensuring that each step of the routing meets design requirements. This fundamentally avoids large-scale rework later and significantly improves the first-pass yield of the routing path result.

[0047] For example, in a circuit board routing migration scenario, taking the PCB routing migration from a consumer ATX motherboard to a compact MATX motherboard as an example, the reference PCB is a 6-layer ATX motherboard routing path diagram. The target MATX motherboard has a 6-layer routing structure, a smaller board frame size, and a component layout that is offset from the reference board, while meeting preset routing rule constraints. First, based on the component layout, board frame information, and layer information of the target board, combined with the node abstraction rules of the reference routing path diagram, a target routing path diagram is generated. Then, based on the physical connection relationship of the routing and the routing constraint parameters, the nodes in the reference PCB routing path diagram and the target PCB routing path diagram are structurally consistent, and a node mapping relationship is established. On this basis, cross-component connection features and pad-level local routing features are extracted from the reference path diagram, and combined with the target board routing constraints and the node mapping relationship, routing migration guidance information is generated. Finally, based on the routing migration guidance information, the target board is adapted using an EDA automatic routing tool to obtain the routing path result. Under the premise of meeting the design rule constraints, the overall trace length and via number changes are controlled within an acceptable range, and no routing conflicts occur.

[0048] Furthermore, referring to Figure 2 , Figure 2This is the routing flowchart for this application. It involves obtaining input data, including reference PCB routing data, the migrated component layout results, and PCB outline and layer information. A reference PCB routing path diagram is constructed. Based on the obtained reference PCB routing data, core routing structure information is obtained by filtering according to layout information filtering rules. Abstract representation rules for nodes in the core routing structure information are defined based on routing design requirements. Adjacency and cross-layer relationships between nodes within the routing space are established using these abstract representation rules. The core routing structure information is then subjected to node-based abstraction processing based on adjacency, cross-layer relationships, and abstract representation rules. The resulting set of nodes and the connection relationships between nodes are integrated to obtain the reference PCB routing path diagram. The migrated PCB routing path diagram is then constructed. Based on the migrated component layout results and PCB outline and layer information, the reference PCB routing path diagram is constructed. Using the same abstract representation rules and relationship formulation methods, the B-board outline and layer information are used to construct the migrated PCB routing path diagram. Path diagram matching is performed. Based on the reference PCB routing path diagram and the migrated PCB routing path diagram, the connection relationship range of each node is determined. Routing constraint parameters that reflect the network topology attributes, inter-layer connection attributes, local routing direction attributes, and connection topology types of the conductors are extracted. Based on the extracted routing constraint parameters, constraint description information used to describe the consistency of node structure is constructed. According to the routing physical constraint consistency rules, the correspondence between nodes in the reference routing path diagram and the target routing path diagram is determined one by one. On the basis that all nodes meet the routing constraint consistency conditions, the node correspondence mapping relationship between the two routing path diagrams is completed. Based on node mapping relationships, corresponding routing structure features are extracted from the reference PCB routing path diagram. Feasibility screening and adaptation correction are performed on the routing structure features according to the routing constraints of the target circuit board, resulting in a feature subset adapted to the target circuit board's routing environment. Routing guidance rules for the target circuit board are formulated according to the feature subset and node mapping relationships, integrating and generating routing migration guidance information. The migrated routing path results are output. Based on the routing migration guidance information and the node connection relationships of the migrated PCB routing path diagram, a routing execution framework adapted to the migrated PCB routing path diagram is constructed. According to the routing execution framework, the node connection relationships are associated with the routing structure features of the reference circuit board to plan the routing path scheme. The compatibility and feasibility of the routing path scheme are verified. Adaptability adjustments and optimizations are performed on the verified routing conflicts and unreasonable paths, generating the migrated routing path results that meet all design and process constraints of the target circuit board.

[0049] By constructing a routing path graph, mapping node adjacency relationships, generating routing migration guidance information, and designing a complete routing adaptation process, the system solves the problems of routing migration depending on geometric coordinates, difficulty in inheriting routing features, and easy path mismatch under changes in circuit board layout. This improves the robustness, success rate, and routing quality of routing migration and adapts to various engineering scenarios of circuit board layout migration.

[0050] Based on any of the above embodiments, in Embodiment 2 of this application, step S10 includes steps A11 to A14: Step A11: Extract node definition criteria and node construction rules from the reference wiring path diagram of the reference circuit board.

[0051] In this embodiment, the node definition standard is a unified specification that clarifies the type classification, attribute definition, and judgment criteria of various nodes such as component nodes, pad nodes, and mesh nodes in the routing path diagram. The node construction rules are general guidelines that guide the generation methods, feature extraction, attribute assignment, and structuring of various nodes in the routing path diagram.

[0052] As an optional implementation, nodes in the reference routing diagram are explicitly categorized into component nodes, pad nodes, and mesh nodes. Then, for each type of node, its corresponding defining criteria are extracted, including the core attribute definitions, specific basis for type determination, and key elements for feature identification, forming a subset of node defining criteria for each type. Next, based on the subset of defining criteria for each type of node, corresponding construction rules are extracted, covering the node generation process, feature assignment requirements, and structured expression form. After extracting the criteria and rule subsets for all node types, the correlation of each subset is verified to confirm the consistency and coherence of standards and rules between types. Finally, all the subsets of standards and rules for each type are integrated and organized to form a unified and hierarchical system of node defining criteria and node construction rules. This method ensures that the extracted standards and rules are highly consistent with the node types, and the boundaries of the specification criteria for each type of node are clear, providing a clear hierarchical execution basis for subsequent routing diagram construction and ensuring the consistency and standardization of the construction of nodes of the same type.

[0053] As an alternative implementation, the overall structural features of the reference cabling path diagram are first decomposed into two core dimensions: node self-features and the association features between nodes and the cabling environment. Then, from the node self-feature dimension, universal definition standards for all nodes are extracted, including basic node attributes and general requirements for structured expression, while supplementing differentiated judgment conditions for different nodes, forming node definition standards that are both universal and differentiated. Next, from the node-causing-environment association feature dimension, node construction rules are extracted in conjunction with the structural characteristics of the cabling space, covering the adaptation requirements of node generation and feasible cabling areas, the association assignment rules between node features and layer information, and the matching rules between nodes and surrounding cabling structures. After completing the extraction of standards and rules for both dimensions, cross-validation between dimensions is performed to ensure the adaptability of the standards and rules. Finally, they are integrated to form a node definition standard and node construction rule system that integrates the two dimensions. This method allows the extracted standards and rules to take into account the association characteristics between node self-attributes and the cabling environment, closely matching the overall structural features of the cabling path diagram, providing an execution basis that fits the cabling environment for subsequent cabling path diagram construction, and ensuring the adaptability of node construction to the overall cabling space.

[0054] Step A12: Based on the component layout results, board outline information, and layer information of the target circuit board, generate the node set of the target circuit board according to the node definition criteria and the node construction rules.

[0055] In this embodiment, the node set is a structured whole of all component nodes, pad nodes, and mesh nodes on the target circuit board that meet the defined criteria and are generated in accordance with the construction rules.

[0056] As an optional implementation, the node definition standards and node construction rules are first categorized and decomposed according to the types of component nodes, pad nodes, and mesh nodes, forming dedicated definition standards and construction rules for each of the three types of nodes. Then, based on the component layout results of the target circuit board, the position and attribute features of all components are extracted. The type is determined according to the dedicated definition standards of the component nodes, and feature assignment and structured generation are performed according to their dedicated construction rules, forming a subset of component nodes. Next, based on the pin association information in the component layout results, the position and connection features of the pads are extracted, and generation is completed according to the dedicated standards and rules of the pad nodes, forming a subset of pad nodes. Then, combined with the board outline and layer information of the target circuit board, feasible routing areas are divided and area features are extracted. Generation is completed according to the dedicated standards and rules of the mesh nodes, forming a subset of mesh nodes. Finally, the integrity and compliance of the three node subsets are verified, and all nodes that pass the verification are structurally integrated to form the node set of the target circuit board. This method enables the generation process of various nodes to be highly consistent with their own exclusive standard rules, the node attribute definition and feature assignment are highly accurate, the boundaries of each subset are clearly defined, the final node set is highly standardized, and the recognition of various nodes is high, which can lay a precise node foundation for the construction of subsequent node connection relationships.

[0057] Step A13: Analyze the spatial association attributes and wiring reachability of each node in the node set within the wiring space of the target circuit board, and sort out the adjacency relationship information between each node.

[0058] In this embodiment, spatial association attributes refer to the relative positions of nodes within the cabling space, their layer distribution relationships, and their spatial connectivity with surrounding cabling areas. Cabling reachability refers to the feasibility of cabling connections between nodes based on cabling rules. Adjacency information is a summary of adjacency or reachable connections between nodes based on spatial association attributes and cabling reachability.

[0059] As an optional implementation, node sets are split according to component nodes, pad nodes, and mesh nodes, forming independent subsets of these three types of nodes. First, the relative positions and layer distribution relationships of nodes within each subset are analyzed to determine the spatial association attributes of nodes of the same type. Then, the routing reachability of nodes within each subset is determined based on routing rules, completing the initial sorting of adjacency relationships between nodes of the same type. Next, the cross-type spatial association attributes between nodes in different subsets are analyzed, and the routing reachability of cross-type nodes is determined based on inter-layer routing rules, sorting out the adjacency relationships of cross-type nodes. Finally, the adjacency relationships of the same type and cross-type nodes are integrated and verified, eliminating contradictory connections to form structured adjacency relationship information between nodes. This method ensures that the adjacency relationship sorting is highly consistent with node types, with high accuracy in adjacency relationships of nodes of the same type and more targeted analysis of cross-type node associations. The final sorted adjacency relationship information is hierarchically distinct and highly matched with node structural features, providing a precise foundation for subsequent routing path diagram construction.

[0060] As an alternative implementation, the overall topology of the routing space is first constructed based on the board outline and layer information of the target circuit board. The spatial boundaries and connection rules of each routing area and inter-layer connection position are determined. Then, all nodes in the node set are completely mapped to this topology, and the spatial position and layer distribution information of each node are labeled. All nodes in the routing space are traversed throughout the entire space, and the relative positional relationships, inter-layer connection characteristics, topological association features, and routing direction association attributes of each group of nodes are analyzed one by one. The spatial association information between all nodes is uniformly extracted, classified, and standardized, and duplicate and invalid association information is eliminated, ultimately forming a spatial association relationship set covering all nodes and containing complete spatial association features. Subsequently, combined with all routing rules of the target circuit board, the routing connection feasibility of each node pair in this spatial association relationship set is determined one by one, and the routing reachability of each node pair is determined. Finally, based on the spatial association relationship set and the reachability determination results, all node pairs with adjacency or reachability characteristics are integrated, redundant associations without actual routing significance are eliminated, and a complete and consistent set of adjacency relationship information between nodes is formed, fitting the overall routing space. This method achieves global matching of node association and routing space, and can fully capture the spatial association of nodes across regions and layers. The determination of inter-layer routing accessibility is more in line with the overall routing rules. Finally, the adjacency relationship information is highly adapted to the overall topology of the target circuit board routing space, and the node connection relationship across layers and regions is more complete.

[0061] Step A14: Based on the node connection relationship construction rules, associate the node set of the target circuit board with the adjacency relationship information to construct and generate the target wiring path diagram of the target circuit board.

[0062] In this embodiment, the node connection relationship construction rules are general guidelines that guide the corresponding association and structured integration of node sets and adjacency relationship information to form a wiring path diagram.

[0063] As an optional implementation method, this approach extracts the association requirements, structured integration specifications, and routing path diagram forming standards from the connection relationship construction rules. Then, the node set of the target circuit board is divided into subsets based on the types of component nodes, pad nodes, and mesh nodes. The connection relationships of each type of node in the adjacency relationship information are then analyzed to form categorized adjacency relationship subsets. Next, according to the connection specifications of nodes of the same type in the construction rules, each node subset is precisely associated with its corresponding adjacency relationship subset, and the adjacent nodes and reachability attributes of each node are labeled. Subsequently, according to the association requirements of cross-type nodes in the rules, the connection relationships of different types of nodes are connected, and the association identifiers of cross-type nodes are supplemented. Finally, the completeness and logic of all associated nodes and adjacency relationships are verified, association deviations are corrected, redundant connections are eliminated, and the target routing path diagram of the target circuit board is integrated according to the structured standards. This method ensures accurate type correspondence between nodes and adjacency relationships, clear connection structures for each type of node, a high degree of structure in the target routing path diagram, and high consistency with node definition standards and construction rules. It can accurately replicate the structural framework of the reference routing path diagram, providing a unified structural foundation for subsequent node matching.

[0064] As an alternative implementation method, the node connection relationship construction rules are first thoroughly analyzed to determine the global association principles, hierarchical division requirements, and overall adaptation specifications of the routing environment for the node set and adjacency relationship information. Then, the node set of the target circuit board is treated as a whole and globally matched with the adjacency relationship information. Each node's global adjacency nodes, reachability relationships, and inter-layer association attributes are determined, and the corresponding association identifiers for nodes and connections are marked according to the rules. Next, based on the global integration specifications in the construction rules, all nodes and their corresponding adjacency relationships are hierarchically organized, dividing the core connection area into auxiliary connection areas and clarifying the connection priority of nodes in each area. Then, the global association structure is logically verified to eliminate association conflicts and redundant connections, and missing association identifiers are supplemented. Finally, according to the requirements for generating a structured routing path diagram, the globally associated node set and adjacency relationship information are integrated to form the target routing path diagram for the target circuit board. This method can achieve accurate global association of nodes and their adjacency relationships, avoiding omissions in cross-regional and cross-type associations caused by hierarchical associations. The target routing path diagram can fully reflect the overall topological characteristics of the target circuit board routing space, with strong integrity of node connection relationships, which is more in line with the global guidance requirements of subsequent routing migration.

[0065] For example, in the scenario of PCB routing migration, taking the migration of PCB routing from a conventional desktop motherboard to a mini desktop motherboard as an application scenario, firstly, based on the routing path diagram of the reference PCB, a graph structure analysis module is used to extract node definition criteria and node construction rules. The node definition criteria are used to distinguish the classification basis of different types of nodes, and the node construction rules are used to standardize the node attribute assignment and structured generation method. Then, based on the board outline size, routing layer number, and component layout results of the target PCB, a node set of the target PCB is generated according to the extracted node definition criteria and node construction rules. Subsequently, a node association analysis module is used to analyze the node set of the target PCB, sorting out the adjacency relationship information between nodes. Then, according to the node connection relationship construction rules, the node set of the target PCB is associated with the sorted adjacency relationship information to construct a target routing path diagram containing complete nodes and adjacency relationships, consistent with the structure of the reference routing path diagram. This ensures the structural consistency between the target routing path diagram and the reference routing path diagram, providing a reliable structural foundation for the subsequent establishment of routing path diagram mapping relationships and the generation of routing migration guidance information.

[0066] By extracting the node definition standards and construction rules of the reference routing path diagram, generating a target node set, sorting out adjacency relationships, and constructing the target routing path diagram, the problems of non-standard construction of the target routing path diagram, mismatch with the reference structure, and chaotic node associations in routing migration are solved. This improves the accuracy and efficiency of the target routing path diagram construction, lays a reliable foundation for subsequent node matching and routing migration, and is suitable for various PCB routing migration scenarios.

[0067] Based on any of the above embodiments, in Embodiment 3 of this application, step S20 includes steps B11 to B14: Step B11: Determine the connection range of each node based on the physical connection relationship of the wire nodes within the wiring space and the wiring constraints.

[0068] In this embodiment, a conductor node is a basic structural unit within the wiring space that represents the connection, intersection, and transition positions of conductors. The wiring space is the physical carrier space that carries the layout of circuit board nodes, conductor routing, and connection relationships. Physical connection relationships are the physical forms of direct connection, spatial adjacency, and indirect association formed by conductor nodes within the wiring space. Wiring constraints are the process and electrical constraints that limit the connection forms, spatial distribution, and layout specifications of nodes. The scope of connection relationships is the set of objects and spatial boundaries that conductor nodes can associate within the wiring space. Connection relationship constraints include physical connection relationships and wiring constraints.

[0069] As an optional implementation, the method first divides the wiring space into different structural levels according to the hierarchical division rules. For each level, the physical connection characteristics of the wire nodes are analyzed to determine the association between the nodes and surrounding structural units. Then, the wiring constraints specific to that level are matched, and associated objects that meet the constraints are selected. The spatial boundaries and effective association sets of a single node within its corresponding level are defined layer by layer, and the definition results of all levels are integrated to form a complete range of connection relationships. This method, through layered and refined definition, can accurately match the physical connection and constraint characteristics of different levels, resulting in higher precision in defining the range of connection relationships. It also has stronger adaptability to the hierarchical structure of the wiring space and can provide refined range support for subsequent determination of node correspondences.

[0070] As an alternative implementation, the physical connection data of all wire nodes within the cabling space is first collected uniformly. All applicable cabling constraints are then summarized, and the overall physical connection relationships are directly integrated and matched with the constraints. Without dividing the structural hierarchy, the associative objects and spatial boundaries of each node are uniformly defined, directly forming the complete connection relationship range for each node. This method simplifies the definition process through integrated global processing, reduces the number of step-by-step operations, and can quickly complete the definition of the connection relationship range of all nodes, improving overall definition efficiency and providing an efficient range foundation for subsequent mapping relationship construction.

[0071] Step B12: Extract wiring constraint parameters that reflect the network topology attributes, inter-layer connection attributes, local routing direction attributes, and connection topology types of the conductors.

[0072] In this embodiment, network topology attributes refer to the connection layout and overall topological characteristics of the electrical network to which the conductor belongs. Inter-layer connection attributes refer to the attribute characteristics manifested by the conductor in achieving conduction and transition between different wiring layers. Local routing direction attributes refer to the routing and extension direction characteristics of the conductor within a local wiring area. Connection topology type refers to the classification characteristics of the connection form and topology structure formed between conductor nodes. Wiring constraint parameters are the collective term for the constraint parameters that limit the conductor routing, node connections, and topology.

[0073] As an optional implementation method, the extraction dimensions are divided according to the hierarchical distribution of the cabling space, and the extraction categories are split and categorized according to attribute types. Conductor feature identification is carried out layer by layer, sequentially extracting network topology attributes, inter-layer connection attributes, local routing direction attributes, and constraint information corresponding to connection topology types. Constraint information from different levels and categories is standardized into parameters according to a standardized format, and all extraction results are integrated to form a complete set of cabling constraint parameters. This method, through hierarchical and categorized targeted extraction, can accurately match constraint features at each level and attribute category. The completeness, relevance, and standardization of parameter extraction are significantly improved, comprehensively covering the constraint content corresponding to various attributes. This provides a comprehensive and accurate parameter foundation for the subsequent construction of constraint description information, effectively ensuring the validity of constraint references for subsequent node matching.

[0074] As an alternative implementation, this method aggregates various attribute feature data of all conductors within the cabling space, integrating network topology attributes, inter-layer connection attributes, local routing direction attributes, and connection topology type feature information across the entire domain. It directly performs unified identification and filtering without categorizing by level or category, simultaneously extracting constraint information corresponding to all attributes and standardizing it into parameters of a unified format, directly forming a holistic set of cabling constraint parameters. This method simplifies the parameter extraction process through holistic, integrated, and synchronous extraction, eliminating the step-by-step processing of hierarchical classification. It can quickly complete the extraction of all cabling constraint parameters, significantly improving overall extraction efficiency. This provides an efficient and rapid parameter supply for subsequent constraint description information construction, accelerating the overall cabling mapping process.

[0075] Step B13: Construct constraint description information based on the wiring constraint parameters to describe the consistency of the node structure.

[0076] In this embodiment, node structure consistency refers to the degree of matching and compatibility between nodes in the reference routing path diagram and the target routing path diagram in terms of connection form, topological features, and constraint adaptability. Constraint description information is constructed based on routing constraint parameters and is a standardized description used to characterize and determine node structure consistency.

[0077] As an optional implementation, a hierarchical structure is constructed based on the attribute types corresponding to the routing constraint parameters. Network topology attributes, inter-layer connection attributes, local routing direction attributes, and constraint parameters corresponding to connection topology types are categorized into independent levels. The constraint parameters within each level are systematically organized and arranged layer by layer to determine the constraint requirements and judgment logic for node structural consistency at each level. The constraint rules and parameter characteristics of each level are structurally integrated to form constraint description information with hierarchical distinctions and attribute correspondences. This method, through hierarchical structural construction, clearly defines the scope and judgment criteria of different attribute constraints. The constraint description information is clear, well-organized, and targeted, enabling precise matching of different types of node structural characteristics. This significantly improves the targeting and accuracy of subsequent node correspondence determination, providing a refined judgment basis for constructing node mapping relationships.

[0078] As an alternative implementation, all routing constraint parameters are aggregated and integrated across the entire domain. Regardless of the attribute type or functional dimension of the constraint parameters, all parameters are directly standardized and uniformly processed. Common adaptation requirements and overall judgment rules of all constraint parameters are extracted and integrated to form a unified constraint description information without hierarchical distinctions or attribute divisions. This method simplifies the constraint description information construction process through unified integration across the entire domain, eliminating the step-by-step processing of hierarchical classification. It can quickly generate constraint description information, significantly improving overall construction efficiency. It provides a concise and unified judgment standard for subsequent node correspondence determination, effectively accelerating the overall routing mapping process and ensuring its efficient operation.

[0079] Step B14: Determine the correspondence between the nodes in the reference wiring path diagram and the target wiring path diagram according to the wiring physical constraint consistency rules, and construct the node mapping relationship between the nodes if the wiring constraint consistency conditions are met.

[0080] As an optional implementation, the judgment module is divided according to the structural hierarchy of the cabling space. Nodes in the reference cabling path diagram and the target cabling path diagram are categorized and grouped hierarchically. Based on the cabling physical constraint consistency rules, the physical connection relationships, cabling constraint parameters, and structural features of the nodes are compared and verified layer by layer to determine whether the nodes meet the cabling constraint consistency conditions. After confirming the correspondence of nodes that meet the conditions within a single level, a node mapping relationship for that level is established. This process is then repeated at the next level, performing the same judgment and construction operations. After all levels are processed, the mapping results from each level are integrated to form a complete node mapping relationship. This method, through layered judgment and construction, can accurately control the matching quality of nodes at each level, implement constraint consistency verification layer by layer, significantly reduce node matching deviations, and significantly improve the accuracy and reliability of node mapping relationships. This provides a rigorous basis for the generation of subsequent cabling migration guidance information, ensuring accurate adaptation of the cabling structure migration.

[0081] As an alternative implementation, all nodes in both the reference and target cabling paths are included in a unified judgment scope. Without distinguishing structural levels or feature categories, all nodes are synchronously compared for constraint adaptation and structural fit based on cabling physical constraint consistency rules. All node combinations satisfying the cabling constraint consistency conditions are selected in one go, and these matching nodes are directly associated and integrated to generate a complete node mapping relationship. This method simplifies the judgment and construction process through synchronous judgment across the entire domain, eliminating the need for layered and step-by-step processing. It enables rapid completion of node correspondence determination and mapping relationship construction, significantly improving overall processing efficiency and effectively shortening node matching time. This provides efficient node correspondence support for subsequent cabling migration processes, accelerating the overall cabling migration implementation.

[0082] For example, in the scenario of circuit board routing migration, taking a four-layer PCB routing space as the application scenario, the total number of conductor nodes is set to 126. Based on the physical connection relationship of conductor nodes in the routing space and routing constraints such as line width, line spacing, and inter-layer conductivity, the connection relationship range of each node is determined to cover 3 to 5 adjacent nodes. The network topology attributes, inter-layer connection attributes, 0° / 45° / 90° local routing direction attributes, and point-to-point, star, and chain connection topology types of 48 key conductor nodes are extracted to obtain 96 standardized routing constraint parameters. Based on these constraint parameters, node structure consistency constraint description information is constructed. According to the routing physical constraint consistency rules, the node correspondence relationship between the reference routing path diagram and the target routing path diagram, both with 126 nodes, is determined. 118 node combinations that meet the routing constraint consistency conditions are selected, and the node mapping relationship between the two routing path diagrams is completed.

[0083] Furthermore, referring to Figure 3, Figure 3 This document presents a flowchart illustrating the process of establishing the routing path mapping relationship for this application. First, a reference PCB routing path diagram and a migrated PCB routing path diagram are obtained. Based on the physical connection relationships and routing constraints within the routing space, the connection range of each node is determined, and routing constraint parameters reflecting network topology attributes, layer distribution attributes, and routing direction attributes are extracted. The routing constraint parameters are then described for structural consistency, and the correspondence between nodes is determined according to the routing physical constraint consistency rules. Candidate correspondences that violate routing rules or have conflicts are corrected to establish stable node mapping relationships. A data structure containing node mapping relationships and consistency determination results is output, providing a basis for subsequent routing migration guidance information generation.

[0084] By constructing node mapping relationships through node connection relationship analysis, wiring structure feature extraction, and wiring constraint consistency determination, it breaks away from the single dependence of node matching on geometric coordinates in traditional wiring migration, effectively avoids node mismatch problems, makes up for the lack of accuracy in mapping relationships, and greatly improves the accuracy of node matching and the stability and reliability of mapping relationship construction, which can be efficiently adapted to circuit board wiring migration scenarios.

[0085] Based on any of the above embodiments, in Embodiment 4 of this application, referring to Figure 4 , Figure 4 This is a flowchart illustrating the fourth embodiment of the circuit board routing migration method based on a routing path diagram according to this application. Step B14 includes steps C11-C13: Step C11: Perform constraint consistency correction on the correspondence of candidate nodes that violate wiring physical constraints or have structural conflicts.

[0086] In this embodiment, routing physical constraints are hard constraints that limit the physical connections of nodes, interlayer continuity, and process specifications within the circuit board routing space. Structural conflict refers to a contradictory state in candidate node correspondences where the reference and target nodes do not match in terms of connection structure or topology. Candidate node correspondences are the preliminary selection of reference and target node correspondences during the node correspondence determination stage, which have not yet undergone constraint verification. Constraint consistency correction is the process of adjusting and optimizing candidate node correspondences that violate routing physical constraints or have structural conflicts to make them conform to the constraint requirements.

[0087] As an optional implementation, candidate node correspondences are first categorized according to the hierarchical structure of the cabling space. For each level, the physical constraints of the reference and target nodes are compared one by one to identify structural conflicts in adjacent connections and topology, thus clarifying the specific problem type of each group of non-compliant or conflicting candidate correspondences. Combining cabling constraint parameters and constraint descriptions, each problematic candidate correspondence is individually adjusted to correct node correspondence deviations, ensuring the corrected correspondences are fully compatible with the cabling physical constraints of that level and structurally conflict-free. After completing the correction for a single level, this process is sequentially extended to all levels until all candidate node correspondences pass the constraint consistency check. This method, through hierarchical correction, accurately pinpoints the root cause of problems in each group of candidate correspondences, achieving extremely high correction accuracy. It maximizes the constraint compatibility and structural consistency of candidate node correspondences, providing solid support for establishing stable and accurate node mapping relationships subsequently.

[0088] As an alternative implementation, all candidate node correspondences are aggregated, and combinations that violate wiring physical constraints or have structural conflicts are uniformly screened. Violating and conflicting candidate correspondences are categorized by problem type, and common characteristics and correction rules for each type of problem are identified. A unified classification and correction strategy is formulated by combining wiring physical constraint consistency rules and constraint description information. Correction operations are performed simultaneously on candidate correspondences of the same type of problem, adjusting node correspondence logic, eliminating structural conflicts, and correcting constraint violations. After correcting one type of problem, all problem types are processed sequentially until all candidate node correspondences meet the wiring physical constraint and structural fit requirements, completing constraint consistency correction. This method uses global conflict classification and correction, eliminating the need for layered and step-by-step processing, and can quickly complete the correction operation for all candidate correspondences, significantly improving correction efficiency. It can also resolve similar conflict problems in batches, ensuring the global uniformity of candidate node correspondences after correction, providing efficient support for the rapid construction of node mapping relationships.

[0089] Step C12: Retain the target correspondence that meets the consistency threshold of the routing rules among the multiple candidate correspondences.

[0090] In this embodiment, the consistency degree of routing rules refers to the degree of matching between candidate correspondences and routing physical constraints and structural consistency requirements. The threshold is a benchmark limit for determining whether a candidate correspondence is qualified. The target correspondence is a qualified node correspondence that meets the consistency degree threshold requirement and is retained after screening.

[0091] As an optional implementation, candidate correspondences are categorized and aggregated according to the structural hierarchy of the cabling space. A consistency threshold for cabling rules is set separately for different structural hierarchies to match the cabling characteristics of each level. The consistency of candidate correspondences within each level is compared layer by layer to determine the fit between each group of candidate correspondences and the corresponding level threshold. Candidate correspondences that meet the level threshold are retained. After screening all levels sequentially, the qualified combinations retained from each level are integrated to form a complete target correspondence. This method, through hierarchical differentiated threshold screening, can accurately match the cabling constraint characteristics of different levels, achieving high screening accuracy and better fit between the target correspondence and the cabling rules of each level. It effectively retains qualified combinations that match the structural characteristics of the hierarchical structure, improving the targeting and adaptability of the target correspondence. The disadvantage is that it requires layered and step-by-step operations, involves many process steps, and has a relatively long screening time. Its effectiveness focuses on ensuring the screening accuracy and hierarchical adaptability of the target correspondence.

[0092] As an alternative implementation, all candidate correspondences are included in a unified processing scope. A universally applicable wiring rule consistency threshold is set, and all candidate correspondences are simultaneously compared and judged for consistency. Candidate correspondences that meet the unified threshold are directly filtered and retained, without distinguishing structural levels or feature types. The filtering and retention of target correspondences are completed in one go, forming a unified set of target correspondences across the entire domain. This method uses a unified threshold for filtering across the entire domain, has a simple process without hierarchical operations, and fewer filtering steps, which can quickly complete the retention of target correspondences and has higher overall filtering efficiency. The disadvantage is that it does not adapt to hierarchical differences, and the filtering accuracy of candidate correspondences with some special structures is insufficient. The effect focuses on improving filtering efficiency, ensuring the uniformity of target correspondences across the entire domain, and accelerating the construction process of node mapping relationships.

[0093] Step C13: Generate stable node mapping relationships between nodes based on the corrected target correspondence.

[0094] In this embodiment, the corrected target correspondence is the combination of qualified node correspondences retained after constraint consistency correction and screening to meet the consistency threshold of routing rules. Stable node mapping relationships are constructed based on qualified target correspondences, with no constraint conflicts or correspondence deviations, and can support fixed node correspondence associations for long-term routing migration.

[0095] As an optional implementation, the corrected target correspondences are first categorized and collected according to the structural hierarchy of the cabling space. The node association logic within each level is then systematically analyzed, verifying the consistency and coherence of the target correspondences across levels. Potential node correspondence deviations and logical conflicts within each level are identified and eliminated. The target correspondences at each level are then solidified, clarifying the fixed correspondence rules for nodes within that level. After solidifying a single level, the solidification results of all levels are integrated, and the connection logic of node correspondences between levels is analyzed to ensure no conflicts or gaps between levels. Ultimately, a stable node mapping relationship with clear layers, logical coherence, and no deviations is generated. This method, through layered solidification and layered connection verification, maximizes the stability and accuracy of the node mapping relationship, ensuring that the mapping relationship fully adapts to cabling constraints and node structural characteristics. This provides a refined and highly reliable node correspondence foundation for the generation of subsequent cabling migration guidance information, effectively avoiding node correspondence deviations during subsequent cabling migration.

[0096] As an alternative implementation, this method aggregates all corrected target mappings, without distinguishing the structural hierarchy and node types of the cabling space. It unifies and integrates all target mappings, analyzes the overall association logic of all node mapping combinations, conducts a domain-wide node mapping consistency check, identifies and eliminates potential mapping conflicts and logical disconnections across the entire domain, and solidifies the integrated target mappings. It clarifies the fixed mapping associations of all nodes, directly forming a stable node mapping relationship that is unified and logically consistent across the entire domain, without needing to distinguish hierarchical connection logic. This method simplifies the mapping relationship generation process through unified integration and solidification across the entire domain, significantly improving the efficiency of mapping relationship generation. It can quickly complete the construction of node mapping relationships, ensuring the domain-wide uniformity of mapping relationships. This provides efficient and convenient node mapping support for the subsequent generation of domain-wide cabling migration guidance information, accelerating the overall cabling migration process.

[0097] For example, in the scenario of circuit board routing migration, taking the migration of a six-layer PCB circuit board as the application scenario, the reference PCB routing path diagram and the target PCB routing path diagram each contain 210 wire nodes. First, the correspondence of the 210 candidate nodes is verified, and 32 candidate node correspondences that violate the routing physical constraints or have structural conflicts are identified. Constraint consistency correction is performed on the 32 candidate correspondences according to the routing constraint parameters and the routing physical constraint consistency rules to eliminate node connection conflicts and constraint violations. Then, the routing rule consistency threshold is set to 90%, and the consistency degree of all candidate correspondences is compared. 197 target correspondences that meet the consistency degree threshold are retained, and 13 candidate correspondences that do not meet the threshold are eliminated. Finally, the node association logic is integrated and solidified based on the corrected 197 target correspondences to generate a stable node mapping relationship between the two routing path diagrams.

[0098] By using constraint correction, threshold filtering, and mapping fixation, the problems of conflicting nodes and unstable mapping relationships in circuit board routing migration are solved, thereby improving node matching accuracy and routing migration process stability.

[0099] Based on any of the above embodiments, in Embodiment 5 of this application, step S30 includes steps D11 to D13: Step D11: Based on the node mapping relationship between the reference wiring path diagram and the target wiring path diagram, extract the wiring structure features corresponding to the node mapping relationship from the reference wiring path diagram.

[0100] In this embodiment, the node mapping relationship is a one-to-one, structured, and complete association system formed by the effective matching nodes in the reference routing path diagram and the target routing path diagram. The routing structure features are the core routing attribute set in the reference routing path diagram, which is composed of node connection logic, neighborhood connection attributes, and inter-layer association rules.

[0101] As an optional implementation, the nodes in the reference routing path diagram and the target routing path diagram are first classified into component nodes, pad nodes, and mesh nodes according to the node mapping relationship. The range of nodes in the reference routing path diagram corresponding to the mapping relationship is then locked for each category. First, coarse-grained routing structure features corresponding to each type of node are extracted, including the overall connection trend of the node and cross-region association logic. Then, fine-grained routing structure features of the corresponding nodes are extracted, including the local connection attributes of the node and neighborhood association details. The features of each type of node are independently verified to confirm the accuracy of the correspondence between features and node mapping relationships. Irrelevant and redundant features are removed, and missing feature information is supplemented. After feature extraction is completed for each category, the categorized routing structure features are regularized and integrated to form a routing structure feature set that corresponds one-to-one with the node type. This method can achieve accurate extraction of routing structure features by category, with high correspondence between features and node mapping relationships, and complete preservation of fine-grained features. It can effectively ensure the accurate transmission of various features in subsequent routing migration, providing an accurate feature foundation for the generation of categorized routing guidance information.

[0102] Step D12: Based on the wiring constraints of the target circuit board, perform feasibility screening and adaptability correction on the wiring structure features to obtain a feature subset that adapts to the wiring environment of the target circuit board.

[0103] In this embodiment, routing constraints are all the restrictive conditions that the target circuit board routing must follow, including board outline boundary limitations, inter-layer routing rules, component spacing requirements, and manufacturing process specifications. Adaptability correction involves adjusting and optimizing the retained features to conform to the target circuit board routing constraints. The feature subset is a set of compliant routing structure features that, after screening and correction, fully adapt to the target circuit board routing environment.

[0104] As an optional implementation, the routing constraints of the target circuit board are broken down into independent constraint dimensions based on board outline boundaries, inter-layer rules, process specifications, and spacing requirements. Then, the routing structure features are mapped to each constraint dimension for feasibility screening, determining the compliance of each feature with its corresponding constraint. Infeasible features conflicting with any constraint dimension are directly eliminated. For the retained features, adaptation modifications are made according to the requirements of the corresponding constraint dimension, adjusting the feature connection logic and association methods to fit the constraint conditions. After single-dimensional modification, cross-dimensional verification is performed to ensure that the feature simultaneously meets all constraint requirements. Finally, all compliant and modified features are categorized and integrated according to constraint dimensions to form a feature subset adapted to the target circuit board routing environment. This method processes constraints step-by-step, resulting in precise feature screening and highly targeted modifications. It can completely eliminate conflicts between features and single constraints, and the feature subset has extremely high compliance, providing highly adaptable feature support for the subsequent generation of routing migration guidance information.

[0105] Step D13: Based on the feature subset and the node mapping relationship, formulate the routing guidance rules for the target circuit board and integrate them to generate the routing migration guidance information.

[0106] In this embodiment, the routing guidance rules are formulated based on the mapping relationship between feature subsets and nodes, and are used to standardize the routing path, connection logic and implementation method of the target circuit board.

[0107] As an optional implementation method, the feature subset and node mapping relationship are first synchronously split according to node type, forming independent feature and mapping combination units corresponding to component nodes, pad nodes, and mesh nodes. Then, for each combination unit, based on the adaptive routing structure features within the feature subset and combined with the mapping association attributes of the corresponding node, exclusive routing guidance rules are formulated for each type of node, determining the specific criteria for routing direction, connection priority, and neighborhood association method for each type of node. After completing the formulation of routing guidance rules for all types of nodes, the rules are standardized within each type and verified for inter-type connection to eliminate rule conflicts and connection deviations. Finally, the routing execution logic of node types is layered and integrated, and all standardized and orderly routing guidance rules are uniformly encapsulated, ultimately generating clearly organized routing migration guidance information partitioned by node type. This method enables precise formulation of routing guidance rules by type, with a high degree of matching between rules and corresponding nodes and features. The guidance information is highly targeted and executable, effectively ensuring the accurate implementation of subsequent routing for each type of node, and providing a standardized and reliable guidance basis for type-based routing adaptation.

[0108] As an alternative implementation, the feature subset and node mapping relationships are first integrated globally, forming a unified global feature and mapping association system regardless of node type. Based on this global system, unified routing guidance rules are then formulated according to the overall routing execution logic, clarifying the overall routing direction, core node connection priority, and cross-type node association constraints across the entire scope. During rule formulation, the compatibility of the global rules with all nodes and features is simultaneously verified to ensure that the rules cover all mapped nodes and compliant features. After completing the global routing guidance rule formulation, the rules are comprehensively reviewed and optimized, eliminating redundant constraints and supplementing missing guidance. Then, they are integrated according to the execution logic of the target circuit board's overall routing environment, ultimately generating globally unified, type-free routing migration guidance information. This method enables globally integrated formulation of routing guidance rules, eliminating the need for type splitting and step-by-step verification. The formulation process is simple and efficient, and the overall coherence of the guidance information is strong, effectively ensuring the smooth implementation of subsequent global routing adaptation and providing efficient and unified guidance for overall routing execution.

[0109] For example, in the scenario of circuit board routing migration, taking the migration of routing from an industrial control board PCB to a small chemical control board as an application scenario, firstly, based on the node mapping relationship between the reference routing path diagram and the target routing path diagram, a routing feature extraction process is used to extract the routing structure features corresponding to the node mapping relationship from the reference routing path diagram. Next, the routing constraints of the target circuit board are obtained, and through a feature filtering and correction process, the extracted routing structure features are filtered and corrected, eliminating invalid features that conflict with the target routing constraints and correcting features with adaptation deviations, resulting in a feature subset adapted to the target routing environment. Subsequently, through rule generation, combined with the adapted feature subset and node mapping relationship, multiple types of routing guidance rules are formulated and integrated to generate routing migration guidance information for guiding the routing migration of the target circuit board.

[0110] By generating guidance information through feature extraction, filtering and correction, and rule integration, the problems of poor feature adaptation and non-standard guidance information in routing migration are solved, thereby improving the accuracy and adaptability of routing migration guidance and making it suitable for circuit board routing migration scenarios.

[0111] Based on any of the above embodiments, in Embodiment Six of this application, step S40 includes steps E11 to E13: Step E11: Based on the cabling migration guidance information and the node connection relationships of the target cabling path diagram, construct a cabling execution framework adapted to the target cabling path diagram.

[0112] In this embodiment, the node connection relationship refers to the adjacency and hierarchical connection relationship formed by each node in the target routing path graph based on spatial association and routing reachability. The routing execution framework is a complete execution system built by combining routing migration guidance information and node connection relationships, used to standardize the routing operations of the target circuit board.

[0113] As an optional implementation method, the routing migration guidance information is first broken down into modular guidance corresponding to different execution stages according to routing guidance rules. Simultaneously, the node connection relationships of the target routing path diagram are analyzed according to component nodes, pad nodes, and mesh nodes, dividing the path into independent routing execution units. The modular guidance is then precisely bound to the node connection relationships of each execution unit, determining the execution order, connection constraints, and feature adaptation standards for routing within each unit. Next, the execution logic of each execution unit is validated to eliminate process conflicts between units, and the execution priority of the guidance information is adjusted based on the hierarchy of node connection relationships. Finally, the specifications and logic of all execution units are integrated to construct a routing execution framework that is highly adapted by node type partitioning, rules, and connection relationships. This method constructs units by node type, achieves high accuracy in matching guidance information with node connection relationships, provides clear and standardized execution unit logic, and offers a highly targeted and implementable routing execution framework. It can provide precise execution basis for type-based routing implementation and significantly reduce the risk of deviation in routing execution within units.

[0114] Step E12: Based on the routing execution framework, the node connection relationship is associated with the routing structure features of the reference circuit board to obtain a routing path scheme.

[0115] In this embodiment, association planning is a comprehensive design process that matches, arranges, and connects node connection relationships with wiring structure characteristics according to the requirements of the wiring execution framework. The wiring path scheme is a complete path planning result formed after association planning, guiding the specific wiring direction and connection method of the target circuit board.

[0116] As an optional implementation, the routing execution framework is divided into corresponding partition execution specifications based on the types of component nodes, pad nodes, and mesh nodes. Then, the node connection relationships of each type of node in the target routing path diagram are extracted one by one, and the corresponding reference circuit board routing structure features are retrieved simultaneously. The connection relationships of each type of node are matched and associated with the routing structure features one by one according to the partition execution specifications. Local routing paths are planned according to the execution order set by the execution framework, determining the routing direction, connection method, and feature adaptation requirements for each type of node. After completing the single-type association planning, compliance verification within the partition is carried out to ensure that the path is completely consistent with the framework, features, and connection relationships. Finally, the local paths planned in each partition are integrated according to the node type connection logic to form a routing path scheme with clear partitions and type adaptation. This method, which plans by node type partition association, has high matching accuracy between node connection relationships and routing structure features, strong local path planning targeting, and high consistency with the partition specifications of the execution framework. It can effectively ensure the compliance and accuracy of routing paths for each type of node, providing a reliable path basis for the implementation of type-based routing.

[0117] As an alternative implementation method, the routing execution framework is first integrated into a globally unified execution criterion. All reference circuit board routing structure features are retrieved, and a comprehensive, interconnected planning process is conducted on node connection relationships and routing structure features according to the global execution criterion. Based on the overall routing logic, the direction, connectivity, and feature adaptation standards of the global path are set, and the routing connection sequence and overall layout of all nodes are planned uniformly. Global consistency verification is performed simultaneously during the planning process to eliminate path conflicts and connection deviations, ensuring that the entire path meets the overall execution requirements. Finally, the globally interconnected path system is integrated to form a seamless, globally interconnected routing path solution. This method employs a globally integrated interconnected planning approach, eliminating the need to split node types and the execution framework. The planning process is simple and efficient, the overall consistency of the routing path is strong, and it is highly compatible with the global criteria of the execution framework, effectively ensuring the smoothness of the overall routing process and providing an efficient path basis for the implementation of globally integrated routing.

[0118] Step E13: Verify the compatibility and feasibility of the routing path scheme, and make adaptation adjustments and optimizations for the routing conflicts and unreasonable paths after verification to generate routing path results that meet all design and process constraints of the target circuit board.

[0119] In this embodiment, compatibility feasibility verification is a comprehensive compliance verification process that checks whether the routing path scheme conforms to the target circuit board design constraints, process requirements, and node connection logic. Routing conflicts refer to problems such as path intersections, conflicting node connections, and constraint mismatches in the routing path scheme. Unreasonable paths are non-optimal paths that do not conform to routing processes, spatial layout, and design specifications.

[0120] As an optional implementation method, the design and process constraints of the target circuit board are first broken down into multiple independent dimensions, including electrical compatibility, spatial boundaries, node connections, and process implementation. The routing path scheme is then checked for compatibility and feasibility along each dimension, accurately identifying routing conflicts and unreasonable paths within each dimension. Targeted adaptation adjustments are made to address issues in a single dimension, correcting conflicts such as path intersections and node connection contradictions, and optimizing unreasonable layouts such as routing patterns and path directions. After single-dimensional adjustments, multi-dimensional cross-validation is performed to ensure that the adjusted path simultaneously meets all constraint requirements. The optimized path is then standardized and normalized, unifying path connection logic and execution standards, ultimately generating a routing path result that perfectly fits all constraints. This method, with its dimension-by-dimensional verification and adjustment, provides precise problem identification and highly targeted optimization, completely eliminating routing conflicts and unreasonable paths across all dimensions. The resulting routing path exhibits high compliance and adaptability, providing a conflict-free and highly feasible final solution for the target circuit board routing implementation.

[0121] For example, in the scenario of circuit board routing migration, taking the migration of routing from a consumer electronics PCB to an ultra-thin consumer electronics PCB as an application scenario, routing migration guidance information and a target routing path diagram are obtained. The routing migration guidance information includes multiple types of routing guidance rules, and the target routing path diagram includes various nodes and node connection relationships. An execution framework is used to construct rules, combining the routing guidance rules in the routing migration guidance information with the node connection relationships in the target routing path diagram to build a routing execution framework adapted to the target routing path diagram. Through path planning rules, based on the constructed routing execution framework, the node connection relationships in the target routing path diagram are associated with the routing structure features of the reference circuit board to generate a preliminary routing path scheme. Through a feasibility verification and optimization process, the preliminary generated routing path scheme is subjected to compatibility feasibility verification, identifying routing conflicts and unreasonable paths in the scheme. Adaptability adjustments and optimizations are made to the identified problems, ultimately generating a routing path result that meets all design and process constraints of the target circuit board, completing the routing migration adaptation from a consumer electronics PCB to an ultra-thin consumer electronics PCB.

[0122] By constructing an execution framework, planning path schemes, and performing verification optimizations, the problems of lack of execution standards, path conflicts, and failure to meet constraints in routing migration are solved, thereby improving the feasibility and adaptability of routing paths and making them suitable for circuit board routing migration scenarios.

[0123] Based on any of the above embodiments, in Embodiment 7 of this application, before step S10, steps F11 to F14 are further included: Step F11: Obtain the attribute information of all components in the reference circuit board, the pin association information of the pads, the wiring trajectory and layer distribution information, and filter the core wiring structure information according to the layout information filtering rules.

[0124] In this embodiment, the layout information filtering rules are the criteria used to filter core routing-related information and eliminate redundant and invalid content. The core routing structure information is a set of core routing-related information that, after filtering, has key reference value for the migration of routing on the target circuit board.

[0125] As an optional implementation method, the data collection scope is first divided according to the type of components, pads, wiring, and layer distribution. The attribute information of all components in the reference circuit board is acquired one by one, and the core attributes of each type of component are recorded in detail. Next, the pin association information of all pads is collected, clarifying the connection correspondence between pads and pins, and between pads themselves. Simultaneously, all wiring trajectories are collected, recording details such as the direction of the wires and connection nodes. Finally, layer distribution information is collected to clarify the layer number and distribution pattern of each wiring. After collection, the collected information is filtered according to layout information filtering rules, removing redundant and irrelevant invalid information and retaining content with core reference value for wiring migration. The filtered information is then organized and integrated to form clearly categorized and highly targeted core wiring structure information. This method involves step-by-step collection and filtering by type, ensuring comprehensive information collection and precise filtering. It accurately retains core information for each category, effectively avoiding confusion between different types of information, providing precise support for subsequent categorized wiring feature extraction, and ensuring a high degree of alignment between core information and wiring migration requirements.

[0126] Step F12: Based on the cabling design requirements, define the abstract representation rules of the nodes in the core cabling structure information.

[0127] In this embodiment, the abstract representation rules are a standard system that provides a unified abstract description and standardized definition of the attributes, types, connection relationships, and distribution characteristics of nodes.

[0128] As an optional implementation method, cabling design requirements are broken down into multiple sub-dimensions, including functional matching, electrical connections, layout constraints, and process adaptation. Combining the types and attributes of nodes in the core cabling structure information, abstract representation rules for component nodes, pad nodes, and cabling nodes are defined one by one according to each sub-dimension. The description methods, attribute annotation specifications, and connection relationship representation forms for each type of node are clarified. The rules for different dimensions are verified to ensure a high degree of consistency with the corresponding design requirements. Then, the sub-dimension rules are integrated and standardized according to node type, unifying the expression form and execution standards to form a sub-dimension and sub-type node abstract representation rule system. This method, with its dual definition based on requirement dimensions and node types, has highly targeted rules, high accuracy in adapting to cabling design requirements, and outstanding consistency and standardization in node abstract representation. It provides a standardized basis for subsequent accurate node modeling and effectively reduces the deviation in node feature extraction.

[0129] Step F13: Determine the adjacency and cross-layer relationships between nodes in the wiring space through the abstract representation rules of the nodes.

[0130] In this embodiment, the wiring space is the overall spatial range within the circuit board used for arranging wires, nodes, and achieving electrical connections. Adjacency relationship refers to the direct proximity of nodes on the same layer within the wiring space, enabling direct connection. Cross-layer relationship refers to the inter-layer connection and connectivity between nodes in different wiring layers of the wiring space, formed through a through-structure.

[0131] As an optional implementation method, firstly, all nodes in the cabling space are standardized and abstractly labeled according to the abstract representation rules of nodes. Then, the cabling layers to which the nodes belong are divided into levels. For nodes within the same level, the adjacency conditions are determined by combining the position and connection attributes in the abstract representation rules, and the adjacency relationship of each node within the same layer is determined one by one. Then, for nodes at different levels, the inter-layer association conditions are determined by the layer attributes and continuity attributes in the abstract representation rules, and the cross-layer relationship of each node is determined one by one. All adjacency and cross-layer relationships are checked in layers to ensure that the relationship determination is completely consistent with the abstract representation rules. Finally, a clear and accurate node adjacency and cross-layer relationship system is formed. This implementation method determines the relationship step by step according to the cabling layer, with high relationship recognition accuracy, strong adaptability to the abstract representation rules, and can clearly distinguish the logic of adjacency within the same layer and continuity across layers. It provides accurate relationship support for subsequent refined cabling topology modeling and greatly reduces the deviation of node relationship determination.

[0132] As an alternative implementation, all nodes within the cabling space are first subjected to a unified global abstraction based on the node abstraction representation rules. Without dividing cabling layers, all nodes are directly traversed, incorporating adjacency and cross-layer relationships into the same judgment logic. The association relationships of all nodes are simultaneously determined based on the global attribute standards of the abstraction representation rules. After completing the global relationship determination, an overall consistency check is performed to ensure that all relationships conform to the general requirements of the abstraction representation rules, ultimately forming a globally unified, layer-free node adjacency and cross-layer relationship system. This method employs a unified global judgment, eliminating the need for layered splitting, resulting in a simple and efficient process. It can quickly complete the determination of relationships for all nodes, providing unified relationship support for subsequent global cabling topology modeling and effectively improving the overall efficiency of node relationship construction.

[0133] Step F14: Based on the adjacency relationship, cross-layer relationship and abstract representation rules, the core wiring structure information is subjected to node-based abstraction processing, and the resulting node set and the connection relationship between nodes are integrated to obtain the reference wiring path diagram of the reference circuit board.

[0134] In this embodiment, node-based abstraction is a process of transforming core wiring structure information into standardized nodes and node associations according to abstract representation rules.

[0135] As an optional implementation, the core routing structure information is first broken down into component nodes, pad nodes, and routing nodes. Then, based on abstraction and representation rules, each type of information is abstracted into nodes, transforming components, pads, and routing connection points into standardized nodes, and determining the attributes and representation specifications of each node. Subsequently, the connection relationships of nodes within the same routing layer are determined based on adjacency relationships, and the interconnection relationships of nodes in different routing layers are clarified based on cross-layer relationships. The connection relationships between nodes are sorted out according to the routing layer hierarchy, and the node sets and corresponding connection relationships are integrated by type and layer. The association logic of each layer and each type of node is verified, and abstraction deviations and connection relationship errors are corrected to ensure that the nodes and connection relationships conform to the actual routing of the reference circuit board. Finally, the layered and categorized nodes and connection relationships are integrated as a whole to form a reference routing path diagram with clear layers, standardized nodes, and accurate connections. This method processes by type and layer, with accurate node abstraction, detailed connection relationship sorting, high conformity with the routing structure of the reference circuit board, and accurate restoration of routing logic, providing a high-quality benchmark for subsequent refined routing migration.

[0136] As an alternative implementation, the core cabling structure information is first uniformly analyzed across the entire domain, without distinguishing node types or cabling levels. Based on abstraction and representation rules, all information is simultaneously abstracted into nodes, transforming all types of core information into standardized nodes to form a global node set. Subsequently, all nodes are traversed synchronously, and adjacency and cross-layer relationships are considered to determine and organize the connections between all nodes in one go. Without hierarchical classification or splitting, the global node set and node connection relationships are directly integrated. A global consistency check is performed on the overall abstraction result and connection logic, correcting node representation deviations and connection conflicts to ensure the overall cabling logic is coherent. This ultimately forms a globally unified reference cabling path diagram without hierarchical classification. This implementation adopts a unified, domain-wide processing approach, eliminating the need for type and level splitting. The process is simple and efficient, enabling rapid node abstraction and path diagram construction, and adapting to subsequent global cabling migration requirements.

[0137] For example, in the scenario of circuit board routing migration, taking a server motherboard PCB as a reference, an information acquisition module is used to obtain all component attribute information, pad pin association information, routing trajectory, and routing layer distribution information of the server motherboard PCB. According to preset layout information filtering rules, the collected information is filtered and processed to remove redundant data, obtaining the core routing structure information. Based on the routing design requirements of the server motherboard, a rule definition module is used to define node abstraction representation rules. Based on the defined node abstraction representation rules, relationship construction rules are used to define the node adjacency relationships and cross-layer relationships within the routing space. Using abstract modeling rules, based on the aforementioned node adjacency relationships, cross-layer relationships, and node abstraction representation rules, the filtered core routing structure information is subjected to node-based abstraction processing. The node set and node connection relationships obtained after node-based abstraction processing are integrated to construct a standard reference routing path diagram, providing a standard reference carrier for node mapping, routing path comparison, and routing guidance information generation during subsequent circuit board routing migration.

[0138] Furthermore, referring to Figure 5 , Figure 5This is a block diagram of the routing system of this application. The input module acquires reference PCB routing data, the migrated component layout results, and PCB outline and layer information, and transmits the above information to the routing path diagram construction module. The node generation unit in the routing path diagram construction module completes node abstraction processing based on the acquired information, according to the core routing structure information and abstract representation rules, and generates a standardized node set. The node connection relationship construction unit formulates the adjacency relationship and cross-layer relationship between nodes in the routing space according to the node abstract representation rules, integrates the node set and the connection relationship between nodes to obtain the reference routing path diagram and the target routing path diagram, and then transmits the constructed routing path diagram to the routing migration guidance module. The path diagram matching unit in the routing migration guidance module constructs constraint description information to describe the consistency of node structure based on the routing constraint parameters, determines the correspondence between nodes in the reference routing path diagram and the target routing path diagram according to the routing physical constraint consistency rules, and constructs the node mapping relationship between nodes when the routing constraint consistency conditions are met. Then, based on the node mapping relationship, the corresponding routing structure features are extracted from the reference routing path diagram. According to the routing constraints of the target circuit board, the routing structure features are screened for feasibility and modified for adaptability, resulting in a feature subset adapted to the routing environment of the target circuit board. The routing guidance information generation unit formulates the routing guidance rules of the target circuit board according to the feature subset and the node mapping relationship, integrates and generates routing migration guidance information, and finally transmits the routing migration guidance information to the output module. The output module constructs a routing execution framework adapted to the target routing path diagram according to the routing migration guidance information and the node connection relationship of the target routing path diagram. According to the routing execution framework, the node connection relationship is associated with the routing structure features of the reference circuit board to plan the routing path scheme. The compatibility and feasibility of the routing path scheme are verified. Adaptability adjustments and optimizations are made for the verified routing conflicts and unreasonable paths to generate the migrated routing path result that meets all design and process constraints of the target circuit board.

[0139] By filtering information, defining rules, establishing relationships, and abstracting and modeling nodes, the problems of chaotic abstraction of reference routing structures, ambiguous node relationships, and non-standard path diagram construction are solved, thereby improving the accuracy and standardization of reference routing path diagrams and adapting them to circuit board routing migration scenarios.

[0140] Based on any of the above embodiments, in Embodiment 8 of this application, after step S50, steps G11~G14 are further included: Step G11: Verify the signal integrity, electromagnetic compatibility, manufacturing feasibility, and consistency with the wiring migration guidance information of the wiring path result, and record the wiring feedback data during the verification process.

[0141] In this embodiment, signal integrity refers to the characteristics of signal transmission in the routing path that is distortion-free, interference-free, and timing-stable. Electromagnetic compatibility (EMC) refers to the ability of the routing path to resist external electromagnetic interference and not generate excessive electromagnetic interference during operation. Manufacturing feasibility refers to the characteristics of the routing path that meet the requirements of circuit board manufacturing processes and can be successfully mass-produced. Fit refers to the degree of matching and compliance between the routing path result and the routing migration guidance information. Routing feedback data refers to relevant data such as problems, deviations, and compliance status of the routing path recorded during the verification process.

[0142] As an optional implementation method, the four verification dimensions are first broken down into independent modules. Verification is then carried out sequentially in the order of signal integrity, electromagnetic compatibility, manufacturing feasibility, and guidance information fit. Each dimension employs its own verification logic, meticulously investigating non-compliant wiring paths within that dimension to accurately determine the compliance status of each verification indicator. After verification of each dimension, wiring feedback data for that dimension is recorded synchronously, clearly marking the problem location, deviation type, and details of non-compliance, ensuring a one-to-one correspondence and precise association between feedback data and verification dimensions. After verification of all dimensions, the four types of feedback data are organized and integrated according to the verification dimensions, marking the verification conclusions and data relationships for each dimension, forming a clearly categorized and detailed set of verification results and feedback data. This method performs step-by-step verification by dimension, resulting in detailed and targeted verification that can accurately locate specific problems in each dimension. The feedback data is highly accurate and well-categorized, providing clear guidance for targeted optimization in each dimension.

[0143] Step G12: Analyze the causes of various problems in the cabling feedback data, locate the core cabling nodes, connection rules and parameter settings that cause the problems, and find unreasonable design points in the cabling migration guidance information formulation and cabling path diagram matching, and integrate them to obtain a feedback analysis report.

[0144] In this embodiment, the causes of problems are the various defects, conflicts, and non-compliance issues in the cabling feedback data. Core cabling nodes are the key node units that trigger cabling problems. Connection rules are the related constraints such as adjacency, cross-layer connections, and cabling routes between nodes. Parameter setting involves configuring electrical, process, and spatial parameters during the cabling process. Unreasonable design points are design defects such as non-standardization, mismatch, and inappropriateness in the guidance information formulation and path map matching. The feedback analysis report is an analytical summary document that integrates the causes, core nodes, rules, parameters, and unreasonable design points.

[0145] As an optional implementation method, the cabling feedback data is first divided into modules according to problem type. The causes of each problem are analyzed in detail, accurately locating the core cabling nodes, associated connection rules, and parameter settings for each problem. Then, unreasonable design points in the cabling migration guidance information formulation logic and cabling path diagram matching process are investigated one by one. The source tracing results and design defects for each type of problem are fully recorded, and the causes, nodes, rules, parameters, and unreasonable design points are organized according to problem type to ensure that the analysis content accurately corresponds to the problem type. Finally, the classification and analysis results are integrated to form a clear and comprehensive feedback analysis report. This method involves detailed analysis by problem type, meticulous tracing of causes, accurate location of core nodes and rules, comprehensive identification of unreasonable design points, and highly targeted feedback analysis reports. It provides clear source tracing basis for subsequent multi-dimensional optimization, effectively improving the accuracy and implementation of problem rectification.

[0146] As an alternative implementation method, this approach simultaneously analyzes the root causes of all problems, pinpointing the core cabling nodes, connection rules, and parameter settings that trigger various issues. It also comprehensively uncovers unreasonable design points in the formulation of cabling migration guidance information and the matching of cabling path diagrams. All source tracing results and design defects are then uniformly summarized, extracting core problems and key unreasonable design points, eliminating redundant analysis content, and generating a concise, efficient, and globally comprehensive feedback analysis report. This method employs a holistic, integrated analysis approach, eliminating the need for categorized processing. The analysis process is simple and efficient, enabling rapid source tracing and design defect discovery for all problems, significantly improving analysis efficiency, and providing rapid and comprehensive analytical support for subsequent global optimization and overall process improvement.

[0147] Step G13: Based on the optimization direction and problem location results in the feedback analysis report, adjust the wiring parameters of the problem location results according to the corresponding optimization direction to generate a parameter optimization strategy.

[0148] In this embodiment, the parameter optimization strategy is a standardized and executable parameter adjustment scheme formed by adjusting the wiring parameters according to the optimization direction.

[0149] As an optional implementation method, the optimization direction and problem location results are broken down by parameter type based on the feedback analysis report. Each parameter is matched with the corresponding routing parameters that need adjustment, and the cause of the anomaly and optimization goal for each type of parameter are determined. Single-type routing parameters are precisely adjusted according to the corresponding optimization direction, determining the adjustment range, constraints, and adaptation standards. After adjusting each type of parameter, compatibility checks are performed to ensure that the optimized parameters are conflict-free and can be executed collaboratively. The parameter specifications, adjustment basis, and execution requirements after type-based adjustments are then integrated to form a clearly categorized and precisely adjusted parameter optimization strategy. This method, which subdivides adjustments by parameter type, ensures precise parameter matching, reasonable optimization range, and highly targeted and executable strategies. It effectively solves routing problems caused by corresponding parameter types, providing precise support for subsequent refined parameter calibration and routing path optimization.

[0150] Step G14: Update the relevant parameters according to the parameter optimization strategy to optimize the next wiring migration process.

[0151] In this embodiment, the relevant parameters are configuration parameters such as wiring spacing, line width, and layer spacing that need to be adjusted according to the optimization strategy during the wiring migration process. The wiring migration process is a complete process of migrating the wiring structure of a reference circuit board to the target circuit board. Updating the relevant parameters involves modifying and adjusting the corresponding parameter configurations during the wiring process according to the requirements of the parameter optimization strategy. Optimizing the next wiring migration process involves updating the parameters to reduce problems in the next wiring migration and improve its efficiency and compliance.

[0152] As an optional implementation method, the parameter optimization strategy is first broken down by parameter type. Each parameter is then updated according to its type during the cabling migration process. The update standards, adjustment ranges, and corresponding cabling stages for each parameter type are determined. Parameter updates are then performed step-by-step according to parameter type. After each parameter type is updated, its compatibility with the corresponding cabling stage is simultaneously verified. Only after confirming that the parameter update is correct and meets the optimization requirements is the next parameter type updated. After all parameters are updated, a list of updated parameters is compiled, noting the update basis, optimization objectives, and corresponding cabling stages for each parameter type. This forms a standardized parameter update file, providing accurate parameter support for the next cabling migration process. This ensures that all parameters are compatible with the specifications in the next migration and reduces the recurrence of similar cabling problems. This method, which updates parameters step-by-step by type, ensures accurate parameter updates, strong compatibility with cabling stages, and can specifically address migration problems caused by various parameters, guaranteeing refined optimization for the next cabling migration.

[0153] For example, in the scenario of circuit board routing migration, taking the migration of automotive electronic control PCB routing as an example, a multi-dimensional verification module verifies the signal integrity, electromagnetic compatibility, manufacturing feasibility, and consistency with the routing migration guidance information of the routing path results. 32 routing feedback data entries are recorded, including 11 anomalies and unreasonable items. The root cause analysis module analyzes the feedback data, locating 14 core routing nodes, 3 problematic connection rules, and 5 parameter setting points. It also identifies 4 unreasonable design points where the routing migration guidance information does not match the routing path diagram, and integrates these findings to generate a feedback analysis report. Based on the report's optimization direction and problem location results, the corresponding routing parameters are corrected using parameter adjustment rules, generating a parameter optimization strategy containing 8 parameter adjustment schemes. Following this strategy, relevant parameters such as line width, spacing, and layer spacing are updated, completing the parameter closed-loop iteration.

[0154] Furthermore, referring to Figure 6 , Figure 6 This is a block diagram of the routing path matching system for this application. The input module obtains the reference PCB routing path diagram and the migrated PCB routing path diagram, and transmits them to the connection relationship analysis module. The connection relationship analysis module determines the connection relationship range of each node based on the physical connection relationship of the conductor nodes in the routing space and the routing constraints through the node connection range determination unit. At the same time, it analyzes the physical connection relationship in the routing space through the routing physical connection relationship analysis unit, and transmits the connection relationship range and physical connection relationship data to the routing constraint description construction module. The routing constraint description construction module extracts routing constraint parameters reflecting the network topology attributes of the conductor through the network topology attribute extraction unit, extracts routing constraint parameters reflecting the inter-layer connection attributes of the conductor through the inter-layer connection attribute extraction unit, and extracts routing constraint parameters reflecting the local routing direction attributes and connection topology type of the conductor through the routing direction and spatial distribution description unit. Then, the structural consistency description vector generation unit constructs constraint description information for describing the structural consistency of the nodes based on the extracted routing constraint parameters, and transmits the constraint description information to the structural consistency judgment and mapping establishment module. The structural consistency determination and mapping establishment module, through the routing constraint consistency determination unit, determines the correspondence between nodes in the reference routing path diagram and the target routing path diagram according to the routing physical constraint consistency rules. The conflict constraint correction unit corrects the constraint consistency of candidate node correspondences that violate routing physical constraints or have structural conflicts, retaining the target correspondences that meet the routing rule consistency threshold among multiple candidate correspondences. Then, the node mapping relationship generation unit generates stable mapping relationships between nodes based on the corrected target correspondences, transmitting the mapping relationships and determination results to the output module. The output module outputs the node mapping relationships through the node mapping relationship output unit and the consistency determination result data structure through the determination result data output unit, providing the node correspondence basis for subsequent routing migration guidance information generation.

[0155] By implementing a closed-loop process involving verification, analysis, optimization, and iteration, the system solves the problems of difficult traceability, unreasonable parameters, and lack of basis for iteration in routing migration, thereby improving the stability and closed-loop optimization capabilities of routing migration and adapting it to circuit board routing migration scenarios.

[0156] It should be noted that the node adjacency connection traversal and connection relationship constraint construction first-level determination process described in the above embodiments is only an optional implementation method for establishing path graph mapping relationship. Those skilled in the art can use other methods to establish mapping relationship without departing from the technical concept of this application.

[0157] This application provides a circuit board routing migration device, which includes: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, which are executed by the at least one processor to enable the at least one processor to perform the circuit board routing migration method based on the routing path diagram in the first embodiment described above.

[0158] The following is for reference. Figure 7 This document illustrates a structural schematic diagram suitable for implementing a circuit board routing migration device according to embodiments of this application. The circuit board routing migration device in embodiments of this application may include, but is not limited to, mobile terminals such as mobile phones, laptops, laser circuit board line correction machines, personal digital assistants (PDAs), tablet computers (PADs), portable multimedia players (PMPs), circuit board routing rework stations, etc., as well as fixed terminals such as high-density circuit board routing migration devices, desktop computers, etc. Figure 7 The circuit board wiring migration device shown is merely an example and should not impose any limitation on the functionality and scope of use of the embodiments of this application.

[0159] like Figure 7As shown, the circuit board routing migration device may include a processing unit 1001 (e.g., a central processing unit, a graphics processing unit, etc.) that can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 1002 or a program loaded from a storage device 1003 into a random access memory (RAM) 1004. The RAM 1004 also stores various programs and data required for the operation of the circuit board routing migration device. The processing unit 1001, the read-only memory 1002, and the RAM 1004 are interconnected via a bus 1005. An input / output (I / O) interface 1006 is also connected to the bus. Typically, the following systems can be connected to I / O interface 1006: input devices 1007 including, for example, touchscreens, touchpads, keyboards, mice, image sensors, microphones, accelerometers, gyroscopes, etc.; output devices 1008 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; storage devices 1003 including, for example, magnetic tapes, hard disks, etc.; and communication devices 1009. Communication device 1009 allows the circuit board migration device to communicate wirelessly or wiredly with other devices to exchange data. Although circuit board migration devices with various systems are shown in the figures, it should be understood that it is not required to implement or possess all the systems shown. More or fewer systems can be implemented alternatively.

[0160] Specifically, according to the embodiments disclosed in this application, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments disclosed in this application include a computer program product comprising a computer program carried on a computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication device, or installed from storage device 1003, or installed from read-only memory 1002. When the computer program is executed by processing device 1001, it performs the functions defined in the methods of the embodiments disclosed in this application.

[0161] The circuit board routing migration device provided in this application employs the circuit board routing migration method based on routing path diagrams in the above embodiments, which can solve the technical problem of poor circuit board routing quality. Compared with the prior art, the beneficial effects of the circuit board routing migration device provided in this application are the same as those of the circuit board routing migration method based on routing path diagrams provided in the above embodiments, and other technical features of this circuit board routing migration device are the same as those disclosed in the previous embodiment method, and will not be repeated here.

[0162] It should be understood that the various parts disclosed in this application can be implemented using hardware, software, firmware, or a combination thereof. In the description of the above embodiments, specific features, structures, materials, or characteristics can be combined in any suitable manner in one or more embodiments or examples.

[0163] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

[0164] This application provides a computer-readable storage medium having computer-readable program instructions (i.e., a computer program) stored thereon, which are used to execute the circuit board routing migration method based on the wiring path diagram in the above embodiments.

[0165] The computer-readable storage medium provided in this application may be, for example, a USB flash drive, but is not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices, or any combination thereof. More specific examples of computer-readable storage media may include, but are not limited to: electrical connections having one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof. In this embodiment, the computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, system, or device. The program code contained on the computer-readable storage medium may be transmitted using any suitable medium, including but not limited to: wires, optical cables, radio frequency (RF), etc., or any suitable combination thereof.

[0166] The aforementioned computer-readable storage medium may be included in the circuit board routing migration device; or it may exist independently and not be assembled into the circuit board routing migration device.

[0167] The aforementioned computer-readable storage medium carries one or more programs. When these programs are executed by the circuit board routing migration device, the circuit board routing migration device: constructs a target routing path diagram for the target circuit board based on the component layout results, board outline information, and layer information of the target circuit board, combined with a reference routing path diagram of a corresponding reference circuit board; establishes a node mapping relationship between the target routing path diagram and the reference routing path diagram based on the connection constraints between conductors and pads in the routing space; extracts routing structure features from the reference routing path diagram, and generates routing migration guidance information by combining the routing constraints of the target circuit board and the node mapping relationship; and performs routing on the target circuit board according to the routing migration guidance information to obtain a routing path result.

[0168] Computer program code for performing the operations of this application can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, and C++, as well as conventional procedural programming languages ​​such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0169] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0170] The modules described in the embodiments of this application can be implemented in software or hardware. The names of the modules do not necessarily limit the functionality of the unit itself.

[0171] The readable storage medium provided in this application is a computer-readable storage medium that stores computer-readable program instructions (i.e., a computer program) for executing the above-described circuit board routing migration method based on wiring path diagrams, thereby solving the technical problem of poor circuit board routing quality. Compared with the prior art, the beneficial effects of the computer-readable storage medium provided in this application are the same as those of the circuit board routing migration method based on wiring path diagrams provided in the above embodiments, and will not be repeated here.

[0172] The above description is only a part of the embodiments of this application and does not limit the patent scope of this application. All equivalent structural transformations made under the technical concept of this application and using the contents of the specification and drawings of this application, or direct / indirect applications in other related technical fields, are included in the patent protection scope of this application.

Claims

1. A circuit board routing migration method based on routing path diagram, characterized in that, The method includes: Based on the component layout results, board outline information, and layer information of the target circuit board, and in conjunction with the reference routing path diagram of the corresponding reference circuit board, the target routing path diagram of the target circuit board is constructed. Based on the connection constraints between conductors and pads in the routing space, establish the node mapping relationship between the target routing path diagram and the reference routing path diagram; Extract the wiring structure features from the reference wiring path diagram, combine them with the wiring constraints of the target circuit board and the node mapping relationship, and generate wiring migration guidance information. The target circuit board is routed according to the routing migration guidance information to obtain the routing path result.

2. The circuit board routing migration method based on routing path diagram as described in claim 1, characterized in that, The step of constructing the target routing path diagram of the target circuit board based on the component layout results, board outline information, and layer information of the target circuit board, combined with the reference routing path diagram of the corresponding reference circuit board, includes: Extract node delimitation criteria and node construction rules from the reference wiring path diagram of the reference circuit board; Based on the component layout results, board outline information, and layer information of the target circuit board, a node set of the target circuit board is generated according to the node definition criteria and the node construction rules. Analyze the spatial association attributes and wiring reachability of each node in the node set within the wiring space of the target circuit board, and sort out the adjacency relationship information between each node; Based on the node connection relationship construction rules, the node set of the target circuit board is associated with the adjacency relationship information to construct and generate the target wiring path diagram of the target circuit board.

3. The circuit board routing migration method based on routing path diagram as described in claim 1, characterized in that, The step of establishing the node mapping relationship between the target routing path diagram and the reference routing path diagram based on the connection relationship constraints between the conductors and pads in the routing space includes: Based on the physical connection relationship of the wire nodes within the wiring space and the wiring constraints, the connection relationship range of each node is determined. Extract routing constraint parameters that reflect the network topology attributes, inter-layer connection attributes, local routing direction attributes, and connection topology types of the conductors; Based on the wiring constraint parameters, constraint description information is constructed to describe the consistency of the node structure; The correspondence between the nodes in the reference routing path diagram and the target routing path diagram is determined according to the routing physical constraint consistency rule, and the node mapping relationship between the nodes is constructed when the routing constraint consistency condition is met.

4. The circuit board routing migration method based on routing path diagram as described in claim 3, characterized in that, The step of determining the correspondence between nodes in the reference routing path diagram and the target routing path diagram according to the routing physical constraint consistency rule, and constructing the node mapping relationship between nodes under the condition of satisfying the routing constraint consistency condition, includes: Constraint consistency correction is performed on the correspondence between candidate nodes that violate wiring physical constraints or have structural conflicts; Retain the target correspondence that satisfies the consistency threshold of the routing rules from among the multiple candidate correspondences; A stable node mapping relationship is generated between the nodes based on the corrected target correspondence.

5. The circuit board routing migration method based on routing path diagram as described in claim 1, characterized in that, The step of extracting the routing structure features from the reference routing path diagram, combining them with the routing constraints of the target circuit board and the node mapping relationship, to generate routing migration guidance information includes: Based on the node mapping relationship between the reference routing path diagram and the target routing path diagram, the routing structure features corresponding to the node mapping relationship are extracted from the reference routing path diagram; Based on the wiring constraints of the target circuit board, the wiring structure features are subjected to feasibility screening and adaptability correction to obtain a feature subset that is adapted to the wiring environment of the target circuit board. Based on the feature subset and the node mapping relationship, the routing guidance rules for the target circuit board are formulated, and the routing migration guidance information is generated.

6. The circuit board routing migration method based on routing path diagram as described in claim 1, characterized in that, The step of routing the target circuit board according to the routing migration guidance information to obtain the routing path result includes: Based on the cabling migration guidance information and the node connection relationships of the target cabling path graph, a cabling execution framework adapted to the target cabling path graph is constructed. Based on the routing execution framework, the node connection relationships are associated with the routing structure features of the reference circuit board to obtain a routing path scheme; Verify the compatibility and feasibility of the routing path scheme, and make adaptation adjustments and optimizations for the routing conflicts and unreasonable paths after verification to generate routing path results that meet all design and process constraints of the target circuit board.

7. The circuit board routing migration method based on routing path diagram as described in claim 1, characterized in that, Before the step of constructing the target routing path diagram of the target circuit board based on the component layout results, board outline information, and layer information of the target circuit board, combined with the reference routing path diagram of the corresponding reference circuit board, the circuit board routing migration method based on the routing path diagram further includes: Obtain the attribute information, pad pin association information, wiring trajectory and layer distribution information of all components in the reference circuit board, and filter the core wiring structure information according to the layout information filtering rules; Based on the cabling design requirements, the abstract representation rules of the nodes in the core cabling structure information are defined. The adjacency and cross-layer relationships between nodes within the wiring space are defined by the abstract representation rules of the nodes. Based on the adjacency relationship, cross-layer relationship and abstract representation rules, the core wiring structure information is subjected to node-based abstraction processing, and the resulting node set and the connection relationship between nodes are integrated to obtain the reference wiring path diagram of the reference circuit board.

8. The circuit board routing migration method based on routing path diagram as described in claim 1, characterized in that, After the step of routing the target circuit board according to the routing migration guidance information to obtain the routing path result, the circuit board routing migration method based on the routing path diagram further includes: Verify the signal integrity, electromagnetic compatibility, manufacturing feasibility, and consistency with the wiring migration guidance information of the wiring path results, and record the wiring feedback data during the verification process; The causes of various problems in the cabling feedback data are analyzed to identify the core cabling nodes, connection rules, and parameter settings that cause the problems. Unreasonable design points in the formulation of cabling migration guidance information and the matching of cabling path diagrams are also identified and integrated to obtain a feedback analysis report. Based on the optimization direction and problem location results in the feedback analysis report, the wiring parameters of the problem location results are adjusted according to the corresponding optimization direction to generate a parameter optimization strategy; Update the relevant parameters according to the parameter optimization strategy to optimize the next cabling migration process.

9. A circuit board wiring migration device, characterized in that, The circuit board routing migration device includes: a memory, a processor, and a computer program stored in the memory and executable on the processor, the computer program being configured to implement the steps of the circuit board routing migration method based on a routing path diagram as described in any one of claims 1 to 8.

10. A storage medium, characterized in that, The storage medium is a computer-readable storage medium, and a computer program is stored on the storage medium. When the computer program is executed by a processor, it implements the steps of the circuit board routing migration method based on the wiring path diagram as described in any one of claims 1 to 8.

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