Gate driver, display device, and electronic device

Abstract

This disclosure relates to gate drivers, display devices, and electronic devices. A gate driver may include: a control signal generation block configured to generate a first common control signal and a second common control signal; an output control signal generation block configured to generate an output control signal; a first gate signal output control block configured to generate a first output control voltage based on the output control signal, a first carry signal, and a second carry signal; a first gate signal control block configured to output a plurality of first gate signals and a boost control signal; a second gate signal output control block configured to generate a second output control voltage; and a second gate signal control block configured to output a plurality of second gate signals.

Description

Technical Field

[0001] Embodiments of the present invention relate to gate drivers, display devices including gate drivers, and electronic devices including gate drivers. More specifically, embodiments of the present invention relate to gate drivers with reduced power consumption, display devices including gate drivers, and electronic devices including gate drivers. Background Technology

[0002] Generally, a display device includes a display panel and a display panel driver. The display panel includes multiple gate lines, multiple data lines, and multiple pixels. The display panel driver includes a gate driver that provides gate signals to the gate lines, a data driver that provides data voltages to the data lines, and a drive controller that controls the gate driver and the data driver.

[0003] Sensing operations can be performed to generate sensor data for pixels. Summary of the Invention

[0004] Embodiments of the present invention provide a gate driver for performing sensing operations.

[0005] Embodiments of the present invention also provide a display device including a gate driver.

[0006] Embodiments of the present invention also provide electronic devices including gate drivers.

[0007] According to an embodiment, the gate driver may include: a control signal generation block configured to generate a first common control signal based on a first carry signal and a second carry signal, and to generate a second common control signal based on a third carry signal and a fourth carry signal; an output control signal generation block configured to generate an output control signal based on a first input signal, a second input signal, and a boost control signal; a first gate signal output control block configured to generate a first output control voltage based on the output control signal, the first carry signal, and the second carry signal; a first gate signal control block configured to output a plurality of first gate signals and a boost control signal based on the first common control signal, the first output control voltage, a boost clock signal, and a plurality of first clock signals; a second gate signal output control block configured to generate a second output control voltage based on the output control signal, the third carry signal, and the fourth carry signal; and a second gate signal control block configured to output a plurality of second gate signals based on the second common control signal, the second output control voltage, the boost clock signal, and a plurality of second clock signals.

[0008] In an embodiment, the output control signal generation block may include: a first output control transistor, including a control electrode for receiving a first input signal, a first electrode for receiving a boost control signal, and a second electrode connected to a first output control node; a second output control transistor, including a control electrode for receiving the first input signal, a first electrode connected to the first output control node, and a second electrode connected to a second output control node; a third output control transistor, including a control electrode connected to the second output control node and a second electrode connected to the first output control node; a fourth output control transistor, including a control electrode for receiving a second input signal, a first electrode connected to the first output control node, and a second electrode connected to a first common control node; and an output control capacitor, including a first electrode for receiving a first high voltage and a second electrode connected to the second output control node.

[0009] In an embodiment, when the first input signal has an activation level and the boost clock signal has a clock high level, the output control signal generation block can store the output control signal.

[0010] In an embodiment, when the second input signal has an activation level, the output control signal generation block can output an output control signal.

[0011] In this embodiment, the first gate signal control block can also output a carry signal based on the carry clock signal. When the first input signal has an activation level, the carry clock signal can have a clock high level.

[0012] In this embodiment, the frame period during which the gate driver is driven may include an active period during which multiple first gate signals are output and a blanking period following the active period. During the blanking period, a first gate signal among the multiple first gate signals may have an active level. During the blanking period, a second gate signal among the multiple second gate signals may have an active level.

[0013] In an embodiment, during the blanking period, the first output control voltage may have a first high voltage, and the first clock signal corresponding to the first gate signal among the plurality of first clock signals may switch between clock high level and clock low level.

[0014] In this embodiment, during the blanking period, other first gate signals among the plurality of first gate signals may have an inactive level. Similarly, during the blanking period, other second gate signals among the plurality of second gate signals may have an inactive level.

[0015] In this embodiment, the first output control voltage may have a first high voltage or a second high voltage lower than the first high voltage. The second output control voltage may have a first high voltage or a second high voltage. When the first output control voltage has a first high voltage, a plurality of first gate signals may be output. When the second output control voltage has a first high voltage, a plurality of second gate signals may be output.

[0016] In this embodiment, the plurality of first gate signals may include a first scan gate signal and a second scan gate signal. The frame period during which the gate driver is driven may include an active period during which the plurality of first gate signals are output and a blanking period following the active period. The period during which the first scan gate signal has an active level may coincide with the period during which the second scan gate signal has an active level.

[0017] In this embodiment, the first output control voltage may have a first high voltage or a second high voltage lower than the first high voltage. The second output control voltage may have a first high voltage or a second high voltage. When the first output control voltage has a first high voltage, a first gate signal may be output. When the second output control voltage has a first high voltage, a second gate signal may be output. During the first frame period, a second gate signal with an activation level may be output.

[0018] In an embodiment, the first gate signal may include a first scan gate signal and a second scan gate signal. The period of the first scan gate signal having an activation level may be consistent with the period of the second scan gate signal having an activation level.

[0019] In an embodiment, the first output control voltage may have a first high voltage or a second high voltage lower than the first high voltage. The second output control voltage may have a first high voltage or a second high voltage. When the first output control voltage has a first high voltage, a first gate signal may be output. When the second output control voltage has a first high voltage, a second gate signal may be output. The first gate signal output control block may include: a first output transistor, including a control electrode for receiving a first carry signal, a first electrode for receiving the first high voltage, and a second electrode connected to the first output voltage node; a second output transistor, including a control electrode for receiving a boost control signal, a first electrode for receiving the second high voltage, and a second electrode connected to the first output voltage node; a third output transistor, including a control electrode for receiving a second carry signal, a first electrode for receiving the second high voltage, and a second electrode connected to the first output voltage node; and a fourth output transistor, including a control electrode for receiving a second input signal, a first electrode for receiving an output control signal, and a second electrode connected to the first output voltage node. The second gate signal output control block may include: a fifth output transistor, including a control electrode for receiving a third carry signal, a first electrode for receiving a first high voltage, and a second electrode connected to a second output voltage node; a sixth output transistor, including a control electrode for receiving a boost control signal, a first electrode for receiving a second high voltage, and a second electrode connected to a second output voltage node; a seventh output transistor, including a control electrode for receiving a fourth carry signal, a first electrode for receiving a second high voltage, and a second electrode connected to a second output voltage node; and an eighth output transistor, including a control electrode for receiving a second input signal, a first electrode for receiving an output control signal, and a second electrode connected to a second output voltage node.

[0020] In an embodiment, the second gate signal control block may include: a first transistor, including a control electrode connected to a first control line, a first electrode receiving a boost clock signal, and a second electrode connected to a first control node; a second transistor, including a control electrode connected to a second control line, a first electrode connected to the first control node, and a second electrode receiving a first low voltage; a third transistor, including a control electrode connected to the first control line, a first electrode receiving a carry clock signal, and a second electrode connected to a carry output node; a fourth transistor, including a control electrode connected to the second control line, a first electrode connected to the carry output node, and a second electrode receiving a first low voltage; a fifth transistor, including a control electrode connected to the first node, a first electrode receiving a first clock signal, and a second electrode connected to the second node; a sixth transistor, including a control electrode receiving a second output control voltage, a first electrode connected to the first control line, and a second electrode connected to the first node; a seventh transistor, including a control electrode connected to the second control line, a first electrode connected to the second node, and a second electrode receiving a second low voltage; and a capacitor, including a first electrode connected to the first node and a second electrode connected to the first control node.

[0021] According to an embodiment, the display device may include: a display panel including a plurality of pixels; a gate driver configured to output a plurality of gate signals to the plurality of pixels; a data driver configured to apply a data voltage to the plurality of pixels; and a drive controller configured to control the gate driver and the data driver. The gate driver may include multiple stages. At least one of the multiple stages may include: a control signal generation block configured to generate a first common control signal based on a first carry signal and a second carry signal, and to generate a second common control signal based on a third carry signal and a fourth carry signal; an output control signal generation block configured to generate an output control signal based on a first input signal, a second input signal, and a boost control signal; a first gate signal output control block configured to generate a first output control voltage based on the output control signal, the first carry signal, and the second carry signal; a first gate signal control block configured to output a plurality of first gate signals and a boost control signal based on the first common control signal, the first output control voltage, a boost clock signal, and a plurality of first clock signals; a second gate signal output control block configured to generate a second output control voltage based on the output control signal, the third carry signal, and the fourth carry signal; and a second gate signal control block configured to output a plurality of second gate signals based on the second common control signal, the second output control voltage, the boost clock signal, and a plurality of second clock signals.

[0022] In an embodiment, the output control signal generation block may include: a first output control transistor, including a control electrode for receiving a first input signal, a first electrode for receiving a boost control signal, and a second electrode connected to a first output control node; a second output control transistor, including a control electrode for receiving the first input signal, a first electrode connected to the first output control node, and a second electrode connected to a second output control node; a third output control transistor, including a control electrode connected to the second output control node and a second electrode connected to the first output control node; a fourth output control transistor, including a control electrode for receiving a second input signal, a first electrode connected to the first output control node, and a second electrode connected to a first common control node; and an output control capacitor, including a first electrode for receiving a first high voltage and a second electrode connected to the second output control node.

[0023] In this embodiment, the gate driver may include a first stage and a second stage. The plurality of gate signals may include a first scan gate signal, a second scan gate signal, a third scan gate signal, and a fourth scan gate signal, as well as a first sense gate signal, a second sense gate signal, a third sense gate signal, and a fourth sense gate signal. The first stage may output the first scan gate signal, the second scan gate signal, the first sense gate signal, and the second sense gate signal. The second stage may output the third scan gate signal, the fourth scan gate signal, the third sense gate signal, and the fourth sense gate signal.

[0024] In an embodiment, during the blanking period, the scan gate signal applied to at least one pixel may have an activation level.

[0025] In an embodiment, the display device may further include: a sensing driver configured to perform a sensing operation on at least one of a plurality of pixels. The frame period during which the plurality of pixels are driven may include an active period during which a data voltage is applied and a blanking period during which the sensing operation on the at least one pixel is performed. When the at least one pixel is connected to a first stage, a first output control voltage and a second output control voltage of the first stage may have a first high voltage during the blanking period. During the blanking period, a scan gate signal applied to the at least one pixel has an active level, and a sensing gate signal applied to the at least one pixel may also have an active level.

[0026] In an embodiment, the display device may further include a sensing driver connected to the pixel via a sensing line. At least one pixel may include: a driving transistor including a control electrode connected to a first node, a first electrode receiving a first electrical voltage, and a second electrode connected to a second node; a scanning transistor configured to apply a data voltage to the first node in response to a scanning gate signal; a sensing transistor configured to connect the sensing line to the second node in response to a sensing gate signal; and a light-emitting element including a first electrode connected to the second node and a second electrode receiving a second electrical voltage. The scanning gate signal may be a first gate signal, and the sensing gate signal may be a second gate signal.

[0027] According to an embodiment, the electronic device may include: a controller configured to output input image data and input control signals; a display panel configured to display an image based on the input image data; and a panel driver configured to drive the display panel based on the input image data and input control signals. The display panel may include a plurality of pixels. The panel driver may include a gate driver configured to output a plurality of first gate signals and a plurality of second gate signals to the pixels. The gate driver may include: a control signal generation block configured to generate a first common control signal based on a first carry signal and a second carry signal, and to generate a second common control signal based on a third carry signal and a fourth carry signal; an output control signal generation block configured to generate an output control signal based on a first input signal, a second input signal, and a boost control signal; a first gate signal output control block configured to generate a first output control voltage based on the output control signal, the first carry signal, and the second carry signal; a first gate signal control block configured to output a plurality of first gate signals and a boost control signal based on the first common control signal, the first output control voltage, a boost clock signal, and a plurality of first clock signals; a second gate signal output control block configured to generate a second output control voltage based on the output control signal, the third carry signal, and the fourth carry signal; and a second gate signal control block configured to output a plurality of second gate signals based on the second common control signal, the second output control voltage, the boost clock signal, and a plurality of second clock signals. The input control signal may include data for selecting a driving mode for the display panel.

[0028] In an embodiment, when the input control signal includes data driven by sensing, the first input signal may have an activation level, the boost clock signal may have a clock high level, and the output control signal generation block may store the output control signal.

[0029] In an embodiment, when the input control signal includes data driven by sensing, the second input signal may have an activation level, and the output control signal generation block may output an output control signal.

[0030] In an embodiment, when the input control signal includes sensing-driven data, a sensing operation can be performed on at least one pixel, and the sensing gate signal applied to at least one pixel can have an activation level.

[0031] According to the gate driver, the display device including the gate driver, and the electronic device including the gate driver, multiple gate signals can be output based on a common control signal. Therefore, the integration of the gate driver can be improved. Furthermore, since the gate signals can be output based on a common control signal, the reliability of the gate signals can be improved. Therefore, the display quality of the display panel can be improved.

[0032] Furthermore, the gate driver can output a signal for performing sensing operations based on the input signal. Therefore, sensing operations can be performed on at least one pixel among a plurality of pixels. This allows for further improvement in the display quality of the display panel.

[0033] Furthermore, the gate driver can be driven at a high frequency, which can further improve the display quality of the display panel.

[0034] In addition, the display panel can be driven at a variable frequency, which reduces the power consumption of the display device. Attached Figure Description

[0035] The above and other features and advantages of the present invention will become more apparent from the detailed description of embodiments of the invention with reference to the accompanying drawings.

[0036] Figure 1 This is a block diagram illustrating a display device according to an embodiment of the concept of the present invention.

[0037] Figure 2 It is shown that it includes Figure 1 A block diagram of a gate driver in a display device.

[0038] Figure 3 It is shown Figure 2 A block diagram of an example of a level.

[0039] Figure 4 It shows that it is applied to Figure 2 A timing diagram of an example of the gate driver signal.

[0040] Figure 5A It is shown Figure 3 The circuit diagram shows an example of a control signal generation block and an output control signal generation block.

[0041] Figure 5B It is shown Figure 3 A circuit diagram of an example of the first gate signal control block.

[0042] Figure 5C It is shown Figure 3 The circuit diagram of the first gate signal output control block.

[0043] Figure 5D It is shown Figure 3 A circuit diagram of an example of the second gate signal control block.

[0044] Figure 5E It is shown Figure 3 The circuit diagram of the second gate signal output control block.

[0045] Figure 6 It shows that it is applied to Figure 5C The timing diagram of the first gate signal output control block.

[0046] Figure 7 It shows that it is applied to Figure 5E Timing diagram of the second gate signal output control block.

[0047] Figure 8 It shows that it is applied to Figure 2 A timing diagram of an example of the gate driver signal.

[0048] Figure 9 It shows that it is applied to Figure 5C The timing diagram of the first gate signal output control block.

[0049] Figure 10 It shows that it is applied to Figure 5E Timing diagram of the second gate signal output control block.

[0050] Figure 11 It is shown Figure 3 The control signal generation block and the output control signal generation block are in Figure 8 The circuit diagram for the operation in the third cycle.

[0051] Figure 12 It is shown Figure 3 The control signal generation block and the output control signal generation block are in Figure 8 The circuit diagram for the operation in the fifth cycle.

[0052] Figure 13 It is shown Figure 3 The first gate signal output control block in Figure 8 The circuit diagram for the operation in the fifth cycle.

[0053] Figure 14 It is shown Figure 3 The second gate signal output control block in Figure 8 The circuit diagram for the operation in the fifth cycle.

[0054] Figure 15 It is shown Figure 3 The first gate signal control block in Figure 8 The circuit diagram for the operation in the sixth cycle.

[0055] Figure 16 It is shown Figure 3 The second gate signal control block in Figure 8 The circuit diagram for the operation in the sixth cycle.

[0056] Figure 17 It shows that it is applied to Figure 2 A timing diagram of an example of the gate driver signal.

[0057] Figure 18 It shows that it is applied to Figure 2 A timing diagram of an example of the gate driver signal.

[0058] Figure 19 It shows that it is applied to Figure 2 A timing diagram of an example of the gate driver signal.

[0059] Figure 20 It is shown Figure 1 A circuit diagram of an example pixel.

[0060] Figure 21 It is shown Figure 3 A circuit diagram of an example of the first gate signal control block.

[0061] Figure 22 It is shown Figure 3 A circuit diagram of an example of the second gate signal control block.

[0062] Figure 23 This is a block diagram illustrating an example of an electronic device according to an embodiment. Detailed Implementation

[0063] The concept of the invention will be described in detail below with reference to the accompanying drawings.

[0064] Figure 1 It is shown Figure 1 A block diagram of an example of display device 1.

[0065] Reference Figure 1 The display device 1 may include a display panel 100 and a panel driver. The panel driver may include a drive controller 200, a gate driver 300, a gamma reference voltage generator 400, a data driver 500, and a sensor driver 600.

[0066] The display panel 100 may have a display area on which an image is displayed and a peripheral area adjacent to the display area.

[0067] The display panel 100 may include multiple gate lines GL, multiple data lines DL, multiple sensing lines SL, and multiple pixels PX electrically connected to the gate lines GL, data lines DL, and sensing lines SL. The gate lines GL may extend in a first direction D1. The data lines DL may extend in a second direction D2 intersecting the first direction D1. The sensing lines SL may extend in the second direction D2.

[0068] The drive controller 200 can receive input image data IMG and input control signals CONT from an external device. For example, the input image data IMG may include red image data, green image data, and blue image data. The input image data IMG may also include white image data. The input image data IMG may also include magenta image data, cyan image data, and yellow image data. The input control signal CONT may include a master clock signal and a data enable signal. The input control signal CONT may also include a vertical synchronization signal and a horizontal synchronization signal.

[0069] The drive controller 200 can generate a first control signal CONT1, a second control signal CONT2, a third control signal CONT3, a fourth control signal CONT4, and a data signal DATA based on the input image data IMG and the input control signal CONT.

[0070] The drive controller 200 can generate a first control signal CONT1 for controlling the operation of the gate driver 300 based on the input control signal CONT, and output the first control signal CONT1 to the gate driver 300. The first control signal CONT1 may include a vertical start signal and a gate clock signal.

[0071] The drive controller 200 can generate a second control signal CONT2 based on the input control signal CONT for controlling the operation of the data driver 500, and output the second control signal CONT2 to the data driver 500. The second control signal CONT2 may include a horizontal start signal and a load signal.

[0072] The drive controller 200 can generate a data signal DATA based on the input image data IMG. The drive controller 200 can output the data signal DATA to the data driver 500.

[0073] The drive controller 200 can generate a third control signal CONT3 based on the input control signal CONT for controlling the operation of the gamma reference voltage generator 400, and output the third control signal CONT3 to the gamma reference voltage generator 400.

[0074] The drive controller 200 can generate a fourth control signal CONT4 for controlling the operation of the sensor driver 600 based on the input control signal CONT, and output the fourth control signal CONT4 to the sensor driver 600.

[0075] The gate driver 300 can generate a gate signal for driving the gate line GL in response to a first control signal CONT1 received from the drive controller 200. For example, the gate signal may include a first gate signal and a second gate signal. For example, the first gate signal may be... Figure 2 The scan gate signal SC. For example, the second gate signal could be... Figure 2 The gate signal SS is sensed. The gate driver 300 can output the gate signal to the gate line GL.

[0076] In one embodiment, the gate driver 300 may be disposed in the peripheral region. Alternatively, the gate driver 300 may be integrated into the peripheral region.

[0077] The gamma reference voltage generator 400 generates a gamma reference voltage VGREF in response to a third control signal CONT3 received from the drive controller 200. The gamma reference voltage generator 400 provides the gamma reference voltage VGREF to the data driver 500. The gamma reference voltage VGREF has a value corresponding to the level of the data signal DATA.

[0078] In this embodiment, the gamma reference voltage generator 400 may be located in the drive controller 200 or in the data driver 500.

[0079] The data driver 500 receives a second control signal CONT2 and a data signal DATA from the drive controller 200, and receives a gamma reference voltage VGREF from the gamma reference voltage generator 400. The data driver 500 uses the gamma reference voltage VGREF to convert the data signal DATA into a data voltage VDATA of analog type. The data driver 500 outputs the data voltage VDATA to the data line DL.

[0080] In one embodiment, the data driver 500 may be located in the peripheral area. Alternatively, the data driver 500 may be integrated into the peripheral area.

[0081] The sense driver 600 can receive a fourth control signal CONT4 from the drive controller 200. The sense driver 600 can generate sense data SD by sensing pixels PX via sense lines SL. For example, during a blanking period, the sense driver 600 can sense at least one pixel in the pixel PX. For example, the sense driver 600 can sense the driving characteristics (e.g., mobility and / or threshold voltage) of the driving transistor of the pixel PX by measuring the sense current (or sense voltage) of the driving transistor via the sense line SL. For example, the operation of sensing the driving characteristics (e.g., mobility and / or threshold voltage) of the driving transistor can be referred to as a sensing operation.

[0082] Figure 2 It is shown that it includes Figure 1 A block diagram of the gate driver 300 in the display device 1.

[0083] Reference Figure 1 and Figure 2 The gate driver 300 may include multiple stages: a first stage STAGE 1, a second stage STAGE 2, a third stage STAGE 3 to an Nth stage STAGE N. At least one of the first stage STAGE 1, the second stage STAGE 2, the third stage STAGE 3 to the Nth stage STAGE N may output a gate signal based on a first input signal S1, a second input signal S2, a first clock signal, a second clock signal, a previous carry signal CR[n-1], and a subsequent carry signal CR[n+1]. The at least one stage may receive a clock signal corresponding to the gate signal generated by the at least one stage. However, the inventive concept is not limited to the number of gate signals output by the at least one stage.

[0084] For example, the first stage STAGE 1 can output the first scan gate signal SC[1] to the sixth scan gate signal SC[6] and the first sensing gate signal SS[1] to the sixth sensing gate signal SS[6]. The previous carry signal CR[n-1] of the first stage STAGE 1 can be the vertical start signal S5. The subsequent carry signal CR[n+1] of the first stage STAGE 1 can be the second stage carry signal CR[2]. The first stage STAGE 1 can output the first scan gate signal SC[1] to the sixth scan gate signal SC[6] and the first sensing gate signal SS[1] to the sixth sensing gate signal SS[6] based on the first input signal S1, the second input signal S2, the vertical start signal S5 and the second stage carry signal CR[2].

[0085] For example, the second stage STAGE 2 can output the seventh scan gate signal SC[7] to the twelfth scan gate signal SC

[12] and the seventh sensing gate signal SS[7] to the twelfth sensing gate signal SS

[12] . The previous carry signal CR[n-1] of the second stage STAGE 2 can be the first stage carry signal CR[1]. The subsequent carry signal CR[n+1] of the second stage STAGE 2 can be the third stage carry signal CR[3]. The second stage STAGE 2 can output the seventh scan gate signal SC[7] to the twelfth scan gate signal SC

[12] and the seventh sensing gate signal SS[7] to the twelfth sensing gate signal SS

[12] based on the first input signal S1, the second input signal S2, the first stage carry signal CR[1] and the third stage carry signal CR[3].

[0086] For example, STAGE 3 can output the thirteenth scan gate signal SC

[13] to the eighteenth scan gate signal SC

[18] and the thirteenth sense gate signal SS

[13] to the eighteenth sense gate signal SS

[18] . The previous carry signal CR[n-1] of STAGE 3 can be the second carry signal CR[2]. The subsequent carry signal CR[n+1] of STAGE 3 can be the fourth carry signal (not shown). STAGE 3 can output the thirteenth scan gate signal SC

[13] to the eighteenth scan gate signal SC

[18] and the thirteenth sense gate signal SS

[13] to the eighteenth sense gate signal SS

[18] based on the first input signal S1, the second input signal S2, the second carry signal CR[2] and the fourth carry signal.

[0087] For example, Stage N can output the (n-5)th scan gate signal SC[n-5] to the nth scan gate signal SC[n] and the (n-5)th sense gate signal SS[n-5] to the nth sense gate signal SS[n]. The previous carry signal CR[n-1] of Stage N can be the (N-1)th stage carry signal (not shown). The subsequent carry signal CR[n+1] of Stage N can be the third carry signal CR_CK3. Stage N can output the (n-5)th scan gate signal SC[n-5] to the nth scan gate signal SC[n] and the (n-5)th sense gate signal SS[n-5] to the nth sense gate signal SS[n] based on the first input signal S1, the second input signal S2, the (N-1)th stage carry signal, and the third carry signal CR_CK3. Here, N is a positive integer, and n is a positive integer greater than 5.

[0088] Figure 3 It is shown Figure 2 A block diagram of an example of a stage.

[0089] Reference Figures 1 to 3 The stage included in the gate driver 300 may include a control signal generation block 310, an output control signal generation block 320, a first gate signal control block 330, a first gate signal output control block 340, a second gate signal control block 350, and a second gate signal output control block 360.

[0090] The control signal generation block 310 can receive the previous first carry signal CR[n-1]_SC, the previous second carry signal CR[n-1]_SS, the subsequent first carry signal CR[n+1]_SC, the subsequent second carry signal CR[n+1]_SS, the first reset signal RST_SC, and the second reset signal RST_SS. The control signal generation block 310 can generate a first common control signal QCS_SC based on the previous first carry signal CR[n-1]_SC, the subsequent first carry signal CR[n+1]_SC, and the first reset signal RST_SC. The control signal generation block 310 can output the first common control signal QCS_SC to the first gate signal control block 330. The first common control signal QCS_SC can be applied to the first common control line QL_SC. The control signal generation block 310 can generate a second common control signal QCS_SS based on the previous second carry signal CR[n-1]_SS, the subsequent second carry signal CR[n+1]_SS, and the second reset signal RST_SS. The control signal generation block 310 can output the second common control signal QCS_SS to the second gate signal control block 350. The second common control signal QCS_SS can be applied to the second common control line QL_SS.

[0091] The output control signal generation block 320 can receive the first input signal S1, the second input signal S2, and the boost control signal BCR. The output control signal generation block 320 and the control signal generation block 310 can be connected via a first common control line QL_SC. The output control signal generation block 320 and the control signal generation block 310 can be connected via a second common control line QL_SS. The output control signal generation block 320 can generate an output control signal OCS based on the first input signal S1, the second input signal S2, and the boost control signal BCR. The output control signal generation block 320 can output the output control signal OCS to the first gate signal output control block 340. The output control signal generation block 320 can also output the output control signal OCS to the second gate signal output control block 360.

[0092] The first gate signal control block 330 can receive a first common control signal QCS_SC, a first output control voltage OV_SC, a boost clock signal BCK, and first gate clock signals SCCK[1] to SCCK[k]. The first gate signal control block 330 can generate first gate signals SC[1] to SC[k] and a boost control signal BCR based on the first common control signal QCS_SC, the first output control voltage OV_SC, the boost clock signal BCK, and the first gate clock signals SCCK[1] to SCCK[k]. The first output control voltage OV_SC can have a first high voltage or a second high voltage lower than the first high voltage. When the first output control voltage OV_SC has a first high voltage, the first gate signals SC[1] to SC[k] with an active level can be output. When the first output control voltage OV_SC has a second high voltage, the first gate signals SC[1] to SC[k] can have an inactive level. For example, the first gate signals SC[1] to SC[k] with an active level can be output sequentially. For example, the first gate signals SC[1] to SC[k] can refer to the scan gate signals. For example, when the first output control voltage OV_SC has a first high voltage, the first scan gate signals to the Kth scan gate signals with active levels can be output sequentially. For example, when the first output control voltage OV_SC has a first high voltage, the first gate signals SC[1] to SC[k] corresponding to the first gate clock signals SCCK[1] to SCCK[k] can be output. For example, when the first output control voltage OV_SC has a second high voltage, the first scan gate signals to the Kth scan gate signals can have inactive levels. The first gate signal control block 330 can output the boost control signal BCR based on the boost clock signal BCK.

[0093] The first gate signal output control block 340 can receive the output control signal OCS, the previous first carry signal CR[n-1]_SC, the second input signal S2, and the subsequent first carry signal CR[n+1]_SC. The first gate signal output control block 340 can output a first output control voltage OV_SC based on the output control signal OCS, the previous first carry signal CR[n-1]_SC, and the subsequent first carry signal CR[n+1]_SC.

[0094] The second gate signal control block 350 can receive a second common control signal QCS_SS, a second output control voltage OV_SS, a boost clock signal BCK, and second gate clock signals SSCK[1] to SSCK[k]. The second gate signal control block 350 can generate second gate signals SS[1] to SS[k] based on the second common control signal QCS_SS, the second output control voltage OV_SS, the boost clock signal BCK, and the second gate clock signals SSCK[1] to SSCK[k]. The second output control voltage OV_SS can have a first high voltage or a second high voltage. When the second output control voltage OV_SS has a first high voltage, the second gate signals SS[1] to SS[k] with an active level can be output. When the second output control voltage OV_SS has a second high voltage, the second gate signals SS[1] to SS[k] can have an inactive level. For example, the second gate signals SS[1] to SS[k] with an active level can be output sequentially. For example, the second gate signals SS[1] to SS[k] can refer to a sense gate signal. For example, when the second output control voltage OV_SS has a first high voltage, the first sensing gate signal to the Kth sensing gate signal, which have an active level, can be output sequentially. For example, when the second output control voltage OV_SS has a first high voltage, the second gate signals SS[1] to SS[k], which correspond to the second gate clock signals SSCK[1] to SSCK[k], can be output. For example, when the second output control voltage OV_SS has a second high voltage, the first sensing gate signal to the Kth sensing gate signal can have an inactive level.

[0095] The second gate signal output control block 360 can receive the output control signal OCS, the previous second carry signal CR[n-1]_SS, the second input signal S2, and the subsequent second carry signal CR[n+1]_SS. The second gate signal output control block 360 can output a second output control voltage OV_SS based on the output control signal OCS, the previous second carry signal CR[n-1]_SS, and the subsequent second carry signal CR[n+1]_SS. Here, K is a positive integer less than or equal to N, and k is a positive integer less than or equal to n.

[0096] Figure 4 It shows that it is applied to Figure 2 Gate driver 300 (see Figure 1 A timing diagram of an example of a signal. Figure 5A It is shown Figure 3 The circuit diagram shows an example of the control signal generation block 310 and the output control signal generation block 320. Figure 5B It is shown Figure 3 A circuit diagram of an example of the first gate signal control block 330. Figure 5CIt is shown Figure 3 The circuit diagram of the first gate signal output control block 340. Figure 5D It is shown Figure 3 A circuit diagram of an example of the second gate signal control block 350. Figure 5E It is shown Figure 3 The circuit diagram of the second gate signal output control block 360. Figure 6 It shows that it is applied to Figure 5C Timing diagram of the first gate signal output control block 340. Figure 7 It shows that it is applied to Figure 5E Timing diagram of the second gate signal output control block 360.

[0097] Reference Figure 4 The frame period during which the gate driver 300 is driven may include a first period TP1A, a second period TP2A, a third period TP3A, and a fourth period TP4A. For example, the frame period during which the gate driver 300 is driven may include an active period during which the gate signal is output and a blanking period. In this embodiment, the active period may include the first period TP1A, the second period TP2A, and the third period TP3A. The blanking period may include the fourth period TP4A. For example, the operation of the gate driver 300 during the frame period including the first period TP1A, the second period TP2A, the third period TP3A, and the fourth period TP4A may be referred to as a first operation MODE 1. For example, the first operation MODE 1 may be referred to as normal operation.

[0098] Reference Figures 1 to 7 The control signal generation block 310 may include a first scan gate transistor T1_SC, a second scan gate transistor T2_SC, a third scan gate transistor T3_SC, a fourth scan gate transistor T4_SC, a fifth scan gate transistor T5_SC, a sixth scan gate transistor T6_SC, a seventh scan gate transistor T7_SC, an eighth scan gate transistor T8_SC, a ninth scan gate transistor T9_SC, a tenth scan gate transistor T10_SC, an eleventh scan gate transistor T11_SC, a twelfth scan gate transistor T12_SC, a thirteenth scan gate transistor T13_SC, a fourteenth scan gate transistor T14_SC, a fifteenth scan gate transistor T15_SC, a sixteenth scan gate transistor T16_SC, and a seventeenth scan gate transistor T17_SC (see See Figure 5A ).

[0099] The first scan gate transistor T1_SC may include a control electrode that receives a first reset signal RST_SC, a first electrode connected to the first scan node SCN1, and a second electrode that receives a first low voltage VGL1. The first scan gate transistor T1_SC may apply the first low voltage VGL1 to the first scan node SCN1 in response to the first reset signal RST_SC. For example, the first scan gate transistor T1_SC may initialize the first scan node SCN1 to the first low voltage VGL1 in response to the first reset signal RST_SC.

[0100] The second scan gate transistor T2_SC may include a control electrode receiving a first reset signal RST_SC, a first electrode connected to a first common control node Q_SC, and a second electrode connected to a first scan node SCN1. The second scan gate transistor T2_SC may connect the first common control node Q_SC and the first scan node SCN1 in response to the first reset signal RST_SC. Therefore, the first common control node Q_SC may be initialized to a first low voltage VGL1 in response to the first reset signal RST_SC.

[0101] The third scan gate transistor T3_SC may include a control electrode that receives a subsequent first carry signal CR[n+1]_SC, a first electrode connected to the first scan node SCN1, and a second electrode that receives a first low voltage VGL1. The third scan gate transistor T3_SC may apply the first low voltage VGL1 to the first scan node SCN1 in response to the subsequent first carry signal CR[n+1]_SC. For example, the third scan gate transistor T3_SC may initialize the first scan node SCN1 to the first low voltage VGL1 in response to the subsequent first carry signal CR[n+1]_SC.

[0102] The fourth scan gate transistor T4_SC may include a control electrode that receives a subsequent first carry signal CR[n+1]_SC, a first electrode connected to the first common control node Q_SC, and a second electrode connected to the first scan node SCN1. The fourth scan gate transistor T4_SC may connect the first common control node Q_SC and the first scan node SCN1 in response to the subsequent first carry signal CR[n+1]_SC. Therefore, the first common control node Q_SC may be initialized to a first low voltage VGL1 in response to the subsequent first carry signal CR[n+1]_SC.

[0103] The fifth scan gate transistor T5_SC may include a control electrode connected to the first inverting common control node QB_SC, a first electrode connected to the first scan node SCN1, and a second electrode receiving a first low voltage VGL1. The fifth scan gate transistor T5_SC may apply the first low voltage VGL1 to the first scan node SCN1 in response to the voltage of the first inverting common control node QB_SC.

[0104] The sixth scan gate transistor T6_SC may include a control electrode connected to the first inverting common control node QB_SC, a first electrode connected to the first common control node Q_SC, and a second electrode connected to the first scan node SCN1. The sixth scan gate transistor T6_SC can connect the first common control node Q_SC and the first scan node SCN1 in response to the voltage of the first inverting common control node QB_SC. The first inverting common control node QB_SC can be connected to the first inverting common control line QBL_SC.

[0105] The seventh scan gate transistor T7_SC may include a control electrode that receives the previous first carry signal CR[n-1]_SC, a first electrode that receives the previous first carry signal CR[n-1]_SC, and a second electrode connected to the first scan node SCN1.

[0106] The eighth scan gate transistor T8_SC may include a control electrode that receives the previous first carry signal CR[n-1]_SC, a first electrode connected to the first scan node SCN1, and a second electrode connected to the first common control node Q_SC. The eighth scan gate transistor T8_SC may connect the first scan node SCN1 and the first common control node Q_SC in response to the previous first carry signal CR[n-1]_SC. The first common control node Q_SC may be connected to the first common control line QL_SC.

[0107] The ninth scan gate transistor T9_SC may include a control electrode connected to the second scan node SCN2, a first electrode receiving the second high voltage VGH2, and a second electrode connected to the first electrode of the thirteenth scan gate transistor T13_SC.

[0108] The tenth scan gate transistor T10_SC may include a control electrode receiving a second high voltage VGH2, a first electrode receiving the second high voltage VGH2, and a second electrode connected to the first electrode of the eleventh scan gate transistor T11_SC. The eleventh scan gate transistor T11_SC may include a control electrode receiving the second high voltage VGH2, a first electrode connected to the second electrode of the tenth scan gate transistor T10_SC, and a second electrode connected to the second scan node SCN2. The tenth scan gate transistor T10_SC and the eleventh scan gate transistor T11_SC may be connected in series. In an embodiment, the tenth scan gate transistor T10_SC and the eleventh scan gate transistor T11_SC may be configured as a single transistor.

[0109] The twelfth scan gate transistor T12_SC may include a control electrode connected to the first common control node Q_SC, a first electrode connected to the second scan node SCN2, and a second electrode receiving a second low voltage VGL2. The second low voltage VGL2 may be higher than the first low voltage VGL1. For example, the first low voltage VGL1 may be approximately -9V. For example, the second low voltage VGL2 may be approximately -5V. However, the inventive concept is not limited to the values ​​of the first low voltage VGL1 and the second low voltage VGL2.

[0110] The thirteenth scan gate transistor T13_SC may include a control electrode connected to the first common control node Q_SC, a first electrode connected to the second electrode of the ninth scan gate transistor T9_SC, and a second electrode receiving a first low voltage VGL1.

[0111] The fourteenth scanning gate transistor T14_SC may include a control electrode that receives the second input signal S2, a first electrode that is connected to the second electrode of the fifteenth scanning gate transistor T15_SC, and a second electrode that receives the first low voltage VGL1.

[0112] The fifteenth scanning gate transistor T15_SC may include a control electrode that receives the boost control signal BCR, a first electrode connected to the first inverting common control node QB_SC, and a second electrode connected to the first electrode of the fourteenth scanning gate transistor T14_SC.

[0113] The sixteenth scan gate transistor T16_SC may include a control electrode connected to the first common control node Q_SC, a first electrode receiving a first high voltage VGH1, and a second electrode connected to the first electrode of the seventeenth scan gate transistor T17_SC. The seventeenth scan gate transistor T17_SC may include a control electrode connected to the first common control node Q_SC, a first electrode connected to the second electrode of the sixteenth scan gate transistor T16_SC, and a second electrode connected to the first scan node SCN1. Therefore, the first high voltage VGH1 can be applied to the first scan node SCN1 in response to the voltage of the first common control node Q_SC. The sixteenth scan gate transistor T16_SC and the seventeenth scan gate transistor T17_SC may be connected in series. In an embodiment, the sixteenth scan gate transistor T16_SC and the seventeenth scan gate transistor T17_SC may be formed as a single transistor. The first high voltage VGH1 may be higher than the second high voltage VGH2. For example, the first high voltage VGH1 may be approximately 25V. For example, the second high voltage VGH2 may be approximately 15V. However, the present invention is not limited to the values ​​of the first high voltage VGH1 and the second high voltage VGH2.

[0114] In this embodiment, the first common control node Q_SC can output a first common control signal QCS_SC. The first common control signal QCS_SC can be applied to the first common control line QL_SC.

[0115] The output control signal generation block 320 may include a first output control transistor OCT1, a second output control transistor OCT2, a third output control transistor OCT3, a fourth output control transistor OCT4, a fifth output control transistor OCT5, and an output control capacitor OCC.

[0116] The first output control transistor OCT1 may include a control electrode that receives a first input signal S1, a first electrode that receives a boost control signal BCR, and a second electrode connected to the first output control node OCN1. The first output control transistor OCT1 may apply the boost control signal BCR to the first output control node OCN1 in response to the first input signal S1.

[0117] The second output control transistor OCT2 may include a control electrode receiving the first input signal S1, a first electrode connected to the first output control node OCN1, and a second electrode connected to the second output control node OCN2. The second output control transistor OCT2 may connect the first output control node OCN1 and the second output control node OCN2 in response to the first input signal S1. For example, the second output control transistor OCT2 may apply a boost control signal BCR to the second output control node OCN2 in response to the first input signal S1.

[0118] The third output control transistor OCT3 may include a control electrode connected to the second output control node OCN2, a first electrode receiving a first high voltage VGH1, and a second electrode connected to the first output control node OCN1. The third output control transistor OCT3 may apply the first high voltage VGH1 to the first output control node OCN1 in response to the voltage of the second output control node OCN2.

[0119] The fourth output control transistor OCT4 may include a control electrode that receives the second input signal S2, a first electrode connected to the first output control node OCN1, and a second electrode connected to the first common control node Q_SC. The fourth output control transistor OCT4 may connect the first output control node OCN1 and the first common control node Q_SC in response to the second input signal S2.

[0120] The fifth output control transistor OCT5 may include a control electrode that receives the second input signal S2, a first electrode connected to the first output control node OCN1, and a second electrode connected to the second common control node Q_SS. The fifth output control transistor OCT5 may connect the first output control node OCN1 and the second common control node Q_SS in response to the second input signal S2.

[0121] The output control capacitor OCC may include a first electrode receiving a first high voltage VGH1 and a second electrode connected to a second output control node OCN2. The output control capacitor OCC may store the voltage of the second output control node OCN2. For example, the second output control node OCN2 may store a boost control signal BCR applied to the second output control node OCN2.

[0122] In this embodiment, the first output control node OCN1 can output the output control signal OCS. The first gate signal control block 330 may include a first signal generating transistor BT1_SC, a second signal generating transistor BT2_SC, a third signal generating transistor BT3_SC, a fourth signal generating transistor BT4_SC, a fifth signal generating transistor BT5_SC, a sixth signal generating transistor BT6_SC, a seventh signal generating transistor BT7_SC, an eighth signal generating transistor BT8_SC, a ninth signal generating transistor BT9_SC, a tenth signal generating transistor BT10_SC, an eleventh signal generating transistor BT11_SC, a twelfth signal generating transistor BT12_SC, a thirteenth signal generating transistor BT13_SC, a fourteenth signal generating transistor BT14_SC, a fifteenth signal generating transistor BT14_SC, and a fifteenth signal generating transistor BT15_SC. Signal generating transistors BT15_SC, BT16_SC, BT17_SC, BT18_SC, BT19_SC, BT20_SC, BT21_SC, BT22_SC, and BCC1_SC, BCC2_SC, BCC3_SC, BCC4_SC, BCC5_SC, BCC6_SC, and BCC7_SC (see also...) Figure 5B ).

[0123] The first signal generating transistor BT1_SC may include a control electrode connected to a first common control line QL_SC, a first electrode receiving a boost clock signal BCK, and a second electrode connected to a boost control node BCRN_SC. The first signal generating transistor BT1_SC may apply the boost clock signal BCK to the boost control node BCRN_SC in response to the first common control signal QCS_SC. The boost control node BCRN_SC may output a boost control signal BCR. The boost control node BCRN_SC may be connected to a boost control line BCRL_SC.

[0124] The second signal generating transistor BT2_SC may include a control electrode connected to the first inverting common control line QBL_SC, a first electrode connected to the boost control node BCRN_SC, and a second electrode receiving a first low voltage VGL1. The second signal generating transistor BT2_SC can apply the first low voltage VGL1 to the boost control node BCRN_SC in response to the voltage of the first inverting common control node QB_SC.

[0125] The third signal generating transistor BT3_SC may include a control electrode connected to the first common control line QL_SC, a first electrode receiving the first carry clock signal CRCK_SC, and a second electrode connected to the first carry output node CON1_SC. The first carry output node CON1_SC can output the first carry signal CR[n]_SC.

[0126] The fourth signal generating transistor BT4_SC may include a control electrode connected to the first inverting common control line QBL_SC, a first electrode connected to the first carry output node CON1_SC, and a second electrode receiving a second low voltage VGL2. The fourth signal generating transistor BT4_SC can apply the second low voltage VGL2 to the first carry output node CON1_SC in response to the voltage of the first inverting common control node QB_SC.

[0127] The fifth signal generating transistor BT5_SC may include a control electrode connected to the first signal generating node GN1_SC, a first electrode receiving the first scan clock signal SCCK[1], and a second electrode connected to the second signal generating node GN2_SC. The fifth signal generating transistor BT5_SC may apply the first scan clock signal SCCK[1] to the second signal generating node GN2_SC in response to the voltage of the first signal generating node GN1_SC. The second signal generating node GN2_SC may output the first scan gate signal SC[1].

[0128] The sixth signal generating transistor BT6_SC may include a control electrode receiving the first output control voltage OV_SC, a first electrode connected to the first common control line QL_SC, and a second electrode connected to the first signal generating node GN1_SC. The sixth signal generating transistor BT6_SC may apply a first common control signal QCS_SC to the first signal generating node GN1_SC in response to the first output control voltage OV_SC. The sixth signal generating transistor BT6_SC may be turned on when the first output control voltage OV_SC has a first high voltage VGH1. The sixth signal generating transistor BT6_SC being turned on allows the first common control signal QCS_SC to be applied to the first signal generating node GN1_SC. The first common control signal QCS_SC being applied to the first signal generating node GN1_SC allows the fifth signal generating transistor BT5_SC to be turned on. Therefore, the first scan clock signal SCCK[1] may be applied to the second signal generating node GN2_SC. Therefore, the first scan gate signal SC[1] corresponding to the first scan clock signal SCCK[1] may be output. When the first output control voltage OV_SC has a second high voltage VGH2, the sixth signal generation transistor BT6_SC can be turned off.

[0129] The seventh signal generating transistor BT7_SC may include a control electrode connected to the first inverting common control line QBL_SC, a first electrode connected to the second signal generating node GN2_SC, and a second electrode receiving a second low voltage VGL2. The seventh signal generating transistor BT7_SC may apply the second low voltage VGL2 to the second signal generating node GN2_SC in response to the voltage of the first inverting common control node QB_SC.

[0130] The eighth signal generating transistor BT8_SC may include a control electrode connected to the third signal generating node GN3_SC, a first electrode receiving the second scan clock signal SCCK[2], and a second electrode connected to the fourth signal generating node GN4_SC. The eighth signal generating transistor BT8_SC may apply the second scan clock signal SCCK[2] to the fourth signal generating node GN4_SC in response to the voltage of the third signal generating node GN3_SC. The fourth signal generating node GN4_SC may output the second scan gate signal SC[2].

[0131] The ninth signal generating transistor BT9_SC may include a control electrode receiving the first output control voltage OV_SC, a first electrode connected to the first common control line QL_SC, and a second electrode connected to the third signal generating node GN3_SC. The ninth signal generating transistor BT9_SC may apply the first common control signal QCS_SC to the third signal generating node GN3_SC in response to the first output control voltage OV_SC. The ninth signal generating transistor BT9_SC may be turned on when the first output control voltage OV_SC has a first high voltage VGH1. The ninth signal generating transistor BT9_SC being turned on allows the first common control signal QCS_SC to be applied to the third signal generating node GN3_SC. The first common control signal QCS_SC being applied to the third signal generating node GN3_SC allows the eighth signal generating transistor BT8_SC to be turned on. Therefore, the second scan clock signal SCCK[2] may be applied to the fourth signal generating node GN4_SC. Therefore, the second scan gate signal SC[2] corresponding to the second scan clock signal SCCK[2] may be output. When the first output control voltage OV_SC has a second high voltage VGH2, the ninth signal generation transistor BT9_SC can be turned off.

[0132] The tenth signal generating transistor BT10_SC may include a control electrode connected to the first inverting common control line QBL_SC, a first electrode connected to the fourth signal generating node GN4_SC, and a second electrode receiving a second low voltage VGL2. The tenth signal generating transistor BT10_SC may apply the second low voltage VGL2 to the fourth signal generating node GN4_SC in response to the voltage of the first inverting common control node QB_SC.

[0133] The eleventh signal generating transistor BT11_SC may include a control electrode connected to the fifth signal generating node GN5_SC, a first electrode receiving the third scan clock signal SCCK[3], and a second electrode connected to the sixth signal generating node GN6_SC. The eleventh signal generating transistor BT11_SC may apply the third scan clock signal SCCK[3] to the sixth signal generating node GN6_SC in response to the voltage of the fifth signal generating node GN5_SC. The sixth signal generating node GN6_SC may output the third scan gate signal SC[3].

[0134] The twelfth signal generating transistor BT12_SC may include a control electrode receiving the first output control voltage OV_SC, a first electrode connected to the first common control line QL_SC, and a second electrode connected to the fifth signal generating node GN5_SC. The twelfth signal generating transistor BT12_SC may apply a first common control signal QCS_SC to the fifth signal generating node GN5_SC in response to the first output control voltage OV_SC. The twelfth signal generating transistor BT12_SC may be turned on when the first output control voltage OV_SC has a first high voltage VGH1. The twelfth signal generating transistor BT12_SC being turned on allows the first common control signal QCS_SC to be applied to the fifth signal generating node GN5_SC. The first common control signal QCS_SC being applied to the fifth signal generating node GN5_SC allows the eleventh signal generating transistor BT11_SC to be turned on. Therefore, the third scan clock signal SCCK[3] may be applied to the sixth signal generating node GN6_SC. Therefore, the third scan gate signal SC[3] corresponding to the third scan clock signal SCCK[3] may be output. When the first output control voltage OV_SC has a second high voltage VGH2, the twelfth signal generation transistor BT12_SC can be turned off.

[0135] The thirteenth signal generating transistor BT13_SC may include a control electrode connected to the first inverting common control line QBL_SC, a first electrode connected to the sixth signal generating node GN6_SC, and a second electrode receiving a second low voltage VGL2. The thirteenth signal generating transistor BT13_SC may apply the second low voltage VGL2 to the sixth signal generating node GN6_SC in response to the voltage of the first inverting common control node QB_SC.

[0136] The fourteenth signal generating transistor BT14_SC may include a control electrode connected to the seventh signal generating node GN7_SC, a first electrode receiving the fourth scan clock signal SCCK[4], and a second electrode connected to the eighth signal generating node GN8_SC. The fourteenth signal generating transistor BT14_SC may apply the fourth scan clock signal SCCK[4] to the eighth signal generating node GN8_SC in response to the voltage of the seventh signal generating node GN7_SC. The eighth signal generating node GN8_SC may output the fourth scan gate signal SC[4].

[0137] The fifteenth signal generating transistor BT15_SC may include a control electrode receiving the first output control voltage OV_SC, a first electrode connected to the first common control line QL_SC, and a second electrode connected to the seventh signal generating node GN7_SC. The fifteenth signal generating transistor BT15_SC may apply the first common control signal QCS_SC to the seventh signal generating node GN7_SC in response to the first output control voltage OV_SC. The fifteenth signal generating transistor BT15_SC may be turned on when the first output control voltage OV_SC has a first high voltage VGH1. The fifteenth signal generating transistor BT15_SC being turned on allows the first common control signal QCS_SC to be applied to the seventh signal generating node GN7_SC. The first common control signal QCS_SC being applied to the seventh signal generating node GN7_SC allows the fourteenth signal generating transistor BT14_SC to be turned on. Therefore, the fourth scan clock signal SCCK[4] may be applied to the eighth signal generating node GN8_SC. Therefore, the fourth scan gate signal SC[4] corresponding to the fourth scan clock signal SCCK[4] may be output. When the first output control voltage OV_SC has a second high voltage VGH2, the fifteenth signal generation transistor BT15_SC can be turned off.

[0138] The sixteenth signal generating transistor BT16_SC may include a control electrode connected to the first inverting common control line QBL_SC, a first electrode connected to the eighth signal generating node GN8_SC, and a second electrode receiving a second low voltage VGL2. The sixteenth signal generating transistor BT16_SC may apply the second low voltage VGL2 to the eighth signal generating node GN8_SC in response to the voltage of the first inverting common control node QB_SC.

[0139] The seventeenth signal generating transistor BT17_SC may include a control electrode connected to the ninth signal generating node GN9_SC, a first electrode receiving the fifth scan clock signal SCCK[5], and a second electrode connected to the tenth signal generating node GN10_SC. The seventeenth signal generating transistor BT17_SC may apply the fifth scan clock signal SCCK[5] to the tenth signal generating node GN10_SC in response to the voltage of the ninth signal generating node GN9_SC. The tenth signal generating node GN10_SC may output the fifth scan gate signal SC[5].

[0140] The eighteenth signal generating transistor BT18_SC may include a control electrode receiving the first output control voltage OV_SC, a first electrode connected to the first common control line QL_SC, and a second electrode connected to the ninth signal generating node GN9_SC. The eighteenth signal generating transistor BT18_SC may apply the first common control signal QCS_SC to the ninth signal generating node GN9_SC in response to the first output control voltage OV_SC. The eighteenth signal generating transistor BT18_SC may be turned on when the first output control voltage OV_SC has a first high voltage VGH1. The eighteenth signal generating transistor BT18_SC being turned on allows the first common control signal QCS_SC to be applied to the ninth signal generating node GN9_SC. The first common control signal QCS_SC being applied to the ninth signal generating node GN9_SC allows the seventeenth signal generating transistor BT17_SC to be turned on. Therefore, the fifth scan clock signal SCCK[5] may be applied to the tenth signal generating node GN10_SC. Therefore, the fifth scan gate signal SC[5] corresponding to the fifth scan clock signal SCCK[5] may be output. When the first output control voltage OV_SC has a second high voltage VGH2, the eighteenth signal generation transistor BT18_SC can be turned off.

[0141] The nineteenth signal generating transistor BT19_SC may include a control electrode connected to the first inverting common control line QBL_SC, a first electrode connected to the tenth signal generating node GN10_SC, and a second electrode receiving a second low voltage VGL2. The nineteenth signal generating transistor BT19_SC may apply the second low voltage VGL2 to the tenth signal generating node GN10_SC in response to the voltage of the first inverting common control node QB_SC.

[0142] The twentieth signal generating transistor BT20_SC may include a control electrode connected to the eleventh signal generating node GN11_SC, a first electrode receiving the sixth scan clock signal SCCK[6], and a second electrode connected to the twelfth signal generating node GN12_SC. The twentieth signal generating transistor BT20_SC may apply the sixth scan clock signal SCCK[6] to the twelfth signal generating node GN12_SC in response to the voltage of the eleventh signal generating node GN11_SC. The twelfth signal generating node GN12_SC may output the sixth scan gate signal SC[6].

[0143] The 21st signal generating transistor BT21_SC may include a control electrode receiving the first output control voltage OV_SC, a first electrode connected to the first common control line QL_SC, and a second electrode connected to the 11th signal generating node GN11_SC. The 21st signal generating transistor BT21_SC may apply the first common control signal QCS_SC to the 11th signal generating node GN11_SC in response to the first output control voltage OV_SC. The 21st signal generating transistor BT21_SC may be turned on when the first output control voltage OV_SC has a first high voltage VGH1. The 21st signal generating transistor BT21_SC is turned on, so that the first common control signal QCS_SC may be applied to the 11th signal generating node GN11_SC. The first common control signal QCS_SC may be applied to the 11th signal generating node GN11_SC, so that the 20th signal generating transistor BT20_SC is turned on. Therefore, the sixth scan clock signal SCCK[6] may be applied to the 12th signal generating node GN12_SC. Therefore, the sixth scan gate signal SC[6] corresponding to the sixth scan clock signal SCCK[6] can be output. When the first output control voltage OV_SC has a second high voltage VGH2, the twenty-first signal generation transistor BT21_SC can be turned off.

[0144] The 22nd signal generating transistor BT22_SC may include a control electrode connected to the first inverting common control line QBL_SC, a first electrode connected to the 12th signal generating node GN12_SC, and a second electrode for receiving a second low voltage VGL2. The 22nd signal generating transistor BT22_SC may apply the second low voltage VGL2 to the 12th signal generating node GN12_SC in response to the voltage of the first inverting common control node QB_SC.

[0145] The first boost capacitor BCC1_SC may include a first electrode connected to the first common control node Q_SC and a second electrode connected to the boost control node BCRN_SC. The second boost capacitor BCC2_SC may include a first electrode connected to the first signal generation node GN1_SC and a second electrode connected to the boost control node BCRN_SC. The third boost capacitor BCC3_SC may include a first electrode connected to the third signal generation node GN3_SC and a second electrode connected to the boost control node BCRN_SC. The fourth boost capacitor BCC4_SC may include a first electrode connected to the fifth signal generation node GN5_SC and a second electrode connected to the boost control node BCRN_SC. The fifth boost capacitor BCC5_SC may include a first electrode connected to the seventh signal generation node GN7_SC and a second electrode connected to the boost control node BCRN_SC. The sixth boost capacitor BCC6_SC may include a first electrode connected to the ninth signal generation node GN9_SC and a second electrode connected to the boost control node BCRN_SC. The seventh boost capacitor BCC7_SC may include a first electrode connected to the eleventh signal generation node GN11_SC and a second electrode connected to the boost control node BCRN_SC.

[0146] The first gate signal output control block 340 may include a first output transistor CT1_SC, a second output transistor CT2_SC, a third output transistor CT3_SC, a fourth output transistor CT4_SC, and a fifth output transistor CT5_SC (see [link to documentation]). Figure 5C ).

[0147] The first output transistor CT1_SC may include a control electrode that receives a previous first carry signal CR[n-1]_SC, a first electrode that receives a first high voltage VGH1, and a second electrode connected to the first electrode of the second output transistor CT2_SC. The second output transistor CT2_SC may include a control electrode that receives a previous first carry signal CR[n-1]_SC, a first electrode connected to the second electrode of the first output transistor CT1_SC, and a second electrode connected to the first output node OVN_SC. The first output transistor CT1_SC and the second output transistor CT2_SC may be connected in series. In an embodiment, the first output transistor CT1_SC and the second output transistor CT2_SC may be configured as a single transistor. The first output transistor CT1_SC and the second output transistor CT2_SC may be turned on in response to the previous first carry signal CR[n-1]_SC. When the first output transistor CT1_SC and the second output transistor CT2_SC are turned on, the first high voltage VGH1 may be applied to the first output node OVN_SC. When the first high voltage VGH1 is applied to the first output node OVN_SC, the first output control voltage OV_SC can have the first high voltage VGH1.

[0148] The third output transistor CT3_SC may include a control electrode connected to the boost control line BCRL_SC, a first electrode receiving the second high voltage VGH2, and a second electrode connected to the first output node OVN_SC. The third output transistor CT3_SC may apply the second high voltage VGH2 to the first output node OVN_SC in response to the boost control signal BCR. When the second high voltage VGH2 is applied to the first output node OVN_SC, the first output control voltage OV_SC may have the second high voltage VGH2.

[0149] The fourth output transistor CT4_SC may include a control electrode that receives a subsequent first carry signal CR[n+1]_SC, a first electrode that receives a second high voltage VGH2, and a second electrode connected to the first output node OVN_SC. The fourth output transistor CT4_SC may apply the second high voltage VGH2 to the first output node OVN_SC in response to the subsequent first carry signal CR[n+1]_SC.

[0150] The fifth output transistor CT5_SC may include a control electrode that receives the second input signal S2, a first electrode that receives the output control signal OCS, and a second electrode connected to the first output node OVN_SC. The fifth output transistor CT5_SC may apply the output control signal OCS to the first output node OVN_SC in response to the second input signal S2.

[0151] In the first cycle TP1A, the first input signal S1 may have an active level, and the vertical start signal S5_SC may also have an active level. In an embodiment, the vertical start signal S5_SC may be the previous first carry signal CR[n-1]_SC.

[0152] In the first cycle TP1A, the seventh scan gate transistor T7_SC and the eighth scan gate transistor T8_SC can be turned on in response to the vertical start signal S5_SC. The turn-on of the seventh scan gate transistor T7_SC and the eighth scan gate transistor T8_SC allows the vertical start signal S5_SC, with an activation level, to be applied to the first common control node Q_SC. For example, the activation level voltage of the vertical start signal S5_SC can be a first high voltage VGH1. In the first cycle TP1A, the first common control node Q_SC can have a first high voltage VGH1. The thirteenth scan gate transistor T13_SC can be turned on in response to the voltage of the first common control node Q_SC. The turn-on of the thirteenth scan gate transistor T13_SC allows a first low voltage VGL1 to be applied to the first inverting common control node QB_SC. In the first cycle TP1A, the first common control signal QCS_SC, with the first high voltage VGH1, can be output to the first common control line QL_SC. The first signal generating transistor BT1_SC and the third signal generating transistor BT3_SC can be turned on in response to the first common control signal QCS_SC.

[0153] In the first cycle TP1A, the first output transistor CT1_SC and the second output transistor CT2_SC can be turned on in response to the vertical start signal S5_SC. The turn-on of the first output transistor CT1_SC and the second output transistor CT2_SC allows a first high voltage VGH1 to be applied to the first output node OVN_SC. Therefore, the first output control voltage OV_SC can have a first high voltage VGH1. In response to the first output control voltage OV_SC, the sixth signal generation transistor BT6_SC, the ninth signal generation transistor BT9_SC, the twelfth signal generation transistor BT12_SC, the fifteenth signal generation transistor BT15_SC, the eighteenth signal generation transistor BT18_SC, and the twenty-first signal generation transistor BT21_SC can be turned on. The sixth signal generating transistor BT6_SC, the ninth signal generating transistor BT9_SC, the twelfth signal generating transistor BT12_SC, the fifteenth signal generating transistor BT15_SC, the eighteenth signal generating transistor BT18_SC, and the twenty-first signal generating transistor BT21_SC can be turned on, so that the fifth signal generating transistor BT5_SC, the eighth signal generating transistor BT8_SC, the eleventh signal generating transistor BT11_SC, the fourteenth signal generating transistor BT14_SC, the seventeenth signal generating transistor BT17_SC, and the twentieth signal generating transistor BT20_SC can be turned on.

[0154] In the second cycle TP2A, the first-stage boost clock signal BCK1 can have an active level. The first signal generating transistor BT1_SC can be turned on based on the first-stage boost clock signal BCK1 and the first common control signal QCS_SC of the first stage with a first high voltage VGH1. Therefore, the first-stage boost clock signal BCK1 can be applied to the boost control node BCRN_SC. Therefore, the boost control signal BCR with an active level can be output. In response to the boost control signal BCR with an active level, the third output transistor CT3_SC can be turned on. The third output transistor CT3_SC can be turned on, so that a second high voltage VGH2, which is lower than the first high voltage VGH1, can be output to the first output node OVN_SC. Therefore, the first output control voltage OV_SC can have the second high voltage VGH2. Based on the first output control voltage OV_SC with a second high voltage VGH2 and the first common control signal QCS_SC with a first high voltage VGH1, the sixth signal generating transistor BT6_SC, the ninth signal generating transistor BT9_SC, the twelfth signal generating transistor BT12_SC, the fifteenth signal generating transistor BT15_SC, the eighteenth signal generating transistor BT18_SC, and the twenty-first signal generating transistor BT21_SC can be turned off. The sixth signal generating transistor BT6_SC, the ninth signal generating transistor BT9_SC, the twelfth signal generating transistor BT12_SC, the fifteenth signal generating transistor BT15_SC, the eighteenth signal generating transistor BT18_SC, and the twenty-first signal generating transistor BT21_SC can be turned off, allowing the first signal generating node GN1_SC, the third signal generating node GN3_SC, the fifth signal generating node GN5_SC, the seventh signal generating node GN7_SC, the ninth signal generating node GN9_SC, and the eleventh signal generating node GN11_SC to be floated.

[0155] In the second cycle TP2A, the voltages of the first signal generation node GN1_SC, the third signal generation node GN3_SC, the fifth signal generation node GN5_SC, the seventh signal generation node GN7_SC, the ninth signal generation node GN9_SC, and the eleventh signal generation node GN11_SC can be boosted through the coupling of the second boost capacitor BCC2_SC, the third boost capacitor BCC3_SC, the fourth boost capacitor BCC4_SC, the fifth boost capacitor BCC5_SC, the sixth boost capacitor BCC6_SC, and the seventh boost capacitor BCC7_SC, respectively.

[0156] In the second cycle TP2A, the first scan clock signal SCCK[1], the second scan clock signal SCCK[2], the third scan clock signal SCCK[3], the fourth scan clock signal SCCK[4], the fifth scan clock signal SCCK[5], and the sixth scan clock signal SCCK[6], all with activation levels, can be output. For example, the first scan clock signal SCCK[1], the second scan clock signal SCCK[2], the third scan clock signal SCCK[3], the fourth scan clock signal SCCK[4], the fifth scan clock signal SCCK[5], and the sixth scan clock signal SCCK[6] can be output sequentially. Therefore, the first scan clock signal SCCK[1], the second scan clock signal SCCK[2], the third scan clock signal SCCK[3], the fourth scan clock signal SCCK[4], the fifth scan clock signal SCCK[5], and the sixth scan clock signal SCCK[6] can be applied to the second signal generation node GN2_SC, the fourth signal generation node GN4_SC, the sixth signal generation node GN6_SC, the eighth signal generation node GN8_SC, the tenth signal generation node GN10_SC, and the twelfth signal generation node GN12_SC, respectively. Therefore, the second signal generation node GN2_SC, the fourth signal generation node GN4_SC, the sixth signal generation node GN6_SC, the eighth signal generation node GN8_SC, the tenth signal generation node GN10_SC, and the twelfth signal generation node GN12_SC can output the first gate signal SC[1] to SC[6].

[0157] In the second cycle TP2A, the first-stage boost clock signal BCK1 can be changed from an active level to an inactive level. Therefore, the inactive first-stage boost clock signal BCK1 can be applied to the boost control node BCRN_SC. Based on the voltage change of the boost control node BCRN_SC, the first signal generation node GN1_SC, the third signal generation node GN3_SC, the fifth signal generation node GN5_SC, the seventh signal generation node GN7_SC, the ninth signal generation node GN9_SC, and the eleventh signal generation node GN11_SC can be coupled. Therefore, the voltages of the first signal generation node GN1_SC, the third signal generation node GN3_SC, the fifth signal generation node GN5_SC, the seventh signal generation node GN7_SC, the ninth signal generation node GN9_SC, and the eleventh signal generation node GN11_SC can be reduced by changing the voltage of the boost control node BCRN_SC. Furthermore, the subsequent first carry signal CR[n+1]_SC can have an active level, allowing the first low voltage VGL1 to be applied to the first common control node Q_SC. Therefore, the fifth signal generating transistor BT5_SC, the eighth signal generating transistor BT8_SC, the eleventh signal generating transistor BT11_SC, the fourteenth signal generating transistor BT14_SC, the seventeenth signal generating transistor BT17_SC, and the twentieth signal generating transistor BT20_SC can be turned off.

[0158] In the second cycle TP2A, the second-stage boost clock signal BCK2 can have an activation level. Based on the second-stage boost clock signal BCK2 and the second-stage first common control signal QCS_SC, the second-stage first gate signals SC[7] to SC

[12] can be output. For example, based on the second-stage first common control signal QCS_SC, the second-stage first gate signals SC[7] to SC

[12] can be output sequentially.

[0159] In the second cycle TP2A, the first carry clock signal CR_CK_SC2 of the second stage can have an active level. When the first carry clock signal CR_CK_SC2 of the second stage has an active level, the subsequent first carry signal CR[n+1]_SC can also have an active level. Therefore, the third scan gate transistor T3_SC and the fourth scan gate transistor T4_SC can be turned on. The third scan gate transistor T3_SC and the fourth scan gate transistor T4_SC can be turned on, allowing the first low voltage VGL1 to be applied to the first common control node Q_SC. Therefore, the first common control node Q_SC can be initialized to the first low voltage VGL1. The first common control node Q_SC can have the first low voltage VGL1, allowing the twelfth scan gate transistor T12_SC and the thirteenth scan gate transistor T13_SC to be turned off. The tenth scan gate transistor T10_SC and the eleventh scan gate transistor T11_SC can be turned on. The tenth scan gate transistor T10_SC and the eleventh scan gate transistor T11_SC can be turned on, and the twelfth scan gate transistor T12_SC and the thirteenth scan gate transistor T13_SC can be turned off, allowing the second scan node SCN2 to have a second high voltage VGH2. The second scan node SCN2 having a second high voltage VGH2 allows this second high voltage VGH2 to be applied to the first inverting common control node QB_SC. The second high voltage VGH2 applied to the first inverting common control node QB_SC causes the second signal generating transistor BT2_SC, the fourth signal generating transistor BT4_SC, the seventh signal generating transistor BT7_SC, the tenth signal generating transistor BT10_SC, the thirteenth signal generating transistor BT13_SC, the sixteenth signal generating transistor BT16_SC, the nineteenth signal generating transistor BT19_SC, and the twenty-second signal generating transistor BT22_SC to be turned on. Therefore, the first low voltage VGL1 can be applied to the boost control node BCRN_SC. Furthermore, the second low voltage VGL2 can be applied to the second signal generation node GN2_SC, the fourth signal generation node GN4_SC, the sixth signal generation node GN6_SC, the eighth signal generation node GN8_SC, the tenth signal generation node GN10_SC, and the twelfth signal generation node GN12_SC. Additionally, the subsequent first carry signal CR[n+1]_SC can have an activation level, allowing the second high voltage VGH2 to be applied to the first output node OVN_SC. Therefore, the first output control voltage OV_SC can have the second high voltage VGH2.

[0160] In the third cycle TP3A, the second input signal S2 can have an activation level. Therefore, the first output control node OCN1 can be initialized. For example, the first output control node OCN1 can be initialized using the voltage of the first common control node Q_SC.

[0161] In the fourth cycle TP4A, the first input signal S1 and the first reset signal RST_SC can have an active level. In the fourth cycle TP4A, the first output control transistor OCT1 and the second output control transistor OCT2 can be turned on in response to the first input signal S1. In the fourth cycle TP4A, the boost control signal BCR can have a first low voltage VGL1. Therefore, the second output control node OCN2 can be initialized to the first low voltage VGL1. Furthermore, the first scan gate transistor T1_SC and the second scan gate transistor T2_SC can be turned on in response to the first reset signal RST_SC. The turn-on of the first scan gate transistor T1_SC and the second scan gate transistor T2_SC allows the first low voltage VGL1 to be applied to the first common control node Q_SC.

[0162] Reference Figure 5A The control signal generation block 310 may further include a first sensing gate transistor T1_SS, a second sensing gate transistor T2_SS, a third sensing gate transistor T3_SS, a fourth sensing gate transistor T4_SS, a fifth sensing gate transistor T5_SS, a sixth sensing gate transistor T6_SS, a seventh sensing gate transistor T7_SS, an eighth sensing gate transistor T8_SS, a ninth sensing gate transistor T9_SS, a tenth sensing gate transistor T10_SS, an eleventh sensing gate transistor T11_SS, a twelfth sensing gate transistor T12_SS, a thirteenth sensing gate transistor T13_SS, a fourteenth sensing gate transistor T14_SS, a fifteenth sensing gate transistor T15_SS, a sixteenth sensing gate transistor T16_SS, and a seventeenth sensing gate transistor T17_SS.

[0163] The first sensing gate transistor T1_SS may include a control electrode that receives a second reset signal RST_SS, a first electrode connected to the first sensing node SSN1, and a second electrode that receives a first low voltage VGL1. The first sensing gate transistor T1_SS may apply the first low voltage VGL1 to the first sensing node SSN1 in response to the second reset signal RST_SS. For example, the first sensing gate transistor T1_SS may initialize the first sensing node SSN1 to the first low voltage VGL1 in response to the second reset signal RST_SS.

[0164] The second sensing gate transistor T2_SS may include a control electrode receiving a second reset signal RST_SS, a first electrode connected to a second common control node Q_SS, and a second electrode connected to a first sensing node SSN1. The second sensing gate transistor T2_SS may connect the second common control node Q_SS and the first sensing node SSN1 in response to the second reset signal RST_SS. Therefore, the second common control node Q_SS may be initialized to a first low voltage VGL1 in response to the second reset signal RST_SS.

[0165] The third sensing gate transistor T3_SS may include a control electrode that receives a subsequent second carry signal CR[n+1]_SS, a first electrode connected to the first sensing node SSN1, and a second electrode that receives a first low voltage VGL1. The third sensing gate transistor T3_SS may apply the first low voltage VGL1 to the first sensing node SSN1 in response to the subsequent second carry signal CR[n+1]_SS. For example, the third sensing gate transistor T3_SS may initialize the first sensing node SSN1 to the first low voltage VGL1 in response to the subsequent second carry signal CR[n+1]_SS.

[0166] The fourth sensing gate transistor T4_SS may include a control electrode that receives a subsequent second carry signal CR[n+1]_SS, a first electrode connected to the second common control node Q_SS, and a second electrode connected to the first sensing node SSN1. The fourth sensing gate transistor T4_SS may connect the second common control node Q_SS and the first sensing node SSN1 in response to the subsequent second carry signal CR[n+1]_SS. Therefore, the second common control node Q_SS may be initialized to a first low voltage VGL1 in response to the subsequent second carry signal CR[n+1]_SS.

[0167] The fifth sensing gate transistor T5_SS may include a control electrode connected to the second inverting common control node QB_SS, a first electrode connected to the first sensing node SSN1, and a second electrode receiving a first low voltage VGL1. The fifth sensing gate transistor T5_SS may apply the first low voltage VGL1 to the first sensing node SSN1 in response to the voltage of the second inverting common control node QB_SS.

[0168] The sixth sensing gate transistor T6_SS may include a control electrode connected to the second inverting common control node QB_SS, a first electrode connected to the second common control node Q_SS, and a second electrode connected to the first sensing node SSN1. The sixth sensing gate transistor T6_SS can connect the second common control node Q_SS and the first sensing node SSN1 in response to the voltage of the second inverting common control node QB_SS. The second inverting common control node QB_SS can be connected to the second inverting common control line QBL_SS.

[0169] The seventh sensing gate transistor T7_SS may include a control electrode that receives the previous second carry signal CR[n-1]_SS, a first electrode that receives the previous second carry signal CR[n-1]_SS, and a second electrode connected to the first sensing node SSN1.

[0170] The eighth sensing gate transistor T8_SS may include a control electrode that receives a previous second carry signal CR[n-1]_SS, a first electrode connected to the first sensing node SSN1, and a second electrode connected to the second common control node Q_SS. The eighth sensing gate transistor T8_SS may connect the first sensing node SSN1 and the second common control node Q_SS in response to the previous second carry signal CR[n-1]_SS. The second common control node Q_SS may be connected to the second common control line QL_SS.

[0171] The ninth sensing gate transistor T9_SS may include a control electrode connected to the second sensing node SSN2, a first electrode receiving the second high voltage VGH2, and a second electrode connected to the first electrode of the thirteenth sensing gate transistor T13_SS.

[0172] The tenth sensing gate transistor T10_SS may include a control electrode receiving a second high voltage VGH2, a first electrode receiving the second high voltage VGH2, and a second electrode connected to the first electrode of the eleventh sensing gate transistor T11_SS. The eleventh sensing gate transistor T11_SS may include a control electrode receiving the second high voltage VGH2, a first electrode connected to the second electrode of the tenth sensing gate transistor T10_SS, and a second electrode connected to the second sensing node SSN2. The tenth sensing gate transistor T10_SS and the eleventh sensing gate transistor T11_SS may be connected in series. In an embodiment, the tenth sensing gate transistor T10_SS and the eleventh sensing gate transistor T11_SS may be configured as a single transistor.

[0173] The twelfth sensing gate transistor T12_SS may include a control electrode connected to the second common control node Q_SS, a first electrode connected to the second sensing node SSN2, and a second electrode receiving the second low voltage VGL2.

[0174] The thirteenth sensing gate transistor T13_SS may include a control electrode connected to the second common control node Q_SS, a first electrode connected to the second electrode of the ninth sensing gate transistor T9_SS, and a second electrode receiving a first low voltage VGL1.

[0175] The fourteenth sensing gate transistor T14_SS may include a control electrode that receives the second input signal S2, a first electrode that is connected to the second electrode of the fifteenth sensing gate transistor T15_SS, and a second electrode that receives the first low voltage VGL1.

[0176] The fifteenth sensing gate transistor T15_SS may include a control electrode that receives the boost control signal BCR, a first electrode connected to the second inverting common control node QB_SS, and a second electrode connected to the first electrode of the fourteenth sensing gate transistor T14_SS.

[0177] The sixteenth sensing gate transistor T16_SS may include a control electrode connected to the second common control node Q_SS, a first electrode receiving a first high voltage VGH1, and a second electrode connected to the first electrode of the seventeenth sensing gate transistor T17_SS. The seventeenth sensing gate transistor T17_SS may include a control electrode connected to the second common control node Q_SS, a first electrode connected to the second electrode of the sixteenth sensing gate transistor T16_SS, and a second electrode connected to the first sensing node SSN1. Therefore, the first high voltage VGH1 can be applied to the first sensing node SSN1 in response to the voltage of the second common control node Q_SS. The sixteenth sensing gate transistor T16_SS and the seventeenth sensing gate transistor T17_SS may be connected in series. In an embodiment, the sixteenth sensing gate transistor T16_SS and the seventeenth sensing gate transistor T17_SS may be configured as a single transistor.

[0178] In this embodiment, the second common control node Q_SS can output a second common control signal QCS_SS. The second common control signal QCS_SS can be applied to the second common control line QL_SS.

[0179] The output control signal generation block 320 may include a first output control transistor OCT1, a second output control transistor OCT2, a third output control transistor OCT3, a fourth output control transistor OCT4, a fifth output control transistor OCT5, and an output control capacitor OCC.

[0180] Reference Figure 5C The first gate signal output control block 340 may include a first output transistor CT1_SC, a second output transistor CT2_SC, a third output transistor CT3_SC, a fourth output transistor CT4_SC, and a fifth output transistor CT5_SC.

[0181] The first output transistor CT1_SC may include a control electrode that receives a previous first carry signal CR[n-1]_SC, a first electrode that receives a first high voltage VGH1, and a second electrode connected to the first electrode of the second output transistor CT2_SC. The second output transistor CT2_SC may include a control electrode that receives a previous first carry signal CR[n-1]_SC, a first electrode connected to the second electrode of the first output transistor CT1_SC, and a second electrode connected to the first output node OVN_SC. The first output transistor CT1_SC and the second output transistor CT2_SC may be connected in series. In an embodiment, the first output transistor CT1_SC and the second output transistor CT2_SC may be configured as a single transistor. The first output transistor CT1_SC and the second output transistor CT2_SC may be turned on in response to the previous first carry signal CR[n-1]_SC. When the first output transistor CT1_SC and the second output transistor CT2_SC are turned on, the first high voltage VGH1 may be applied to the first output node OVN_SC. When the first high voltage VGH1 is applied to the first output node OVN_SC, the first output control voltage OV_SC can have the first high voltage VGH1.

[0182] The third output transistor CT3_SC may include a control electrode connected to the boost control line BCRL_SC, a first electrode receiving the second high voltage VGH2, and a second electrode connected to the first output node OVN_SC. The third output transistor CT3_SC may apply the second high voltage VGH2 to the first output node OVN_SC in response to the boost control signal BCR. When the second high voltage VGH2 is applied to the first output node OVN_SC, the first output control voltage OV_SC may have the second high voltage VGH2.

[0183] The fourth output transistor CT4_SC may include a control electrode that receives a subsequent first carry signal CR[n+1]_SC, a first electrode that receives a second high voltage VGH2, and a second electrode connected to the first output node OVN_SC. The fourth output transistor CT4_SC may apply the second high voltage VGH2 to the first output node OVN_SC in response to the subsequent first carry signal CR[n+1]_SC.

[0184] The fifth output transistor CT5_SC may include a control electrode that receives the second input signal S2, a first electrode that receives the output control signal OCS, and a second electrode connected to the first output node OVN_SC. The fifth output transistor CT5_SC may apply the output control signal OCS to the first output node OVN_SC in response to the second input signal S2.

[0185] The second gate signal control block 350 may include a first signal generating transistor BT1_SS, a second signal generating transistor BT2_SS, a third signal generating transistor BT3_SS, a fourth signal generating transistor BT4_SS, a fifth signal generating transistor BT5_SS, a sixth signal generating transistor BT6_SS, a seventh signal generating transistor BT7_SS, an eighth signal generating transistor BT8_SS, a ninth signal generating transistor BT9_SS, a tenth signal generating transistor BT10_SS, an eleventh signal generating transistor BT11_SS, a twelfth signal generating transistor BT12_SS, a thirteenth signal generating transistor BT13_SS, a fourteenth signal generating transistor BT14_SS, and a fifteenth signal generating transistor BT14_SS. Signal generating transistors BT15_SS, BT16_SS, BT17_SS, BT18_SS, BT19_SS, BT20_SS, BT21_SS, BT22_SS, and BCC1_SS, BCC2_SS, BCC3_SS, BCC4_SS, BCC5_SS, BCC6_SS, and BCC7_SS (see also...) Figure 5D ).

[0186] The first signal generating transistor BT1_SS may include a control electrode connected to the second common control line QL_SS, a first electrode receiving the boost clock signal BCK, and a second electrode connected to the boost control node BCRN_SS. The first signal generating transistor BT1_SS can apply the boost clock signal BCK to the boost control node BCRN_SS in response to the second common control signal QCS_SS. The boost control node BCRN_SS may be connected to the boost control line BCRL_SS.

[0187] The second signal generating transistor BT2_SS may include a control electrode connected to the second inverting common control line QBL_SS, a first electrode connected to the boost control node BCRN_SS, and a second electrode receiving a first low voltage VGL1. The second signal generating transistor BT2_SS may apply the first low voltage VGL1 to the boost control node BCRN_SS in response to the voltage of the second inverting common control node QB_SS.

[0188] The third signal generating transistor BT3_SS may include a control electrode connected to the second common control line QL_SS, a first electrode receiving the second carry clock signal CRCK_SS, and a second electrode connected to the second carry output node CON1_SS. The second carry output node CON1_SS can output the second carry signal CR[n]_SS.

[0189] The fourth signal generating transistor BT4_SS may include a control electrode connected to the second inverting common control line QBL_SS, a first electrode connected to the second carry output node CON1_SS, and a second electrode receiving a second low voltage VGL2. The fourth signal generating transistor BT4_SS can apply the second low voltage VGL2 to the second carry output node CON1_SS in response to the voltage of the second inverting common control node QB_SS.

[0190] The fifth signal generating transistor BT5_SS may include a control electrode connected to the first signal generating node GN1_SS, a first electrode receiving the first sensing clock signal SSCK[1], and a second electrode connected to the second signal generating node GN2_SS. The fifth signal generating transistor BT5_SS may apply the first sensing clock signal SSCK[1] to the second signal generating node GN2_SS in response to the voltage of the first signal generating node GN1_SS. The second signal generating node GN2_SS may output the first sensing gate signal SS[1].

[0191] The sixth signal generating transistor BT6_SS may include a control electrode receiving the second output control voltage OV_SS, a first electrode connected to the second common control line QL_SS, and a second electrode connected to the first signal generating node GN1_SS. The sixth signal generating transistor BT6_SS may apply the second common control signal QCS_SS to the first signal generating node GN1_SS in response to the second output control voltage OV_SS. The sixth signal generating transistor BT6_SS may be turned on when the second output control voltage OV_SS has a first high voltage VGH1. The sixth signal generating transistor BT6_SS being turned on allows the second common control signal QCS_SS to be applied to the first signal generating node GN1_SS. The second common control signal QCS_SS being applied to the first signal generating node GN1_SS allows the fifth signal generating transistor BT5_SS to be turned on. Therefore, the first sensing clock signal SSCK[1] may be applied to the second signal generating node GN2_SS. Therefore, the first sensing gate signal SS[1] corresponding to the first sensing clock signal SSCK[1] may be output. When the second output control voltage OV_SS has a second high voltage VGH2, the sixth signal generation transistor BT6_SS can be turned off.

[0192] The seventh signal generating transistor BT7_SS may include a control electrode connected to the second inverting common control line QBL_SS, a first electrode connected to the second signal generating node GN2_SS, and a second electrode receiving a second low voltage VGL2. The seventh signal generating transistor BT7_SS may apply the second low voltage VGL2 to the second signal generating node GN2_SS in response to the voltage of the second inverting common control node QB_SS.

[0193] The eighth signal generating transistor BT8_SS may include a control electrode connected to the third signal generating node GN3_SS, a first electrode receiving the second sensing clock signal SSCK[2], and a second electrode connected to the fourth signal generating node GN4_SS. The eighth signal generating transistor BT8_SS may apply the second sensing clock signal SSCK[2] to the fourth signal generating node GN4_SS in response to the voltage of the third signal generating node GN3_SS. The fourth signal generating node GN4_SS may output the second sensing gate signal SS[2].

[0194] The ninth signal generating transistor BT9_SS may include a control electrode receiving the second output control voltage OV_SS, a first electrode connected to the second common control line QL_SS, and a second electrode connected to the third signal generating node GN3_SS. The ninth signal generating transistor BT9_SS may apply the second common control signal QCS_SS to the third signal generating node GN3_SS in response to the second output control voltage OV_SS. The ninth signal generating transistor BT9_SS may be turned on when the second output control voltage OV_SS has a first high voltage VGH1. The ninth signal generating transistor BT9_SS being turned on allows the second common control signal QCS_SS to be applied to the third signal generating node GN3_SS. The second common control signal QCS_SS being applied to the third signal generating node GN3_SS allows the eighth signal generating transistor BT8_SS to be turned on. Therefore, the second sensing clock signal SSCK[2] may be applied to the fourth signal generating node GN4_SS. Therefore, the second sensing gate signal SS[2] corresponding to the second sensing clock signal SSCK[2] may be output. When the second output control voltage OV_SS has a second high voltage VGH2, the ninth signal generation transistor BT9_SS can be turned off.

[0195] The tenth signal generating transistor BT10_SS may include a control electrode connected to the second inverting common control line QBL_SS, a first electrode connected to the fourth signal generating node GN4_SS, and a second electrode receiving a second low voltage VGL2. The tenth signal generating transistor BT10_SS may apply the second low voltage VGL2 to the fourth signal generating node GN4_SS in response to the voltage of the second inverting common control node QB_SS.

[0196] The eleventh signal generating transistor BT11_SS may include a control electrode connected to the fifth signal generating node GN5_SS, a first electrode receiving the third sensing clock signal SSCK[3], and a second electrode connected to the sixth signal generating node GN6_SS. The eleventh signal generating transistor BT11_SS may apply the third sensing clock signal SSCK[3] to the sixth signal generating node GN6_SS in response to the voltage of the fifth signal generating node GN5_SS. The sixth signal generating node GN6_SS may output the third sensing gate signal SS[3].

[0197] The twelfth signal generating transistor BT12_SS may include a control electrode receiving the second output control voltage OV_SS, a first electrode connected to the second common control line QL_SS, and a second electrode connected to the fifth signal generating node GN5_SS. The twelfth signal generating transistor BT12_SS may apply the second common control signal QCS_SS to the fifth signal generating node GN5_SS in response to the second output control voltage OV_SS. The twelfth signal generating transistor BT12_SS may be turned on when the second output control voltage OV_SS has a first high voltage VGH1. The twelfth signal generating transistor BT12_SS being turned on allows the second common control signal QCS_SS to be applied to the fifth signal generating node GN5_SS. The second common control signal QCS_SS being applied to the fifth signal generating node GN5_SS allows the eleventh signal generating transistor BT11_SS to be turned on. Therefore, the third sensing clock signal SSCK[3] may be applied to the sixth signal generating node GN6_SS. Therefore, the third sensing gate signal SS[3] corresponding to the third sensing clock signal SSCK[3] may be output. When the second output control voltage OV_SS has a second high voltage VGH2, the twelfth signal generation transistor BT12_SS can be turned off.

[0198] The thirteenth signal generating transistor BT13_SS may include a control electrode connected to the second inverting common control line QBL_SS, a first electrode connected to the sixth signal generating node GN6_SS, and a second electrode receiving a second low voltage VGL2. The thirteenth signal generating transistor BT13_SS may apply the second low voltage VGL2 to the sixth signal generating node GN6_SS in response to the voltage of the second inverting common control node QB_SS.

[0199] The fourteenth signal generating transistor BT14_SS may include a control electrode connected to the seventh signal generating node GN7_SS, a first electrode receiving the fourth sensing clock signal SSCK[4], and a second electrode connected to the eighth signal generating node GN8_SS. The fourteenth signal generating transistor BT14_SS may apply the fourth sensing clock signal SSCK[4] to the eighth signal generating node GN8_SS in response to the voltage of the seventh signal generating node GN7_SS. The eighth signal generating node GN8_SS may output the fourth sensing gate signal SS[4].

[0200] The fifteenth signal generating transistor BT15_SS may include a control electrode receiving the second output control voltage OV_SS, a first electrode connected to the second common control line QL_SS, and a second electrode connected to the seventh signal generating node GN7_SS. The fifteenth signal generating transistor BT15_SS may apply the second common control signal QCS_SS to the seventh signal generating node GN7_SS in response to the second output control voltage OV_SS. The fifteenth signal generating transistor BT15_SS may be turned on when the second output control voltage OV_SS has a first high voltage VGH1. The fifteenth signal generating transistor BT15_SS being turned on allows the second common control signal QCS_SS to be applied to the seventh signal generating node GN7_SS. The second common control signal QCS_SS being applied to the seventh signal generating node GN7_SS allows the fourteenth signal generating transistor BT14_SS to be turned on. Therefore, the fourth sensing clock signal SSCK[4] may be applied to the eighth signal generating node GN8_SS. Therefore, the fourth sensing gate signal SS[4] corresponding to the fourth sensing clock signal SSCK[4] may be output. When the second output control voltage OV_SS has a second high voltage VGH2, the fifteenth signal generation transistor BT15_SS can be turned off.

[0201] The sixteenth signal generating transistor BT16_SS may include a control electrode connected to the second inverting common control line QBL_SS, a first electrode connected to the eighth signal generating node GN8_SS, and a second electrode receiving a second low voltage VGL2. The sixteenth signal generating transistor BT16_SS may apply the second low voltage VGL2 to the eighth signal generating node GN8_SS in response to the voltage of the second inverting common control node QB_SS.

[0202] The seventeenth signal generating transistor BT17_SS may include a control electrode connected to the ninth signal generating node GN9_SS, a first electrode receiving the fifth sensing clock signal SSCK[5], and a second electrode connected to the tenth signal generating node GN10_SS. The seventeenth signal generating transistor BT17_SS may apply the fifth sensing clock signal SSCK[5] to the tenth signal generating node GN10_SS in response to the voltage of the ninth signal generating node GN9_SS. The tenth signal generating node GN10_SS may output the fifth sensing gate signal SS[5].

[0203] The eighteenth signal generating transistor BT18_SS may include a control electrode receiving the second output control voltage OV_SS, a first electrode connected to the second common control line QL_SS, and a second electrode connected to the ninth signal generating node GN9_SS. The eighteenth signal generating transistor BT18_SS may apply the second common control signal QCS_SS to the ninth signal generating node GN9_SS in response to the second output control voltage OV_SS. The eighteenth signal generating transistor BT18_SS may be turned on when the second output control voltage OV_SS has a first high voltage VGH1. The eighteenth signal generating transistor BT18_SS being turned on allows the second common control signal QCS_SS to be applied to the ninth signal generating node GN9_SS. The second common control signal QCS_SS being applied to the ninth signal generating node GN9_SS allows the seventeenth signal generating transistor BT17_SS to be turned on. Therefore, the fifth sensing clock signal SSCK[5] may be applied to the tenth signal generating node GN10_SS. Therefore, the fifth sensing gate signal SS[5] corresponding to the fifth sensing clock signal SSCK[5] may be output. When the second output control voltage OV_SS has a second high voltage VGH2, the eighteenth signal generation transistor BT18_SS can be turned off.

[0204] The nineteenth signal generating transistor BT19_SS may include a control electrode connected to the second inverting common control line QBL_SS, a first electrode connected to the tenth signal generating node GN10_SS, and a second electrode receiving a second low voltage VGL2. The nineteenth signal generating transistor BT19_SS may apply the second low voltage VGL2 to the tenth signal generating node GN10_SS in response to the voltage of the second inverting common control node QB_SS.

[0205] The twentieth signal generating transistor BT20_SS may include a control electrode connected to the eleventh signal generating node GN11_SS, a first electrode receiving the sixth sensing clock signal SSCK[6], and a second electrode connected to the twelfth signal generating node GN12_SS. The twentieth signal generating transistor BT20_SS may apply the sixth sensing clock signal SSCK[6] to the twelfth signal generating node GN12_SS in response to the voltage of the eleventh signal generating node GN11_SS. The twelfth signal generating node GN12_SS may output the sixth sensing gate signal SS[6].

[0206] The 21st signal generating transistor BT21_SS may include a control electrode receiving the second output control voltage OV_SS, a first electrode connected to the second common control line QL_SS, and a second electrode connected to the 11th signal generating node GN11_SS. The 21st signal generating transistor BT21_SS may apply the second common control signal QCS_SS to the 11th signal generating node GN11_SS in response to the second output control voltage OV_SS. The 21st signal generating transistor BT21_SS may be turned on when the second output control voltage OV_SS has a first high voltage VGH1. The 21st signal generating transistor BT21_SS may be turned on, so that the second common control signal QCS_SS may be applied to the 11th signal generating node GN11_SS. The second common control signal QCS_SS may be applied to the 11th signal generating node GN11_SS, so that the 20th signal generating transistor BT20_SS may be turned on. Therefore, the sixth sensing clock signal SSCK[6] may be applied to the 12th signal generating node GN12_SS. Therefore, the sixth sensing gate signal SS[6] corresponding to the sixth sensing clock signal SSCK[6] can be output. When the second output control voltage OV_SS has a second high voltage VGH2, the twenty-first signal generating transistor BT21_SS can be turned off.

[0207] The 22nd signal generating transistor BT22_SS may include a control electrode connected to the second inverting common control line QBL_SS, a first electrode connected to the 12th signal generating node GN12_SS, and a second electrode receiving a second low voltage VGL2. The 22nd signal generating transistor BT22_SS may apply the second low voltage VGL2 to the 12th signal generating node GN12_SS in response to the voltage of the second inverting common control node QB_SS.

[0208] The first boost capacitor BCC1_SS may include a first electrode connected to the second common control node Q_SS and a second electrode connected to the boost control node BCRN_SS. The second boost capacitor BCC2_SS may include a first electrode connected to the first signal generation node GN1_SS and a second electrode connected to the boost control node BCRN_SS. The third boost capacitor BCC3_SS may include a first electrode connected to the third signal generation node GN3_SS and a second electrode connected to the boost control node BCRN_SS. The fourth boost capacitor BCC4_SS may include a first electrode connected to the fifth signal generation node GN5_SS and a second electrode connected to the boost control node BCRN_SS. The fifth boost capacitor BCC5_SS may include a first electrode connected to the seventh signal generation node GN7_SS and a second electrode connected to the boost control node BCRN_SS. The sixth boost capacitor BCC6_SS may include a first electrode connected to the ninth signal generation node GN9_SS and a second electrode connected to the boost control node BCRN_SS. The seventh boost capacitor BCC7_SS may include a first electrode connected to the eleventh signal generation node GN11_SS and a second electrode connected to the boost control node BCRN_SS.

[0209] Reference Figure 5E The second gate signal output control block 360 may include a first output transistor CT1_SS, a second output transistor CT2_SS, a third output transistor CT3_SS, a fourth output transistor CT4_SS, and a fifth output transistor CT5_SS.

[0210] The first output transistor CT1_SS may include a control electrode that receives a previous second carry signal CR[n-1]_SS, a first electrode that receives a first high voltage VGH1, and a second electrode connected to the first electrode of the second output transistor CT2_SS. The second output transistor CT2_SS may include a control electrode that receives a previous second carry signal CR[n-1]_SS, a first electrode connected to the second electrode of the first output transistor CT1_SS, and a second electrode connected to the first output node OVN_SS. The first output transistor CT1_SS and the second output transistor CT2_SS may be connected in series. In an embodiment, the first output transistor CT1_SS and the second output transistor CT2_SS may be configured as a single transistor. The first output transistor CT1_SS and the second output transistor CT2_SS may be turned on in response to the previous second carry signal CR[n-1]_SS. When the first output transistor CT1_SS and the second output transistor CT2_SS are turned on, the first high voltage VGH1 may be applied to the first output node OVN_SS. When the first high voltage VGH1 is applied to the first output node OVN_SS, the second output control voltage OV_SS can have the first high voltage VGH1.

[0211] The third output transistor CT3_SS may include a control electrode connected to the boost control line BCRL_SS, a first electrode receiving a second high voltage VGH2, and a second electrode connected to the first output node OVN_SS. The third output transistor CT3_SS may apply the second high voltage VGH2 to the first output node OVN_SS in response to the boost control signal BCR. When the second high voltage VGH2 is applied to the first output node OVN_SS, the second output control voltage OV_SS may have the second high voltage VGH2.

[0212] The fourth output transistor CT4_SS may include a control electrode that receives a subsequent second carry signal CR[n+1]_SS, a first electrode that receives a second high voltage VGH2, and a second electrode connected to the first output node OVN_SS. The fourth output transistor CT4_SS may apply the second high voltage VGH2 to the first output node OVN_SS in response to the subsequent second carry signal CR[n+1]_SS.

[0213] The fifth output transistor CT5_SS may include a control electrode that receives the second input signal S2, a first electrode that receives the output control signal OCS, and a second electrode connected to the first output node OVN_SS. The fifth output transistor CT5_SS may apply the output control signal OCS to the first output node OVN_SS in response to the second input signal S2.

[0214] In the first cycle TP1A, the first input signal S1 may have an active level, and the vertical start signal S5_SS may also have an active level. In an embodiment, the vertical start signal S5_SS may be the previous second carry signal CR[n-1]_SS.

[0215] In the first cycle TP1A, the seventh sensing gate transistor T7_SS and the eighth sensing gate transistor T8_SS can be turned on in response to the vertical start signal S5_SS. The turning on of the seventh sensing gate transistor T7_SS and the eighth sensing gate transistor T8_SS allows the vertical start signal S5_SS, with an activation level, to be applied to the second common control node Q_SS. For example, the activation level voltage of the vertical start signal S5_SS can be a first high voltage VGH1. In the first cycle TP1A, the second common control node Q_SS can have the first high voltage VGH1. The thirteenth sensing gate transistor T13_SS can be turned on in response to the voltage of the second common control node Q_SS. The turning on of the thirteenth sensing gate transistor T13_SS allows the first low voltage VGL1 to be applied to the second inverting common control node QB_SS. In the first cycle TP1A, the second common control signal QCS_SS, with the first high voltage VGH1, can be output to the second common control line QL_SS. The first signal generating transistor BT1_SS and the third signal generating transistor BT3_SS can be turned on in response to the second common control signal QCS_SS.

[0216] In the first cycle TP1A, the first output transistor CT1_SS and the second output transistor CT2_SS can be turned on in response to the vertical start signal S5_SS. The turn-on of the first output transistor CT1_SS and the second output transistor CT2_SS allows a first high voltage VGH1 to be applied to the first output node OVN_SS. Therefore, the first output control voltage OV_SS can have a first high voltage VGH1. In response to the first output control voltage OV_SS, the sixth signal generation transistor BT6_SS, the ninth signal generation transistor BT9_SS, the twelfth signal generation transistor BT12_SS, the fifteenth signal generation transistor BT15_SS, the eighteenth signal generation transistor BT18_SS, and the twenty-first signal generation transistor BT21_SS can be turned on. The sixth signal generating transistor BT6_SS, the ninth signal generating transistor BT9_SS, the twelfth signal generating transistor BT12_SS, the fifteenth signal generating transistor BT15_SS, the eighteenth signal generating transistor BT18_SS, and the twenty-first signal generating transistor BT21_SS can be turned on, so that the fifth signal generating transistor BT5_SS, the eighth signal generating transistor BT8_SS, the eleventh signal generating transistor BT11_SS, the fourteenth signal generating transistor BT14_SS, the seventeenth signal generating transistor BT17_SS, and the twentieth signal generating transistor BT20_SS can be turned on.

[0217] In the second cycle TP2A, the first-stage boost clock signal BCK1 can have an active level. The first signal generation transistor BT1_SS can be turned on based on the first-stage boost clock signal BCK1 and the second common control signal QCS_SS of the first stage having a first high voltage VGH1. Therefore, the first-stage boost clock signal BCK1 can be applied to the boost control node BCRN_SS. In response to the voltage of the boost control node BCRN_SS, the third output transistor CT3_SS can be turned on. The third output transistor CT3_SS being turned on allows a second high voltage VGH2, which is lower than the first high voltage VGH1, to be output to the first output node OVN_SS. Therefore, the first output control voltage OV_SS can have the second high voltage VGH2. Based on the first output control voltage OV_SS with a second high voltage VGH2 and the second common control signal QCS_SS with a first high voltage VGH1, the sixth signal generating transistor BT6_SS, the ninth signal generating transistor BT9_SS, the twelfth signal generating transistor BT12_SS, the fifteenth signal generating transistor BT15_SS, the eighteenth signal generating transistor BT18_SS, and the twenty-first signal generating transistor BT21_SS can be turned off. The sixth signal generating transistor BT6_SS, the ninth signal generating transistor BT9_SS, the twelfth signal generating transistor BT12_SS, the fifteenth signal generating transistor BT15_SS, the eighteenth signal generating transistor BT18_SS, and the twenty-first signal generating transistor BT21_SS can be turned off, allowing the first signal generating node GN1_SS, the third signal generating node GN3_SS, the fifth signal generating node GN5_SS, the seventh signal generating node GN7_SS, the ninth signal generating node GN9_SS, and the eleventh signal generating node GN11_SS to be floated.

[0218] In the second cycle TP2A, the voltages of the first signal generation node GN1_SS, the third signal generation node GN3_SS, the fifth signal generation node GN5_SS, the seventh signal generation node GN7_SS, the ninth signal generation node GN9_SS, and the eleventh signal generation node GN11_SS can be boosted through the coupling of the second boost capacitor BCC2_SS, the third boost capacitor BCC3_SS, the fourth boost capacitor BCC4_SS, the fifth boost capacitor BCC5_SS, the sixth boost capacitor BCC6_SS, and the seventh boost capacitor BCC7_SS, respectively.

[0219] In the second cycle TP2A, the first sensing clock signal SSCK[1], the second sensing clock signal SSCK[2], the third sensing clock signal SSCK[3], the fourth sensing clock signal SSCK[4], the fifth sensing clock signal SSCK[5], and the sixth sensing clock signal SSCK[6], all with activation levels, can be output. For example, the first sensing clock signal SSCK[1], the second sensing clock signal SSCK[2], the third sensing clock signal SSCK[3], the fourth sensing clock signal SSCK[4], the fifth sensing clock signal SSCK[5], and the sixth sensing clock signal SSCK[6] can be output sequentially. Therefore, the first sensing clock signal SSCK[1], the second sensing clock signal SSCK[2], the third sensing clock signal SSCK[3], the fourth sensing clock signal SSCK[4], the fifth sensing clock signal SSCK[5], and the sixth sensing clock signal SSCK[6] can be applied to the second signal generation node GN2_SS, the fourth signal generation node GN4_SS, the sixth signal generation node GN6_SS, the eighth signal generation node GN8_SS, the tenth signal generation node GN10_SS, and the twelfth signal generation node GN12_SS, respectively. Therefore, the second signal generation node GN2_SS, the fourth signal generation node GN4_SS, the sixth signal generation node GN6_SS, the eighth signal generation node GN8_SS, the tenth signal generation node GN10_SS, and the twelfth signal generation node GN12_SS can output the second gate signal SS[1] to SS[6].

[0220] In the second cycle TP2A, the first-stage boost clock signal BCK1 can be changed from an active level to an inactive level. Therefore, the inactive first-stage boost clock signal BCK1 can be applied to the boost control node BCRN_SS. Based on the voltage change of the boost control node BCRN_SS, the first signal generation node GN1_SS, the third signal generation node GN3_SS, the fifth signal generation node GN5_SS, the seventh signal generation node GN7_SS, the ninth signal generation node GN9_SS, and the eleventh signal generation node GN11_SS can be coupled. Therefore, the voltages of the first signal generation node GN1_SS, the third signal generation node GN3_SS, the fifth signal generation node GN5_SS, the seventh signal generation node GN7_SS, the ninth signal generation node GN9_SS, and the eleventh signal generation node GN11_SS can be reduced by changing the voltage of the boost control node BCRN_SS. Furthermore, the subsequent second carry signal CR[n+1]_SS can have an active level, allowing the first low voltage VGL1 to be applied to the second common control node Q_SS. Therefore, the fifth signal generating transistor BT5_SS, the eighth signal generating transistor BT8_SS, the eleventh signal generating transistor BT11_SS, the fourteenth signal generating transistor BT14_SS, the seventeenth signal generating transistor BT17_SS, and the twentieth signal generating transistor BT20_SS can be turned off.

[0221] In the second cycle TP2A, the second-stage boost clock signal BCK2 can have an activation level. Based on the second-stage boost clock signal BCK2 and the second common control signal QCS_SS of the second stage, the second gate signals SS[7] to SS

[12] of the second stage can be output. For example, based on the second common control signal QCS_SS of the second stage, the second gate signals SS[7] to SS

[12] of the second stage can be output sequentially.

[0222] In the second cycle TP2A, the second carry clock signal CR_CK_SS2 of the second stage can have an active level. When the second carry clock signal CR_CK_SS2 of the second stage has an active level, the subsequent second carry signal CR[n+1]_SS can also have an active level. Therefore, the third sensing gate transistor T3_SS and the fourth sensing gate transistor T4_SS can be turned on. The third sensing gate transistor T3_SS and the fourth sensing gate transistor T4_SS can be turned on, allowing the first low voltage VGL1 to be applied to the second common control node Q_SS. Therefore, the second common control node Q_SS can be initialized to the first low voltage VGL1. The second common control node Q_SS can have the first low voltage VGL1, allowing the twelfth sensing gate transistor T12_SS and the thirteenth sensing gate transistor T13_SS to be turned off. The tenth sensing gate transistor T10_SS and the eleventh sensing gate transistor T11_SS can be turned on. The tenth sensing gate transistor T10_SS and the eleventh sensing gate transistor T11_SS can be turned on, and the twelfth sensing gate transistor T12_SS and the thirteenth sensing gate transistor T13_SS can be turned off, allowing the second sensing node SSN2 to have a second high voltage VGH2. The second sensing node SSN2 having a second high voltage VGH2 allows this second high voltage VGH2 to be applied to the second inverting common control node QB_SS. The second high voltage VGH2 applied to the second inverting common control node QB_SS causes the second signal generating transistor BT2_SS, the fourth signal generating transistor BT4_SS, the seventh signal generating transistor BT7_SS, the tenth signal generating transistor BT10_SS, the thirteenth signal generating transistor BT13_SS, the sixteenth signal generating transistor BT16_SS, the nineteenth signal generating transistor BT19_SS, and the twenty-second signal generating transistor BT22_SS to be turned on. Therefore, the first low voltage VGL1 can be applied to the boost control node BCRN_SS. Furthermore, the second low voltage VGL2 can be applied to the second signal generation node GN2_SS, the fourth signal generation node GN4_SS, the sixth signal generation node GN6_SS, the eighth signal generation node GN8_SS, the tenth signal generation node GN10_SS, and the twelfth signal generation node GN12_SS. Additionally, the subsequent second carry signal CR[n+1]_SS can have an activation level, allowing the second high voltage VGH2 to be applied to the first output node OVN_SS. Therefore, the first output control voltage OV_SS can have the second high voltage VGH2.

[0223] In the third cycle TP3A, the second input signal S2 can have an activation level. Therefore, the first output control node OCN1 can be initialized. For example, the first output control node OCN1 can be initialized to the voltage of the second common control node Q_SS.

[0224] In the fourth cycle TP4A, the first input signal S1 and the second reset signal RST_SS can have an active level. In the fourth cycle TP4A, the first output control transistor OCT1 and the second output control transistor OCT2 can be turned on in response to the first input signal S1. In the fourth cycle TP4A, the boost control signal BCR can have a first low voltage VGL1. Therefore, the second output control node OCN2 can be initialized to the first low voltage VGL1. Furthermore, the first sense gate transistor T1_SS and the second sense gate transistor T2_SS can be turned on in response to the second reset signal RST_SS. The turning on of the first sense gate transistor T1_SS and the second sense gate transistor T2_SS allows the first low voltage VGL1 to be applied to the second common control node Q_SS.

[0225] Figure 8 It shows that it is applied to Figure 2 Gate driver 300 (see Figure 1 A timing diagram of an example of a signal. Figure 9 It shows that it is applied to Figure 5C Timing diagram of the first gate signal output control block 340. Figure 10 It shows that it is applied to Figure 5E Timing diagram of the second gate signal output control block 360. Figure 11 It is shown Figure 3 The control signal generation block 310 and the output control signal generation block 320 are in Figure 8 The circuit diagram for the operation in the third cycle TP3B. Figure 12 It is shown Figure 3 The control signal generation block 310 and the output control signal generation block 320 are in Figure 8 The circuit diagram for the operation of TP5B in the fifth cycle. Figure 13 It is shown Figure 3 The first gate signal output control block 340 in Figure 8 The circuit diagram for the operation of TP5B in the fifth cycle. Figure 14 It is shown Figure 3 The second gate signal output control block 360 in Figure 8 The circuit diagram for the operation of TP5B in the fifth cycle. Figure 15 It is shown Figure 3 The first gate signal control block 330 in Figure 8 The circuit diagram for the operation of TP6B in the sixth cycle. Figure 16 It is shown Figure 3 The second gate signal control block 350 in Figure 8 The circuit diagram for the operation of TP6B in the sixth cycle.

[0226] Reference Figures 1 to 16 The frame period in which the gate driver 300 is driven may include a first period TP1B, a second period TP2B, a third period TP3B, a fourth period TP4B, a fifth period TP5B, and a sixth period TP6B. For example, the frame period in which the gate driver 300 is driven may include an active period in which the gate signal is output and a blanking period following the active period. In this embodiment, the active period may include the first period TP1B, the second period TP2B, the third period TP3B, the fourth period TP4B, and the fifth period TP5B. The blanking period may include the sixth period TP6B. For example, the driving of the gate driver 300 in the frame period including the first period TP1B, the second period TP2B, the third period TP3B, the fourth period TP4B, the fifth period TP5B, and the sixth period TP6B may be referred to as a second driving mode 2. For example, the second driving mode 2 may be referred to as a sensing drive.

[0227] In the first cycle TP1B, the first input signal S1 can have an activation level, and the vertical start signals S5_SC and S5_SS can also have activation levels.

[0228] In the first cycle TP1B, the seventh scan gate transistor T7_SC, the eighth scan gate transistor T8_SC, the seventh sensing gate transistor T7_SS, and the eighth sensing gate transistor T8_SS can be turned on in response to the vertical start signals S5_SC and S5_SS. The turn-on of these transistors allows the first common control signal QCS_SC and the second common control signal QCS_SS to be output.

[0229] In the second cycle TP2B, the first-stage boost clock signal BCK1 can have an activation level. Based on the first-stage boost clock signal BCK1 and the first common control signal QCS_SC of the first stage, the first gate signals SC[1] to SC[6] of the first stage can be output. For example, based on the first common control signal QCS_SC of the first stage, the first gate signals SC[1] to SC[6] of the first stage can be output sequentially. Based on the first-stage boost clock signal BCK and the second common control signal QCS_SS of the first stage, the second gate signals SS[1] to SS[6] of the first stage can be output.

[0230] In the third cycle TP3B, the first input signal S1 can have an activation level. Furthermore, in the third cycle TP3B, the first-stage boost clock signal BCK1 can have an activation level. In response to the first input signal S1, the first output control transistor OCT1 and the second output control transistor OCT2 can be turned on. The turning on of the first output control transistor OCT1 and the second output control transistor OCT2 allows the activation level (e.g., a high clock level) of the first-stage boost clock signal BCK1 to be applied to the first output control node OCN1. The output control capacitor OCC can store the high clock level applied to the first output control node OCN1.

[0231] For example, the first carry clock signal CR_CK_SC1 of the first stage can have an activation level. For example, the second carry clock signal CR_CK_SS1 of the first stage can have an activation level. In the embodiment, in the third cycle TP3B, the length of the cycle in which the first input signal S1 has an activation level and the length of the cycle in which the first carry clock signal CR_CK_SC1 of the first stage has an activation level can be substantially the same. In the embodiment, in the third cycle TP3B, the length of the cycle in which the first input signal S1 has an activation level and the length of the cycle in which the second carry clock signal CR_CK_SS1 of the first stage has an activation level can be substantially the same. Therefore, the reliability of the first scan gate signal SC[1] and the first sense gate signal SS[1] output in the sixth cycle TP6B can be improved.

[0232] In the fourth cycle TP4B, the second-stage boost clock signal BCK2 can have an activation level. Based on the second-stage boost clock signal BCK2 and the first common control signal QCS_SC of the second stage, the first gate signals SC[7] to SC

[12] of the second stage can be output. For example, based on the first common control signal QCS_SC of the second stage, the first gate signals SC[7] to SC

[12] of the second stage can be output sequentially. Based on the second common control signal QCS_SS of the second stage, the second gate signals SS[7] to SS

[12] of the second stage can be output.

[0233] In the fifth cycle TP5B, the second input signal S2 can have an activation level. In the fifth cycle TP5B, the fourth output control transistor OCT4 can be turned on in response to the second input signal S2. In the fifth cycle TP5B, the fifth output control transistor OCT5 can be turned on in response to the second input signal S2. Furthermore, the third output control transistor OCT3 can be turned on. The turning on of the third output control transistor OCT3 allows the output control signal OCS with a first high voltage VGH1 to be output.

[0234] In the fifth cycle TP5B, the fifth output transistors CT5_SC and CT5_SS can be turned on in response to the second input signal S2. The turn-on of the fifth output transistors CT5_SC and CT5_SS allows a first high voltage VGH1 to be applied to the output nodes OVN_SC and OVN_SS. Therefore, the output control voltages OV_SC and OV_SS can have the first high voltage VGH1.

[0235] In the sixth cycle TP6B, the first scan clock signal SCCK[1] can be output. For example, in the sixth cycle TP6B, the first scan clock signal SCCK[1] can switch between clock high voltage and clock low voltage. For example, in the sixth cycle TP6B, the first scan clock signal SCCK[1] can switch approximately twice. However, the present invention is not limited to the timing of the first scan clock signal SCCK[1].

[0236] In the sixth cycle TP6B, the first sensing clock signal SSCK[1] can be output. For example, in the sixth cycle TP6B, the first sensing clock signal SSCK[1] can be switched between clock high voltage and clock low voltage.

[0237] For example, during the blanking cycle, a sensing operation can be performed on at least one pixel row of pixels in the display panel 100. For example, the at least one pixel row can be connected to a K-th stage. The K-th stage may include a P-th scan gate line and a P-th sensing gate line. In this embodiment, the K-th stage can perform sensing drive. Therefore, during the blanking cycle, the scan gate signal and the sensing gate signal can be output to the P-th scan gate line and the P-th sensing gate line connected to the at least one pixel row.

[0238] For example, the P-th scan gate signal applied to the P-th scan gate line of the K-th stage during the blanking period can have an active level. For example, the remaining scan gate signals, except for the P-th scan gate signal of the K-th stage, can have an inactive level during the blanking period. For example, the remaining stages, except for the K-th stage, can stop outputting scan gate signals and sense gate signals during the blanking period. For example, the P-th sense gate signal applied to the P-th sense gate line of the K-th stage during the blanking period can have an active level. For example, the remaining sense gate signals, except for the P-th sense gate signal of the K-th stage, can have an inactive level during the blanking period. Here, P is a positive integer.

[0239] Therefore, a sensing operation can be performed on at least one pixel row. Thus, when multiple gate signals are output based on a logic generation block (e.g., output control signal generation block 320), a sensing operation can be performed on at least one pixel row. The sensing operation can be performed so that a data signal DATA based on the sensing data SD can be generated. Therefore, the display quality of the display panel 100 can be improved.

[0240] Furthermore, the stage of the gate driver to which at least one pixel is connected can operate during the blanking period, and the stage of the gate driver to which at least one pixel is not connected can stop operating during the blanking period, thereby reducing the power consumption of the display device 1.

[0241] Figure 17 It shows that it is applied to Figure 2 Gate driver 300 (see Figure 1 A timing diagram of an example of a signal.

[0242] In addition to the activation level period of the first scan clock signal SCCK[1] being the same as that of the second scan clock signal SCCK[2], the activation level period of the first sensing clock signal SSCK[1] being the same as that of the second sensing clock signal SSCK[2], the activation level period of the third scan clock signal SCCK[3] being the same as that of the fourth scan clock signal SCCK[4], the activation level period of the third sensing clock signal SSCK[3] being the same as that of the fourth sensing clock signal SSCK[4], the activation level period of the fifth scan clock signal SCCK[5] being the same as that of the sixth scan clock signal SCCK[6], the activation level period of the fifth sensing clock signal SSCK[5] being the same as that of the sixth sensing clock signal SSCK[6], the seventh scan clock... The activation level period of the clock signal SCCK[7] is the same as the activation level period of the eighth scan clock signal SCCK[8], the activation level period of the seventh sensing clock signal SSCK[7] is the same as the activation level period of the eighth sensing clock signal SSCK[8], the activation level period of the ninth scan clock signal SCCK[9] is the same as the activation level period of the tenth scan clock signal SCCK

[10] , the activation level period of the ninth sensing clock signal SSCK[9] is the same as the activation level period of the tenth sensing clock signal SSCK

[10] , the activation level period of the eleventh scan clock signal SCCK

[11] is the same as the activation level period of the twelfth scan clock signal SCCK

[12] , and the activation level period of the eleventh sensing clock signal SSCK

[11] is the same as the activation level period of the twelfth sensing clock signal SSCK

[12] . Figure 17 The lengths of the activation level period of the scan gate signal and the activation level period of the sense gate signal are... Figure 4 The length of the activation level period of the scan gate signal is approximately twice the length of the activation level period of the sense gate signal. Figure 17 The timing diagram and Figure 4 The timing diagrams are essentially the same. Therefore, the same reference numerals will be used to refer to the same components, and any repeated descriptions of the above components will be omitted.

[0243] Reference Figures 1 to 10 as well as Figure 17 The drive of the gate driver 300 can be referred to as the third drive MODE 3. The activation level period of the first scan clock signal SCCK[1] is the same as the activation level period of the second scan clock signal SCCK[2], the activation level period of the first sensing clock signal SSCK[1] is the same as the activation level period of the second sensing clock signal SSCK[2], the activation level period of the third scan clock signal SCCK[3] is the same as the activation level period of the fourth scan clock signal SCCK[4], the activation level period of the third sensing clock signal SSCK[3] is the same as the activation level period of the fourth sensing clock signal SSCK[4], the activation level period of the fifth scan clock signal SCCK[5] is the same as the activation level period of the sixth scan clock signal SCCK[6], the activation level period of the fifth sensing clock signal SSCK[5] is the same as the activation level period of the sixth sensing clock signal SSCK[6], and the seventh scan clock... The activation level period of signal SCCK[7] is the same as the activation level period of the eighth scan clock signal SCCK[8]. The activation level period of the seventh sensing clock signal SSCK[7] is the same as the activation level period of the eighth sensing clock signal SSCK[8]. The activation level period of the ninth scan clock signal SCCK[9] is the same as the activation level period of the tenth scan clock signal SCCK

[10] . The activation level period of the ninth sensing clock signal SSCK[9] is the same as the activation level period of the tenth sensing clock signal SSCK

[10] . The activation level period of the eleventh scan clock signal SCCK

[11] is the same as the activation level period of the twelfth scan clock signal SCCK

[12] . The activation level period of the eleventh sensing clock signal SSCK

[11] is the same as the activation level period of the twelfth sensing clock signal SSCK

[12] . Figure 17 The length of the activation level period of the scan gate signal and the length of the activation level period of the sensing gate signal can be... Figure 4The active level period of the scan gate signal is approximately twice as long. For example, the period in which the first scan gate signal SC[1] has an active level can be the same as the period in which the second scan gate signal SC[2] has an active level. Furthermore, the length of the effective period in the third drive MODE 3 can be approximately 0.5 times the length of the effective period in the first drive (first operation) MODE 1. Therefore, the driving frequency of the display panel 100 can be increased. For example, the display panel 100 can be driven at a high frequency in the third drive MODE 3. Furthermore, the length of the active level period of the scan gate signal can be approximately twice as long as the length of the active level period of the sensing gate signal, thereby improving the reliability of the gate signal applied to the pixel PX. The improved reliability of the gate signal applied to the pixel PX improves the accuracy of the data voltage VDATA applied to the pixel PX. Therefore, the display quality of the display panel 100 can be improved.

[0244] Figure 18 It shows that it is applied to Figure 2 Gate driver 300 (see Figure 1 A timing diagram of an example of a signal.

[0245] Reference Figures 1 to 10 as well as Figure 18 The frame period in which the gate driver 300 is driven may include a first frame period FR1A and a second frame period FR2A. In the first frame period FR1A, the first gate signals SC[1] to SC[k] may have an inactive level. In the second frame period FR2A, the first gate signals SC[1] to SC[k] with an active level may be output. For example, in the second frame period FR2A, the first gate signals SC[1] to SC[k] with an active level may be output sequentially. For example, in the first frame period FR1A and the second frame period FR2A, the gate driver 300 may be driven in a fourth drive MODE 4. For example, the fourth drive MODE 4 may be referred to as a variable frequency drive.

[0246] During the first frame period FR1A, the first clock signals SCCK[1], SCCK[2], SCCK[3], SCCK[4], SCCK[5], SCCK[6], SCCK[7], SCCK[8], SCCK[9], SCCK

[10] , SCCK

[11] , and SCCK

[12] can remain at an inactive level. Therefore, during the first frame period FR1A, the first gate signals SC[1] to SC

[12] corresponding to the first clock signals SCCK[1], SCCK[2], SCCK[3], SCCK[4], SCCK[5], SCCK[6], SCCK[7], SCCK[8], SCCK[9], SCCK

[10] , SCCK

[11] , and SCCK

[12] can remain at an inactive level. In this embodiment, the first gate signals SC[1] to SC

[12] can be applied to the write transistor that applies the data voltage VDATA to the pixel PX. The first gate signals SC[1] to SC

[12] can remain at an inactive level during the first frame period FR1A, and the data voltage VDATA can be left unapplied to pixel PX. Therefore, during the first frame period FR1A, pixel PX can emit light based on the data voltage VDATA of the previous frame. When the third carry signal CR_CK3 is at an active level, the variable frequency drive can be stopped.

[0247] In the second frame period FR2A, the first clock signals SCCK[1], SCCK[2], SCCK[3], SCCK[4], SCCK[5], SCCK[6], SCCK[7], SCCK[8], SCCK[9], SCCK

[10] , SCCK

[11] , and SCCK

[12] can have an active level. Therefore, in the second frame period FR2A, the first gate signals SC[1] to SC

[12] corresponding to the first clock signals SCCK[1], SCCK[2], SCCK[3], SCCK[4], SCCK[5], SCCK[6], SCCK[7], SCCK[8], SCCK[9], SCCK

[10] , SCCK

[11] , and SCCK

[12] can have an active level. The first gate signals SC[1] to SC

[12] having an active level in the second frame period FR2A allows the data voltage VDATA to be applied to the pixel PX. Therefore, in the second frame period FR2A, pixel PX can emit light based on the data voltage VDATA of the current frame.

[0248] In this embodiment, the gate driver 300 can be driven at a variable frequency. Therefore, the power consumption of the display device 1 can be reduced.

[0249] Figure 19 It shows that it is applied to Figure 2Gate driver 300 (see Figure 1 A timing diagram of an example of a signal.

[0250] Reference Figures 1 to 10 as well as Figure 19 The frame period in which the gate driver 300 is driven may include a first frame period FR1B and a second frame period FR2B. In the first frame period FR1B, the first gate signals SC[1] to SC[k] may have an inactive level. In the second frame period FR2B, the first gate signals SC[1] to SC[k] with an active level may be output. For example, in the second frame period FR2B, the first gate signals SC[1] to SC[k] with an active level may be output sequentially. For example, in the first frame period FR1B and the second frame period FR2B, the gate driver 300 may be driven in a fifth drive MODE 5. For example, the fifth drive MODE 5 may be referred to as a variable high-frequency drive.

[0251] In addition to the activation level period of the first scan clock signal SCCK[1] being the same as that of the second scan clock signal SCCK[2], the activation level period of the first sensing clock signal SSCK[1] being the same as that of the second sensing clock signal SSCK[2], the activation level period of the third scan clock signal SCCK[3] being the same as that of the fourth scan clock signal SCCK[4], the activation level period of the third sensing clock signal SSCK[3] being the same as that of the fourth sensing clock signal SSCK[4], the activation level period of the fifth scan clock signal SCCK[5] being the same as that of the sixth scan clock signal SCCK[6], the activation level period of the fifth sensing clock signal SSCK[5] being the same as that of the sixth sensing clock signal SSCK[6], the seventh scan clock... The activation level period of the clock signal SCCK[7] is the same as the activation level period of the eighth scan clock signal SCCK[8], the activation level period of the seventh sensing clock signal SSCK[7] is the same as the activation level period of the eighth sensing clock signal SSCK[8], the activation level period of the ninth scan clock signal SCCK[9] is the same as the activation level period of the tenth scan clock signal SCCK

[10] , the activation level period of the ninth sensing clock signal SSCK[9] is the same as the activation level period of the tenth sensing clock signal SSCK

[10] , the activation level period of the eleventh scan clock signal SCCK

[11] is the same as the activation level period of the twelfth scan clock signal SCCK

[12] , and the activation level period of the eleventh sensing clock signal SSCK

[11] is the same as the activation level period of the twelfth sensing clock signal SSCK

[12] . Figure 19The length of the activation level period of the scan gate signal and the length of the activation level period of the sense gate signal are Figure 18 The length of the activation level period of the scan gate signal is approximately twice the length of the activation level period of the sense gate signal. Figure 19 The timing diagram and Figure 18 The timing diagrams are essentially the same. Therefore, the same reference numerals will be used to refer to the same components, and any repeated descriptions of the above components will be omitted.

[0252] The length of the effective period in the fifth driving mode 5 can be approximately 0.5 times the length of the effective period in the fourth driving mode 4. Therefore, the driving frequency of the display panel 100 can be increased. For example, the display panel 100 can be driven at a variable high frequency in the fifth driving mode 5. Furthermore, the length of the activation level period of the scan gate signal can be approximately twice the length of the activation level period of the sensing gate signal, thereby improving the reliability of the gate signal applied to the pixel PX. Improved reliability of the gate signal applied to the pixel PX improves the accuracy of the data voltage VDATA applied to the pixel PX. Therefore, the display quality of the display panel 100 can be improved.

[0253] Furthermore, the gate driver 300 can be driven at a variable high frequency, which reduces the power consumption of the display device 1.

[0254] Figure 20 It is shown Figure 1 A circuit diagram of an example pixel PX.

[0255] Reference Figure 1 and Figure 20 A pixel PX includes a first transistor T1, a second transistor T2, a third transistor T3, a storage capacitor CST, and a light-emitting element EE. For example, a pixel PX may have a 3T1C structure. However, the inventive concept is not limited to the structure of the pixel PX.

[0256] The first transistor T1 may include a control electrode connected to the first node N1, a first electrode receiving a first power voltage ELVDD, and a second electrode connected to the second node N2. The first transistor T1 can generate a drive current based on the voltage of the first node N1. For example, the first transistor T1 may be referred to as a drive transistor.

[0257] The second transistor T2 may include a control electrode that receives a scan gate signal SC, a first electrode that receives a data voltage VDATA, and a second electrode connected to the first node N1. The second transistor T2 may apply the data voltage VDATA to the first node N1 in response to the scan gate signal SC. For example, the second transistor T2 may be referred to as a scan transistor. For example, the second transistor T2 may be referred to as a write transistor.

[0258] The third transistor T3 may include a control electrode that receives a sensing gate signal SS, a first electrode connected to a sensing line SL, and a second electrode connected to a second node N2. The third transistor T3 may connect the sensing line SL and the second node N2 in response to the sensing gate signal SS. For example, the third transistor T3 may be referred to as a sensing transistor.

[0259] The storage capacitor CST may include a first electrode connected to a first node N1 and a second electrode connected to a second node N2.

[0260] The light-emitting element EE may include a first electrode connected to the second node N2 and a second electrode receiving a second electrical voltage ELVSS. The light-emitting element EE may emit light based on a driving current.

[0261] Figure 21 It is shown Figure 3 A circuit diagram of an example of the first gate signal control block 330.

[0262] In addition to the first gate signal control block 330B, it also includes a first reset transistor RT1_SC, a second reset transistor RT2_SC, a third reset transistor RT3_SC, and a fourth reset transistor RT4_SC. Figure 21 The first gate signal control block 330B and Figure 5B The first gate signal control block 330 is substantially the same. Therefore, the same reference numerals will be used to refer to the same components, and any repeated descriptions of the above components will be omitted.

[0263] The first gate signal control block 330B may further include a first reset transistor RT1_SC, a second reset transistor RT2_SC, a third reset transistor RT3_SC, and a fourth reset transistor RT4_SC.

[0264] The first reset transistor RT1_SC may include a control electrode connected to the first inverting common control line QBL_SC, a first electrode receiving a first output control voltage OV_SC, and a second electrode connected to the first electrode of the second reset transistor RT2_SC. The second reset transistor RT2_SC may include a control electrode connected to the first inverting common control line QBL_SC, a first electrode connected to the second electrode of the first reset transistor RT1_SC, and a second electrode receiving a third low voltage VGL3. The first reset transistor RT1_SC and the second reset transistor RT2_SC may be connected in series. In an embodiment, the first reset transistor RT1_SC and the second reset transistor RT2_SC may be configured as a single transistor.

[0265] The third reset transistor RT3_SC may include a control electrode receiving a first reset signal RST_SC, a first electrode receiving a first output control voltage OV_SC, and a second electrode connected to the first electrode of the fourth reset transistor RT4_SC. The fourth reset transistor RT4_SC may include a control electrode receiving the first reset signal RST_SC, a first electrode connected to the second electrode of the third reset transistor RT3_SC, and a second electrode receiving a third low voltage VGL3. The third reset transistor RT3_SC and the fourth reset transistor RT4_SC may be connected in series. In an embodiment, the third reset transistor RT3_SC and the fourth reset transistor RT4_SC may be configured as a single transistor.

[0266] The first gate signal control block 330B can initialize the voltage of the line receiving the first output control voltage OV_SC using the first reset transistor RT1_SC, the second reset transistor RT2_SC, the third reset transistor RT3_SC, and the fourth reset transistor RT4_SC. For example, the line receiving the first output control voltage OV_SC can be initialized to a third low voltage VGL3.

[0267] Figure 22 It is shown Figure 3 A circuit diagram of an example of the second gate signal control block 350.

[0268] In addition to the second gate signal control block 350B, it also includes a first reset transistor RT1_SS, a second reset transistor RT2_SS, a third reset transistor RT3_SS, and a fourth reset transistor RT4_SS. Figure 22 The second gate signal control block 350B and Figure 5D The second gate signal control block 350 is essentially the same. Therefore, the same reference numerals will be used to refer to the same components, and any repeated descriptions of the above components will be omitted.

[0269] The second gate signal control block 350B may also include a first reset transistor RT1_SS, a second reset transistor RT2_SS, a third reset transistor RT3_SS, and a fourth reset transistor RT4_SS.

[0270] The first reset transistor RT1_SS may include a control electrode connected to the second inverting common control line QBL_SS, a first electrode receiving the second output control voltage OV_SS, and a second electrode connected to the first electrode of the second reset transistor RT2_SS. The second reset transistor RT2_SS may include a control electrode connected to the second inverting common control line QBL_SS, a first electrode connected to the second electrode of the first reset transistor RT1_SS, and a second electrode receiving the third low voltage VGL3. The first reset transistor RT1_SS and the second reset transistor RT2_SS may be connected in series. In an embodiment, the first reset transistor RT1_SS and the second reset transistor RT2_SS may be configured as a single transistor.

[0271] The third reset transistor RT3_SS may include a control electrode that receives the second reset signal RST_SS, a first electrode that receives the second output control voltage OV_SS, and a second electrode connected to the first electrode of the fourth reset transistor RT4_SS. The fourth reset transistor RT4_SS may include a control electrode that receives the second reset signal RST_SS, a first electrode connected to the second electrode of the third reset transistor RT3_SS, and a second electrode that receives the third low voltage VGL3. The third reset transistor RT3_SS and the fourth reset transistor RT4_SS may be connected in series. In an embodiment, the third reset transistor RT3_SS and the fourth reset transistor RT4_SS may be configured as a single transistor.

[0272] The second gate signal control block 350B can initialize the voltage of the line receiving the second output control voltage OV_SS using the first reset transistor RT1_SS, the second reset transistor RT2_SS, the third reset transistor RT3_SS, and the fourth reset transistor RT4_SS. For example, the line receiving the second output control voltage OV_SS can be initialized to a third low voltage VGL3.

[0273] Figure 23 This is a block diagram illustrating an electronic device 2101 according to an embodiment.

[0274] Reference Figures 1 to 23The electronic device 2101 can output various information via the display module 2140 in the operating system. When the processor 2110 executes an application stored in the memory 2120, the display module 2140 can provide application information to the user via the display panel 2141. For example, the display module 2140 can refer to the display device 1. For example, the processor 2110 can refer to a controller. For example, the processor 2110 can output input image data IMG and input control signal CONT to the drive controller 200. In an embodiment, the processor 2110 can select a first drive MODE 1, a second drive MODE 2, a third drive MODE 3, a fourth drive MODE 4, and a fifth drive MODE 5. The input control signal CONT can include information containing the first drive MODE 1, the second drive MODE 2, the third drive MODE 3, the fourth drive MODE 4, and the fifth drive MODE 5.

[0275] Processor 2110 can obtain external input via input module 2130 or sensor module 2161 and can execute applications corresponding to the external input. For example, when a user selects the camera icon displayed on display panel 2141, processor 2110 can obtain user input via input sensor 2161-2 and activate camera module 2171. Processor 2110 can transmit image data corresponding to the image captured by camera module 2171 to display module 2140. Display module 2140 can display the image corresponding to the captured image via display panel 2141.

[0276] As another example, when personal information authentication is performed in display module 2140, fingerprint sensor 2161-1 can obtain the input fingerprint information as input data. Processor 2110 can compare the input data obtained by fingerprint sensor 2161-1 with the authentication data stored in memory 2120, and can execute the application based on the comparison result. Display module 2140 can display the information executed according to the application logic via display panel 2141.

[0277] As another example, when the music stream icon displayed on display module 2140 is selected, processor 2110 obtains user input via input sensor 2161-2 and can activate the music stream application stored in memory 2120. When a music execution command is entered in the music stream application, processor 2110 can activate sound output module 2163 to provide the user with sound information corresponding to the music execution command.

[0278] The operation of electronic device 2101 has been briefly described above. The configuration of electronic device 2101 will be described in detail below. Some components of electronic device 2101 described below can be integrated and provided as a single component, or a single component can be provided separately as two or more components.

[0279] Electronic device 2101 can communicate with external electronic device 2102 via a network (e.g., a short-range wireless communication network or a long-range wireless communication network). In embodiments, electronic device 2101 may include processor 2110, memory 2120, input module 2130, display module 2140, power management module 2150, internal module 2160, and external module 2170. In embodiments, at least one of the components may be omitted from electronic device 2101, or one or more other components may be added to electronic device 2101. In embodiments, some of the components (e.g., sensor module 2161, antenna module 2162, or voice output module 2163) may be implemented as a single component (e.g., display module 2140).

[0280] The processor 2110 can execute software to control at least one other component (e.g., a hardware or software component) of the electronic device 2101 coupled to the processor 2110, and can perform various data processing or calculations. According to an embodiment, as at least part of the data processing or calculation, the processor 2110 can store commands or data received from another component (e.g., input module 2130, sensor module 2161, or communication module 2173) in volatile memory 2121, can process commands or data stored in volatile memory 2121, and can store result data in non-volatile memory 2122.

[0281] Processor 2110 may include one or more processors, and may include a main processor 2111 and an auxiliary processor 2112. Main processor 2111 may include one or more of a central processing unit (CPU) 2111-1 and an application processor (AP). Main processor 2111 may also include one or more of a graphics processing unit (GPU) 2111-2, a communication processor (CP), and an image signal processor (ISP). Main processor 2111 may also include a neural processing unit (NPU) 2111-3. NPU 2111-3 may be a processor specifically designed to process artificial intelligence models, and the artificial intelligence models may be generated through machine learning. The artificial intelligence model may include multiple layers of artificial neural networks. The artificial neural networks may be deep neural networks (DNNs), convolutional neural networks (CNNs), recurrent neural networks (RNNs), restricted Boltzmann machines (RBMs), deep belief networks (DBNs), bidirectional recurrent deep neural networks (BRDNNs), deep Q-networks, or combinations of two or more of these, but are not limited thereto. In addition to hardware architecture, the artificial intelligence model may additionally or optionally include software architecture. At least two of the processing units and processors described above can be implemented as integrated components (e.g., a single chip), or the corresponding processing units and processors can be implemented as independent components (e.g., multiple chips).

[0282] The auxiliary processor 2112 may include a controller. The controller may include interface conversion circuitry and timing control circuitry. The controller can receive image signals from the main processor 2111, convert the data format of the image signals to meet the interface specifications with the display module 2140, and output image data. The controller can output various control signals required to drive the display module 2140.

[0283] The auxiliary processor 2112 may also include a data conversion circuit 2112-2, a gamma correction circuit 2112-3, or a rendering circuit 2112-4, etc. The data conversion circuit 2112-2 can receive image data from the controller. The data conversion circuit 2112-2 can compensate the image data to display an image at a desired brightness according to the characteristics of the electronic device 2101 or user settings, or it can convert the image data to reduce power consumption or eliminate afterimages. The gamma correction circuit 2112-3 can convert image data or a gamma reference voltage so that the image displayed on the electronic device 2101 has desired gamma characteristics. The rendering circuit 2112-4 can receive image data from the controller and can render the image data taking into account the pixel arrangement of the display panel 2141 in the electronic device 2101. At least one of the data conversion circuit 2112-2, the gamma correction circuit 2112-3, and the rendering circuit 2112-4 can be integrated into another component (e.g., the main processor 2111 or the controller). At least one of the data conversion circuit 2112-2, the gamma correction circuit 2112-3, and the rendering circuit 2112-4 can be integrated into the data driver 2143 described below.

[0284] Memory 2120 may store various data used by at least one component of electronic device 2101 (e.g., processor 2110 or sensor module 2161). For example, the various data may include input data or output data for commands associated with it. Memory 2120 may include at least one of volatile memory 2121 and non-volatile memory 2122.

[0285] The input module 2130 can receive commands or data from outside the electronic device 2101 (e.g., a user or external electronic device 2102) that will be used by components of the electronic device 2101 (e.g., processor 2110, sensor module 2161, or sound output module 2163).

[0286] Input module 2130 may include a first input module 2131 for receiving commands or data from a user and a second input module 2132 for receiving commands or data from an external electronic device 2102. The first input module 2131 may include a microphone, mouse, keyboard, keys (e.g., buttons), or pen (e.g., a passive or active pen). The second input module 2132 may support a specified protocol that enables the electronic device 2101 to be connected to the external electronic device 2102 via wiring or wirelessly. In embodiments, the second input module 2132 may include a High Definition Multimedia Interface (HDMI), a Universal Serial Bus (USB) interface, a Secure Digital (SD) card interface, or an audio interface. The second input module 2132 may include a connector that can physically connect the electronic device 2101 to the external electronic device 2102. For example, the second input module 2132 may include an HDMI connector, a USB connector, an SD card connector, or an audio connector (e.g., a headphone connector).

[0287] Display module 2140 can visually provide information to the user. Display module 2140 may include display panel 2141, gate driver 2142, and data driver 2143. Display module 2140 may also include a window, bracket, and support for protecting display panel 2141.

[0288] Display panel 2141 may include a liquid crystal display panel, an organic light-emitting display panel, or an inorganic light-emitting display panel, but the type of display panel 2141 is not limited to these. Display panel 2141 may be a rigid type display panel or a flexible type display panel that can be rolled or folded. Display module 2140 may also include a support member, bracket, or heat dissipation component that supports display panel 2141.

[0289] Gate driver 2142 can be mounted as a driver chip on display panel 2141. In embodiments, gate driver 2142 can be integrated into display panel 2141. For example, gate driver 2142 may include an amorphous silicon thin-film transistor (TFT) gate (ASG) driver circuit, a low-temperature polycrystalline silicon (LTPS) TFT gate driver circuit, or an oxide semiconductor TFT gate (OSG) driver circuit embedded in display panel 2141. Gate driver 2142 can receive control signals from controller and can output scan signals to display panel 2141 in response to control signals. For example, gate driver 2142 may include a stage that generates a common control signal and outputs multiple gate signals based on the common control signal. Based on input control signal CONT, gate driver 2142 can be driven according to any one of the first drive MODE 1, second drive MODE 2, third drive MODE 3, fourth drive MODE 4, and fifth drive MODE 5. For example, when processor 2110 selects first drive MODE 1, gate driver 2142 can be driven in the timing of first drive MODE 1 (e.g., Figure 4 The gate driver 2142 can be driven according to the timing of the second drive MODE 2. For example, when the processor 2110 selects the second drive MODE 2, the gate driver 2142 can be driven according to the timing of the second drive MODE 2 (e.g., the timing of the second drive MODE 2). Figure 8 The gate driver 2142 can be driven according to the timing of the third drive MODE 3. For example, when the processor 2110 selects the third drive MODE 3, the gate driver 2142 can be driven according to the timing of the third drive MODE 3 (e.g., the timing of the third drive MODE 3). Figure 17 The gate driver 2142 can be driven according to the timing of the fourth drive MODE 4. For example, when the processor 2110 selects the fourth drive MODE 4, the gate driver 2142 can be driven according to the timing of the fourth drive MODE 4 (e.g., the timing of the fourth drive MODE 4). Figure 18 The gate driver 2142 can be driven using the timing of the fifth drive MODE 5. For example, when the processor 2110 selects the fifth drive MODE 5, the gate driver 2142 can be driven using the timing of the fifth drive MODE 5 (e.g., ...). Figure 19 The timing is driven.

[0290] The display panel 2141 may also include a transmitter driver. The transmitter driver can output a transmitter control signal to the display panel 2141 in response to a control signal received from the controller. The transmitter driver may be formed separately from the gate driver 2142, or it may be integrated into the gate driver 2142.

[0291] The data driver 2143 can receive control signals from the controller, can convert image data into analog voltages (e.g., data voltages) in response to the control signals, and can then output the data voltages to the display panel 2141.

[0292] The data driver 2143 can be incorporated into other components (e.g., a controller). Furthermore, the functions of the interface conversion circuitry and timing control circuitry of the controller described above can be integrated into the data driver 2143.

[0293] The display module 2140 may also include a transmitter driver or a voltage generator circuit, etc. The voltage generator circuit can output various voltages for driving the display panel 2141.

[0294] Power management module 2150 can supply power to components of electronic device 2101. Power management module 2150 may include a battery charged with a power supply voltage. The battery may include a non-rechargeable primary battery, a rechargeable secondary battery, or a fuel cell. Power management module 2150 may include a power management integrated circuit (PMIC). The PMIC can optimally supply power to each of the modules described above and below. Power management module 2150 may include a wireless power transmitting / receiving component electrically connected to the battery. The wireless power transmitting / receiving component may include multiple antenna radiators in the form of coils.

[0295] The electronic device 2101 may also include an internal module 2160 and an external module 2170. The internal module 2160 may include a sensor module 2161, an antenna module 2162, and a sound output module 2163. The external module 2170 may include a camera module 2171, an optical module 2172, and a communication module 2173.

[0296] Sensor module 2161 can detect input via the user's body or via the pen of the first input module 2131, and can generate an electrical signal or data value corresponding to the input. Sensor module 2161 may include at least one of fingerprint sensor 2161-1, input sensor 2161-2, and digitizer 2161-3.

[0297] The fingerprint sensor 2161-1 can generate data values ​​corresponding to a user's fingerprint. The fingerprint sensor 2161-1 can include either an optical fingerprint sensor or a capacitive fingerprint sensor.

[0298] Input sensor 2161-2 can generate data values ​​corresponding to the coordinate information of user body input or pen input. Input sensor 2161-2 can convert capacitance changes caused by input into data values. Input sensor 2161-2 can detect input via a passive pen, or can send data to or receive data from an active pen.

[0299] Input sensor 2161-2 can measure biosignals such as blood pressure, water content, or body fat. For example, when a part of a user's body touches the sensor layer or sensing panel and remains stationary for a specific period of time, input sensor 2161-2 can detect biosignals based on changes in the electric field caused by said part of the body and output the user's desired information to display module 2140.

[0300] The digitizer 2161-3 can generate data values ​​corresponding to coordinate information input via a pen. The digitizer 2161-3 can convert the amount of electromagnetic change caused by the input into data values. The digitizer 2161-3 can detect input via a passive pen, or can send data to or receive data from an active pen.

[0301] At least one of the fingerprint sensor 2161-1, the input sensor 2161-2, and the digitizer 2161-3 can be implemented as a sensor layer formed on the display panel 2141 by a continuous process. The fingerprint sensor 2161-1, the input sensor 2161-2, and the digitizer 2161-3 can be disposed above the display panel 2141, or at least one of the fingerprint sensor 2161-1, the input sensor 2161-2, and the digitizer 2161-3 can be disposed below the display panel 2141.

[0302] Two or more of the fingerprint sensor 2161-1, input sensor 2161-2, and digitizer 2161-3 can be integrated into a single sensing panel using the same process. When integrated into a single sensing panel, the sensing panel can be positioned between the display panel 2141 and a window positioned above the display panel 2141. In an embodiment, the sensing panel can be positioned on the window, but the position of the sensing panel is not limited thereto.

[0303] At least one of the fingerprint sensor 2161-1, the input sensor 2161-2, and the digitizer 2161-3 can be embedded in the display panel 2141. In other words, at least one of the fingerprint sensor 2161-1, the input sensor 2161-2, and the digitizer 2161-3 can be formed simultaneously by a process for forming elements (e.g., light-emitting elements, transistors, etc.) included in the display panel 2141.

[0304] Furthermore, sensor module 2161 can generate electrical signals or data values ​​corresponding to the internal or external states of electronic device 2101. For example, sensor module 2161 may also include a gesture sensor, gyroscope sensor, atmospheric pressure sensor, magnetic sensor, accelerometer, grip sensor, proximity sensor, color sensor, infrared (IR) sensor, biometric sensor, temperature sensor, humidity sensor, or illuminance sensor.

[0305] Antenna module 2162 may include one or more antennas for transmitting or receiving signals or power to or from an external source. In an embodiment, communication module 2173 may transmit or receive signals to or from external electronic device 2102 via an antenna suitable for a communication method. The antenna pattern of antenna module 2162 may be integrated into a component of display module 2140 (e.g., display panel 2141) or into input sensors 2161-2.

[0306] The sound output module 2163 can output sound signals to the outside of the electronic device 2101. For example, the sound output module 2163 may include a speaker or a receiver. The speaker can be used for general purposes such as playing multimedia or playing recordings. The receiver can be used to receive incoming calls. In embodiments, the receiver can be implemented separately from the speaker or as part of the speaker. The sound output pattern of the sound output module 2163 can be integrated into the display module 2140.

[0307] Camera module 2171 can capture still images and moving images. In embodiments, camera module 2171 may include one or more lenses, an image sensor, or an image signal processor. Camera module 2171 may also include an infrared camera capable of measuring the presence or absence of a user, the user's position, and the user's line of sight.

[0308] The optical module 2172 can provide light. The optical module 2172 may include a light-emitting diode or a xenon lamp. The optical module 2172 can operate in conjunction with the camera module 2171, or it can operate independently of the camera module 2171.

[0309] Communication module 2173 can support the establishment of a wired or wireless communication channel between electronic device 2101 and external electronic device 2102, and perform communication via the established communication channel. Communication module 2173 may include a wireless communication module (e.g., a cellular communication module, a short-range wireless communication module, or a Global Navigation Satellite System (GNSS) communication module) or a wired communication module (e.g., a local area network (LAN) communication module or a power line communication (PLC) module). Communication module 2173 can communicate via a short-range communication network (e.g., Bluetooth). ® The communication module 2173 communicates with external electronic devices 2102 via Wi-Fi Direct or Infrared Data Association (IrDA) networks or remote communication networks (e.g., cellular networks, the Internet, or computer networks (e.g., LANs or WANs)). These various types of communication modules 2173 can be implemented as a single chip or as multiple chips that are separate from each other.

[0310] Input module 2130, sensor module 2161 and camera module 2171, etc., can be used in conjunction with processor 2110 to control the operation of display module 2140.

[0311] The processor 2110 can output commands or data to the display module 2140, the sound output module 2163, the camera module 2171, or the optical module 2172 based on the input data received from the input module 2130. For example, the processor 2110 can generate image data corresponding to the input data applied by a mouse or active pen, and can output the image data to the display module 2140. In an embodiment, the processor 2110 can generate command data corresponding to the input data, and can output the command data to the camera module 2171 or the optical module 2172. When no input data is received from the input module 2130 within a certain time period, the processor 2110 can switch the operating mode of the electronic device 2101 to a low-power mode or a sleep mode, thereby reducing the power consumption of the electronic device 2101.

[0312] Processor 2110 can output commands or data to display module 2140, sound output module 2163, camera module 2171, or optical module 2172 based on sensing data received from sensor module 2161. For example, processor 2110 can compare authentication data applied by fingerprint sensor 2161-1 with authentication data stored in memory 2120, and then execute an application based on the comparison result. Processor 2110 can execute commands or output corresponding image data to display module 2140 based on sensing data sensed by input sensor 2161-2 or digitizer 2161-3. If sensor module 2161 includes a temperature sensor, processor 2110 can receive temperature data from sensor module 2161 and can also perform brightness correction on image data based on the temperature data.

[0313] Processor 2110 can receive measurement data from camera module 2171 regarding the presence or absence of a user, the user's position, and the user's gaze. Processor 2110 can also perform brightness correction on image data based on the measurement data. For example, after processor 2110 determines the presence or absence of a user based on input from camera module 2171, data conversion circuit 2112-2 or gamma correction circuit 2112-3 can perform brightness correction on the image data, and processor 2110 can provide the brightness-corrected image data to display module 2140.

[0314] At least some of the components described above can be coupled to each other and transmit signals (e.g., commands or data) between them via inter-peripheral communication schemes (e.g., bus, general purpose input and output (GPIO), serial peripheral interface (SPI), mobile industrial processor interface (MIPI), or ultrapath interconnect (UPI)). Processor 2110 can communicate with display module 2140 via a pre-defined interface. Furthermore, any of the communication methods described above can be used between processor 2110 and display module 2140, but the communication methods between processor 2110 and display module 2140 are not limited to those described above.

[0315] The electronic device 2101 according to the various embodiments described above can be of various types. For example, the electronic device 2101 may include at least one of a portable communication device (e.g., a smartphone), a computer device, a portable multimedia device, a portable medical device, a camera, a wearable device, and a home appliance. However, the electronic device 2101 according to the embodiments is not limited to the devices described above.

[0316] The display device according to the embodiments can be applied to display devices including computers, laptops, mobile phones, smartphones, smart tablets, portable multimedia players (PMPs), personal digital assistants (PDAs), or MP3 players.

[0317] The foregoing is illustrative of the inventive concept and is not to be construed as limiting it. Although several embodiments of the inventive concept have been described, those skilled in the art will readily appreciate that numerous modifications are possible in the embodiments without substantially departing from the novel teachings and advantages of the inventive concept. Therefore, all such modifications are intended to be included within the scope of the inventive concept as defined in the claims. In the claims, the method plus function clause is intended to cover not only the structures described herein for performing the recited functions, but also equivalent structures. Therefore, it will be understood that the foregoing is illustrative of the inventive concept and is not to be construed as limiting it to the specific embodiments disclosed, and modifications to the disclosed embodiments and other embodiments are intended to be included within the scope of the appended claims. The inventive concept is defined by the appended claims, including equivalents of the claims.

Claims

1. A gate driver, wherein, The gate driver includes: The control signal generation block is configured to generate a first common control signal based on a first carry signal and a second carry signal, and to generate a second common control signal based on a third carry signal and a fourth carry signal; The output control signal generation block is configured to generate an output control signal based on the first input signal, the second input signal, and the boost control signal. The first gate signal output control block is configured to generate a first output control voltage based on the output control signal, the first carry signal, and the second carry signal; The first gate signal control block is configured to output a plurality of first gate signals and the boost control signal based on the first common control signal, the first output control voltage, the boost clock signal and a plurality of first clock signals; The second gate signal output control block is configured to generate a second output control voltage based on the output control signal, the third carry signal, and the fourth carry signal; and The second gate signal control block is configured to output a plurality of second gate signals based on the second common control signal, the second output control voltage, the boost clock signal and a plurality of second clock signals.

2. The gate driver according to claim 1, wherein, The output control signal generation block includes: The first output control transistor includes a control electrode that receives the first input signal, a first electrode that receives the boost control signal, and a second electrode connected to the first output control node. The second output control transistor includes a control electrode that receives the first input signal, a first electrode connected to the first output control node, and a second electrode connected to the second output control node. The third output control transistor includes a control electrode connected to the second output control node and a second electrode connected to the first output control node; The fourth output control transistor includes a control electrode for receiving the second input signal, a first electrode connected to the first output control node, and a second electrode connected to the first common control node; and The output control capacitor includes a first electrode that receives a first high voltage and a second electrode that is connected to the second output control node.

3. The gate driver according to claim 1, wherein, When the first input signal has an activation level and the boost clock signal has a clock high level, the output control signal generation block stores the output control signal.

4. The gate driver according to claim 3, wherein, When the second input signal has an activation level, the output control signal generation block outputs the output control signal.

5. The gate driver according to claim 3, wherein, The first gate signal control block also outputs a carry signal based on the carry clock signal, and When the first input signal has the activation level, the carry clock signal has a clock high level.

6. The gate driver according to any one of claims 1 to 5, wherein, The frame period in which the gate driver is driven includes the effective period during which the plurality of first gate signals are output and the blanking period following the effective period. During the blanking period, the first gate signal among the plurality of first gate signals has an activation level, and During the blanking period, the second gate signal among the plurality of second gate signals has an activation level.

7. The gate driver according to claim 6, wherein, During the blanking period, the first output control voltage has a first high voltage, and the first clock signal corresponding to the first gate signal among the plurality of first clock signals switches between clock high level and clock low level.

8. The gate driver according to claim 7, wherein, During the blanking period, the other first gate signals among the plurality of first gate signals have an inactive level, and During the blanking period, other second gate signals among the plurality of second gate signals have an inactive level.

9. The gate driver according to any one of claims 1 to 5, wherein, The first output control voltage has a first high voltage or a second high voltage that is lower than the first high voltage. Wherein, the second output control voltage has either the first high voltage or the second high voltage. Specifically, when the first output control voltage has the first high voltage, the plurality of first gate signals are output, and Specifically, when the second output control voltage has the first high voltage, the plurality of second gate signals are output.

10. The gate driver according to any one of claims 1 to 5, wherein, The plurality of first gate signals include a first scan gate signal and a second scan gate signal. The frame period in which the gate driver is driven includes the effective period during which the plurality of first gate signals are output and the blanking period following the effective period. The period during which the first scan gate signal has an activation level is the same as the period during which the second scan gate signal has an activation level.

11. A display device, wherein, The display device includes: The display panel includes multiple pixels; A gate driver configured to output a plurality of gate signals to the plurality of pixels; A data driver configured to apply a data voltage to the plurality of pixels; and The drive controller is configured to control the gate driver and the data driver. The gate driver includes multiple stages. Wherein, at least one of the plurality of levels includes: The control signal generation block is configured to generate a first common control signal based on a first carry signal and a second carry signal, and to generate a second common control signal based on a third carry signal and a fourth carry signal; The output control signal generation block is configured to generate an output control signal based on the first input signal, the second input signal, and the boost control signal. The first gate signal output control block is configured to generate a first output control voltage based on the output control signal, the first carry signal, and the second carry signal; The first gate signal control block is configured to output a plurality of first gate signals and the boost control signal from the plurality of gate signals based on the first common control signal, the first output control voltage, the boost clock signal and a plurality of first clock signals; The second gate signal output control block is configured to generate a second output control voltage based on the output control signal, the third carry signal, and the fourth carry signal; and The second gate signal control block is configured to output a plurality of second gate signals from the plurality of gate signals based on the second common control signal, the second output control voltage, the boost clock signal and a plurality of second clock signals.

12. The display device according to claim 11, wherein, The output control signal generation block includes: The first output control transistor includes a control electrode that receives the first input signal, a first electrode that receives the boost control signal, and a second electrode connected to the first output control node. The second output control transistor includes a control electrode that receives the first input signal, a first electrode connected to the first output control node, and a second electrode connected to the second output control node. The third output control transistor includes a control electrode connected to the second output control node and a second electrode connected to the first output control node; The fourth output control transistor includes a control electrode for receiving the second input signal, a first electrode connected to the first output control node, and a second electrode connected to the first common control node; and The output control capacitor includes a first electrode that receives a first high voltage and a second electrode that is connected to the second output control node.

13. The display device according to claim 11 or 12, wherein, The gate driver includes a first stage and a second stage. The plurality of gate signals include a first scan gate signal, a second scan gate signal, a third scan gate signal, and a fourth scan gate signal, as well as a first sensing gate signal, a second sensing gate signal, a third sensing gate signal, and a fourth sensing gate signal. The first stage outputs the first scan gate signal, the second scan gate signal, the first sensing gate signal, and the second sensing gate signal, and... The second stage outputs the third scan gate signal, the fourth scan gate signal, the third sensing gate signal, and the fourth sensing gate signal.

14. The display device according to claim 13, wherein, The display device further includes: a sensor driver configured to perform a sensing operation on at least one of the plurality of pixels. The frame period during which the plurality of pixels are driven includes an effective period during which the data voltage is applied and a blanking period during which the sensing operation is performed on the at least one pixel. Wherein, when the at least one pixel is connected to the first stage, the first output control voltage of the first stage has a first high voltage during the blanking period.

15. An electronic device, wherein, The electronic device includes: The controller is configured to output input image data and input control signals; A display panel configured to display an image based on the input image; and A panel driver configured to drive the display panel based on the input image data and the input control signals. The display panel includes multiple pixels. The panel driver includes a gate driver according to any one of claims 1 to 10, the gate driver being configured to output a plurality of first gate signals and a plurality of second gate signals to the plurality of pixels. The input control signal includes data that selects the driving mode of the display panel.

Images