Display panel and driving method thereof

Abstract

This disclosure relates to the field of display technology, and mainly to display panels and their driving methods. The display panel includes multiple subpixel rows, multiple data traces, and multiple scan lines. In two adjacent subpixel rows, one subpixel row includes a first subpixel group, and the other subpixel row includes a second subpixel group. Both the second and second subpixel groups include two adjacent subpixels in the same row. The multiple data traces and multiple scan lines intersect to define multiple subpixel regions, and the length of each subpixel region along the scan line extension direction is greater than its length along the data trace extension direction. Two subpixels in the first subpixel group are connected to the same data trace and to different scan lines. Two subpixels in the second subpixel group are connected to the same data trace and to different scan lines. The display panel includes three types of subpixels located in three adjacent subpixel rows, with each row of subpixels having the same color. This display panel can reduce the risk of horizontal stripes.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more specifically, to a display panel and a driving method thereof. Background Technology

[0002] In related technologies, the display panel is controlled by alternating odd and even driving of the gate-on-a-side (GOA) circuit. However, under this driving method, for sub-pixels in the same column, there will be alternating changes between the near and far ends, and the charging rate will also vary accordingly. The closer the sub-pixels are to the left and right edges, the greater the difference in charging rate. When the charging rate is insufficient, fine horizontal lines will be generated.

[0003] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0004] The purpose of this disclosure is to overcome the shortcomings of the prior art and provide a display panel and its driving method that can reduce the risk of horizontal stripes.

[0005] According to one aspect of this disclosure, a display panel is provided, the display panel including a plurality of subpixel rows arranged sequentially; in two adjacent subpixel rows, one subpixel row includes a plurality of first subpixel groups arranged sequentially, the first subpixel group including two subpixels adjacent to each other in the same row; the other subpixel row includes a plurality of second subpixel groups arranged sequentially, the second subpixel group including two subpixels adjacent to each other in the same row; adjacent first subpixel groups and second subpixel groups are alternately arranged;

[0006] The display panel further includes multiple data traces and multiple scan lines. The multiple data traces and multiple scan lines intersect each other to define multiple sub-pixel areas. Each sub-pixel area has one sub-pixel. The length of the sub-pixel area along the extension direction of the scan line is greater than the length of the sub-pixel area along the extension direction of the data trace.

[0007] The two sub-pixels of the first sub-pixel group are connected to the same data trace but to different scan lines; the two sub-pixels of the second sub-pixel group are connected to the same data trace but to different scan lines.

[0008] The display panel includes three types of sub-pixels, which are located in three adjacent rows of sub-pixels, and the sub-pixels in the same row have the same color.

[0009] In one embodiment of this disclosure, the display panel includes a plurality of sub-pixel column groups;

[0010] The sub-pixel column group includes a first sub-pixel column; the first sub-pixel column includes a plurality of third sub-pixel groups arranged sequentially; the third sub-pixel group includes two adjacent sub-pixels in the same column;

[0011] The two sub-pixels of the third sub-pixel group are connected to the same scan line.

[0012] In one embodiment of this disclosure, the three sub-pixels have different colors.

[0013] In one embodiment of this disclosure, the display panel includes multiple scan line groups, each scan line group includes multiple scan lines, and each scan line in the same scan line group is connected to the output of the same shift register through a multiplexer.

[0014] In one embodiment of this disclosure, the display panel has a plurality of pixels, the pixels including a plurality of sub-pixels of different colors arranged sequentially along a column direction; the number of scan lines in the scan line group is the same as the number of sub-pixels of the pixel.

[0015] In one embodiment of this disclosure, the display panel has multiple pixel rows, and the scan line group is configured to correspond one-to-one with the pixel rows; each scan line of the scan line group is used to drive the corresponding pixel row.

[0016] In one embodiment of this disclosure, the data traces connected to the first sub-pixel group are located between two sub-pixels of the first sub-pixel group, and the data traces connected to the second sub-pixel group are located between two sub-pixels of the second sub-pixel group.

[0017] In one embodiment of this disclosure, in two adjacent sub-pixel rows connected to the same data trace, a scan line connected to two intersecting sub-pixels is located between the two adjacent sub-pixel rows.

[0018] In one embodiment of this disclosure, the display panel has a first gate driving circuit and a second gate driving circuit, which are distributed on both sides of the display panel.

[0019] The shift registers connected to two adjacent scan line groups are located in the first gate drive circuit and the second gate drive circuit, respectively.

[0020] In one embodiment of this disclosure, one of the two sub-pixels in the first sub-pixel group is arranged in the same column as one of the two sub-pixels in the second sub-pixel group.

[0021] According to another aspect of this disclosure, a method for driving a display panel is also provided, comprising:

[0022] The display panel is driven alternately using the first driving mode and the second driving mode;

[0023] In the first driving mode, within the same frame, the voltage of the pixel electrode of each sub-pixel driven by the even-numbered data line is not less than the voltage of the common electrode, and the voltage of the pixel electrode of each sub-pixel driven by the odd-numbered data line is not greater than the voltage of the common electrode.

[0024] In the second driving mode, within the same frame, the voltage of the pixel electrode of each sub-pixel driven by the even-numbered data line is not greater than the voltage of the common electrode, and the voltage of the pixel electrode of each sub-pixel driven by the odd-numbered data line is not less than the voltage of the common electrode.

[0025] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0026] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0027] Figure 1 This is a schematic diagram of the structure of the display panel in one embodiment of the present disclosure.

[0028] Figure 2 This is a schematic diagram of the structure of the display panel in one embodiment of the present disclosure, wherein, Figure 2 Only the data trace located in the middle is shown; the data traces at both ends are not shown.

[0029] Figure 3 This is a schematic diagram of the structure of the display panel in one embodiment of the present disclosure.

[0030] Figure 4 This is a schematic diagram of the structure of the display panel in one embodiment of the present disclosure.

[0031] Figure 5 This is a schematic diagram of the structure of the display panel in one embodiment of the present disclosure.

[0032] Figure 6 This is a schematic diagram of the structure of the display panel in one embodiment of the present disclosure.

[0033] Figure 7 This is a schematic diagram of the structure of the display panel in one embodiment of the present disclosure.

[0034] Figure 8 This is a waveform diagram of data routing under a solid color screen in one embodiment of the present disclosure.

[0035] Figure 9 This is a schematic diagram of the structure of the display panel in another embodiment of the present disclosure. Detailed Implementation

[0036] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore detailed descriptions of them will be omitted. Furthermore, the drawings are merely illustrative of this disclosure and are not necessarily drawn to scale.

[0037] Although relative terms such as "up" and "down" are used in this specification to describe the relative relationship of one component of an icon to another, these terms are used only for convenience, such as according to the orientation of the examples shown in the accompanying drawings. It is understood that if the device of the icon is flipped upside down, the component described as "up" will become the component described as "down." When a structure is "up" of another structure, it may mean that the structure is integrally formed on the other structure, or that the structure is "directly" mounted on the other structure, or that the structure is "indirectly" mounted on the other structure through another structure.

[0038] The terms “a,” “one,” “the,” and “the” are used to indicate the existence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.; the terms “first,” “second,” and “third,” etc., are used only as markers and are not a limitation on the number of objects.

[0039] In this application, unless otherwise expressly specified and limited, the term "connection" shall be interpreted broadly. For example, "connection" may be a fixed connection, a detachable connection, or an integral part; it may be a direct connection or an indirect connection through an intermediate medium.

[0040] In this embodiment, a thin-film transistor (TFT) includes an active layer, a gate insulating layer, and a gate, stacked together. The active layer is located within the semiconductor layer and includes a channel region and source and drain electrodes located on opposite sides of the channel region. The channel region retains semiconductor characteristics, while both the source and drain electrodes are conductive. In this embodiment, in cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source" and "drain" are sometimes interchanged; that is, the "drain" and "source" electrodes can be interchanged. In this embodiment, for any given transistor, one of the "source" and "drain" electrodes is referred to as the first electrode of the transistor, and the other is referred to as the second electrode of the transistor.

[0041] This disclosure provides a liquid crystal display panel (PNL), see [link to previous document]. Figure 1 The liquid crystal display panel (PNL) includes an array substrate (ARR) and a color filter substrate (CF) arranged in pairs, and a liquid crystal layer (LC) sandwiched between the ARR and CF. The PNL also has a sealing adhesive (FSA) surrounding the LC. The ARR drives the deflection of the liquid crystal molecules in the LC to control the amount of light transmitted, achieving grayscale display. The CF allows light transmitted through the LC to pass through and form corresponding colored light, thus achieving full-color display.

[0042] See Figure 2 The display panel PNL includes a display area AA and a non-display area BB located outside the display area AA. The non-display area BB can be a continuous annular area surrounding the display area AA, or it can be a discontinuous area surrounding the display area AA. The display area AA can emit light to display images, while the non-display area BB does not emit light.

[0043] See Figures 1-7 ,exist Figures 2-4In this embodiment, the array substrate ARR is a substrate facing the backlight module. By changing the signals and voltages on the array substrate ARR, the rotation direction of the liquid crystal molecules in the liquid crystal layer LC is controlled, thereby controlling whether polarized light is emitted from each pixel, thus achieving the display purpose. In the display area AA, the array substrate ARR has multiple scan lines GL and multiple data lines DL located on one side of the substrate SBT. In this example, the scan lines GL are arranged along the row direction, and the data lines DL are arranged along the column direction. The multiple scan lines GL and multiple data lines DL intersect in their extending directions, defining multiple sub-pixel areas PA. Sub-pixels PIX and pixel driving circuits can be located in these sub-pixel areas PA. In this example, the pixel driving circuit can be a thin-film transistor acting as a switching transistor. The sub-pixel PIX can include a pixel electrode and a common electrode, with the pixel electrode and the common electrode at least partially overlapping to form a capacitor. The array substrate ARR can also be provided with a common voltage line extending along the row direction. The second terminal of the switching transistor is electrically connected to the data trace DL, the first terminal is electrically connected to the pixel electrode, the gate of the switching transistor is electrically connected to the scan line GL, and the common electrode is electrically connected to the common voltage trace. During operation, the common voltage trace can apply a common voltage to the common electrode; the switching transistor can respond to the scan signal applied on the scan line GL by applying the driving voltage from the data trace DL to the pixel electrode. In this way, by controlling the electric field strength between the pixel electrode and the common electrode, the degree of twisting or collapsing of the liquid crystal molecules within the corresponding range of the pixel electrode can be adjusted, thereby adjusting the polarization direction of the polarized light passing through the liquid crystal molecules, and ultimately adjusting the light extraction efficiency of the display panel PNL within the corresponding range of the pixel electrode, thus achieving brightness control of the sub-pixel (PIX).

[0044] In one example disclosed herein, see Figure 6 The switching transistor is a bottom-gate thin-film transistor. It will be understood that in other embodiments of this disclosure, see [reference needed]. Figure 7The switching transistor can also be a top-gate thin-film transistor. For example, the array substrate (ARR) includes a substrate SBT, a semiconductor layer, a gate insulating layer GI, a gate layer GT, an interlayer dielectric layer, source / drain metal layers, a passivation layer, and a pixel electrode layer stacked together. The gate layer GT has side branches, which can serve as the gate of the switching transistor. The semiconductor layer forms the active layer of the switching transistor, which includes a channel region of the switching transistor and a first electrode and a second electrode of the switching transistor located on both sides of the channel region. Multiple pixel electrodes are disposed within the pixel electrode layer, with a certain gap reserved between adjacent pixel electrodes. The source / drain metal layer forms data traces, as well as a first connection line and a second connection line; the first connection line is used to electrically connect the data traces to the first electrode of the switching transistor, and the second connection line is used to electrically connect the second electrode of the switching transistor to the pixel electrode. The gate insulating layer GI has connection vias that expose partial regions of the first and second electrodes of the switching transistor, respectively. A first connection line is electrically connected to the first electrode of the switching transistor through the connection vias in the gate insulating layer GI, and one end of a second connection line is electrically connected to the second electrode of the switching transistor through the connection vias in the gate insulating layer GI. The passivation layer has connection vias that expose partial regions of the second connection line, and the pixel electrode is electrically connected to the second connection line through the connection vias in the passivation layer.

[0045] In one embodiment of this disclosure, the non-display area BB of the array substrate ARR is bonded with an active-stage driving circuit and a gate driving circuit. The gate driving circuit is electrically connected to each scan line GL and is used to apply a scan signal to the scan line GL to turn on the switching transistor. The active-stage driving circuit is electrically connected to the data trace DL and is used to generate a data voltage based on the screen synchronization data and apply it to the data trace DL.

[0046] In related technologies, liquid crystal display panels have gate driving circuits on both sides. These gate driving circuits have multiple cascaded gate driving units. The gate driving circuits (GOAs) on both sides control the display panel using an alternating odd-even driving method. The left gate driving circuit (GOA) controls odd-numbered rows, scanning from left to right, while the right gate driving circuit (GOA) controls even-numbered rows, scanning from right to left. For sub-pixels within the same row, there is a near-far difference. The far end needs to pass through the load of the display area of ​​the panel. Therefore, for sub-pixels in the same column, there will be an alternating near-far change, and the charging rate will vary accordingly. The closer to the left and right edges of the display panel, the greater the difference in charging rate between adjacent columns of sub-pixels. Insufficient charging rate will result in fine horizontal lines, a defective phenomenon.

[0047] To address the aforementioned issues, in one embodiment of this disclosure, the connection method of the data trace (DL) is optimized, such that two adjacent sub-pixels (PIX) located in the same row are connected to the same data trace (DL). For details, see [link to relevant documentation]. Figures 2-5 The display panel PNL includes multiple subpixel rows arranged sequentially. In two adjacent subpixel rows, one subpixel row includes multiple first subpixel groups PIXS1 arranged sequentially, each first subpixel group PIXS1 including two adjacent subpixels in the same row; the other subpixel row includes multiple second subpixel groups PIXS2 arranged sequentially, each second subpixel group PIXS2 including two adjacent subpixels in the same row; adjacent first subpixel groups PIXS1 and second subpixel groups PIXS2 are alternately arranged. It can be understood that if two adjacent subpixel rows are defined as first subpixel row PIXH1 and second subpixel row PIXH2 respectively, then the display panel PNL includes multiple first subpixel rows PIXH1 and multiple second subpixel rows PIXH2. In this design, both the first sub-pixel row PIXH1 and the second sub-pixel row PIXH2 extend along the row direction, and are alternately arranged along the column direction (in this disclosure, the row direction is the extension direction of the scan line GL, and the column direction is the extension direction of the data trace DL). The first sub-pixel row PIXH1 includes multiple sequentially arranged first sub-pixel groups PIXS1, each including two adjacent sub-pixels in the same row. The second sub-pixel row PIXH2 includes multiple sequentially arranged second sub-pixel groups PIXS2, each including two adjacent sub-pixels in the same row. It is understood that the multiple first sub-pixel groups PIXS1 extend sequentially along the row direction, and the multiple second sub-pixel groups PIXS2 extend sequentially along the row direction. In adjacent rows, adjacent first sub-pixel groups PIXS1 and second sub-pixel groups PIXS2 are staggered (it is understood that the first sub-pixel groups PIXS1 and second sub-pixel groups PIXS2 in adjacent rows are staggered in the column direction).

[0048] In this example, interleaving refers to one of the two sub-pixels in the first sub-pixel group PIXS1 being placed in the same column as one of the two sub-pixel pixels in the second sub-pixel group PIXS2. This means that one sub-pixel in each of the first and second sub-pixel groups PIXS1 overlaps in the column direction. The two sub-pixel pixels in the first sub-pixel group PIXS1 are connected to the same data trace DL but to different scan lines GL; similarly, the two sub-pixel pixels in the second sub-pixel group PIXS2 are connected to the same data trace DL but to different scan lines GL. In this disclosure, adjacent data lines DL are interleaved (two adjacent data lines DL connect two sub-pixels in the first sub-pixel group PIXS1 located in odd-numbered rows and two sub-pixels in the second sub-pixel group PIXS2 located in even-numbered rows, respectively). This method reverses the column polarity along the row direction, changing the polarity reversal direction of the sub-pixels connected on adjacent data lines DL from +, -, +, - to +, +, -, +, +, -. When the first and second sub-pixels have the same polarity, it effectively pre-charges the second sub-pixel, thereby increasing the charging rate of some sub-pixels and reducing the frequency of pixel flipping. It also disperses the high-charging-rate sub-pixels, reducing the risk of horizontal stripes.

[0049] In one embodiment of this disclosure, see [link to relevant documentation]. Figure 2 The length of the sub-pixel region PA along the scan line GL is greater than the length of the sub-pixel region PA along the data trace DL.

[0050] In one embodiment of this disclosure, the display panel PNL includes three types of sub-pixels, which are located in three adjacent sub-pixel rows. Sub-pixels located in the same sub-pixel row have the same color. For example, in three adjacent sub-pixel rows, the first sub-pixel row can display red, the second sub-pixel row can display green, and the third sub-pixel row can display blue.

[0051] In one embodiment of this disclosure, multiple sub-pixels (PIX) connected to the same data trace DL are connected to different scan lines.

[0052] See in this example. Figure 5 and Figure 9 In adjacent rows of first sub-pixels connected to the same data trace DL, the two scan lines GL connected to two intersecting sub-pixels PIX are located between two adjacent first sub-pixel groups. Thus, during display, the sub-pixels PIX on the same data trace DL form a Z-shaped lighting sequence. For example... Figure 5As shown, this is the order in which sub-pixels are lit up on the same data trace DL. The new pixel architecture reduces the flipping frequency of source-level data in solid color images, while increasing the charging rate of some sub-pixels. These sub-pixels with high charging rates are distributed in a dotted pattern, reducing the risk of horizontal stripes.

[0053] In one embodiment of this disclosure, see [link to relevant documentation]. Figure 3 The display panel PNL has multiple subpixel column groups PIXLC; the subpixel column group PIXLC includes a first subpixel column PIXV1; the first subpixel column PIXV1 includes a third subpixel group PIXS3 arranged sequentially; the third subpixel group PIXS3 includes two adjacent subpixels in the same column; the two subpixels of the third subpixel group PIXS3 are connected to the same scan line GL. In this disclosure, the two subpixels in the third subpixel group PIXS3 in the same column are connected to the same scan line GL, which facilitates display control and reduces the difficulty of control.

[0054] In one embodiment of this disclosure, see [link to relevant documentation]. Figures 2-5 Sub-pixels (PIX) located in the same row have the same color. It is understood that the pixels of this display panel PNL are arranged horizontally (in this disclosure, horizontal pixels refer to sub-pixels of the same color arranged sequentially along the row direction). Under heavy load of solid color images, the horizontal stripe phenomenon is more pronounced. See also... Figure 8 Where D1 represents the first data trace DL1, using the scheme disclosed herein, pre-charging of some sub-pixels under the same polarity can greatly alleviate the horizontal stripe phenomenon. In this example, "same color" means that each sub-pixel displays the same color during the display stage. This can be understood as the light emitted from the backlight module passing through the color filter layer and then exiting, resulting in each row of sub-pixels displaying the same color. Of course, in other examples, it can also be understood as the backlight module directly emitting the same colored light when displaying each row of sub-pixels.

[0055] In one embodiment of this disclosure, see [link to relevant documentation]. Figure 2 and Figure 3The display panel PNL includes multiple scan line groups (GLS), and each scan line group (GLS) includes multiple scan lines (GL). The scan lines (GL) within the same scan line group (GLS) are connected to the output of the same shift register via a multiplexer. This disclosure employs a multiplexed gate drive circuit architecture. Under this architecture, one gate drive unit can drive multiple rows of gate scan lines (GL), effectively reducing the total number of transistors in the gate drive circuit, thereby enabling the multi-gate display panel to achieve a narrow bezel. The solution disclosed herein is particularly suitable for multi-gate display panels because, under a multiplexed gate drive circuit architecture, the period between the far and near ends of the sub-pixel PIX will be increased. Within a certain range, the larger the period, the more obvious the horizontal stripes. However, with the solution disclosed herein, under a multiplexed gate drive circuit architecture, by using the method of interleaving two adjacent data lines DL (two adjacent data lines DL connect two sub-pixel PIXs in the first sub-pixel group PIXS1 located in odd-numbered rows and two sub-pixel PIXs in the second sub-pixel group PIXS2 located in even-numbered rows respectively), when the front sub-pixel PIX is lit, it will have a pre-charging effect on the rear sub-pixel PIX, reducing the flip frequency of the source-level data and increasing the charging rate of some sub-pixel PIXs. These high-charging-rate pixels are distributed in a dotted pattern, reducing the risk of horizontal stripes.

[0056] In one embodiment of this disclosure, see [link to relevant documentation]. Figure 3 and Figure 4 The display panel PNL has multiple pixels PIXL, and each pixel PIXL includes multiple sub-pixels PIX of different colors arranged sequentially along the column direction. Figure 4 In the example shown, only the green sub-pixel GPIX is displayed. The number of scan lines GL in the scan line group GLS is the same as the number of sub-pixels PIX in the pixel PIXL. In one example, the pixel PIXL includes three sub-pixels PIX: red sub-pixel RPIX, green sub-pixel GPIX, and blue sub-pixel BPIX. Under this feature, the number of scan lines GL in the scan line group GLS is three. This display panel PNL is a Triple-Gate architecture display panel PNL. The Triple-Gate architecture display panel PNL can greatly reduce the number of data traces DL while maintaining the same product resolution, thereby reducing the number of source-level ICs and lowering costs.

[0057] In one embodiment of this disclosure, see [link to relevant documentation]. Figure 3 and Figure 4The display panel PNL has multiple pixel rows (PIXLS), and scan line groups (GLS) are configured one-to-one with the pixel rows (PIXLS). Each scan line (GL) of the scan line group (GLS) is used to drive the corresponding pixel row (PIXLS). It is understood that, in one example, the display panel PNL in this disclosure flips every three rows sequentially. In this disclosure, each multiplexer controls three scan lines (GL), and the sub-pixels (PIX) corresponding to these three scan lines (GL) are not lit simultaneously. In one example, the sub-pixels (PIX) corresponding to these three scan lines (GL) are lit sequentially. It is understood that a switching transistor can be added between each scan line (GL) and the multiplexer, and the opening and closing of the corresponding scan line (GL) connected to the sub-pixel (PIX) can be achieved by turning the switching transistor on and off.

[0058] In one embodiment of this disclosure, see [link to relevant documentation]. Figure 2 The data trace DL connected to the first sub-pixel group PIXS1 is located between two sub-pixels of the first sub-pixel group PIXS1, and the data trace DL connected to the second sub-pixel group PIXS2 is located between two sub-pixels of the second sub-pixel group PIXS2. In this disclosure, the data trace DL is located between two adjacent sub-pixels to improve the aperture ratio.

[0059] In one embodiment of this disclosure, see [link to relevant documentation]. Figures 2-4 The display panel PNL has multiple first data traces DL1 and multiple second data traces DL2, which are arranged alternately along the row direction. A sub-pixel column PIXV is provided between adjacent first data traces DL1 and second data traces DL2. It can be understood that odd-numbered rows of data traces DL can be defined as first data traces DL1, and even-numbered rows of data traces DL can be defined as second data traces DL2. First data traces DL1 are connected to a sub-pixel PIX in either the first sub-pixel row PIXH1 or the second sub-pixel row PIXH2, and second data traces DL2 are connected to a sub-pixel PIX in either the first sub-pixel row PIXH1 or the second sub-pixel row PIXH2. In one example, first data traces DL1 are connected to sub-pixels in the second sub-pixel row PIXH2, and second data traces DL2 are connected to sub-pixels in the first sub-pixel row PIXH1.

[0060] In one embodiment of this disclosure, the display panel PNL has a first gate driving circuit and a second gate driving circuit, which are distributed on both sides of the display panel PNL (in one example, the first gate driving circuit controls the odd-numbered rows with a scanning direction from left to right, and the second gate driving circuit controls the even-numbered rows with a scanning direction from right to left; of course, in other examples, the settings can be reversed); the shift registers connected to two adjacent scan line groups (GLS) are located in the first gate driving circuit and the second gate driving circuit, respectively. Using the display panel PNL of this disclosure, the horizontal lines can be alleviated during alternating odd and even driving.

[0061] Based on the above display panel, the driving method for the PNL of the display panel includes:

[0062] The display panel PNL is driven alternately using the first driving mode and the second driving mode;

[0063] In the first driving mode, within the same frame, the voltage of the pixel electrode of each sub-pixel PIX driven by the even-numbered data line DL is not less than the voltage of the common electrode, and the voltage of the pixel electrode of each sub-pixel PIX driven by the odd-numbered data line DL is not greater than the voltage of the common electrode.

[0064] In the second driving mode, within the same frame, the voltage of the pixel electrode of each sub-pixel PIX driven by the even-numbered data line DL is not greater than the voltage of the common electrode, and the voltage of the pixel electrode of each sub-pixel PIX driven by the odd-numbered data line DL is not less than the voltage of the common electrode.

[0065] In another embodiment of this disclosure, the following can be employed: Figure 9 The layout of the display panel is determined by the connection method described in the example. In this example, the two subpixels of the third subpixel group are connected to different scan lines GL. In this example, the switching transistors in the two adjacent first subpixel groups in the first subpixel row are symmetrically arranged. The switching transistors in the two adjacent second subpixel groups in the second subpixel row are also symmetrically arranged.

[0066] In one embodiment of this disclosure, see [link to relevant documentation]. Figures 1-4The color filter substrate (CF) is the user-facing substrate. The CF contains color filter units and a black matrix surrounding the color filter units (not shown in the diagram). This black matrix needs to cover metal traces such as data lines (DL), common voltage lines, and scan lines (GL) to prevent reflections from these metal traces. Furthermore, the data lines (DL), scan lines (GL), etc., form edge electric fields with electrodes such as common electrodes and pixel electrodes. These edge electric fields can cause disordered deflection of liquid crystal molecules at the edges of the common electrodes and pixel electrodes, easily leading to abnormal reflections at the pixel edges. To ensure the normal display of the liquid crystal display panel (PNL), the black matrix needs to cover the edges of the common electrodes or pixel electrodes.

[0067] In one embodiment of this disclosure, an alignment layer is disposed between an array substrate (ARR) and a color filter substrate (CF). For example, a first alignment layer is disposed on the upper surface of the ARR (the surface of the ARR away from the substrate SBT), and a second alignment layer is disposed on the lower surface of the CF (the surface of the CF close to the substrate SBT). The first alignment layer is formed on a first transparent conductive film (as a pixel layer), and the second alignment layer is formed on a second transparent conductive film (as a common electrode layer).

[0068] In one embodiment of this disclosure, the first transparent conductive film and the second transparent conductive film may be made of indium tin oxide (ITO).

[0069] In one embodiment of this disclosure, polarizers are provided on opposite sides of the array substrate ARR and the color filter substrate CF. For example, a first polarizer is provided on the lower surface of the array substrate ARR (the surface of the array substrate ARR closest to the substrate SBT), and a second polarizer is provided on the upper surface of the color filter substrate CF (the surface of the color filter substrate CF furthest from the substrate SBT).

[0070] In one embodiment of this disclosure, the deflection properties of the first polarizer and the second polarizer can be the same. Of course, they can also be different, for example, perpendicular to each other.

[0071] In one embodiment of this disclosure, to ensure the aesthetic appearance of the entire display screen, monitor, or display device, a second polarizer disposed on the color filter substrate CF can extend outward to the edge of the color filter substrate CF. This prevents an abrupt step on the user-facing side of the color filter substrate CF due to the presence of the second polarizer, thus improving the aesthetics of the display screen, monitor, or display device. Alternatively, the first polarizer disposed on the array substrate ARR can only cover the area of ​​the array substrate ARR located inside the sealing adhesive FSA, thereby saving material for the first polarizer and reducing costs. After the backlight module emits light, the light passes through the first polarizer on the array substrate ARR, illuminates the array substrate ARR, passes through the array substrate ARR, rotates through the liquid crystal layer LC, and then exits from the color filter substrate CF, passing through the second polarizer on the color filter substrate CF to display the image.

[0072] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. A display panel, characterized by, The display panel includes a plurality of sub-pixel rows arranged sequentially; in two adjacent sub-pixel rows, one sub-pixel row includes a plurality of first sub-pixel groups arranged sequentially, the first sub-pixel group including two adjacent sub-pixels in the same row; the other sub-pixel row includes a plurality of second sub-pixel groups arranged sequentially, the second sub-pixel group including two adjacent sub-pixels in the same row; adjacent first sub-pixel groups and second sub-pixel groups are alternately arranged; The display panel further includes multiple data traces and multiple scan lines. The multiple data traces and multiple scan lines intersect each other to define multiple sub-pixel areas. Each sub-pixel area has one sub-pixel. The length of the sub-pixel area along the extension direction of the scan line is greater than the length of the sub-pixel area along the extension direction of the data trace. The two sub-pixels of the first sub-pixel group are connected to the same data trace but to different scan lines; the two sub-pixels of the second sub-pixel group are connected to the same data trace but to different scan lines. The display panel includes three types of sub-pixels, which are located in three adjacent rows of sub-pixels, and the sub-pixels in the same row have the same color.

2. The display panel of claim 1, wherein, The display panel includes multiple sub-pixel column groups; The sub-pixel column group includes a first sub-pixel column; the first sub-pixel column includes a plurality of third sub-pixel groups arranged sequentially; the third sub-pixel group includes two adjacent sub-pixels in the same column; The two sub-pixels of the third sub-pixel group are connected to the same scan line.

3. The display panel of claim 1, wherein, The three types of sub-pixels have different colors.

4. The display panel of claim 1, wherein, The display panel includes multiple scan line groups, each scan line group includes multiple scan lines, and each scan line in the same scan line group is connected to the output of the same shift register through a multiplexer.

5. The display panel of claim 4, wherein, The display panel has multiple pixels, each pixel including multiple sub-pixels of different colors arranged sequentially along the column direction; the number of scan lines in the scan line group is the same as the number of sub-pixels of the pixel.

6. The display panel of claim 5, wherein, The display panel has multiple pixel rows, and the scan line group is set to correspond one-to-one with the pixel rows; each scan line of the scan line group is used to drive the corresponding pixel row.

7. The display panel of claim 1, wherein, The data traces connected to the first sub-pixel group are located between two sub-pixels of the first sub-pixel group, and the data traces connected to the second sub-pixel group are located between two sub-pixels of the second sub-pixel group.

8. The display panel of claim 1, wherein, In two adjacent sub-pixel rows connected to the same data trace, the scan lines connected to a set of two intersecting sub-pixels are located between the two adjacent sub-pixel rows.

9. The display panel of claim 6, wherein, The display panel has a first gate driving circuit and a second gate driving circuit, which are distributed on both sides of the display panel. The shift registers connected to two adjacent scan line groups are located in the first gate drive circuit and the second gate drive circuit, respectively.

10. The display panel of claim 1, wherein, One of the two sub-pixels in the first sub-pixel group is set in the same column as one of the two sub-pixels in the second sub-pixel group.

11. A driving method of a display panel, characterized by, include: The display panel is driven alternately using the first driving mode and the second driving mode; In the first driving mode, within the same frame, the voltage of the pixel electrode of each sub-pixel driven by the even-numbered data line is not less than the voltage of the common electrode, and the voltage of the pixel electrode of each sub-pixel driven by the odd-numbered data line is not greater than the voltage of the common electrode. In the second driving mode, within the same frame, the voltage of the pixel electrode of each sub-pixel driven by the even-numbered data line is not greater than the voltage of the common electrode, and the voltage of the pixel electrode of each sub-pixel driven by the odd-numbered data line is not less than the voltage of the common electrode.

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