Memory system based on ubm protocol packaging

Abstract

This invention relates to the field of chip technology, and more particularly to a memory system based on the UBM protocol packaging, comprising a UBM device, a silicon interposer, and a GPU, wherein the GPU includes a UBM physical layer; the UBM device, silicon interposer, and UBM physical layer are interconnected based on a preset UBM physical interconnect protocol, where UBM is an ultra-high bandwidth memory, with a bandwidth higher than that of HBM4; the UBM physical interconnect protocol includes: the UBM device being connected to the silicon interposer using a hybrid bonding packaging method, the UBM physical layer being connected to the silicon interposer using a hybrid bonding packaging method, and the UBM device and the UBM physical layer establishing an interconnection through wiring resources in the silicon interposer. This invention improves the bandwidth line density and bandwidth areal density of the memory system packaging structure.

Description

Technical Field

[0001] This invention relates to the field of chip technology, and in particular to a memory system based on UBM protocol packaging. Background Technology

[0002] High Bandwidth Memory (HBM) is a communication protocol for high-bandwidth memory systems, and it has evolved to HBM4. HBM4 utilizes advanced packaging methods, such as Through Silicon Vias (TSV) technology, to vertically stack multiple Dynamic Random Access Memory (DRAM) chips and interconnect them with GPUs (Graphics Processing Units) or other processors via silicon interposers, thus achieving a high-capacity, high-bandwidth memory system in a smaller physical space. Existing HBM4-based packaging structures use micro-bump technology to interconnect the HBM4 physical layer (PHY) in the GPU with HBM4 devices through a silicon interposer, forming a memory system packaging structure based on the HBM4 protocol. However, this results in lower bandwidth line density and bandwidth areal density. Furthermore, while silicon interposers offer abundant wiring resources, existing HBM4-based memory systems only utilize a portion of the silicon interposer's boundary area. Utilizing the central region of the silicon interposer for interconnection would be prohibitively expensive. Therefore, improving the bandwidth line density and bandwidth areal density of memory system packaging structures has become an urgent technical problem to be solved. Summary of the Invention

[0003] The purpose of this invention is to provide a memory system based on the UBM protocol, which improves the bandwidth line density and bandwidth areal density of the memory system packaging structure.

[0004] This invention provides a memory system based on the UBM protocol, including a UBM device, a silicon interposer, and a GPU, wherein the GPU includes a UBM physical layer;

[0005] The UBM device, silicon interposer, and UBM physical layer are interconnected based on a preset UBM physical interconnect protocol. UBM is an ultra-high bandwidth memory, and the bandwidth corresponding to UBM is higher than that corresponding to HBM4. The UBM physical interconnect protocol includes: the UBM device is connected to the silicon interposer based on a hybrid bonding package, the UBM physical layer is connected to the silicon interposer based on a hybrid bonding package, and the UBM device and the UBM physical layer are interconnected through the winding resources in the silicon interposer.

[0006] Compared with existing technologies, this invention has significant advantages and beneficial effects. Through the above technical solution, the memory system based on the UBM protocol provided by this invention achieves considerable technological advancement and practicality, and has broad industrial application value. It has at least the following beneficial effects:

[0007] In the memory system described in this invention, the UBM device is connected to the silicon interposer using a hybrid bonding package method, and the UBM physical layer is also connected to the silicon interposer using a hybrid bonding package method. The UBM device and the UBM physical layer are interconnected through the winding resources in the silicon interposer. The interconnect spacing of the hybrid bonding package is smaller than that of the uBump package, thus increasing the I / O per unit area and thereby improving the bandwidth line density and bandwidth areal density of the memory system package structure. Attached Figure Description

[0008] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0009] Figure 1 A memory system architecture diagram based on the UBM protocol provided in this embodiment of the invention;

[0010] Figure 2 This is a schematic diagram of a memory system based on the UBM protocol encapsulation provided in Embodiment 1 of the present invention;

[0011] Figure 3 This is a schematic diagram of a memory system based on the UBM protocol encapsulation provided in Embodiment 2 of the present invention. Detailed Implementation

[0012] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0013] This invention provides a memory system based on the UBM protocol, such as... Figure 1 As shown, the device includes a UBM device, a silicon interposer, and a GPU, wherein the GPU includes a UBM physical layer (PHY). A silicon interposer is an intermediate connection structure used to connect different chips or a chip to a packaging substrate.

[0014] The UBM device, silicon interposer, and UBM physical layer are interconnected based on a preset UBM physical interconnect protocol. UBM is an ultra-high bandwidth memory (UBM), and the bandwidth of UBM is higher than that of HBM4. The UBM physical interconnect protocol includes: the UBM device is connected to the silicon interposer based on a hybrid bonding package, the UBM physical layer is connected to the silicon interposer based on a hybrid bonding package, and the UBM device and the UBM physical layer are interconnected through the winding resources in the silicon interposer.

[0015] In a preferred embodiment, the interconnect pitch of the hybrid bonding package in the preset UBM physical interconnect protocol is less than or equal to 9 micrometers, specifically 3-9 micrometers. Based on this, the area of ​​the UBM physical layer can be reduced to 1 / 4 or even more compared to the area of ​​the UBM physical layer in existing memory systems based on the HBM4 protocol, thereby saving chip area and reducing system power consumption.

[0016] The UBM device includes multi-layered stacked DRAM and a buffer die. The buffer die is located at the bottom of the multi-layered stacked DRAM. The UBM device is interconnected with the silicon interposer via the buffer die using a hybrid bonding method. Specifically, the silicon interposer and the buffer die are interconnected using a face-back hybrid bonding method, that is, the metal surface of the silicon interposer and the side of the buffer die containing circuitry and devices are interconnected using a hybrid bonding method. The devices in the GPU and the silicon interposer are interconnected using a face-2face hybrid bonding method, that is, the metal surface of the GPU and the metal surface of the silicon interposer are interconnected using a hybrid bonding method.

[0017] It should be noted that the UBM protocol is an improved version of the HBM4 protocol. A memory system packaged based on the HBM4 protocol includes HBM4 devices, a silicon interposer, and a GPU, with the GPU including an HBM4 physical layer. The HBM4 devices are connected to the silicon interposer using a uBump package, and the HBM4 physical layer is also connected to the silicon interposer using a uBump package. The HBM4 devices and the HBM4 physical layer are interconnected through wiring resources in the silicon interposer. The interconnect pitch of the uBump package is approximately 45-55 micrometers. Therefore, interconnection via the UBM protocol significantly reduces the interconnect pitch, increasing I / O per unit area and thus improving the bandwidth line density and bandwidth areal density of the memory system package structure. Furthermore, the memory system based on this invention can reduce the memory frequency, allowing for the use of lower-end chip manufacturing processes. For example, existing technologies based on the HBM4 protocol require a 12nm process, while the system described in this invention can use a 28nm process.

[0018] The memory system may further include a package substrate and a printed circuit board (PCB), with the package substrate located between the chip and the PCB.

[0019] In one embodiment, the UBM device and the UBM physical layer communicate based on a preset UBM logic protocol. This UBM logic protocol includes setting a truth table for UBM row commands. The truth table for UBM row commands includes X bits of information, where X is greater than or equal to 15. The truth table for HBM4 row commands includes 10 bits of information. The activation information in the truth table of the HBM4 row commands is distributed across three activation sequences, requiring 1.5 cycles to execute the row activation command based on these three sequences. Alternatively, the activation information in the truth table of the UBM row commands is distributed across two activation sequences, requiring one cycle to execute the row activation command based on these two sequences. Therefore, based on the HBM4 protocol, executing a row activation command requires two cycles, while this application, based on the UBM protocol, can complete the execution of the row activation command within one cycle. Row activation (ACT) is a crucial command. Upon receiving the ACT command, the memory chip activates the corresponding memory row according to the provided row address. This process involves complex internal circuit operations within the chip. Specifically, the chip's row decoder decodes the row address, finds the corresponding row line, and then activates all the memory cells in that row by turning on a series of transistors.

[0020] The UBM protocol is an improved version of HBM4. In the truth table of the UBM line command, bits 10 to X of the information other than the activation information are set to empty, and bits 0 to 9 of the corresponding information are the same as the information in the truth table of the HBM4 line command.

[0021] The preset UBM logic protocol includes: setting the number of channels for each memory controller to 32, the bit width for each channel to 256 bits, the number of data I / O operations to 8192, and the burst length to 2. Preferably, other information in the preset UBM logic protocol can be adapted by referring to the logic protocol information of HBM4 and adjusting the bit width, data I / O operations, and burst length for each channel according to the preset UBM logic protocol. As an embodiment, other information in the preset UBM logic protocol can also be implemented based on the logic protocol of HBM4, which will not be elaborated here.

[0022] Silicon interposers offer abundant wiring resources, but existing HBM4-based protocol-packaged memory systems only utilize a portion of the silicon interposer's boundary area, with the central region used solely for power and ground wiring. Existing HBM4-based protocol packages are based on uBump packages, which have interconnect pitches of approximately 45-55 micrometers. Utilizing the central region of the silicon interposer for interconnects would be very costly. In contrast, the hybrid bonding package used in this application has an interconnect pitch of less than or equal to 9 micrometers. Utilizing the central region of the silicon interposer for interconnects is not costly and effectively utilizes the wiring resources of the central region.

[0023] The following two embodiments illustrate how the present invention effectively utilizes the winding resources in the middle region of the silicon interposer:

[0024] Example 1

[0025] The system includes M UBM devices, and the GPU includes M UBM physical layers. Each UBM device corresponds to one UBM physical layer. The GPU and the M UBM devices are disposed on a silicon interposer. The GPU is located in the middle, and the M UBM devices are disposed on one or more sides of the GPU. Each UBM device is interconnected with its corresponding UBM physical layer, and the corresponding UBM physical layer is disposed on the edge of the GPU adjacent to the UBM device.

[0026] The GPU also includes M memory controllers (MCs), N compute cores (APs), and N last-level caches (LLCs). Each memory controller includes P channels, each compute core corresponds to one last-level cache, each last-level cache corresponds to one or more channels, and each UBM device corresponds to a set of memory controllers. The M memory controllers and N last-level caches are located in the middle of the GPU, and the N compute cores are located on one or more sides of the M memory controllers and N last-level caches. Each compute core is interconnected with its corresponding last-level cache, and each memory controller is interconnected with its corresponding UBM device through the UBM physical layer.

[0027] This invention allows for a change in the GPU layout, placing the last-level cache in the center of the GPU. This facilitates rapid access by each computing core to other last-level caches and their corresponding UBM devices via the on-chip network, reducing access latency and improving efficiency. It should be noted that each computing core is connected to the on-chip network.

[0028] Each computing core is connected to its corresponding L1 cache via GPU on-chip interconnect. Each L1 cache is connected to the corresponding channel in the memory controller via GPU on-chip interconnect. Each set of memory controllers is connected to its corresponding UBM physical layer via GPU on-chip interconnect or hybrid bonding. Preferably, each set of memory controllers is connected to its corresponding UBM physical layer via hybrid bonding, thereby reducing the consumption of GPU on-chip resources and improving the utilization of silicon interposer wiring. It should be noted that the silicon interposer can specifically use horizontal or vertical wiring to establish the interconnection between each set of memory controllers and the corresponding UBM device without affecting the power and ground wiring.

[0029] Taking M=4 and N as an even number as an example, M memory controllers and N last-level caches are located in the middle of the GPU, M UBM devices are located on both sides of the GPU, and N computing cores are located on both sides of the M memory controllers and N last-level caches. The corresponding structure is as follows: Figure 2 As shown.

[0030] Example 2

[0031] The system includes M UBM devices, and the GPU includes M UBM physical layers. Each UBM device corresponds to one UBM physical layer. The GPU and the M UBM devices are disposed on a silicon interposer. The GPU is located in the middle, and the M UBM devices are disposed on one or more sides of the GPU. Each UBM device is interconnected with its corresponding UBM physical layer, and the corresponding UBM physical layer is disposed on the edge of the GPU adjacent to the UBM device.

[0032] The GPU also includes M memory controllers (MCs), N compute cores (APs), and N last-level caches (LLCs). Each memory controller includes P channels. Each compute core corresponds to one last-level cache, and each last-level cache corresponds to one or more channels. Each UBM device corresponds to one set of memory controllers. The last-level cache is located in the middle of the GPU, and the N compute cores are located on either side or multiple sides of the last-level cache. Each set of memory controllers is located between the corresponding UBM physical layer and the compute cores.

[0033] This invention allows for a change in the GPU layout, placing the last-level cache in the center of the GPU. This facilitates rapid access by each computing core to other last-level caches and their corresponding UBM devices via the on-chip network, reducing access latency and improving efficiency. It should be noted that each computing core is connected to the on-chip network.

[0034] In this architecture, each computing core is connected to its corresponding L1 cache via GPU on-chip interconnect. Each L1 cache is connected to the channel in its corresponding memory controller via GPU on-chip interconnect or hybrid bonding. Each set of memory controllers is connected to its corresponding UBM physical layer via GPU on-chip interconnect. Preferably, each L1 cache is connected to the channel in its corresponding memory controller via hybrid bonding, thereby reducing the consumption of GPU on-chip resources and improving the utilization of silicon interposer wiring. It should be noted that the silicon interposer can specifically use horizontal or vertical wiring to establish the interconnection between each set of memory controllers and the corresponding UBM device without affecting the power and ground wiring.

[0035] Taking M=4 and N as an even number as an example, the last-level cache is located in the middle of the GPU, M UBM devices are located on both sides of the GPU, and N computing cores are located on both sides of the M memory controllers and N last-level caches. The corresponding structure is as follows: Figure 3 As shown.

[0036] In the memory system described in this embodiment of the invention, the UBM device is connected to the silicon interposer based on a hybrid bonding package, and the UBM physical layer is also connected to the silicon interposer based on a hybrid bonding package. The UBM device and the UBM physical layer are interconnected through the winding resources in the silicon interposer. The interconnect spacing of the hybrid bonding package is smaller than that of the uBump package, thus increasing the I / O per unit area and thereby improving the bandwidth line density and bandwidth areal density of the memory system package structure.

[0037] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the scope of the present invention.

Claims

1. A memory system based on the UBM protocol, characterized in that, It includes a UBM device, a silicon interposer, and a GPU, wherein the GPU includes a UBM physical layer; The UBM device, silicon interposer, and UBM physical layer are interconnected based on a preset UBM physical interconnect protocol. UBM is an ultra-high bandwidth memory, and the bandwidth corresponding to UBM is higher than that corresponding to HBM4. The UBM physical interconnect protocol includes: the UBM device is connected to the silicon interposer based on a hybrid bonding package, the UBM physical layer is connected to the silicon interposer based on a hybrid bonding package, and the UBM device and the UBM physical layer are interconnected through the winding resources in the silicon interposer.

2. The system according to claim 1, characterized in that, In the preset UBM physical interconnect protocol, the interconnect spacing of the hybrid bonding package is less than or equal to 9 micrometers.

3. The system according to claim 1, characterized in that, The UBM device and the UBM physical layer communicate based on a preset UBM logic protocol. The UBM logic protocol includes: setting a truth table for UBM line commands. The truth table for UBM line commands includes X-bit column information, where X is greater than or equal to 15. The truth table for HBM 4 line commands includes 10-bit column information. The activation information in the truth table of the HBM4 line command is distributed in three activation sequences, and the line activation command needs to be executed based on the three activation sequences in 1.5 cycles. The activation information of the truth table of the UBM row command is distributed in two activation sequences, and the row activation command needs to be executed based on the two activation sequences in one cycle. In the truth table of the UBM line command, bits 10 to X are set to empty for all information except activation information, and bits 0 to 9 are the same as the information in the truth table of the HBM4 line command.

4. The system according to claim 3, characterized in that, The preset UBM logic protocol includes: setting the number of channels for each memory controller to 32, setting the number of bits corresponding to each channel to 256 bits, setting the number of data I / Os to 8192, and setting the burst length to 2.

5. The system according to claim 1, characterized in that, The system includes M UBM devices, and the GPU includes M UBM physical layers. Each UBM device corresponds to one UBM physical layer. The GPU and the M UBM devices are disposed on a silicon interposer. The GPU is located in the middle, and the M UBM devices are disposed on one or more sides of the GPU. Each UBM device is interconnected with the UBM physical layer corresponding to the UBM device. The UBM physical layer corresponding to the UBM device is disposed on the edge of the GPU adjacent to the UBM device and the GPU.

6. The system according to claim 5, characterized in that, The GPU also includes M memory controllers, N computing cores, and N last-level caches. Each memory controller includes P channels. Each computing core corresponds to one last-level cache. Each last-level cache corresponds to one or more channels. Each UBM device corresponds to a set of memory controllers. The M memory controllers and N last-level caches are located in the middle of the GPU. The N computing cores are located on one or more sides of the M memory controllers and N last-level caches. Each computing core is interconnected with its corresponding last-level cache. Each memory controller is interconnected with its corresponding UBM device through the UBM physical layer.

7. The system according to claim 1, characterized in that, Each computing core is connected to its corresponding last-level cache via GPU on-chip interconnect. Each last-level cache is connected to the channel in its corresponding memory controller via GPU on-chip interconnect. Each set of memory controllers is connected to its corresponding UBM physical layer via GPU on-chip interconnect or hybrid bonding.

8. The system according to claim 5, characterized in that, The GPU also includes M memory controllers, N computing cores and N last-level caches. Each memory controller includes P channels. Each computing core corresponds to one last-level cache. Each last-level cache corresponds to one or more channels. Each UBM device corresponds to a set of memory controllers. The last-level cache is located in the middle of the GPU. The N computing cores are located on both sides or multiple sides of the last-level cache. Each set of memory controllers is located between the corresponding UBM physical layer and the computing core.

9. The system according to claim 8, characterized in that, Each computing core is connected to its corresponding last-level cache via GPU on-chip interconnect. Each last-level cache is connected to the channel in its corresponding memory controller via GPU on-chip interconnect or hybrid bonding. Each set of memory controllers is connected to its corresponding UBM physical layer via GPU on-chip interconnect.

10. The system according to claim 1, characterized in that, The UBM device includes a multi-layer stacked DRAM and a buffer chip. The buffer chip is located at the bottom of the multi-layer stacked DRAM. The UBM device is interconnected with the silicon interposer through the buffer chip using a hybrid bonding method.

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