Information processing apparatus, information processing method, and program

Abstract

Information processing apparatus, information processing method, and program are provided that can balance the three aspects of computational accuracy, computational speed, and circuit scale. The information processing apparatus (1) has a reservoir disposed between an input layer and an output layer having one or more nodes. The reservoir has a storage unit that stores an input-output relationship that can uniquely determine the output value output to the output layer based on information input from the nodes of the input layer. In addition, it is preferable that the storage unit is implemented by one or more LUTs on an FPGA, and more preferably that a node constituting the reservoir is implemented by one LUT.

Description

Technical Field

[0001] This invention relates to an information processing apparatus, and more particularly to a reservoir computing apparatus. Furthermore, this invention relates to an information processing method, and more particularly to an information processing method using a reservoir computing apparatus. Additionally, this invention relates to a program for operating a computer as an information processing apparatus. Background Technology

[0002] Previously, neural networks (NNs) that mimic the function and structure of nerve cells in the human brain were known. In addition, regressive neural networks (RNNs) with structures where signals are traced back within the network (the output of a certain layer is traced back into the input).

[0003] Furthermore, as a type of RNN, Reservoir Computing (RC) is known. RC is one of the most watched AI technologies in recent years, applied to real-time data processing. By mounting RC on an FPGA (Field Programmable Gate Array), high-speed and low-power systems can be realized.

[0004] Here, as documents related to RC, there are non-patent documents 1 to 6.

[0005] Existing technical documents

[0006] Non-patent literature

[0007] Non-patent literature 1: Kawashima, Y. Katori, T. Morie, and H. Tamukoh, "Anareaefficient multiply-accumulation architecture and implementations for time-domain neural processing," in 2021 International Conference on Field-Programmable Technology (ICFPT). IEEE, pp. 1-4, 2021.

[0008] Non-Patent Document 2: K. Yoshida, Y. Abe, M. Akai-Kasaya, and T. Asai, “FPGA Architecture for Reservoir Computing with time-division input interfaces and online learning systems,” IEICE Technical Report; IEICE Tech. Rep., 2021.

[0009] Non-Patent Document 3: Herbert Jaeger, “Tutorial on training recurrent neural networks, covering BPPT, RTRL, EKF and the" echo state network" approach”, GMD-Forschungszentrum Informationstechnik, 2002.

[0010] Non-Patent Document 4: Miquel L. Alomar, Vincent Canals, Nicolas Perez-Mora, Victor

[0011] Martinez-Moll, Josep L. Rossello, “FPGA-Based Stochastic Echo State Networks for Time-Series Forecasting”, Computational Intelligence and Neuroscience, 2016.

[0012] Non-patent document 5: Ichiro Kawashima, Yuichi Katori, Takashi Morie, HakaruTamukoh, "An area-efficient multiply-accumulation architecture and implementations for time-domain neural processing", 2021 International Conference on Field-Programmable Technology (ICFPT), pp. 1-4, Online, December 6-10 (9), 2021.

[0013] Non-patent document 6: Victor M. Gan, Yibin Liang, Lianjun Li, Lingjia Liu, YangYi, "A Cost-Efficient Digital ESN Architecture on FPGA for OFDM SymbolDetection", ACM Journal on Emerging Technologies in Computing Systems, Volume17, Issue 4, Article No.47, pp. 1-15, 2021. Summary of the Invention

[0014] As can be seen from Non-Patent Documents 1-6, in RC, the computational complexity and circuit size of the reservoir are dominant (see Non-Patent Document 1).

[0015] Therefore, as an FPGA mounting method for RC (Reference Non-Patent Document 2), a time-division method for reservoir operation has been proposed. This method mounts only a few arithmetic circuits on the FPGA and performs reservoir operations by repeatedly using the arithmetic circuits while changing the data. That is, the circuit size is reduced by decreasing the number of arithmetic circuits mounted on the FPGA. However, this method has the problem of causing a significant increase in operation time.

[0016] On the other hand, a method for quantizing the computation of the reservoir was also proposed (see Non-Patent Document 4). This method reduces the circuit size required for each computation circuit by quantifying the weights and activity values ​​of neurons in each reservoir. Therefore, it can reduce the circuit size, but it still causes a decrease in computational accuracy.

[0017] In addition, an FPGA installation method that simultaneously incorporates these two methods has been proposed (see Non-Patent Literature 5 and 6). However, based on the aforementioned issues, it can be said that in previous FPGA installation methods for reservoir computing, it is difficult to balance the three aspects of computational accuracy, computational speed, and circuit scale.

[0018] Therefore, the purpose of this invention is to provide an information processing device, information processing method, and program that can take into account the three aspects of computational accuracy, computational speed, and circuit scale.

[0019] The information processing apparatus of the present invention includes a reservoir disposed between an input layer and an output layer having one or more nodes. The reservoir has a storage unit that stores an input-output relationship that can uniquely determine the output value output to the output layer based on information input from the nodes of the input layer.

[0020] Therefore, the output is determined relative to the input according to the input-output relationship stored in the storage unit, thus ending the operation of the reservoir.

[0021] In addition, preferably, the storage unit is implemented by one or more LUTs on the FPGA, and more preferably, a node constituting the storage pool is implemented by one LUT.

[0022] Furthermore, it is even more preferable that, when the number of assemblages of a node constituting the reserve pool is k, the number of combinations j (=2) of this number of assemblages k is also preferred. k The output values ​​of the quantities are stored in the LUT's memory Z. i (i=0~j-1)

[0023] Furthermore, preferably, the output layer uses a differential operation method that only calculates the output values ​​of nodes whose states have changed among the nodes constituting the reservoir as the operation method. More preferably, when detecting nodes whose states have changed among the nodes constituting the reservoir, the differential operation method compares the state at a certain moment with the states at multiple moments earlier than that moment, and starts the calculation from the state with the smallest difference.

[0024] On the other hand, the information processing method of the present invention includes: the step of setting up a reservoir between an input layer and an output layer having one or more nodes; the step of storing in a storage unit an input-output relationship that can uniquely determine the output value to be output to the output layer based on information input from nodes of the input layer; and the step of outputting the output value that is uniquely determined by the reservoir by referring to the storage unit based on input data from the input layer to the output layer.

[0025] Furthermore, the program of the present invention is used to enable a computer to operate as an information processing device, the information processing device having a reservoir disposed between an input layer and an output layer having one or more nodes, the reservoir having a storage unit storing an input-output relationship that can uniquely determine the output value output to the output layer based on information input from the nodes of the input layer.

[0026] According to the information processing apparatus of the present invention, the output is determined relative to the input according to the input-output relationship stored in the storage unit, thereby ending the operation of the storage pool. Therefore, it is possible to provide an information processing apparatus that can take into account the three aspects of operation accuracy, operation speed and circuit scale.

[0027] Furthermore, the information processing method and program according to the present invention can achieve the same effect as the information processing device of the present invention. Attached Figure Description

[0028] Figure 1 This is a diagram illustrating an example of a typical reservoir calculation model.

[0029] Figure 2 This is a diagram illustrating an example of a 3-input 1-output LUT operation.

[0030] Figure 3 This is a diagram illustrating an example of a microcomputer development board (microcomputer board, target board).

[0031] Figure 4 This is a schematic diagram representing a node in a typical LUT-Network.

[0032] Figure 5 (A) means Figure 1 The diagram of the structure between the input layer and the reservoir layer is a schematic diagram of the node of the reservoir layer that receives information from the input layer. (B) is a structural diagram of the node composed of LUTs.

[0033] Figure 6 (A) means Figure 1 (A) is a diagram of the structure within the reservoir layer, which is a schematic diagram of the nodes of the reservoir layer with inputs of information (signals) traced back from the reservoir. (B) is a structural diagram of the node composed of LUTs.

[0034] Figure 7 (A) means Figure 1 (A) is a diagram of the structure between the reservoir layer and the output layer, and (B) is a schematic diagram of the node of the output layer. (C) is a general structural diagram of the node.

[0035] Figure 8 This is a diagram illustrating an example of the input-output relationships of neurons in a reservoir stored in a LUT.

[0036] Figure 9 (A) is a diagram illustrating the structure of the operational circuit of the output layer, (B) is a diagram illustrating the general time-division method, and (C) is a diagram illustrating the operational method that only calculates the output value of neurons whose state changes in the neurons that constitute the reservoir.

[0037] Figure 10 This is a structural diagram used to illustrate the operation circuit of the output layer. It is a diagram used to illustrate the operation method of calculating only the output value of neurons whose state changes are from the neurons that constitute the reservoir. That is, when detecting neurons whose state changes are from the neurons that constitute the reservoir, the state at a certain moment is compared with the states at several moments before that moment, and the calculation starts from the state with the smallest difference.

[0038] Figure 11 This is a structural diagram of an information processing device with a reservoir installed on an FPGA.

[0039] Figure 12 This is the node waveform of the reservoir of the reservoir computing device of the present invention. Detailed Implementation

[0040] The embodiments of the present invention will now be described in detail. The description of the constituent elements described below is an example (representative example) of an embodiment of the present invention, and the present invention is not limited to the following content as long as its spirit is not changed. In addition, in this description, neuron and node are synonymous, and reservoir and reservoir layer are synonymous.

[0041] [Reserve Pool Calculation]

[0042] A reservoir is suitable for classification and forecasting using time series data, requiring nonlinear transformation of the input data (time series data). Furthermore, to classify or regress the input data (time series data), the reservoir needs to store (short-term storage) past input data.

[0043] Moreover, as Figure 1 The reservoir calculation models shown include ESN (Echo State Network), LSM (Liquid State Machine), and CBM-RC (Chaotic Boltzmann Machine-RC).

[0044] Here, N i N is the number of nodes in the input layer. r N is the number of nodes in the reserve pool (reserve pool layer). о This is the number of nodes in the output layer. Additionally, W...ir W represents the load (weight) between the input layer and the reservoir. rr It is the load (weight) between the reservoirs, W ro This refers to the load (weight) between the reservoir and the output layer. In the reservoir calculation, W... ir and W rr Fixed by random numbers. On the other hand, W ro It is optimized through ridge regression and other methods.

[0045] [BNN]

[0046] Furthermore, as a general term for (binarized) neural networks that do not use floating decimal points, BNN (Binarized Neural Networks) is known. Compared with other neural network methods, BNN has the advantages of not requiring multiplication operations and significantly reducing memory usage. Therefore, it can be said that BNN is suitable for FPGA installation.

[0047] [LUT-Network]

[0048] Additionally, as a type of BNN, LUT-Network is known. LUT-Network is a neural network implemented on an FPGA (a neural network implemented through LUTs on the FPGA) that further focuses on BNN. A LUT (Lookup Table) is a logic block mounted on an FPGA and is a rewritable part.

[0049] Figure 2 (A) is a 3-input, 1-output LUT (LUT-3), which can be represented as the truth table shown in Figure (B). The table information (truth table) of such a LUT is stored in SRAM, so arbitrary operations can be implemented by rewriting the table information in SRAM.

[0050] In the past, in the reservoir installed on FPGA, neurons were created by using adders or multipliers made by LUTs, and these neurons were aggregated to form the reservoir.

[0051] In addition, LUTs also exist with 4 inputs and 1 output (LUT-4), 6 inputs and 1 output (LUT-6), or other types of LUTs. For example, Figure 3 The microcomputer development board shown is a microcomputer development board manufactured by AMD (Advanced Micro Devices) (manufacturer number: SK-KR260-G), which contains approximately 100,000 LUT-6s.

[0052] Figure 4This is a schematic diagram representing a node in a typical LUT-Network; one node represents one LUT. Figure 4 In the example shown, LUT-6 is used, so the number of inputs to a node is 6 (X0 to X5) when combined with the LUT.

[0053] [The information processing apparatus of the present invention]

[0054] (1. Input layer, storage pool)

[0055] The information processing apparatus of the present invention is a reservoir computing apparatus having a reservoir disposed between an input layer and an output layer having one or more nodes. Number of nodes ( Figure 1 The N shown r The more W, the higher the performance of the reservoir. Furthermore, as mentioned above, in the reservoir calculation, W... ir and W rr Since the input-output relationships of neurons in the reservoir are fixed, they do not need to be rewritten. Therefore, the inventors of this application conceived of storing the input-output relationships of neurons in the reservoir directly in the storage unit.

[0056] Storage units refer to, for example, LUTs, BRAMs (Block RAM), URAMs (Ultra RAM), DRAMs (Dynamic RAM), SRAMs (Static RAM), eDRAMs (Embedded DRAM), MRAMs (Magnetoresistive RAM), and flash memory used in this embodiment. They are not limited to these as long as they can store the input-output relationships of neurons in the storage pool.

[0057] Furthermore, it is known to combine LUTs and SRAMs to create arbitrary circuits, but in this case, there is a drawback that the written data cannot be changed after the circuit is installed. However, in reservoir computing, W ir and W rr It is fixed, so there is no need to change the written data after the circuit is installed.

[0058] Furthermore, the number of LUT inputs is limited due to the exponential increase in circuit size caused by the bonding between nodes in a neural network mounted on an FPGA. However, reservoir layers operate even with loose bonding.

[0059] In view of this situation, the inventors of this application have focused on building a reservoir through LUT-Network and came up with the idea of ​​directly mapping (storing) the input-output relationship of the neurons in the reservoir into the LUT.

[0060] In addition, when constructing the reservoir using LUT-Network, the inventors of this application studied the reservoir calculation model based on the following conditions.

[0061] [Condition 1] Input and output can be implemented using 2 values ​​(1 bit).

[0062] [Condition 2] Combine the action even if it is loose.

[0063] [Condition 3] Do not hold values ​​and determine the output based solely on the input and load.

[0064] Of the conditions 1 to 3 above, LSM and CBM-RC do not satisfy condition 3, and it is difficult to eliminate condition 3. Therefore, in this invention, a binary ESN (input-output ESN) with two values ​​is used.

[0065] More specifically, in this invention, the most general model is adopted, namely, the binary ESN, which is suitable for LUT-Network installation as described above, as the basic model, and then improved upon. Alternatively, LSM (Liquid State Machine), ChNN-RC (Chaotic Neural Network Reservoir Computing), CA-RC (Cellular Automata Reservoir Computing), etc., can be used instead of ESN.

[0066] The general outline of the reservoir computing device of the present invention (hereinafter, the structure mounted on the FPGA in the reservoir computing device is referred to as "LUTNet-RC") will be described, and LUTNet-RC and Figure 1 The typical reservoir computing model shown also includes an input layer with one or more nodes, a reservoir constructed from a LUT-Network, and an output layer. Furthermore, in this embodiment, the LUT used in the reservoir is a 6-input, 1-output (LUT-6) LUT.

[0067] The input layer does not perform calculations but preserves the input data.

[0068] On the other hand, in the storage pool, the output state S at time t+1 i [t+1] is determined by the network state x[t] and the input u(t+1) one time ago (refer to equations (1) to (3)). Here, k is the number of nodes in the reservoir. In this embodiment, the LUT has 6 inputs, so the number of nodes k is 6.

[0069]

Mathematical Expression 1

[0070]

[0071]

Mathematical Expression 2

[0072]

[0073]

Mathematical Formula 3

[0074]

[0075] In addition, the output layer determines the output value based on the output from the reservoir using equation (4).

[0076]

Mathematical Expression 4

[0077]

[0078] Next, the reservoir will be explained in more detail. Previously, nodes that created reservoirs by receiving information from the input layer were constructed using adders or multipliers made using LUTs. That is, conventional reservoir nodes output values ​​from the input layer to the output layer based on the information received from the input layer through a product-sum operation. In contrast, LUTNet-RC's reservoir stores input-output relationships within the LUT, which uniquely determine the output value to the output layer based on the information received from the nodes in the input layer.

[0079] For example, such as Figure 5 As shown in (B), the node in the reservoir that receives information from the input layer is at b. i The input-output relationship is stored in a LUT with +k inputs and 1 output. On the other hand, such as Figure 6 As shown in (B), the nodes of the reservoir with inputs of information (signals) traced back from the reservoir store their input-output relationships in a k-input, 1-output LUT.

[0080] Figure 8 The diagram illustrates an example of the input-output relationship of neurons in the reservoir stored in the LUT. With a node combination number k of 6, the combinations of inputs (0 / 1) from X0 to X5 are 64 (2 to the power of 6). Therefore, based on the information input from the nodes in the input layer (X0 to X5), the output value (Z) output to the output layer is determined by referring to... Figure 8 The input-output relationship shown is used to uniquely determine the input.

[0081] For example, if the information input from the nodes of the input layer is X0:1, X1:0, X2:1, X3:0, X4:0, X5:0, then the output value (Z) is Z stored in the storage unit (hereinafter referred to as "memory"). 40The value in (1). Of course, the input-output relationship stored in the LUT can also be referenced in the operation within the reservoir layer.

[0082] In this way, the output values ​​of each combination of inputs X0 to X5 are stored in specific areas of memory (Z0 to Z5). 63 In this context, a neuron in the reservoir can be constructed from a single LUT. Furthermore, by using the number of nodes N in the reservoir... r A large number of LUTs can form a storage pool with any number of nodes.

[0083] Furthermore, the output values ​​from the nodes in the reservoir formed by LUTs are passed to the number of nodes N. r The output layer of the quantity outputs the result of the product sum operation (see reference). Figure 7 ).

[0084] (2. Output layer)

[0085] Here, the circuit structure for the output layer is considered to adopt... Figure 9 (A) shows a general time-division method. This method calculates the output values ​​of all neurons in the reservoir at time t, but because it calculates the output values ​​of all neurons, the computation time increases proportionally to the number of neurons. That is, if this method is used, it may not achieve sufficient computation speed when the number of neurons in the reservoir is large.

[0086] Therefore, as Figure 9 As shown in (B), consider using an operational method in the output layer circuit structure that only calculates the output values ​​of neurons whose state changes occur within the pool of neurons (this method is referred to as the "differential operation method"). For example, in Figure 9 In the example shown in (B), only the output values ​​of the j1st and j2nd neurons from the state change are calculated, and the value is compared with the previous input value z'. i The difference.

[0087] According to the differential computation method, even with a large number of neurons in the reservoir, it can achieve sufficient computational speed compared to the general time-division method. However, the differential computation method only compares the state one time ago (t-1) with respect to the state at a certain time (t). Therefore, it is effective when there are few neurons with state changes, but if the number of neurons with state changes increases, the computation time increases, and it may not be possible to achieve sufficient computational speed.

[0088] Therefore, the inventors of this application have devised the following method: In the difference operation method, when detecting the state changes of neurons in the neurons constituting the reservoir, the state at a certain moment is compared with the states at multiple moments earlier than that moment, and calculation begins from the state with the smallest difference. This method (hereinafter referred to as the "multi-difference operation method") is as follows: Figure 10 As illustrated, the state at a certain time (t) is compared with the states at several times earlier (t-1 to t-3), and the calculation begins from the state with the smallest difference (the j1-th neuron).

[0089] According to the multiple difference operation method, except for the case where there are few neurons with state changes, even when there are many neurons with state changes, the increase in computation time can be suppressed, thus achieving sufficient computation speed.

[0090] In addition, such as Figure 11 As shown, by installing LUTNet-RC in a PL (Programmable Logic) FPGA, the information processing device (reservoir computing device) 1 of the present invention can be constructed.

[0091] [Example]

[0092] As an example, the following presents experimental results using the reservoir computing device 1 of this embodiment. Furthermore, the LUTNet-RC of the reservoir computing device 1 in this embodiment is N, representing the number of nodes in the reservoir layer. r The overall circuit scale is shown in Tables 1-3.

[0093] Table 1 shows the circuit scale of the input layer and the buffer pool layer, indicating the number of LUTs and FFs per bit precision of the input. Table 2 shows the circuit scale of the output layer, indicating the number of LUTs, FFs, and BRAMs for each circuit structure (time-division, differential, and multiple-differential) of the output layer.

[0094] Furthermore, the speedup rate shown in Table 2 is an indicator of the extent to which the speedup can be achieved compared to the time-division method, and represents the results of software simulation based on the NARMA10 input states. For example, it can be seen that by using the differential operation method in the output layer, a speedup of 18 times can be achieved compared to the time-division method. On the other hand, it can be seen that by using the multiple differential operation method in the output layer (referring to the four states t, t-1, t-2, and t-3), a speedup of 25 times can be achieved compared to the time-division method.

[0095] Table 3 shows the circuit size including the input layer, reservoir layer, and output layer. The number of LUTs and FFs is the sum of the values ​​shown in Tables 1 and 2. Additionally, the bit precision of the inputs in Table 3 is 10.

[0096] Table 1

[0097]

[0098] Table 2

[0099]

[0100] Table 3

[0101]

[0102] [Calculation Precision]

[0103] Table 4 shows a comparison of the computational accuracy of LUTNet-RC with various existing methods. Here, existing methods 1 to 10 are techniques described in the references shown below.

[0104] (Existing method 1) VM Gan, Y. Liang, L. Li, L. Liu, and Y. Yi, "A cost-efficient digital esn architecture on fpga for ofdm symbol detection," ACMJournal on Emerging Technologies in Computing Systems (JETC), vol. 17, no. 4, pp. 1-15, 2021.

[0105] (Existing method 2) C. Lin, Y. Liang, and Y. Yi, “Fpga-based reservoir computing with optimized reservoir node architecture,” in 2022 23rdInternational Symposium on Quality Electronic Design (ISQED). IEEE, 2022, pp.1-6.

[0106] (Existing Method 3) K. Honda and H. Tamukoh, “A hardware-oriented echo state network and its fpga implementation,” Journal of Robotics, Networking and Artificial Life, vol. 7, no. 1, pp. 58-62, 2020.

[0107] (Existing Method 4) D. Kleyko, E. P. Frady, M. Kheffache, and E. Osipov, “Integer echo state networks: Efficient reservoir computing for digital hardware,” IEEE Transactions on Neural Networks and Learning Systems, vol. 33, no. 4, pp. 1688-1701, 2020.

[0108] (Existing Method 5) M. L. Alomar, V. Canals, N. Perez-Mora, V. Martinez-Moll, and J. L. Rossello, “Fpga-based stochastic echo state networks for time-series forecasting,” Computational intelligence and neuroscience, vol. 2016, pp. 15-15, 2016.

[0109] (Existing Method 6) K. Yoshida, Y. Abe, M. Akai-Kasaya, and T. Asai, “Fpga architecture for reservoir computing with time-division input interfaces and online learning systems,” IEICE Technical Report; IEICE Tech. Rep., 2021.

[0110] (Existing Method 7) B. Penkovsky, L. Larger, and D. Brunner, “Efficient design of hardware-enabled reservoir computing in fpgas,” Journal of Applied Physics, vol. 124, no. 16, 2018.

[0111] (Existing Method 8) B. Schrauwen, M. D’Haene, D. Verstraeten, and J. Van Campenhout, “Compact hardware liquid state machines on fpga for real-time speech recognition,” Neural networks, vol. 21, no. 2-3, pp. 511-523, 2008.

[0112] (Existing Method 9) I. Kawashima, Y. Katori, T. Morie, and H. Tamukoh, “An area-efficient multiply-accumulation architecture and implementations for time-domain neural processing,” in 2021 International Conference on Field-Programmable Technology (ICFPT). IEEE, 2021, pp. 1-4.

[0113] (Existing Method 10) D. Pramanta and H. Tamukoh, “Fpga implementation of pulse-coupled phase oscillators working as a reservoir at the edge of chaos,” in 2021 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE, 2021, pp. 1-5.

[0114] [Table 4]

[0115]

[0116] The comparison results show that LUTNet-RC has the highest accuracy in the benchmark task (NARMA10) with lower MSE (mean squared error) than existing methods.

[0117] [Computation speed]

[0118] In addition, Table 5 shows the comparison results of the computation speed of LUTNet-RC with various existing methods. Existing methods 1 to 10 are as described above.

[0119] Table 5

[0120]

[0121] Referring to Table 5, there are existing methods with higher throughput than LUTNet-RC (e.g., existing method 1 or existing method 5) because the number of nodes in the reservoir layer is as low as 32 or 50. Therefore, by matching the number of nodes in existing methods 1 and 5 with the number of nodes in LUTNet-RC (1,500), or with the 100 nodes used in the experimental conditions of the baseline task (NARMA10), the throughput of existing methods 1 and 5 is significantly reduced due to the increased computation time in the reservoir layer.

[0122] Given this fact, the pooling layer of LUTNet-RC stores the input-output relationship in the LUT, which can uniquely determine the output value to be output to the output layer based on the information input from the nodes of the input layer, so the computation ends simply by reading it out (i.e., in 1 clock cycle).

[0123] Therefore, it can be said that the computation speed of the pool layer in LUTNet-RC can be maximized, and further, depending on the circuit structure of the output layer, the computation speed can be further increased. This is evident from the significant increase in throughput when differential or multiple differential computation methods are used in the output layer circuit structure compared to when they are not used.

[0124] in addition, Figure 12 The waveform of the nodes in the LUTNet-RC reservoir indicates that the neuron outputs are frequently and regularly reversed. In other words, there are many neurons undergoing state changes. Therefore, in LUTNet-RC, it is preferable to use a multiple-difference operation method in the output layer compared to the difference operation method.

[0125] In summary, LUTNet-RC can also improve the situation where computation in the pooling layer ends in one clock cycle and the output of neurons in the pooling layer reverses regularly at a high frequency (there are many neurons with state changes) by designing the output layer, thus achieving sufficient computational speed.

[0126] In addition, such as Figure 12 As shown, the reason for the high frequency of regular reversals in the outputs of neurons in the LUTNet-RC reservoir can be attributed to the binarization (binary representation) of the neuron outputs. That is, it can be considered that the microsecond changes in the computed values ​​in the reservoir are rounded to either 0 or 1 by the binary activation function.

[0127] Furthermore, as an application example, by using the multi-difference operation method in the output layer, at least 25 times the speed can be achieved compared to the time-division method, thus enabling the inference of speeds on the order of Mfps.

[0128] [Circuit Scale]

[0129] In addition, Table 6 shows the comparison results of the circuit size of LUTNet-RC and various existing methods. Existing methods 1 to 10 are as described above.

[0130] Additionally, some of the circuit scales (LUT, FF, DSP, BRAM) for LUTNet-RC in Table 6 are larger than those shown in Table 3. This is because Table 6 represents... Figure 11 The overall circuit scale of the system on the PL shown includes the communication circuit with the PS (for example, about 5,000 LUTs are used in DMApub and DMAsub).

[0131] Table 6

[0132]

[0133] The comparison results show that the circuit size of LUTNet-RC, measured by the number of nodes (compared to 1,500 for each existing method), is approximately 1 / 10 to 1 / 100 of the existing methods. In other words, LUTNet-RC, as described above, offers sufficient performance (computational accuracy and speed) while achieving a significant reduction in circuit size. Therefore, it can be said that LUTNet-RC can be installed on edge devices requiring high performance (computational accuracy and speed).

[0134] Based on the above embodiments, it can be said that the information processing device (LUTNet-RC) of the present invention can take into account the three aspects of computing accuracy, computing speed and circuit scale.

[0135] Furthermore, the information processing device (LUTNet-RC) described so far is merely an example of one implementation method, and design changes can be made appropriately as long as the main idea remains unchanged.

[0136] For example, any method can be used to construct LUTNet-RC. Specifically, for the input layer and the reservoir layer, Python can be used to generate the circuit structure (program) stored in the FPGA. For the output layer, Verilog can be used to generate the circuit that incorporates the hardware-directed algorithm.

[0137] Furthermore, in this description, the values ​​stored in the memory are binary data (0 or 1), but the information input from the nodes of the input layer and the output values ​​are certainly not limited to this.

[0138] Industrial utilization potential

[0139] This invention relates to an information processing device, method, and program that can balance computational accuracy, computational speed, and circuit scale. In particular, it can be installed in small devices, and is therefore useful in industry.

[0140] Explanation of reference numerals in the attached figures

[0141] 1. Information processing device (reservoir computing device)

Claims

1. An information processing device comprising a storage pool, The storage pool is positioned between the input layer and the output layer, which have one or more nodes. The reservoir has a storage unit that stores the input-output relationship that can uniquely determine the output value to be output to the output layer based on the information input from the nodes of the input layer.

2. The information processing apparatus according to claim 1, wherein, The storage unit is implemented by one or more LUTs on the FPGA.

3. The information processing apparatus according to claim 2, wherein, A node constituting the reservoir is implemented by a LUT.

4. The information processing apparatus according to claim 3, wherein, When the number of associations of a node constituting the reserve pool is k, The combination number j of the associative number k (=2) k The output values ​​of the quantity are respectively stored in the memory Z of the LUT. i (i=0~j-1) 5. The information processing apparatus according to any one of claims 1 to 4, wherein, The output layer uses a differential operation method as its operation method, which only calculates the output values ​​of nodes whose states have changed from the nodes that constitute the reservoir.

6. The information processing apparatus according to claim 5, wherein, When detecting a node with a changing state among the nodes constituting the reserve pool, the differential operation method compares the state at a certain moment with the states at multiple moments prior to that moment, and starts the calculation from the state with the smallest difference.

7. An information processing method, comprising: The steps to set up a reserve pool between the input layer and the output layer that have more than one node; The step of storing in a storage unit the input-output relationship that can uniquely determine the output value output to the output layer based on the information input from the nodes of the input layer; as well as The step of outputting an output value, uniquely determined by the reservoir by referring to the storage unit, to the output layer based on the input data from the input layer.

8. A program for causing a computer to operate as an information processing device. The information processing device has a storage pool. The storage pool is positioned between the input layer and the output layer, which have one or more nodes. The reservoir has a storage unit that stores the input-output relationship that can uniquely determine the output value to be output to the output layer based on the information input from the nodes of the input layer.

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