Wireless eeg patch device for sleep slow wave monitoring and eeg slow wave monitoring method

Abstract

This invention provides a wireless EEG patch device and method for slow-wave sleep monitoring. The device includes an electrode module, a filtering and amplification module, an analog-to-digital conversion module, and a control module. The electrode module acquires the positive, negative, and reference signals of the target user. The filtering and amplification module performs common-mode suppression, differential amplification, and slow-wave frequency filtering on the EEG signals. The analog-to-digital conversion module converts the analog EEG signals into digital signals. The control module performs slow-wave reliability scoring, phase calculation, and sleep state analysis on the digital signals to determine whether the user is in a state where stimulation can be applied and the timing of stimulation. This invention effectively improves the accuracy of slow-wave sleep signal acquisition, the accuracy of deep sleep identification, and the reliability of stimulation triggering, while reducing the impact of power frequency interference, motion artifacts, and repeated false triggers. It also offers wearing comfort and closed-loop control application value.

Description

Technical Field

[0001] This invention relates to the field of electroencephalography (EEG) detection technology, and more specifically, to a wireless EEG patch device and a method for slow-wave sleep monitoring. Background Technology

[0002] Among existing technologies, polysomnography (PSG) is the most important examination for diagnosing sleep-related breathing disorders, sleep-related movement disorders, parasomnias, and other sleep-related diseases. By monitoring indicators such as electroencephalogram (EEG), electrocardiogram (ECG), electromyography (EMG), respiratory airflow, respiratory effort, and arterial oxygen saturation, it can understand the subject's sleep quality, whether snoring or even sleep apnea occurs, and the lowest arterial oxygen value at the time of apnea. It is the internationally recognized gold standard for diagnosing sleep apnea-hypopnea syndrome and an important auxiliary diagnostic tool for various sleep disorders.

[0003] Currently, the technical specifications for polysomnography (PSG) mainly follow the guidelines specified by the American Academy of Sleep Medicine (AASM Manual). However, even the latest AASM Manual for the Scoring of Sleep and Associated Events ver. 3.0, updated in 2023, still does not specify the bioelectrical signals, especially electroencephalogram (EEG) signals, for home-use PSG.

[0004] In clinical settings, the electrodes used to collect electroencephalogram (EEG) potentials from areas with hair are generally EEG disc electrodes. These disc electrodes are typically used in conjunction with conductive gel. The conductive gel penetrates the hair, creating an electrical connection between the scalp and the electrode. However, applying the conductive gel is cumbersome and prone to falling off, making it inconvenient for home use.

[0005] Secondly, some EEG patches on the market only support single / dual channel acquisition, which is insufficient to meet the requirements for accurate identification of slow waves (0.5–2 Hz) in deep sleep. Summary of the Invention

[0006] To address the shortcomings of existing technologies, the present invention aims to provide a wireless EEG patch device and a method for slow-wave EEG monitoring during sleep.

[0007] The above-mentioned technical objective of the present invention is achieved through the following technical solution: Firstly, a wireless EEG patch device for slow-wave sleep monitoring, comprising: The electrode modules, which are multiple in number, are used to contact the head of a target user to obtain simulated electroencephalogram (EEG) signals, which include: a positive electrode signal, a negative electrode signal, and a reference signal. The filtering and amplification module is used to suppress the common-mode portion of the simulated EEG signal and amplify the differential signal in the simulated EEG signal. The analog-to-digital converter module is used to convert the amplified analog differential signal into a digital differential signal; The control module is used to extract sleep slow waves from the digital differential signal and evaluate the sleep slow waves to obtain highly stable EEG slow wave data. The electrode module is connected to the input terminal of the filter amplification module; the output terminal of the filter amplification module is connected to the input terminal of the analog-to-digital conversion module; and the output terminal of the analog-to-digital conversion module is connected to the control module.

[0008] In one embodiment, the electrode module includes: an insulating substrate and a silver electrode; The silver electrode is embedded in the insulating base layer and includes a connecting part and a bonding part; the connecting part is used for electrical connection with external devices; the bonding part is covered with a full tetrafluorosilver-silver chloride coating to adjust the contact resistance with the skin.

[0009] In one embodiment, the filtering and amplification module includes: A common-mode feedback unit, connected to an electrode module for outputting a reference signal, is used to generate a feedback signal based on the reference signal or a common-mode component, and to apply the feedback signal to the reference electrode to suppress common-mode interference. A differential amplifier unit is used to extract differential components based on the positive signal and the negative signal, and amplify the differential components to output a differential signal. A shaping unit, the input of which is connected to the output of the differential amplifier unit, is used to filter, adjust the gain, and shape the waveform of the differential signal to output an analog differential signal that meets the requirements of analog-to-digital conversion.

[0010] In one embodiment, the differential amplifier unit includes: a sixteenth resistor, a seventeenth resistor, an eighteenth resistor, a twenty-first resistor, a twenty-seventh resistor, a twenty-eighth resistor, a thirty-sixth resistor, a thirty-seventh resistor, a twentieth capacitor, a twenty-first capacitor, a twenty-second capacitor, a first transistor, a second transistor, a third transistor, a fourth transistor, and a differential amplifier chip. The collector of the first transistor is connected to the electrode module through the eighteenth resistor to obtain the negative signal; the emitter of the first transistor is grounded; the collector of the first transistor is grounded through the twentieth capacitor; the base of the first transistor is connected to the second pin of the differential amplifier chip through the seventeenth resistor. The collector of the second transistor is connected to the electrode module through the twenty-first resistor to obtain the positive signal; the emitter of the second transistor is grounded; the collector of the second transistor is grounded through the twenty-second capacitor; the base of the second transistor is connected to the third pin of the differential amplifier chip through the twenty-eighth resistor. The collector of the first transistor is connected to the collector of the second transistor through the twenty-first capacitor; The base of the third transistor is connected to pin 2 of the differential amplifier chip via the seventeenth resistor; the base of the third transistor is connected to the collector of the third transistor via the sixteenth resistor; the emitter of the third transistor is grounded. The base of the fourth transistor is connected to the third pin of the differential amplifier chip through the twenty-eighth resistor; the base of the fourth transistor is connected to the collector of the fourth transistor through the twenty-seventh resistor; the emitter of the fourth transistor is grounded. The first pin of the differential amplifier chip is connected to the common-mode feedback unit through the thirty-seventh resistor; the eighth pin of the differential amplifier chip is connected to the common-mode feedback unit through the thirty-sixth resistor; the fourth pin of the differential amplifier chip is grounded; the fifth pin of the differential amplifier chip is grounded; the sixth pin of the differential amplifier chip is connected to the input terminal of the shaping unit; and the seventh pin of the differential amplifier chip is connected to the 5V voltage terminal.

[0011] In one embodiment, the common-mode feedback unit includes: a 31st resistor, a 32nd resistor, a 34th resistor, a 34th capacitor, a 35th capacitor, a 39th capacitor, a 40th capacitor, a first operational amplifier, a second operational amplifier, a first sliding rheostat, and a voltage regulating chip. The inverting input of the first operational amplifier is connected to the electrode module via the thirty-fourth capacitor to receive the reference signal; the output of the first operational amplifier is connected to the electrode module via the thirty-second resistor or the thirty-fifth capacitor; the inverting input of the first operational amplifier is connected to the second pin of the voltage regulator chip; the inverting input of the first operational amplifier is also connected to the output of the second operational amplifier via the thirty-first resistor; the non-inverting input of the first operational amplifier is connected to the free end of the first sliding rheostat; the first fixed end of the first sliding rheostat is connected to analog ground, and the second fixed end of the first sliding rheostat is connected to digital ground. The positive input terminal of the second operational amplifier is connected to the 5V voltage terminal; the negative input terminal of the second operational amplifier is connected to the analog ground; the non-inverting input terminal of the second operational amplifier is connected to the output terminal of the second operational amplifier; and the inverting input terminal of the second operational amplifier is connected to the third input terminal of the differential amplifier unit.

[0012] In one embodiment, the shaping unit includes: a nineteenth resistor, a twentieth resistor, a twenty-second resistor, a twenty-third resistor, a twenty-fourth resistor, a twenty-fifth resistor, a twenty-sixth resistor, a twenty-ninth resistor, an eighteenth capacitor, a twenty-third capacitor, a twenty-fourth capacitor, a twenty-fifth capacitor, a twenty-sixth capacitor, a twenty-seventh capacitor, a second sliding rheostat, a third operational amplifier, and a fourth operational amplifier. The non-inverting input of the third operational amplifier is connected to the output of the differential amplifier unit through the twenty-fourth capacitor; the non-inverting input of the third operational amplifier is connected to the free end of the second sliding rheostat through the twenty-fourth resistor; the free end of the second sliding rheostat is grounded; the first fixed end of the second sliding rheostat is grounded; the second fixed end of the second sliding rheostat is connected to the inverting input of the third operational amplifier through the twenty-second resistor; the output of the third operational amplifier is connected to the inverting input of the third operational amplifier through either the twenty-ninth resistor or the twenty-seventh capacitor; the positive input of the third operational amplifier is connected to a 5V voltage terminal, and the negative input of the third operational amplifier is grounded. The third operational amplifier is grounded after passing through the twenty-third capacitor and the twenty-third resistor in sequence; the output terminal of the third operational amplifier is connected to the non-inverting input terminal of the fourth operational amplifier after passing through the twenty-third capacitor, the nineteenth resistor, and the twentieth resistor in sequence. The output of the fourth operational amplifier is connected to its non-inverting input via the eighteenth capacitor and the twentieth resistor. The output of the fourth operational amplifier is connected to its inverting input via the twenty-sixth resistor and the twenty-sixth capacitor. The non-inverting input of the fourth operational amplifier is grounded via the twenty-fifth capacitor. The inverting input of the fourth operational amplifier is grounded via the twenty-fifth resistor.

[0013] In one embodiment, the analog-to-digital conversion module includes an analog-to-digital conversion chip, which is used to receive the analog differential signal output by the shaping unit and perform analog-to-digital conversion on the analog differential signal to generate a corresponding digital differential signal. The analog-to-digital converter chip is also used to provide a reference voltage signal, which is used to monitor and compensate for common-mode drift and human body coupling interference in the front-end analog signal link.

[0014] Secondly, a slow-wave EEG monitoring method, applied to the wireless EEG patch device as described in the first aspect, the method comprising: The electrode module is used to acquire the electroencephalogram (EEG) signal of the target user, wherein the EEG signal includes a positive signal, a negative signal, and a reference signal; The EEG signal is processed by the filtering and amplification module to obtain an analog signal containing the slow EEG waves of the target user. The analog-to-digital conversion module is used to convert analog signals containing slow brain waves from analog signals to digital signals; The control module is used to perform signal analysis on the converted EEG slow wave signal. The signal analysis includes at least slow wave confidence scoring and slow wave phase calculation to determine whether the target user is in a state where stimulation can be applied and to determine the timing of stimulation application.

[0015] In one embodiment, when the target user is in a state where stimulation cannot be applied, the EEG signals collected in the current time period are discarded.

[0016] In one embodiment, determining the timing of applying stimulation specifically involves performing phase analysis on the electroencephalogram (EEG) signal, and applying stimulation to the target user within a preset time delay when the phase analysis result is an ascending phase.

[0017] Thirdly, a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the method described in the first aspect.

[0018] Fourthly, a computer device includes a memory and a processor, the memory storing a computer program, the processor executing the computer program to implement the steps of the method described in the first aspect.

[0019] In summary, this invention offers the following advantages: By combining multi-lead electrode acquisition, front-end differential amplification and common-mode feedback suppression, slow-wave band shaping filtering, and high-resolution analog-to-digital conversion, this invention achieves high-precision, low-noise acquisition of sleep slow-wave signals. Furthermore, through slow-wave reliability scoring, phase calculation, and anti-repeated triggering mechanisms, it improves the accuracy of deep sleep state determination and stimulus timing locking, reducing the impact of local artifacts, motion interference, and repeated false triggers. Simultaneously, by incorporating adaptive sampling, wireless communication, and wireless charging, it balances monitoring accuracy, wearing comfort, battery life, and ease of use, making it suitable for long-term sleep monitoring and closed-loop intervention applications. Attached Figure Description

[0020] Figure 1 This is a diagram showing the location of the brain electrode device of the present invention; Figure 2 This is a structural diagram of the wireless EEG patch device for slow-wave sleep monitoring according to the present invention; Figure 3 This is a schematic diagram of the filter amplification module circuit of the present invention; Figure 4 This is a circuit schematic diagram of the analog-to-digital conversion module of the present invention; Figure 5 This is a schematic diagram of the power module circuit of the present invention; Figure 6This is a schematic diagram of the electrode patch structure of the present invention; Figure 7 This is a schematic diagram of the hardware module structure of the present invention; Figure 8 This is a flowchart of the slow-wave brainwave monitoring method of the present invention; Figure 9 This is a schematic diagram of the internal structure of the computer device of the present invention.

[0021] In the diagram: 1. Insulating base layer; 2. All-tetrafluorosilver-silver chloride coating; 3. Silver electrode; 21. Differential amplifier unit; 22. Shaping unit; 23. Common mode feedback unit. Detailed Implementation

[0022] To make the objectives, features, and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Several embodiments of the present invention are shown in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein.

[0023] In this application embodiment, "at least one" refers to one or more, and "more than one" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent the existence of A alone, the simultaneous existence of A and B, or the existence of B alone. A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" and similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, and c can represent: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple.

[0024] Those skilled in the art will recognize that the units and algorithm steps described in the embodiments disclosed herein can be implemented using electronic hardware, computer software, or a combination of electronic hardware and software. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0025] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0026] In the several embodiments provided in this application, any function, if implemented as a software functional unit and sold or used as an independent product, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0027] The above description is merely a specific embodiment of this application. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the protection scope of this application. The protection scope of this application should be determined by the protection scope of the claims.

[0028] The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0029] Example 1 To address the above problems, this invention provides a wireless EEG patch device for slow-wave sleep monitoring, such as... Figure 2 As shown, it includes: an electrode module, an EEG analog front-end circuit, and a control module (MCU). The EEG analog front-end circuit specifically includes: a filtering and amplification module and an analog-to-digital conversion module. All modules are integrated into the flexible patch body and formed into an integrated structure that can be attached to the forehead area of ​​the target user using biocompatible encapsulation materials.

[0030] like Figure 1As shown, multiple electrode modules are used to contact the target user's head to obtain simulated electroencephalogram (EEG) signals, which include positive signals, negative signals, and reference signals. Preferably, the electrode modules adopt a frontal multi-lead structure conforming to the international 10-20 lead layout, and may include an Fp1 working electrode located on the left side of the forehead, an Fp2 working electrode located on the right side of the forehead, an Fp7 working electrode located on the left side of the anterior temporal lobe, an Fp8 working electrode located on the right side of the anterior temporal lobe, and GND and Fz reference electrodes located at the midline of the forehead; the spacing between adjacent electrodes is set to 15-35 mm to analyze the slow wave propagation direction using translead phase difference and suppress local artifacts. The above layout offers several advantages. First, Fp1, Fp2, Fp7, and Fp8 are all located in the forehead and anterior temporal region, enabling stable acquisition of EEG activity related to slow sleep waves without affecting user comfort. This avoids the discomfort caused by the large number of electrodes and wide coverage area of ​​traditional head-mounted EEG devices. Second, the multi-lead distribution on both sides of the forehead and the anterior temporal region forms a sampling array with a certain spatial span. This facilitates comparison of amplitude differences, phase relationships, and propagation timing between different leads, thereby more accurately identifying the onset, propagation, and attenuation processes of slow waves and improving the detection accuracy of slow waves in deep sleep. Furthermore, the inclusion of GND and Fz reference electrodes provides a stable reference benchmark for each working electrode, reducing the impact of common-mode interference and baseline drift on the acquisition results. By controlling the electrode spacing within the range of 15–35 mm, sufficient spatial resolution between adjacent leads can be ensured to reflect the propagation characteristics of slow waves in the forehead region. This avoids the problem of excessively large electrode spacing leading to increased patch volume and decreased fit, or excessively small spacing leading to redundant lead information and insufficient spatial resolution. Therefore, it is more suitable for achieving highly stable and low-artifact EEG slow wave monitoring in sleep scenarios.

[0031] like Figure 6 As shown, the electrode module preferably adopts a dry electrode or semi-dry electrode composite structure to balance sleeping comfort, conductivity stability, and long-term reliability. Specifically, the electrode module includes an insulating base layer 1, a silver electrode 3 disposed on the insulating base layer, and a full tetrafluorosilver-silver chloride coating 2 covering the surface of the silver electrode. The insulating base layer 1 is preferably a high-molecular-weight polyimide base layer. High-molecular-weight polyimide material has good flexibility, mechanical strength, biocompatibility, and electrical insulation properties. It can serve as a supporting carrier for the electrode pads and allow the electrode module to better conform to the curvature of the skin surface when attached to the forehead or anterior temporal region, reducing local lifting, pressure discomfort, and contact fluctuations caused by movement friction, thereby improving the wearing stability during overnight sleep monitoring.

[0032] The silver electrode 3, disposed on the insulating base layer, serves as the main body for electrical signal transmission. The silver electrode 3 preferably includes a connecting portion and a bonding portion. The connecting portion is used for electrical connection with flexible wires, circuit board pads, or other external devices to transmit the acquired EEG signals to the filtering and amplification module. The bonding portion is used for contact with the user's skin to receive the weak bioelectrical signals generated by brain activity. Silver material itself has high conductivity, which can effectively reduce the transmission impedance and signal loss of the electrode body, allowing the positive, negative, and reference signals to be output to the subsequent circuitry more accurately, thus improving the signal integrity of the front-end acquisition.

[0033] Furthermore, a full tetrafluorosilver-silver chloride coating 2 is applied to the surface of the contact portion of the silver electrode. This coating improves the interfacial electrochemical properties between the electrode and the skin, reduces polarization effects, and minimizes contact impedance fluctuations. It also maintains a relatively stable ion-electron conversion capability under gel-free or low-gel conditions, thus facilitating stable conductive contact. Compared to ordinary bare metal electrodes, the full tetrafluorosilver-silver chloride coating makes the electrode less sensitive to impedance changes caused by skin sweat, minute displacements, and prolonged contact, effectively reducing the impact of baseline drift and motion artifacts on EEG acquisition results. Simultaneously, the full tetrafluorosilver-silver chloride coating also exhibits good corrosion resistance and surface stability, improving the performance consistency of the electrode module in scenarios of repeated use or long-term operation. Therefore, the combination of the insulating base layer, silver electrode, and full tetrafluorosilver-silver chloride coating enables the electrode module to simultaneously possess advantages such as flexible skin contact, low impedance conductivity, low polarization noise, and long-term stable acquisition, making it particularly suitable for continuous, low-interference, and highly reliable monitoring of weak slow-wave EEG signals in sleep scenarios.

[0034] The filtering and amplification module is used to suppress the common-mode component of the simulated EEG signal and amplify the differential signal in the simulated EEG signal. Preferably, it includes a differential amplification unit, a common-mode feedback unit, and a shaping unit. The differential amplification unit is connected to the electrode module that outputs positive and negative signals. It is used to extract the differential component based on the positive and negative signals and perform primary amplification on the differential component to output the differential signal. Preferably, the differential amplification unit adopts a low-noise instrumentation amplification structure with a common-mode rejection ratio greater than 100dB. This effectively suppresses power frequency interference and common-mode noise introduced by electrode imbalance while amplifying weak EEG differential signals, improving the accuracy and stability of front-end signal acquisition. The common-mode feedback unit is connected to the electrode module that outputs a reference signal. It detects the common-mode component in the reference channel and generates a feedback signal based on the common-mode component. The feedback signal is then inverted and applied to the reference electrode to achieve active common-mode suppression. This reference feedback method further reduces the impact of human coupling noise, environmental electromagnetic interference, and baseline fluctuations on EEG acquisition results, resulting in a lower input reference noise (preferably less than 1.2 μVrms) in the analog differential signal output by the filtering and amplification module. The input of the shaping unit is connected to the output of the differential amplification unit, used for filtering, gain adjustment, and waveform shaping of the differential signal to output an analog differential signal that meets the requirements of analog-to-digital conversion. Preferably, the shaping unit employs a high-pass and low-pass combination structure, where the high-pass cutoff frequency is approximately 0.3 Hz to remove DC drift and slow baseline shift, and the low-pass cutoff frequency is approximately 45 Hz to suppress high-frequency interference and electromyographic noise. This ensures that the effective signal bandwidth after amplification covers the frequency band of sleep slow waves and improves the reliability of subsequent analog-to-digital conversion and slow wave recognition.

[0035] In some embodiments, such as Figure 3 As shown, the differential amplifier unit 21 is used to perform pre-stage differential extraction and amplification of the weak EEG signals acquired by the electrode module. It can be composed of the sixteenth resistor R16, the seventeenth resistor R17, the eighteenth resistor R18, the twenty-first resistor R21, the twenty-seventh resistor R27, the twenty-eighth resistor R28, the thirty-sixth resistor R36, the thirty-seventh resistor R37, the twentieth capacitor C20, the twenty-first capacitor C21, the twenty-second capacitor C22, the first transistor Q1, the second transistor Q2, the third transistor Q3, the fourth transistor Q4, and the differential amplifier chip U2.

[0036] In this circuit, transistors Q1 and Q2 are connected to the negative and positive signal input channels, respectively. The negative signal output from the electrode module is input to the collector of transistor Q1 via resistor R18 (18th resistor), and the positive signal is input to the collector of transistor Q2 via resistor R21 (21st resistor). The collector of transistor Q1 is grounded via capacitor C20 (20th capacitor), and the collector of transistor Q2 is grounded via capacitor C22 (22nd capacitor), thus performing preliminary bypass filtering of high-frequency glitches and transient interference in the two input signals. Simultaneously, the collector of transistor Q1 is connected to the collector of transistor Q2 via capacitor C21 (21st capacitor), creating an AC coupling relationship between the positive and negative input channels, which helps suppress common-mode fluctuations and improve the dynamic consistency of the two inputs. The base of the first transistor Q1 is connected to the second pin of the differential amplifier chip U2 via the seventeenth resistor R17, and the base of the second transistor Q2 is connected to the third pin of the differential amplifier chip U2 via the twenty-eighth resistor R28, thereby sending the two EEG inputs after conditioning by the pre-stage transistor network to the differential input terminal of the differential amplifier chip U2.

[0037] Furthermore, the third transistor Q3 and the fourth transistor Q4 are respectively configured to work in conjunction with the input branches containing the second and third pins of the differential amplifier chip U2. The base of the third transistor Q3 is connected to the second pin of the differential amplifier chip U2 via the seventeenth resistor R17, and to its collector via the sixteenth resistor R16. The base of the fourth transistor Q4 is connected to the third pin of the differential amplifier chip U2 via the twenty-eighth resistor R28, and to its collector via the twenty-seventh resistor R27. Through this connection method, the third transistor Q3 and the fourth transistor Q4 can assist in stabilizing the operating state of the input terminals of the differential amplifier chip U2, ensuring that the input stage maintains good bias stability and input matching even when faced with fluctuations in human electrode contact impedance, baseline oscillation, and environmental noise coupling, thereby reducing additional errors caused by input imbalance.

[0038] The differential amplifier chip U2 is preferably an instrumentation amplifier. Its second and third pins receive the negative and positive signals, respectively, after conditioning by the preceding transistor network, thereby extracting and amplifying the differential component between the two inputs. Because the instrumentation amplifier itself has high common-mode rejection capability, it can retain the effective components of the EEG differential signal while suppressing common-mode noise caused by power frequency interference, human body noise, and electrode contact imbalance, which coexist in the positive and negative input channels. The sixth pin of the differential amplifier chip U2 serves as the output terminal, connected to the input terminal of the shaping unit, used to output the primary amplified differential EEG signal to the subsequent filtering and shaping stage; its seventh pin is connected to the 5V voltage terminal to provide power to the chip; the fourth and fifth pins are grounded to establish a stable reference ground; the first and eighth pins are connected to the common-mode feedback unit through resistors R37 (thirty-seventh resistor) and R36 (thirty-sixth resistor), respectively, enabling the differential amplifier chip U2 and the subsequent common-mode feedback loop to work in tandem. With this connection method, the common-mode feedback unit can provide feedback compensation for the common-mode components detected by the front end, further reducing the impact of common-mode interference on the input stage and improving the overall noise immunity of the front-end link.

[0039] In actual operation, the positive and negative signals acquired by the electrode module are first input to the front-end networks containing Q2 and Q1 via R21 and R18, respectively. Q1, Q2, and their corresponding RC branches first perform input buffering and preliminary anti-interference processing on the two weak EEG signals, and then send the processed signals to the differential amplifier chip U2. The differential amplifier chip U2 amplifies the potential difference between the positive and negative inputs, thereby outputting the EEG differential signal. For power frequency noise, common-mode drift, and external electromagnetic coupling interference superimposed on the positive and negative inputs, the high common-mode suppression characteristics of U2 and its cooperation with the common-mode feedback unit are used to suppress them. Finally, the differential amplifier unit outputs an analog EEG differential signal with a higher signal-to-noise ratio and a more suitable amplitude for subsequent processing to the shaping unit.

[0040] In the aforementioned differential amplification unit, by utilizing Q1 to Q4 in conjunction with U2 to form a multi-stage input conditioning and differential amplification structure, weak EEG signals can be stabilized and preprocessed before being extracted with high precision by an instrumentation amplifier, thus achieving both high input sensitivity and high amplification stability. Secondly, the input RC network composed of R18, R21, C20, C22, and C21 can suppress high-frequency noise, transient pulses, and inter-channel imbalances, which helps improve the purity of the front-end signal. Q3, Q4, R16, and R27 play an auxiliary stabilizing role in the input stage operating point, enabling the circuit to maintain relatively stable amplification characteristics even when electrode contact impedance changes, the user makes slight movements, or the skin condition changes. Finally, the differential amplification chip U2, connected to the common-mode feedback unit, can further improve the suppression of power frequency interference and human common-mode noise, thereby giving the output EEG signal a higher signal-to-noise ratio and lower baseline drift. Based on the above design, this differential amplifier unit is particularly suitable for continuous, stable and high-precision acquisition of low-amplitude, low-frequency slow-wave EEG signals in sleep scenarios, providing a reliable analog front-end foundation for subsequent analog-to-digital conversion and slow-wave recognition.

[0041] In some embodiments, such as Figure 3 As shown, the common-mode feedback unit 23 is used to detect, adjust, and compensate for common-mode interference between the human body and the front-end acquisition circuit. Specifically, it is composed of the 31st resistor R31, the 32nd resistor R32, the 34th resistor R34, the 34th capacitor C34, the 35th capacitor C35, the 39th capacitor C39, the 40th capacitor C40, the first operational amplifier U4B, the second operational amplifier U4A, the first sliding rheostat VR1, and the voltage regulating chip UT1. The first operational amplifier U4B constitutes the core processing stage of the reference feedback branch, the second operational amplifier U4A constitutes the drive / buffer stage coupled to the differential amplifier unit, the voltage regulating chip UT1 provides a stable common-mode reference potential, and the first sliding rheostat VR1 adjusts the potential relationship between analog ground and digital ground to ensure the common-mode feedback loop obtains a suitable operating reference.

[0042] Specifically, the inverting input of the first operational amplifier U4B is connected to the electrode module via the thirty-fourth capacitor C34 to receive the reference signal. Since the signal sensed by the reference electrode on the human body contains a strong common-mode component, this reference signal can reflect common-mode disturbance information such as power frequency coupling noise, changes in the human body's floating potential, and environmental electromagnetic interference. The thirty-fourth capacitor C34 acts as AC coupling and DC bias isolation in this path, ensuring that the main input to the first operational amplifier U4B is the changing interference component, rather than unnecessary static DC components. The output of the first operational amplifier U4B is connected to the electrode module via the thirty-second resistor R32 or the thirty-fifth capacitor C35, thus the feedback signal processed by U4B can be reapplied to the human body contact point corresponding to the reference electrode. The thirty-second resistor R32 is mainly used to limit the output current and stabilize the loop gain in the feedback path, while the thirty-fifth capacitor C35 is used to improve the dynamic frequency response of the feedback signal, achieving a balance between low-frequency common-mode rejection and high-frequency stability in the feedback path, thereby avoiding oscillation or overcompensation. The inverting input of the first operational amplifier U4B is connected to pin 2 of the voltage regulator chip UT1, indicating that the reference level output by UT1 is introduced to the input side of U4B to establish a stable common-mode reference point for feedback operation. The inverting input of the first operational amplifier U4B is also connected to the output of the second operational amplifier U4A through the thirty-first resistor R31, so that the control quantity output by U4A can be superimposed on the input side of U4B, thereby forming a closed-loop common-mode compensation path that is linked with the preceding differential amplifier unit.

[0043] Furthermore, the non-inverting input of the first operational amplifier U4B is connected to the free end of the first variable resistor VR1. The first fixed end of the first variable resistor VR1 is connected to analog ground, and the second fixed end is connected to digital ground. By adjusting the position of the sliding end of the first variable resistor VR1, the reference level of the non-inverting input of U4B can be fine-tuned, thereby balancing the small potential difference that may exist between analog ground and digital ground, and reducing additional common-mode disturbances caused by ground loops, digital switch noise coupling, or system layout. In other words, VR1 is not just a simple biasing component, but also plays a role in calibrating the operating point of the entire common-mode feedback unit and matching the system ground potential, which helps to improve the accuracy and stability of the reference feedback path.

[0044] The second operational amplifier U4A primarily serves as the driver and buffer in conjunction with the differential amplifier unit. The inverting input of the second operational amplifier U4A is connected to the third input of the differential amplifier unit, enabling it to receive common-mode or bias information from relevant nodes of the differential amplifier unit and use it as the basis for feedback control. Based on the aforementioned structure of the differential amplifier unit, U4A does not process the main EEG differential signal itself, but rather adjusts signals related to common-mode level, input stage bias, and front-end stability. By sending this information to U4A and then coupling it to the input side of U4B via the thirty-first resistor R31, collaborative operation between the differential amplifier unit and the common-mode feedback unit can be achieved. This ensures that common-mode compensation no longer relies solely on the reference electrode path but considers the overall operating state of the front-end input stage. The 34th resistor R34, the 39th capacitor C39, and the 40th capacitor C40 in the diagram together with the branches containing U4A and U4B form an auxiliary voltage regulation, decoupling, and frequency compensation network. This network is used to improve the power supply purity and loop stability of the operational amplifier during operation and reduce feedback errors caused by power supply fluctuations or high-frequency parasitic oscillations.

[0045] In actual operation, the reference signal acquired by the reference electrode is first coupled to the inverting input of the first operational amplifier U4B via the thirty-fourth capacitor C34. U4B amplifies and regulates the common-mode disturbance based on the common-mode disturbance component in the reference signal, the reference level provided by the voltage regulator chip UT1, and the output control quantity of the second operational amplifier U4A introduced through the thirty-first resistor R31. Then, the signal is fed back to the reference electrode in the electrode module via the thirty-second resistor R32 and / or the thirty-fifth capacitor C35. In this way, the common-mode voltage originally present on the human body and electrode system is canceled out by a feedback signal in the opposite direction, thus significantly reducing the common-mode noise entering the differential amplifier unit. Simultaneously, the first sliding rheostat VR1 calibrates the non-inverting input reference of U4B to ensure that the entire feedback loop maintains good suppression performance under different user conditions, attachment states, or system grounding conditions.

[0046] In the aforementioned common-mode feedback unit, the common-mode component of the reference signal is fed back in phase via U4B. This actively cancels human body power frequency coupling noise and environmental common-mode interference before the signal enters the differential amplifier chip. Compared to relying solely on the common-mode rejection capability of the instrumentation amplifier itself, the overall anti-interference effect is stronger. Through the linkage between U4A and related nodes of the differential amplifier unit, the feedback compensation can be dynamically adjusted not only based on the interference sensed by the reference electrode, but also in conjunction with the actual bias and common-mode state of the front-end input stage. Therefore, it can further reduce the impact of input saturation, baseline drift, and channel imbalance on system performance. The voltage regulator chip UT1 and the first sliding rheostat VR1 together provide a calibrable and adjustable working reference, making the common-mode feedback loop more adaptable and adjustable, suitable for sleep monitoring with different skin types, impedance states, and wearing environments. The thirty-second resistor R32, the thirty-fifth capacitor C35, and related decoupling compensation components together ensure the stability of the feedback loop, effectively suppressing low-frequency common-mode noise and avoiding oscillations caused by excessive loop gain. Based on the above design, the common-mode feedback unit can significantly improve the signal-to-noise ratio of the EEG front-end acquisition link, reduce input reference noise and baseline fluctuations, and provide a reliable guarantee for subsequent analog-to-digital conversion and high-stability recognition of slow-wave sleep.

[0047] In some embodiments, such as Figure 3 As shown, the shaping unit 22 is used to further filter, adjust the gain, and shape the waveform of the analog differential signal output by the differential amplifier unit to output an analog differential signal that meets the input requirements of the analog-to-digital conversion module. Specifically, the shaping unit may include a nineteenth resistor R19, a twentieth resistor R20, a twenty-second resistor R22, a twenty-third resistor R23, a twenty-fourth resistor R24, a twenty-fifth resistor R25, a twenty-sixth resistor R26, a twenty-ninth resistor R29, an eighteenth capacitor C18, a twenty-third capacitor C23, a twenty-fourth capacitor C24, a twenty-fifth capacitor C25, a twenty-sixth capacitor C26, a twenty-seventh capacitor C27, a second sliding rheostat VR2, a third operational amplifier U3A, and a fourth operational amplifier U3B. The above components work together to form a two-stage active filtering and shaping amplification structure. The third operational amplifier U3A forms the pre-stage filtering and shaping sub-unit, and the fourth operational amplifier U3B forms the post-stage filtering and shaping sub-unit. The two stages are connected in series to jointly complete the frequency band limitation, baseline adjustment and amplitude optimization of the EEG analog signal.

[0048] The non-inverting input of the third operational amplifier U3A is connected to the output of the differential amplifier unit via the twenty-fourth capacitor C24. Therefore, the primary amplified EEG signal output from the differential amplifier unit is first coupled through the twenty-fourth capacitor C24 before being sent to the third operational amplifier U3A. The twenty-fourth capacitor C24 mainly serves as an AC coupling element here, isolating the DC bias component in the output of the preamplifier stage, ensuring that the main component entering the shaping unit is the effective AC component of the EEG signal, thereby reducing the impact of the preamplifier stage offset voltage and baseline drift on subsequent processing. The non-inverting input of the third operational amplifier U3A is also connected to the free end of the second sliding rheostat VR2 via the twenty-fourth resistor R24. The free end of the second sliding rheostat VR2 is grounded, the first fixed end is grounded, and the second fixed end is connected to the inverting input of the third operational amplifier U3A via the twenty-second resistor R22. With the assistance of the second sliding rheostat VR2 and the twenty-second and twenty-fourth resistors R24, the operating point, gain, or zero point of the input terminal and feedback loop of the third operational amplifier U3A can be finely adjusted to adapt to different electrode contact states, different user individual impedance conditions, and changes in the output amplitude of the preamplifier, thereby improving the adaptability and calibrability of the shaping unit. The output terminal of the third operational amplifier U3A is connected to its inverting input terminal through the twenty-ninth resistor R29 or the twenty-seventh capacitor C27, so the feedback loop of U3A contains both resistive and capacitive feedback branches, thus forming an active frequency selective network. This network can perform preamplifier gain amplification and frequency response shaping on the input EEG signal, preserving the lower-frequency slow-wave components of sleep while suppressing high-frequency interference above the target frequency band.

[0049] The relevant nodes of the third operational amplifier U3A are grounded after passing through the 23rd capacitor C23 and the 23rd resistor R23, forming a bleeder and frequency compensation branch. This further stabilizes the operation of the pre-stage filtering and shaping network, reducing spikes and high-frequency glitches in the output waveform. The output of the third operational amplifier U3A is then connected to the non-inverting input of the fourth operational amplifier U3B after passing through the 23rd capacitor C23, the 19th resistor R19, and the 20th resistor R20. In other words, the signal shaped by the pre-stage amplifier is transmitted to the fourth operational amplifier U3B through an interstage coupling and impedance matching network. This interstage network continues to filter out residual DC components and irrelevant low-frequency drift, and also helps improve the impedance matching between the pre-stage and post-stage amplifiers, preventing the pre-stage output from directly loading the post-stage input and affecting the overall filtering characteristics.

[0050] The fourth operational amplifier U3B constitutes the subsequent shaping and output drive stage. The output of the fourth operational amplifier U3B is connected to its non-inverting input via the eighteenth capacitor C18 and the twentieth resistor R20. This branch forms a positive frequency compensation and dynamic response adjustment structure, which is beneficial for smoothing the output waveform and suppressing sudden fluctuations. The output of the fourth operational amplifier U3B is then connected to its inverting input via the twenty-sixth resistor R26 and the twenty-sixth capacitor C26, thus forming the subsequent active feedback filter network. The twenty-sixth resistor R26 is mainly used to set the amplification factor and DC feedback stability of the subsequent stage, while the twenty-sixth capacitor C26 participates in setting the high-frequency cutoff characteristics, further attenuating high-frequency interference components. Simultaneously, the non-inverting input of the fourth operational amplifier U3B is grounded via the twenty-fifth capacitor C25, and the inverting input is grounded via the twenty-fifth resistor R25. These components together establish the reference input environment and auxiliary filtering path for U3B, enabling it to maintain a relatively stable reference point and good low-noise performance during output signal processing. The signal processed by the fourth operational amplifier U3B can be used as the analog differential signal output by the shaping unit and sent to the subsequent analog-to-digital conversion module for digital sampling.

[0051] The EEG analog signal output from the differential amplifier unit first enters the pre-stage shaping sub-unit composed of U3A, where AC coupling, preliminary filtering, gain adjustment, and operating point calibration are completed. Then, it is fed into the post-stage shaping sub-unit composed of U3B via an inter-stage network consisting of C23, R19, and R20, where high-frequency suppression, waveform smoothing, and output drive are further performed. The combined effect of these two shaping stages concentrates the output signal's frequency band more closely to the target sleep slow-wave detection frequency band, typically demonstrating effective preservation of low-frequency slow-wave components and significant suppression of baseline drift, high-frequency electromyographic noise, and environmental electromagnetic interference.

[0052] This embodiment, by setting the shaping unit 23 described above, utilizes U3A and U3B to form a two-stage active filter shaping structure. Compared to a simple single-stage amplifier circuit, it can more precisely control the signal bandwidth and waveform characteristics, making the output more suitable for subsequent analog-to-digital conversion and algorithm recognition. Through coupling capacitors such as C24 and C23, and adjustment networks such as R24, R22, and VR2, the DC drift and offset components of the preceding stage can be effectively removed, and the zero point and gain can be flexibly adjusted according to different application states, thus improving the system's adaptability to different individuals and different wearing conditions. Through the active frequency selection network composed of feedback elements such as R29, C27, R26, and C26, comprehensive shaping of high-pass and low-pass characteristics can be achieved, suppressing high-frequency interference and irrelevant noise while retaining the effective slow-wave sleep signal, improving the signal-to-noise ratio. The subsequent stage U3B not only performs further filtering but also acts as an output buffer and driver, giving the shaped EEG analog signal better stability and output capability, enabling reliable input to the analog-to-digital conversion module. Based on the above design, the shaping unit can significantly improve the quality of the EEG front-end output signal, providing a reliable basis for high-precision extraction and high-stability evaluation of sleep slow waves.

[0053] Furthermore, such as Figure 4 As shown, the analog-to-digital conversion module includes an analog-to-digital conversion chip U1, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, a sixth capacitor C6, a seventh capacitor C7, an eighth capacitor C8, a ninth capacitor C9, a tenth capacitor C10, a first resistor R1, a second resistor R2, a forty-first resistor R41, and a forty-second resistor R42.

[0054] The analog-to-digital converter chip U1 is preferably an ADS1292RIPBSR, used to receive the analog differential signal output by the shaping unit and convert the analog differential signal into a digital differential signal for output to the control module. Specifically, the first pin of the analog-to-digital converter chip U1 is connected to the second pin through the first capacitor C1, which is used to bypass compensation and stabilize the corresponding preamplifier input node; the third pin of the analog-to-digital converter chip U1 is connected to the analog ground AGND through the forty-first resistor R41, and the fourth pin of the analog-to-digital converter chip U1 is connected to the output terminal of the shaping unit 23 through the forty-second resistor R42, thereby forming an analog EEG input channel; the fifth pin of the analog-to-digital converter chip U1 is reserved in this embodiment, and the sixth pin of the analog-to-digital converter chip U1 can optionally be connected to the output terminal of the second shaping unit to form a dual-channel synchronous sampling structure; the seventh pin of the analog-to-digital converter chip U1 is connected to the eighth pin through the third capacitor C3 to compensate and stabilize the preamplifier node of the other channel. Pins 9 and 10 of the analog-to-digital converter (ADC) chip U1 are reference terminals, connected to the analog reference network in this embodiment, and forming a decoupling / stabilizing branch through capacitors C4 and C5 to improve reference level stability. Pin 11 of the ADC chip U1 is connected to analog ground AGND through capacitor C10 for internal voltage regulation node decoupling. Pin 12 of the ADC chip U1 is connected to the 3.3V voltage terminal, and is also connected to analog ground AGND through capacitors C8 and C9 to perform low-noise decoupling of the analog power supply. Pin 13 of the ADC chip U1 is connected to analog ground AGND. Pin 14 of the ADC chip U1 is connected to the 3.3V voltage terminal through resistor R1 for clock mode configuration. Pin 15 of the ADC chip U1 is connected to the reset control terminal of the control module, and pin 16 of the ADC chip U1 is connected to the start control terminal of the control module. Pin 17 of the ADC chip U1 is grounded through resistor R2 for clock-related configuration. Pin 21 of the analog-to-digital converter (ADC) chip U1 is connected to the control module for outputting the converted digital data. Pin 22 of the ADC chip U1 is also connected to the control module for outputting a data ready signal. Pin 23 of the ADC chip U1 is connected to a 3.3V voltage terminal, and is further connected to pin 24 via capacitors C6 (sixth capacitor) and C7 (seventh capacitor). Pin 24 is connected to digital ground (DGND) to decouple and filter the digital power supply, ensuring stable operation of the digital interface. Pins 18, 19, and 20 of the ADC chip U1 can also be connected to the chip select, serial data input, and serial clock terminals of the control module, respectively, to form an SPI communication interface for transmitting digital differential signals to the control module.Furthermore, pins 28, 29, and 30 of the analog-to-digital converter chip U1 are common-mode feedback related pins, which can be connected to an external common-mode feedback circuit. Pin 30 outputs a common-mode feedback drive signal, while pins 28 and 29 are used to receive feedback detection signals, thereby monitoring and compensating for common-mode drift and human body coupling interference in the front-end analog signal link and improving the stability of EEG acquisition.

[0055] This embodiment employs the aforementioned analog-to-digital conversion module. Through the ADS1292R chip's built-in 24-bit high-resolution analog-to-digital converter and programmable gain amplifier, it can perform high-precision sampling of low-amplitude EEG slow-wave signals, improving the accuracy of subsequent slow-wave recognition. The ADS1292R chip supports dual-channel input expansion, facilitating the formation of a dual-channel synchronous EEG sampling structure. A multi-stage decoupling design of analog power supply, digital power supply, reference terminal, and internal voltage regulator effectively reduces the impact of power supply ripple, digital switching noise, and reference drift on the conversion results, ensuring the authenticity and stability of the digital differential signal. By setting pins such as RLDOUT, RLDIN, and RLDINV in conjunction with an external common-mode feedback circuit, the impact of human body power frequency interference and common-mode drift on the front-end acquisition link can be further reduced, thereby improving the anti-interference capability and long-term monitoring reliability of the entire wireless EEG patch device in sleep scenarios.

[0056] Furthermore, this application also provides a power module, such as... Figure 5 As shown, the power supply module includes a voltage regulator chip U3, a nineteenth capacitor C19, a forty-first capacitor C41, a forty-second capacitor C42, a forty-third capacitor C43, a forty-fourth capacitor C44, a thirty-fifth resistor R35, and a forty-fifth capacitor C45. The voltage regulator chip U3 is preferably a low-dropout linear regulator chip, used to convert the externally input 5V voltage into a stable 3.3V voltage to provide stable power to the analog-to-digital conversion module, the control module, and related low-voltage circuits.

[0057] Specifically, pins 1 and 3 of the voltage regulator chip U3 are both connected to the 5V voltage terminal. Pin 1 is the input terminal, and pin 3 is the enable terminal. Therefore, an external 5V power supply can directly power the voltage regulator chip U3 and put it into operation. Pin 1 of the voltage regulator chip U3 is grounded through the nineteenth capacitor C19, and is also grounded through the forty-first capacitor C41. The nineteenth capacitor C19 and the forty-first capacitor C41 together form an input decoupling filter network. The nineteenth capacitor C19 is preferably a large-capacity capacitor to suppress low-frequency input ripple and voltage fluctuations caused by load changes. The forty-first capacitor C41 is preferably a small-capacity high-frequency bypass capacitor to filter out high-frequency noise in the input power supply, thereby ensuring that the 5V voltage input to the voltage regulator chip U3 has good stability and purity.

[0058] Pin 2 of the voltage regulator chip U3 is grounded to establish a ground reference for normal chip operation. Pin 4 of the voltage regulator chip U3 is grounded through capacitor C42 (pin 42), which corresponds to the chip's noise suppression / feedback terminal. Capacitor C42 is used for compensation filtering at this terminal to reduce output noise and improve output voltage stability. Pin 5 of the voltage regulator chip U3 is the output terminal. Pin 5 is grounded through capacitor C43 (pin 43) and capacitor C44 (pin 44). Capacitors C43 and C44 together form the output decoupling filter network. Preferably, capacitor C43 is a large-capacity output filter capacitor to smooth the regulated output voltage and improve load transient response. Capacitor C44 is preferably a small-capacity high-frequency decoupling capacitor to suppress high-frequency noise and spike interference at the output terminal, thus making the output voltage of the voltage regulator chip U3 more stable.

[0059] Furthermore, pin 5 of the voltage regulator chip U3 is connected to the 3.3V voltage terminal via resistor R35 (the 35th resistor). As shown in the attached diagram, resistor R35 is preferably a ferrite bead or a high-frequency impedance device. It is positioned between the output of the voltage regulator chip U3 and the 3.3V power supply bus to further block and filter high-frequency noise, thereby suppressing the reverse coupling of high-frequency interference generated during switching of subsequent digital circuits to the regulated output, and improving the purity of the 3.3V power supply network. Therefore, after voltage regulation by the voltage regulator chip U3 and filtering isolation by resistor R35 (the 35th resistor), the 3.3V voltage terminal can provide a low-noise, high-stability operating power supply for the EEG acquisition front-end, analog-to-digital conversion module, and control module.

[0060] Furthermore, the common ground (GND) is connected to the virtual ground (VGND) via capacitor C45 (45th capacitor). C45 forms an AC coupling path between the common ground and the virtual ground, allowing high-frequency interference components to be bypassed and discharged between different ground references, while avoiding ground loop interference that might result from direct hard connections between different ground systems. In this way, while ensuring the relative independence of each ground reference, the impact of high-frequency noise, power supply return noise, and digital switch interference on the analog front-end can be reduced, thereby further improving the anti-interference capability of the entire wireless EEG patch device in weak EEG signal acquisition scenarios.

[0061] In summary, the power module uses the low-dropout regulator chip U3 to stably convert 5V to 3.3V, meeting the power supply accuracy and stability requirements of low-power EEG acquisition systems. Multi-stage decoupling capacitors at the input and output terminals effectively suppress power ripple and high-frequency noise, reducing the impact of power supply fluctuations on analog-to-digital conversion and front-end amplification accuracy. High-frequency isolation of the 3.3V output bus via the ferrite bead / impedance device corresponding to resistor R35 further suppresses noise crosstalk during digital circuit operation. High-frequency coupling of different ground references via capacitor C45 reduces ground loop interference and digital ground noise's impact on the analog ground system. The power module provides a low-noise, high-stability, and highly interference-resistant power supply foundation for the entire wireless EEG patch device, making it particularly suitable for applications requiring high-precision acquisition of weak slow-wave sleep EEG signals.

[0062] The control module is used to extract sleep slow waves from the digital differential signal and evaluate the sleep slow waves to obtain highly stable EEG slow wave data. Preferably, the control module can be composed of a microcontroller (MCU) and a sleep slow wave processing and reliability fusion algorithm. The MCU receives the digital differential signal output from the analog-to-digital converter (ADC), first extracts the slow wave frequency band, and then performs phase analysis, amplitude analysis, multi-lead consistency analysis, and signal quality analysis on the extracted slow waves to identify sleep slow waves in the 0.5–2 Hz range. Simultaneously, the control module can also combine the amplitude consistency, phase synchronization, contact impedance changes, signal-to-noise ratio, and motion artifacts between leads to perform reliability scoring on slow wave events, thereby outputting highly stable EEG slow wave data and reducing the impact of single electrode abnormalities, local interference, and motion artifacts on the monitoring results. The electrode module is connected to the input of the filter amplification module, the output of the filter amplification module is connected to the input of the analog-to-digital conversion module, and the output of the analog-to-digital conversion module is connected to the control module, so as to form a complete signal processing link from analog EEG acquisition, differential amplification and filtering, analog-to-digital conversion to sleep slow wave recognition and assessment.

[0063] like Figure 2 , Figure 7As shown, in addition to the aforementioned front-end circuitry, the wireless EEG patch in this embodiment employs a highly integrated, miniaturized circuit structure. The overall design uses an MCU as the control core, with peripheral components including an EEG acquisition module, electrode interface, Bluetooth antenna, power module, NFC control module, and an NFC antenna coil arranged along the patch edge. The electrodes connect to the EEG analog front-end via the electrode interface. The EEG analog front-end amplifies, filters, and performs analog-to-digital conversion on the acquired EEG signals, and transmits the digital EEG data to the MCU via the SPI bus. After obtaining the EEG data, the MCU determines the sleep stage and performs adaptive sampling and power consumption control based on the determination result: when deep sleep is detected and the slow-wave power density exceeds a preset threshold Pδ, the sampling rate is increased from 125Hz to 500Hz to improve slow-wave phase resolution; when in light sleep or a non-slow-wave stage, the sampling rate and processing load are reduced to decrease system power consumption and extend battery life. The wireless communication system establishes a BLE 5.0 connection with an external application via a Bluetooth antenna. In closed-loop operation mode, it only uploads slow-wave trigger timestamps, single-pulse trigger markers, sleep stage tags, and signal quality assessment parameters, without persistently storing the raw continuous EEG data locally, thus balancing transmission efficiency, privacy protection, and low power consumption. The wireless charging system includes an NFC antenna, a lithium battery, and a battery management module. The NFC antenna operates in the 13.56MHz band and achieves wireless charging via magnetic coupling, with a charging power not exceeding 200mW. When an NFC charging field is detected, the battery management module sends a status signal to the MCU. The MCU then controls the shutdown of the EEG acquisition module and the Bluetooth communication module, and puts the system into an isolation protection mode to prevent electromagnetic interference during charging from affecting EEG acquisition. With the above structural layout, the patch can operate stably with a thickness of no more than 3mm and a weight of no more than 8g. Combined with breathable medical adhesive, a sweat-proof structure, and a design for stable overnight application, it meets the requirements for continuous sleep monitoring for at least 12 hours.

[0064] Example 2 Building upon Example 1, this example further provides a method for monitoring slow-wave EEG, applied to the wireless EEG patch device described in Example 1. The method utilizes the collaborative operation of an electrode module, a filtering and amplification module, an analog-to-digital conversion module, and a control module to achieve real-time monitoring, reliability assessment, and trigger time determination of slow-wave sleep in a target user. Specifically, it includes the following steps: S1. Obtain the electroencephalogram (EEG) signal of the target user using the electrode module, wherein the EEG signal includes a positive signal, a negative signal, and a reference signal.

[0065] Specifically, multiple electrode modules attached to the forehead region of the target user collect the user's electroencephalogram (EEG) activity, obtaining EEG signals. These EEG signals include positive signals, negative signals, and a reference signal. The positive and negative signals characterize differential EEG activity between different leads, while the reference signal is used for common-mode interference suppression and reference potential establishment. Preferably, the multiple electrode modules are arranged in a multi-lead configuration on the forehead to obtain synchronized EEG signals from multiple leads, thus providing a multi-lead data foundation for subsequent slow-wave detection, phase analysis, and reliability scoring.

[0066] S2. The EEG signal is processed by the filtering and amplification module to obtain an analog signal containing the slow EEG waves of the target user.

[0067] Specifically, the filtering and amplification module first suppresses common-mode interference in the EEG signal and performs differential extraction and amplification of the positive and negative signals to obtain a differential analog signal containing valid EEG components. Subsequently, the differential analog signal is filtered in the slow-wave band to retain the low-frequency components corresponding to sleep slow waves. Preferably, the filtering process employs a high-pass and low-pass combination structure, where the high-pass filter removes DC drift and slow baseline shift, and the low-pass filter suppresses high-frequency electromyographic noise and environmental interference, thereby obtaining an analog signal containing EEG slow-wave components. It should be noted that the signal obtained in this step is a slow-wave band correlated analog signal, which still needs subsequent analog-to-digital conversion and control analysis to further determine whether it represents a valid slow-wave event.

[0068] S3. Use the analog-to-digital conversion module to convert the EEG slow wave related analog signal from an analog signal to a digital signal.

[0069] Specifically, the analog-to-digital conversion module samples and converts the analog differential signal output in step S2 to generate a corresponding digital differential signal, and outputs the digital differential signal to the control module. Preferably, the analog-to-digital conversion module uses a high-resolution analog-to-digital conversion chip for synchronous sampling to ensure the sampling accuracy of low-frequency, low-amplitude EEG slow-wave signals. In some embodiments, the analog-to-digital conversion module can also dynamically adjust the sampling rate according to the control commands output by the control module to balance monitoring accuracy and system power consumption.

[0070] S4. The control module is used to perform signal analysis on the converted EEG slow wave signal. The signal analysis includes at least slow wave confidence score and slow wave phase calculation to determine whether the target user is in a state where stimulation can be applied and to determine the timing of stimulation application.

[0071] The slow-wave confidence score is used to evaluate the validity and triggering reliability of the current slow-wave event. Preferably, the slow-wave confidence score... It can be calculated by weighting multiple sub-indicators: Among them, it means that among them, For multi-lead amplitude consistency index, As an indicator of phase synchronization, This refers to the signal quality index. As an index for motion artifact suppression, The weighting coefficient is adjustable. By comprehensively analyzing the amplitude consistency, phase synchronization, electrode contact quality, signal-to-noise ratio, power frequency residual interference, and motion artifacts of multiple leads, it can be determined whether the current slow wave event is a valid trigger candidate. Preferably, when the slow wave confidence score is greater than a preset confidence threshold, the current slow wave event is determined to be a valid slow wave event; otherwise, the event is ignored.

[0072] The slow-wave phase calculation is used to determine the timing of stimulus application. Specifically, real-time phase estimation is performed on the filtered slow-wave signal, preferably using Hilbert transform to construct a complex analytic signal. ;in, This is the signal after slow-wave filtering. This is the result of the Hilbert transform. Further, the instantaneous phase of the slow wave is defined as: and normalize the phase range to Preferably, the slow wave rising phase is defined as: ; When multiple leads simultaneously meet the rising phase condition and the slow wave confidence score exceeds a threshold, a trigger candidate event is generated. To improve robustness, phase calculation preferably performs synchronization fusion across multiple leads, including calculating the lead average phase, removing outlier leads, and using phase lock values ​​to assess the degree of synchronization.

[0073] Furthermore, the slow-wave confidence score can also be used to determine whether the target user is in a state where stimulation can be applied, in conjunction with the sleep stage determination results. When the target user is in a deep sleep state and the confidence score of the current slow-wave event exceeds a preset threshold, the target user is determined to be in a state where stimulation can be applied; when the target user is not in a deep sleep state, the EEG signals collected in the current time period are not used as the basis for stimulation triggering, and stimulation triggering events are not generated based on the signals in that time period.

[0074] In some embodiments, EEG signals collected in the current time period can be overwritten and cleared after real-time analysis is completed, without being stored locally persistently.

[0075] Furthermore, determining the timing of applying the stimulus specifically involves performing phase analysis on the EEG signal. When the phase analysis result is a rising phase, the stimulus is applied to the target user within a preset time delay, thereby maintaining a time-locked relationship between the stimulus timing and the rising phase of the slow wave, in order to improve the regulatory effect of the stimulus on the slow waves of deep sleep.

[0076] Furthermore, to avoid multiple triggers within the same slow-wave period, the method may also include an anti-repeated triggering step. Specifically, after generating a valid trigger, the system enters a locking window, during which further triggering is prohibited. The length of the locking window is adaptively determined based on the moving average of the most recent few slow-wave periods. Before the locking window ends, even if a new rising phase is detected again, no new stimulus trigger signal is output. When the slow wave disappears or the slow-wave confidence score falls below a threshold, the system can exit the locking window early and re-enter a waiting state to reduce false triggers caused by high-frequency jitter, local artifacts, or sampling noise.

[0077] Furthermore, during the implementation of the method, the control module can also perform adaptive sampling and power consumption control based on the sleep stage determination result. When the target user is in deep sleep and the slow wave power density exceeds a preset threshold, the sampling rate can be increased from 125 Hz to 500 Hz to improve the slow wave phase resolution; when the target user is in light sleep or a non-slow wave stage, the sampling rate and processing load are reduced to reduce system power consumption and extend the patch battery life.

[0078] Furthermore, in closed-loop operating mode, the device only sends slow-wave trigger timestamps, single-pulse trigger markers, sleep stage tags, and signal quality assessment parameters to external applications via the wireless communication module, without locally persisting the raw continuous EEG data, thus balancing real-time closed-loop control, low-power operation, and user privacy protection.

[0079] Example 3 A computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the slow-wave brainwave monitoring method as described in Example 2.

[0080] Example 4 In one embodiment, a computer device is provided, which may be a server, and its internal structure diagram may be as follows: Figure 9 As shown, the computer device includes a processor, memory, network interface, and database connected via a system bus. The processor provides computational and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system, computer programs, and database. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage media. When the computer program is executed by the processor, it implements a slow-wave brainwave monitoring method.

[0081] Those skilled in the art will understand that Figure 9The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0082] The above description is merely a preferred embodiment of the present invention. The scope of protection of the present invention is not limited to the above embodiments. All technical solutions falling within the scope of the present invention's concept are within the scope of protection of the present invention. It should be noted that for those skilled in the art, any improvements and modifications made without departing from the principles of the present invention should also be considered within the scope of protection of the present invention.

Claims

1. A wireless EEG patch device for slow-wave sleep monitoring, characterized in that, include: The electrode modules, which are multiple in number, are used to contact the head of a target user to obtain simulated electroencephalogram (EEG) signals, which include: a positive electrode signal, a negative electrode signal, and a reference signal. The filtering and amplification module is used to suppress the common-mode portion of the simulated EEG signal and amplify the differential signal in the simulated EEG signal. The analog-to-digital converter module is used to convert the amplified analog differential signal into a digital differential signal; The control module is used to extract sleep slow waves from the digital differential signal and evaluate the sleep slow waves to obtain highly stable EEG slow wave data. The electrode module is connected to the input terminal of the filter amplification module; the output terminal of the filter amplification module is connected to the input terminal of the analog-to-digital conversion module; and the output terminal of the analog-to-digital conversion module is connected to the control module.

2. The wireless EEG patch device for slow-wave sleep monitoring according to claim 1, characterized in that, The electrode module includes: an insulating base layer and silver electrodes; The silver electrode is embedded in the insulating base layer and includes a connecting part and a bonding part; the connecting part is used for electrical connection with external devices; the bonding part is covered with a full tetrafluorosilver-silver chloride coating to reduce and stabilize the contact resistance with the skin.

3. The wireless EEG patch device for slow-wave sleep monitoring according to claim 2, characterized in that, The filtering and amplification module includes: A common-mode feedback unit, connected to an electrode module for outputting a reference signal, is used to generate a feedback signal based on the reference signal or a common-mode component, and to apply the feedback signal to the reference electrode to suppress common-mode interference. A differential amplifier unit is used to extract differential components based on the positive signal and the negative signal, and amplify the differential components to output a differential signal. A shaping unit, the input of which is connected to the output of the differential amplifier unit, is used to filter, adjust the gain, and shape the waveform of the differential signal to output an analog differential signal that meets the requirements of analog-to-digital conversion.

4. The wireless EEG patch device for slow-wave sleep monitoring according to claim 3, characterized in that, The differential amplifier unit includes: a sixteenth resistor, a seventeenth resistor, an eighteenth resistor, a twenty-first resistor, a twenty-seventh resistor, a twenty-eighth resistor, a thirty-sixth resistor, a thirty-seventh resistor, a twentieth capacitor, a twenty-first capacitor, a twenty-second capacitor, a first transistor, a second transistor, a third transistor, a fourth transistor, and a differential amplifier chip; The collector of the first transistor is connected to the electrode module through the eighteenth resistor to obtain the negative signal; the emitter of the first transistor is grounded; the collector of the first transistor is grounded through the twentieth capacitor; the base of the first transistor is connected to the second pin of the differential amplifier chip through the seventeenth resistor. The collector of the second transistor is connected to the electrode module through the twenty-first resistor to obtain the positive signal; the emitter of the second transistor is grounded; the collector of the second transistor is grounded through the twenty-second capacitor; the base of the second transistor is connected to the third pin of the differential amplifier chip through the twenty-eighth resistor. The collector of the first transistor is connected to the collector of the second transistor through the twenty-first capacitor; The base of the third transistor is connected to pin 2 of the differential amplifier chip via the seventeenth resistor; the base of the third transistor is connected to the collector of the third transistor via the sixteenth resistor; the emitter of the third transistor is grounded. The base of the fourth transistor is connected to the third pin of the differential amplifier chip through the twenty-eighth resistor; the base of the fourth transistor is connected to the collector of the fourth transistor through the twenty-seventh resistor; the emitter of the fourth transistor is grounded. The first pin of the differential amplifier chip is connected to the common-mode feedback unit through the thirty-seventh resistor; the eighth pin of the differential amplifier chip is connected to the common-mode feedback unit through the thirty-sixth resistor; the fourth pin of the differential amplifier chip is grounded; the fifth pin of the differential amplifier chip is grounded; the sixth pin of the differential amplifier chip is connected to the input terminal of the shaping unit; and the seventh pin of the differential amplifier chip is connected to the 5V voltage terminal.

5. The wireless EEG patch device for slow-wave sleep monitoring according to claim 4, characterized in that, The common-mode feedback unit includes: a 31st resistor, a 32nd resistor, a 34th resistor, a 34th capacitor, a 35th capacitor, a 39th capacitor, a 40th capacitor, a first operational amplifier, a second operational amplifier, a first sliding rheostat, and a voltage regulation chip. The inverting input of the first operational amplifier is connected to the electrode module via the thirty-fourth capacitor to receive the reference signal; the output of the first operational amplifier is connected to the electrode module via the thirty-second resistor or the thirty-fifth capacitor; the inverting input of the first operational amplifier is connected to the second pin of the voltage regulator chip; the inverting input of the first operational amplifier is also connected to the output of the second operational amplifier via the thirty-first resistor; the non-inverting input of the first operational amplifier is connected to the free end of the first sliding rheostat; the first fixed end of the first sliding rheostat is connected to analog ground, and the second fixed end of the first sliding rheostat is connected to digital ground. The positive input terminal of the second operational amplifier is connected to the 5V voltage terminal; the negative input terminal of the second operational amplifier is connected to the analog ground; the non-inverting input terminal of the second operational amplifier is connected to the output terminal of the second operational amplifier; and the inverting input terminal of the second operational amplifier is connected to the third input terminal of the differential amplifier unit.

6. The wireless EEG patch device for slow-wave sleep monitoring according to claim 5, characterized in that, The shaping unit includes: a nineteenth resistor, a twentieth resistor, a twenty-second resistor, a twenty-third resistor, a twenty-fourth resistor, a twenty-fifth resistor, a twenty-sixth resistor, a twenty-ninth resistor, an eighteenth capacitor, a twenty-third capacitor, a twenty-fourth capacitor, a twenty-fifth capacitor, a twenty-sixth capacitor, a twenty-seventh capacitor, a second sliding rheostat, a third operational amplifier, and a fourth operational amplifier; The non-inverting input of the third operational amplifier is connected to the output of the differential amplifier unit through the twenty-fourth capacitor; the non-inverting input of the third operational amplifier is connected to the free end of the second sliding rheostat through the twenty-fourth resistor; the free end of the second sliding rheostat is grounded; the first fixed end of the second sliding rheostat is grounded; the second fixed end of the second sliding rheostat is connected to the inverting input of the third operational amplifier through the twenty-second resistor; the output of the third operational amplifier is connected to the inverting input of the third operational amplifier through either the twenty-ninth resistor or the twenty-seventh capacitor; the positive input of the third operational amplifier is connected to a 5V voltage terminal, and the negative input of the third operational amplifier is grounded. The third operational amplifier is grounded after passing through the twenty-third capacitor and the twenty-third resistor in sequence; the output terminal of the third operational amplifier is connected to the non-inverting input terminal of the fourth operational amplifier after passing through the twenty-third capacitor, the nineteenth resistor, and the twentieth resistor in sequence. The output of the fourth operational amplifier is connected to its non-inverting input via the eighteenth capacitor and the twentieth resistor. The output of the fourth operational amplifier is connected to its inverting input via the twenty-sixth resistor and the twenty-sixth capacitor. The non-inverting input of the fourth operational amplifier is grounded via the twenty-fifth capacitor. The inverting input of the fourth operational amplifier is grounded via the twenty-fifth resistor.

7. The wireless EEG patch device for slow-wave sleep monitoring according to claim 3, characterized in that, The analog-to-digital conversion module includes an analog-to-digital conversion chip, which receives the analog differential signal output by the shaping unit and performs analog-to-digital conversion on the analog differential signal to generate a corresponding digital differential signal. The analog-to-digital converter chip is also used to provide a reference voltage signal, which is used to monitor and compensate for common-mode drift and human body coupling interference in the front-end analog signal link.

8. A method for monitoring slow-wave brain activity, characterized in that, The method, applied to the wireless EEG patch device as described in any one of claims 1-7, comprises: The electrode module is used to acquire the electroencephalogram (EEG) signal of the target user, wherein the EEG signal includes a positive signal, a negative signal, and a reference signal; The EEG signal is processed by the filtering and amplification module to obtain an analog signal containing the slow EEG waves of the target user. The analog-to-digital conversion module is used to convert analog signals containing slow brain waves from analog signals to digital signals; The control module is used to perform signal analysis on the converted EEG slow wave signal. The signal analysis includes at least slow wave confidence scoring and slow wave phase calculation to determine whether the target user is in a state where stimulation can be applied and to determine the timing of stimulation application.

9. The method for monitoring slow brain waves according to claim 8, characterized in that, When the target user is in a state where stimulation cannot be applied, the EEG signals collected in the current time period are discarded.

10. The method for monitoring slow brain waves according to claim 8, characterized in that, The determination of the timing of applying stimulation specifically involves performing phase analysis on the electroencephalogram (EEG) signal, and applying stimulation to the target user within a preset time delay when the phase analysis result is an ascending phase.

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