Radar chip, processor chip, radar system, and electronic device

Abstract

This application relates to the field of radar technology, and discloses a radar chip, a processor chip, a radar system, and an electronic device. The radar chip of this application includes: a first processing module and a first conversion module connected to the first processing module; the first conversion module is used to connect to the processor chip to form a first link; the first processing module is used to connect to the processor chip to form a second link; the first conversion module is used to obtain service data from the first processing module and transmit the service data to the processor chip through the first link; the first processing module is used to receive control signals from the processor chip through the second link; thereby taking into account the chip's PPA performance, power consumption, area, and data integrity.

Description

Technical Field

[0001] This application relates to the field of radar technology, and in particular to a radar chip, processor chip, radar system, and electronic device. Background Technology

[0002] Currently, with the continuous emergence of new applications such as data centers and artificial intelligence, the data surge in radar systems has increased by several orders of magnitude compared to the past, thus creating a growing demand for high-speed interfaces. Existing high-speed interfaces between radar chips and processor chips are mostly based on a serializer-deserializer (SerDes) design. SerDes boasts speeds up to 128Gbps, effectively addressing the interface's bandwidth bottleneck.

[0003] In related technologies, the SerDes used between radar chips and processor chips include bidirectional SerDes and unidirectional SerDes. However, neither bidirectional nor unidirectional SerDes can simultaneously address the issues of chip PPA (Power-to-Average Power) and data integrity. Summary of the Invention

[0004] The purpose of this application is to provide a radar chip, processor chip, radar system, and electronic device that addresses both the PPA (Power, Power, and Abilities) of the chip and data integrity issues.

[0005] To address the aforementioned technical problems, embodiments of this application provide a radar chip, comprising: a first processing module and a first conversion module connected to the first processing module; the first conversion module is configured to connect to a processor chip to form a first link; the first processing module is configured to connect to the processor chip to form a second link; the first conversion module is configured to acquire service data from the first processing module and transmit the service data to the processor chip via the first link; the first processing module is configured to receive control signals from the processor chip via the second link.

[0006] Embodiments of this application also provide a processor chip, including: at least one second processing module and at least one second conversion module connected to each of the at least one second processing module; one second processing module and a corresponding second conversion module form a communication unit; one communication unit is used to connect to a radar chip; wherein, the second conversion module of one communication unit is connected to one radar chip to form a first link; the second processing module of one communication unit is connected to one radar chip to form a second link; the second conversion module of one communication unit is used to receive service data from one radar chip through the first link; the second processing module of one communication unit is used to transmit control signals to one radar chip through the second link.

[0007] Embodiments of this application also provide a radar system, including: a processor chip and at least one radar chip; each radar chip includes a first processing module and a first conversion module connected to the first processing module; the processor chip includes at least one communication unit connected to at least one of the radar chips in a one-to-one correspondence, each communication unit includes a second processing module and a second conversion module connected to the second processing module; wherein, the first conversion module of one radar chip is connected to the second conversion module of the corresponding communication unit to form a first link; the first conversion module of one radar chip transmits service data to the second conversion module of the corresponding communication unit through the first link; the first processing module of one radar chip is connected to the second processing module of the corresponding communication unit to form a second link; the first processing module of one radar chip receives the control signal from the second processing module of the corresponding communication unit through the second link.

[0008] Embodiments of this application also provide an electronic device, including: a radar chip as described above, or a processor chip as described above, or a radar system as described above.

[0009] The technical solution provided in this application has at least the following advantages:

[0010] In this embodiment, a first link is formed by connecting the first conversion module of the radar chip to the second conversion module of a communication unit of the processor chip. A second link is formed by connecting the first processing module of the radar chip to the second processing module of a communication unit of the processor chip. The radar chip transmits service data to the processor chip through the first link and receives control signals from the processor chip through the second link. Thus, service data with high transmission speed requirements is transmitted through the first link, while control signals with lower transmission speed requirements are transmitted through the second link. The bidirectional transmission of control signals and service data also ensures the integrity of service data transmission. At the same time, the first processing module of the radar chip and the second processing module of the processor chip in this embodiment only need to provide unidirectional ports, resulting in a reduction in the area of ​​the radar chip and the processor chip, a reduction in power consumption, and an improvement in energy efficiency. Attached Figure Description

[0011] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0012] Figure 1 This is a schematic diagram of the structure of a radar chip according to an embodiment of this application;

[0013] Figure 2 This is a schematic diagram of the specific structure of a radar chip according to an embodiment of this application;

[0014] Figure 3 This is a schematic diagram of the process of transmitting service data by a radar chip according to an embodiment of this application;

[0015] Figure 4 This is a schematic diagram of a radar chip transmitting control signals according to an embodiment of this application;

[0016] Figure 5 This is a schematic diagram of the structure of a processor chip according to an embodiment of this application;

[0017] Figure 6 This is a schematic diagram of the specific structure of a processor chip according to an embodiment of this application;

[0018] Figure 7 This is a schematic diagram of a processor chip transmitting service data according to an embodiment of this application;

[0019] Figure 8 This is a schematic diagram of a processor chip transmitting control signals according to an embodiment of this application;

[0020] Figure 9 This is a schematic diagram of the structure of a radar system according to an embodiment of this application;

[0021] Figure 10 This is a schematic diagram of the specific structure of a radar system according to an embodiment of this application. Detailed Implementation

[0022] As can be seen from the background technology, neither bidirectional SerDes nor unidirectional SerDes can simultaneously address the issues of PPA and data integrity.

[0023] Analysis revealed that current bidirectional SerDes systems treat both the uplink and downlink as a single lane for high-speed full-duplex communication. However, the significant difference in traffic between the uplink and downlink results in one link operating in an undersaturated state. This not only wastes resources, leading to high power consumption and halved energy efficiency, but also results in a large footprint on the chip due to the need for TX and RX ports. In contrast, unidirectional SerDes only supports data transmission from the radar chip to the processor. Data transmission errors can compromise data integrity, compromising vehicle safety when the radar system is installed in a vehicle.

[0024] To address the aforementioned technical problems, this application provides a radar chip, a processor chip, a radar system, and an electronic device. A first processing module of the radar chip and a second processing module of the processor chip form a second link for transmitting control signals, thus solving the technical problem that neither bidirectional nor unidirectional SerDes can simultaneously guarantee chip PPA (Performance, Power, Area) and data integrity. In this embodiment, the first conversion module of the radar chip is connected to a second conversion module of a communication unit of the processor chip to form a first link, and the first processing module of the radar chip is connected to a second processing module of a communication unit of the processor chip to form a second link. The radar chip transmits signals through the first link. The radar chip transmits business data to the processor chip via a second link. The radar chip receives control signals from the processor chip through the second link. The first conversion module, such as the first SerDes module, only needs to set the TX port, and the second conversion module, such as the second SerDes module, only needs to set the RX interface. The RX interface of the radar chip is provided by the first processing module, and the TX interface of the processor chip is provided by the corresponding second processing module. This reduces the area of ​​the radar chip and the processor chip, lowers power consumption, and improves energy efficiency. At the same time, the first processing module of the radar chip and the corresponding second processing module of the processor chip form a second link for transmitting control signals, which can also ensure the integrity of the data transmitted by the radar chip and improve the safety of vehicle operation in the field of vehicles.

[0025] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the various embodiments of this application will be described in detail below with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been presented in the various embodiments of this application to enable readers to better understand this application. However, the technical solutions claimed in this application can be implemented even without these technical details and various changes and modifications based on the following embodiments.

[0026] The division of the following embodiments is for ease of description and should not constitute any limitation on the specific implementation of this application. The various embodiments can be combined with and referenced by each other without contradiction.

[0027] This application provides a radar chip for identifying motion, speed, and distance to acquire operational data. For example, the radar chip is positioned in the front, rear, left, and right directions of a vehicle to acquire object information in each of these four directions, thereby providing guidance for vehicle operation. The radar chip in this embodiment can be a millimeter-wave radar chip, a frequency-modulated continuous wave radar chip, etc.

[0028] In this embodiment, the first conversion module of the radar chip is used to connect to the processor chip to form a first link; the first processing module of the radar chip is used to connect to the processor chip to form a second link; the first conversion module is used to obtain service data from the first processing module and transmit the service data to the processor chip through the first link; the first processing module is used to receive control signals from the processor chip through the second link.

[0029] Since the first processing module of the radar chip is directly connected to the processor chip to form a second link, the first processing module receives control signals from the processor chip through the second link. The first processing module is also used to perform bit-width conversion on the control signals to obtain a first intermediate control signal. For example, the first processing module receives a 1-bit control signal from the second link, i.e., the GPIO (General-purpose input / output) link. The first processing module converts the 1-bit control signal into a 130-bit first intermediate control signal. The first intermediate control signal is used to provide feedback control for the transmission of business data in the first processing module.

[0030] Furthermore, the radar chip also includes a first register module connected to the first processing module; the first register module is used to generate a second clock signal according to the first clock signal and preset first configuration information, the first processor module performs bit width conversion on the control signal under the action of the first clock signal, and the first processing module receives the control signal from the second link under the action of the second clock signal.

[0031] To facilitate a better understanding of the working process of the radar chip provided in the above embodiments by those skilled in the art, the following will use... Figure 1 The structural diagram of the radar chip shown is used for explanation.

[0032] The radar chip 10 includes: a first processing module 101 and a first conversion module 102 connected to the first processing module 101; the first conversion module 102 is used to connect to the processor chip 20 to form a first link mainband; the first processing module 101 is used to connect to the processor chip 20 to form a second link sideband; the first conversion module 102 is used to obtain service data from the first processing module 101 and transmit the service data to the processor chip 20 through the first link mainband; the first processing module 101 is used to receive control signals from the processor chip 20 through the second link sideband.

[0033] like Figure 2 The diagram shows the internal structure of the radar chip. In this embodiment, the first processing module 101 has a first application layer C2C_AP1, a first transmission layer C2C_TL1, a first data link layer C2C_DLL1, and a first physical layer C2C_PL1 based on the C2C protocol.

[0034] In this embodiment, the first processing module 101 is also used to receive the decoder's global clock clk or global reset rst, and the dft (Design for Testability) signal. The first processing module 101 is also used to send or receive the sideband signal (tx / rx), the analog power supply amplitude adjustment coefficient c2c_cfg_ana_amplitude (L0s, standby), and the functional safety signal err_eco_sb / db (safety), which detects 1-bit and 2-bit errors in the memory MEM. The error correction signal 1 and error detection signal 2 are used for functional safety. The interrupt convergence output signal c2c_int, the internal interrupt convergence output of the C2C, is used to notify the CPU (Central Processing Unit). The first processing module also includes a first C2C register module c2c_regfile_top1, used to receive or send the APB (Advanced Peripheral Bus) signal.

[0035] The first application layer C2C_AP1 of the first processing module 101 includes a first signal input interface AXI StreamIn1, used to obtain initial service data from the memory of the radar chip 10 via the AXI (Advanced eXtensible Interface) bus. AXI Stream In1 also receives stream data, which may originate from the radar signal processing module (Radio Signal Process, RSP) or the debugging module Debug. The initial service data is in AXI format and is input to AXI Stream In1 via AXI_Stream_S_C2C_In. Another data path is stream data. If the stream data originates from the RSP module, AXI Stream In receives the stream data via AXI_Stream_S_RSP_In; if the stream data originates from the Debug module, AXI Stream In receives the stream data via AXI_Stream_S_Debug_In. The first application layer C2C_AP1 also performs format conversion on the AXI format initial service data to obtain TLP (Transaction Layer Packet) format initial service data and prepares the corresponding packet header.

[0036] For example, when an object is present near the vehicle while it is in motion, the radar chip 10 acquires the distance information of the object around the vehicle. Then, it converts this distance information into initial service data through analog-to-digital conversion and stores it in the first memory of the radar chip 10. The first application layer C2C_AP1 retrieves this initial service data from the memory of the radar chip 10 through the AXI bus and performs format conversion to obtain the initial service data in TLP format.

[0037] The first transport layer C2C_TL1 of the first processing module 101 is used to obtain the initial service data (Data) and the corresponding header (Hrd) from the first application layer C2C_AP1 of the first processing module 101, and package the initial service data (Data) and the header (Hrd) into service data. At this time, the format of the service data is TLP message. Specifically, the first transport layer C2C_TL1 includes a TL1 layer data buffer module c2c_tl_tx_vc1_buf and a TL1 layer packetization module c2c_tl_tx_tlp_pkg. c2c_tl_tx_vc1_buf includes memory MEM1 and a first-in-first-out register Reg / Fifo1. The c2c_tl_tx_vc1_buf of the first transport layer C2C_TL1 obtains initial service data in TLP format and the corresponding header from the first application layer C2C_AP1 of the first processing module 101. The initial service data (Data) in TLP format is stored in memory MEM1, and the header (Hrd) is stored in Reg / Fifo1. c2c_tl_tx_vc1_buf transmits the initial service data and header in TLP format to c2c_tl_tx_tlp_pkg, and c2c_tl_tx_tlp_pkg performs the assemble operation. The package (assembly packet) is formed by packaging the initial service data (Data) in TLP format and the packet header (Hrd) into a TLP message. If there is cross-segment transmission, the 32-bit CRC (Cyclic Redundancy Check) value of the packet header (Hrd) and the initial service data (Data) in TLP format is added to the end of the TLP data packet, i.e., ECRC (End-to-end CRC, Transaction Layer Cyclic Redundancy Check), resulting in Hrd+Data+ECRC.

[0038] The first data link layer C2C_DLL1 of the first processing module 101 is used to receive service data (Hrd+Data+ECRC) from the first transport layer C2C_TL1, add a sequence number (seq) and LCRC (Link CRC, data link layer cyclic redundancy check) to the service data to obtain seq+Hrd+Data+ECRC+LCRC, and then cache the service data. Specifically, the first data link layer C2C_DLL1 includes the DLL1 layer packetization module c2c_dll_pkg, the TLP retransmission buffer module c2c_rty_buf, the DLLP packet generation module c2c_dllp_gen1, and the DLL1 layer transmission control module c2c_dll_tx_ctrl1. After receiving the service data (Hrd+Data+ECRC) from the first transport layer C2C_TL1, the first data link layer C2C_DLL1's c2c_dll_pkg adds a sequence number and LCRC to the service data (TLP packet) to obtain seq+Hrd+Data+ECRC+LCRC, and buffers the service data seq+Hrd+Data+ECRC+LCRC to c2c_rty_buf. The first data link layer C2C_DLL1's c2c_dll_pkg also pushes the service data TLP packet (seq+Hrd+Data+ECRC+LCRC) to the first physical layer C2C_PL1.

[0039] The first physical layer C2C_PL1 is also used to obtain the TLP packet of service data (i.e., seq+Hrd+Data+ECRC+LCRC) from the first data link layer C2C_DLL1, add a data header and a data trailer to the service data and indicate the boundary of the service data, and then transmit the service data to the first conversion module 102. Specifically, the first physical layer C2C_PL1 includes the PL1 layer's sending module c2c_pl_tx. After obtaining the TLP packet of service data (seq+Hrd+Data+ECRC+LCRC) from the first data link layer C2C_DLL1, the c2c_pl_tx of the first physical layer C2C_PL1 adds a data header (STP) and a data trailer (END) to the service data, resulting in a TLP packet of service data as STP+seq+Hrd+Data+ECRC+LCRC+END. At the same time, the boundary indication module Pkt_handle indicates the boundary of the TLP packet, and the TLP packet is processed by the byte stripe module, the scrambling module, the synchronization header module block_gen, and the first bit width conversion module Gearbox1.

[0040] The first physical layer C2C_PL1 also performs bit width conversion on the service data. For example, the service data transmitted internally by the first processing module 101 is 130 bits, while the service data received by the first conversion module 102, i.e. the first SerDes module, is 20 bits. The first physical layer C2C_PL1 of the first processing module 101 needs to convert the 130-bit service data into 20-bit service data so that it can be transmitted to the first conversion module 102.

[0041] After receiving the service data, the first conversion module 102 also needs to perform bit-width conversion on the service data. For example, the first conversion module 102 converts 20-bit service data into a 1-bit service data TLP message, and transmits the 1-bit service data TLP message differentially to the processor chip 20 through the first link mainband. The first conversion module 102, i.e., the first SerDes module, can also convert parallel service data into serial service data.

[0042] The first physical layer C2C_PL1 also includes the control module c2c_pl_ctrl1 of the PL1 layer. c2c_pl_ctrl1 is connected to the sending module c2c_pl_tx of the PL1 layer. c2c_pl_ctrl1 includes the first state machine (Link Training and StatusState Machine) LTSSM1 and the first active state power management (Active State Power Management) ASPM1. LTSSM1 is the master state machine. Under normal working conditions, LTSSM1 can exchange information normally between chips. ASPM1 keeps the chip in a low-power state when there is no service.

[0043] like Figure 3 The diagram shown is a schematic of the radar chip transmitting service data in this embodiment. The radar chip 10 includes a first processing module 101 and a first conversion module 102. The radar chip 10 also includes a first memory 103, which can be AFIFIO (Asynchronous First-In-First-Out memory).

[0044] The initial service data Data is stored in the first memory 103. The first processing module 101 retrieves the initial service data Data from the first memory 103. The initial service data Data can be 130 bits. The first processing module 101 processes the data into a service data TLP message after packetization and bit width conversion, and sends it to the first conversion module 102. The service data TLP message can be 20 bits. The first conversion module 102 converts the 20-bit service data TLP message into a 1-bit service data TLP message after bit width conversion, and transmits it differentially to the processor chip 20 through the first link mainband.

[0045] The first memory 103 also receives the first clock signal c2c_clk1 from inside the radar chip 10 and transmits the first clock signal c2c_clk1 to the first processing module 101. The operating clock of the first clock signal c2c_clk1 is 200MHz. The first processing module 101 also receives the clock signal sds_clk1 from the first conversion module 102. The clock signal sds_clk1 can be 125MHz, 250MHz, 500MHz, etc., and one of them can be selected. In this embodiment, the first conversion module 102 can convert a 20-bit service data TLP message into a 1-bit service data TLP message. The first conversion module 101 operates under the action of the clock signal sds_clk1. The frequency of the clock signal sds_clk1 determines the bandwidth of the 1-bit service data TLP message for differential transmission in the first link mainband. For example, when the clock signal sds_clk1 of the first conversion module 101 is 250MHz, the transmission bandwidth of the 1-bit service data is 5Gbps.

[0046] The above describes the process by which radar chip 10 transmits service data through the first link (mainband). The following details the process by which radar chip 20 receives control signals through the second link (sideband). The second link (sideband) can transmit control signals via the GPIO protocol. GPIO features low power consumption, small package size, and low cost. Furthermore, compared to other protocols, GPIO offers a higher transmission rate, reaching up to 150Mbps. In other embodiments, where the transmission rate requirement is not high, an IIC (Inter-Integrated Circuit Bus) interface can be used.

[0047] In this embodiment, the first physical layer C2C_PL1 of the first processing module 101 is connected to the processor chip 20 through the second link sideband, i.e., the GPIO cable. It receives low-speed control signals from the processor chip 20 through the second link sideband and performs bit-width conversion on the control signals to obtain the first intermediate control signal. The first intermediate control signal is used to control the transmission of service data in the first processing module 101.

[0048] The first physical layer C2C_PL1 also includes the PL1 layer sideband processing module c2c_pl_sideband1. c2c_pl_sideband1 receives control signals and interacts with the LTSSM1 of c2c_pl_ctrl1 to exchange L0 / L0s / L1 / L2 signals. Among them, L0 is the normal working state, and the chips can exchange information normally; L0s is the connection standby state. In L0s mode, the clock is maintained and the power is kept on, but the connection will not actively transmit data; L1 is the low power standby mode. In L1 mode, the reference clock signal remains unchanged, and the power saving efficiency is higher than that of L0s; L2 is the auxiliary power mode. In L2 mode, the power consumption is the lowest. The clock signals of all devices are idle, and only the low-frequency clock used to detect network wake-up function (WAKE) and beacon events remains.

[0049] Since the bit width of the control signal transmitted in the second link sideband (GPIO link) is different from the bit width transmitted inside the first processor, for example, the bit width of the second link sideband (GPIO link) is 1 bit, while the bit width transmitted inside the first processor is 130 bits, the frequency of the clock signal used to receive the low-speed control signal is different from the frequency of the clock signal used by the first processor. In order to convert the 1-bit control signal into a 130-bit first intermediate control signal, this embodiment performs bit width conversion in the first physical layer C2C_PL1.

[0050] like Figure 4 The diagram shown is a schematic of the radar chip transmitting control signals in this embodiment. The radar chip 10 also includes a first register module 104 connected to the first processing module 101.

[0051] The first register module 104 receives preset first configuration information cfg_sideband_clk_div1, which is a set value of the first register module 104 and can be set according to actual needs, for example, cfg_sideband_clk_div1 can be set to 10. The first register module 104 also receives a first clock signal c2c_clk1, which is generated by the clock module inside the radar chip 10. The first register module 104 receives the first clock signal c2c_clk1 according to the clock signal c2c_clk1. 1. The preset first configuration information cfg_sideband_clk_div1 generates the second clock signal div_clk1. The first register module 104 reduces the frequency of the first clock signal c2c_clk1 to the frequency of the second clock signal div_clk1, that is, the frequency of the second clock signal div_clk1 is less than the frequency of the first clock signal c2c_clk1; for example, the first clock signal c2c_clk1 is 200MHz, the first configuration information cfg_sideband_clk_div1 is 10, and the second clock signal div_clk1 output by the first register module 104 is 20MHz.

[0052] The first processing module 101 also receives a control signal Pkg_c via a second sideband, i.e., a GPIO link. The control signal Pkg_c can be 1 bit, and the transmission bandwidth is 20 Mbps. The first processing module 101 performs bit-width conversion on the 1-bit control signal Pkg_c to obtain a first intermediate control signal Pkg_c1, which can be 130 bits. In this embodiment, the first processing module 101 receives the control signal from the second sideband under the action of the second clock signal div_clk1. The first processor module 101 is also used to perform bit-width conversion and transmit the first intermediate control signal Pkg_c1 under the action of the first clock signal c2c_clk1.

[0053] Continue to refer to Figure 2 In this embodiment, the first intermediate control signal includes a retransmission control signal, which indicates whether to retransmit the cached service data. The cached service data is cached by the radar chip 10 during the transmission of service data through the first data link layer C2C_DLL1 of the first processing module 101, specifically cached in c2c_rty_buf of the first data link layer C2C_DLL1. The first intermediate control signal DLLPs also includes a flow control signal, which indicates the remaining storage space information of the second processing module.

[0054] After the first physical layer C2C_PL1 performs bit-width conversion on the control signal to obtain the first intermediate control signal, it transmits the first intermediate control signal to the first CRC check module c2c_dllp_check1 of the first data link layer C2C_DLL1. Specifically, it performs CRC check on the 16-bit DLLPs received by the first data link layer C2C_DLL1. After receiving the retransmission control signal in the first intermediate control signal, c2c_dllp_check1 of the first data link layer C2C_DLL1 determines whether to retransmit the buffered service data based on the retransmission control signal in the first intermediate control signal. The retransmission control signal is either AckDLLP or Nak DLLP. If c2c_dllp_check1 of the first data link layer C2C_DLL1 determines that the buffered service data should be retransmitted, it retransmits the buffered service data. The first data link layer C2C_DLL1 is also used to release the buffered service data if it determines that the buffered service data should not be retransmitted, i.e., when the retransmission control signal is Ack. When DLLP occurs, the service data (TLP message) in the corresponding buffer c2c_rty_buf is released. If the retransmission control signal is Nak DLLP, the service data (TLP message) in the corresponding buffer c2c_rty_buf will be retransmitted.

[0055] The c2c_dllp_check1 of the first data link layer C2C_DLL1 also transmits the flow control signal in the first intermediate control signal to the flow control module c2c_tl_fc1 of the TL1 layer of the first transport layer C2C_TL1 of the first processing module for flow control. The c2c_tl_fc1 of the first transport layer C2C_TL1 is used to determine whether to continue pushing the remaining service data after receiving the flow control signal. The remaining service data is the service data that has not been transmitted through the first link mainband, that is, the service data stored in the memory MEN1 of the first transport layer C2C_TL1. The first transport layer C2C_TL1 is also used to push the remaining service data in MEN1 if it is determined to continue pushing the remaining service data. The first transport layer C2C_TL1 is also used to stop pushing the remaining service data in MEN1 if it is determined to stop pushing the remaining service data.

[0056] In practical applications, the flow control signal is FC DLLP. When the flow control signal FC DLLP from the peer chip (i.e., the processor chip) is received, if the peer chip has sufficient buffer space, the feedback control in the first transport layer C2C_TL1 (c2c_tl_tx_tlp_pkg) continues to push the initial service data (Data) in memory MEM1 and the packet header (Hrd) in Reg / Fifo to the first data link layer C2C_DLL1. If the peer chip has insufficient space, the feedback control in c2c_tl_tx_tlp_pkg does not push the initial service data (Data) and the packet header (Hrd) in Reg / Fifo1, continues to wait, and continues to receive the flow control signal FC DLLP in the control signals to re-evaluate the buffer space of the peer chip. The c2c_tl_fc of the first transport layer C2C_TL1 can also control the DLLP message generation module c2c_dllp_gen1 of the first data link layer C2C_TL1 through feedback, thereby controlling the transmission of service data in the first data link layer C2C_TL1. c2c_dllp_gen1 feeds back the feedback signal to c2c_dll_pkg through c2c_dll_tx_ctrl1, thereby controlling c2c_dll_pkg to stop merging TLP data with sequence number and LCRC into TLP message when the space of the peer chip is insufficient.

[0057] In this embodiment, the radar chip 10 is connected to the processor chip 20 through the first conversion module 102, i.e., the first SerDes module, to form a first link mainband. It is also connected to the processor chip 20 through the first processing module 101 to form a second link sideband. This allows service data with high transmission speed requirements to be transmitted through the first link mainband, while control signals with lower transmission speed requirements are transmitted through the second link sideband. This reduces the area of ​​the first conversion module 102 of the radar chip 10, lowers power consumption, and improves energy efficiency. At the same time, the bidirectional transmission of control signals and service data also ensures the integrity of service data transmission.

[0058] Another embodiment of this application provides a processor chip for acquiring service data from a radar chip and controlling the transmission of service data in a first processing module through control signal feedback.

[0059] The processor chip in this embodiment includes multiple communication units. One communication unit is used to connect to a radar chip. The second conversion module of the communication unit is connected to the radar chip to form a first link, and the second processing module of the communication unit is connected to the radar chip to form a second link. The second conversion module of the communication unit is used to receive service data from a radar chip through the first link. The second processing module of the communication unit is used to transmit control signals to a radar chip through the second link.

[0060] Since the second processing module of a communication unit is connected to a radar chip to form a second link, the second processor module performs bit-width conversion on the second intermediate control signal to obtain the control signal before sending the control signal. For example, the service data transmitted internally by the first processing module is 130 bits, and the second processing module sends a 1-bit control signal through the second link, i.e., the GPIO link. Therefore, the second processing module needs to perform bit-width conversion on the 130-bit second intermediate control signal to obtain a 1-bit control signal, and send it to the radar chip through the GPIO link. The second intermediate control signal is generated by the second processing module based on the service data, and the second intermediate control signal is used to provide feedback control on the transmission of service data in the radar chip.

[0061] Furthermore, the processor chip also includes a second register module connected to the second processing module; the second register module is used to generate a fourth clock signal according to the third clock signal and the preset second configuration information; the second processor module performs bit-width conversion on the second intermediate control signal under the action of the third clock signal to obtain a control signal; and the second processing module sends the control signal to the second link under the action of the fourth clock signal.

[0062] To facilitate a better understanding of the operation of the processor chip provided in the above embodiments by those skilled in the art, the following will use... Figure 5 The structural diagram of the processor chip shown is used for illustration.

[0063] The processor chip 20 includes: at least one second processing module 201, and at least one second conversion module 202 (i.e., a second SerDes module) connected one-to-one with the at least one second processing module 201; one second processing module 202 and its corresponding second conversion module 202 form a communication unit 200; one communication unit 200 is used to connect to a radar chip 10; wherein, the second conversion module 202 of the communication unit is connected to a radar chip 10 to form a first link mainband; the second processing module 201 of the communication unit 200 is connected to a radar chip 10 to form a second link sideband; the second conversion module 202 of the communication unit 200 is used to receive service data from a radar chip 10 through the first link mainband; the second processing module 201 of the communication unit 200 is used to transmit control signals to a radar chip 10 through the second link sideband.

[0064] like Figure 6 The diagram shows the internal structure of the processor chip. In this embodiment, the second processing module internally forms a second transport layer C2C_TL2, a second data link layer C2C_DLL2, and a second physical layer C2C_PL2 based on the C2C protocol. The processor chip 20 also forms a second application layer C2C_AP2 based on the C2C protocol. Multiple second processing modules are connected to a single second application layer C2C_AP2. The diagram uses one communication unit, namely one second processing module 201 and one second conversion module 202, as an example for illustration. In practical applications, the number of communication units can also be multiple.

[0065] In this embodiment, the processor chip is also used to receive the decoder's global clock clk or global reset rst, and dft. The second processing module is also used to send or receive the sideband signal (tx / rx), the analog power supply amplitude adjustment coefficient c2c_cfg_ana_amplitude (L0s, standby), and the functional safety signal err_eco_sb / db (safety) and the interrupt convergence output signal c2c_int. The second processing module also includes a second register module c2c_regfile_top2, used to receive or send the APB signal.

[0066] In this embodiment, during the operation of the processor chip 20, a communication unit 200 corresponds to a radar chip 10. The second conversion module 202 of the communication unit is used to receive service data from the radar chip 10 through the first link mainband. After receiving the service data from the peer chip, i.e., the radar chip 20, the second conversion module 202, i.e. the second SerDes module, performs bit width conversion on the service data, for example, converting 1-bit service data into 20-bit service data, and sends the 20-bit service data to the second physical layer C2C_PL2. The second physical layer C2C_PL2 also performs bit width conversion on the 20-bit service data, for example, converting the 20-bit service data into 130-bit service data. The service data is a TLP message, including STP+seq+Hrd+Data+ECRC+LCRC+END.

[0067] Specifically, the second conversion module 202, namely the second SerDes module, also converts the serial service data into parallel service data and sends it to the second physical layer C2C_PL2.

[0068] The second physical layer C2C_PL2 includes the PL2 layer control module c2c_pl_rx. The PL2 layer receiving module c2c_pl_rx of the second physical layer C2C_PL2 receives parallel service data, namely c2c_pl_tx_lane_proc_wrap, c2c_pl_tx_lane_proc_1, and c2c_pl_tx_lane_proc_0, from the second conversion module 202, namely the second SerDes module. After the second physical layer C2C_PL2's c2c_pl_tx passes through the second bit width conversion module Gearbox2, the synchronization header alignment module block_align, the descramble module Descramble, the byte destriping module byte_unstripe, and the data packet receiving module Pkt_rec, it removes the data header STP and data trailer END from the service data to obtain seq+Hrd+Data+ECRC+LCRC.

[0069] The second data link layer C2C_DLL2 includes the DLL2 layer unpacking module c2c_dll_unpkg, the second CRC check module c2c_dllp_check2, the DLLP packet generation module c2c_dllp_gen2, and the DLL2 layer transmission control module c2c_dll_tx_ctrl2. After receiving service data from the second physical layer C2C_PL2, the second data link layer C2C_DLL2 performs LCRC detection on the TLP packet of the service data, i.e., seq+Hrd+Data+ECRC+LCRC. If the LCRC detection is normal, c2c_dll_unpkg removes the LCRC and Sequence Number from the service data to obtain Hrd+Data+ECRC, and transmits the service data to the second transport layer C2C_TL2. At the same time, it generates a retransmission control signal, ACK DLLP, indicating the release of buffered service data. If the CRC detection is abnormal, the TLP packet is discarded, and a retransmission control signal, Nak DLLP, indicating the retransmission of buffered service data is generated. Both DLLP and Nak DLLP are sent to c2c_dllp_gen2; there is interaction between c2c_dllp_gen2 and c2c_dll_tx_ctrl2.

[0070] The second transport layer C2C_TL2 includes the flow control module c2c_tl_fc2, the unpacking module c2c_tl_rx_tlp_unpkg, and the data buffer module c2c_tl_rx_vc1_buf. c2c_tl_rx_vc1_buf includes memory MEM2 and a first-in-first-out register FifoReg2. c2c_tl_rx_tlp_unpkg is used to obtain service data from c2c_dll_unpkg of the second data link layer C2C_DLL2 and perform ECRC check on the service data. If the ECRC check is normal, the ECRC is removed from the service data to obtain the initial service data (Data) and the packet header (Hrd). The initial service data (Data) is stored in the memory MEM of c2c_tl_rx_vc1_buf, and the packet header (Hrd) is stored in Reg / Fifo2 of c2c_tl_rx_vc1_buf. Subsequently, the second transport layer C2C_TL2 transmits the initial service data (Data) to the second application layer C2C_AP2, and discards the service data in the event of an ECRC check error.

[0071] The second CRC check module c2c_dllp_check2 of the second data link layer C2C_DLL2 controls c2c_tl_fc2 in the second transport layer C2C_TL2 to obtain the remaining storage space information in memory MEM2. This causes c2c_tl_fc2 to feed back the remaining storage space information in memory MEM2 to c2c_dllp_gen2. c2c_dllp_gen2 then generates a flow control signal (FC DLLP) based on this information. The flow control signal represents the remaining storage space information of memory MEM in the second transport layer C2C_TL2 of the second processing module. After receiving the retransmission control signal and the flow control signal, c2c_dllp_gen2 generates a second intermediate control signal based on these signals.

[0072] The second application layer, C2C_AP2, stores the initial service data in the processor chip's second memory after receiving it. Specifically, C2C_AP2 includes a second load balancing scheduling module RR2, an AP2 layer receive processing module c2c_ap_rx_tlp_proc2, and an interface AXI_Master2. After receiving the initial service data Data from the second transport layer C2C_TL2, the data is sequentially routed through RR2 and c2c_ap_rx_tlp_proc2. Once scheduling takes effect, AXI-formatted commands and data are generated and uploaded to the AXI bus via AXI_Master2, writing them into the processor chip's SRAM. The second application layer (C2C_AP2) also includes an address restoration module, Addr_Remap, used to restore addresses.

[0073] like Figure 7 The diagram shown is a schematic of the processor chip transmitting service data in this embodiment. The processor chip 20 includes a second processing module 201 and a second conversion module 202. The processor chip 20 also includes a second memory 203, which can be an AFIFO (Asynchronous First-In-First-Out) memory.

[0074] The second memory 203 receives the second clock signal c2c_clk2 from inside the processor chip and transmits the second clock signal c2c_clk2 to the second processing module 201. The operating clock of the second clock signal c2c_clk2 is 200MHz. The second processing module 201 also receives the clock signal sds_clk2 from the second conversion module 202. The clock signal sds_clk2 can be 125MHz, 250MHz, 500MHz, etc., and one of them can be selected.

[0075] The second conversion module 202 receives service data TLP messages from the radar chip 10 through the first link mainband. The service data TLP message can be 1 bit and the transmission bandwidth is 5Gbps. The second conversion module 202 operates under the action of the clock signal sds_clk2, which can be 250MHz. The second conversion module 202 performs bit width conversion on the service data TLP message to obtain a 20-bit service data TLP message, which is then transmitted to the second processing module 20.

[0076] After receiving the 20-bit service data TLP message, the second processing module 201 performs bit-width conversion, unpacking, and other processing on the service data TLP message to obtain the initial service data Data, which is then stored in the second memory 203. The second memory 203 also sends the initial service data Data to other modules; for example, in the vehicle field, after the second memory 203 of the processor chip 20 obtains the initial service data Data from the radar chip, it sends the initial service data Data to the processor CORE of the processor chip 20. The CORE performs corresponding calculations to provide feedback control for the vehicle and improve the safety of vehicle operation.

[0077] The above describes the process by which the processor chip 20 receives service data through the first link (mainband). The following describes in detail the process by which the processor chip sends control signals through the second link (sideband). The second link can transmit control signals via the GPIO protocol.

[0078] Continue to refer to Figure 6 Under the control of c2c_dllp_check2, c2c_tl_fc2 of the second transport layer C2C_TL2 obtains the remaining storage space information in memory MEM. c2c_tl_fc2 feeds back the remaining storage space information in memory MEM to c2c_dllp_gen2 of the second data link layer C2C_DLL2. c2c_dllp_gen2 generates a flow control signal, i.e., FC DLLP, based on the remaining storage space information in memory MEM2.

[0079] After receiving the service data (TLP message), c2c_dllp_check2 in the second data link layer C2C_DLL2 performs LCRC detection on the service data. If the service data is normal, c2c_dll_unpkg generates an ACK DLLP retransmission control signal indicating the release of buffered service data. If the service data is abnormal, it generates a Nak DLLP retransmission control signal indicating the retransmission of buffered service data. The retransmission control signal indicates whether to retransmit the buffered service data. The buffered service data is cached by the radar chip 10 during service data transmission, specifically in the memory MEM2 of the second transport layer C2C_TL2. Both the ACK DLLP and Nak DLLP retransmission control signals are sent to c2c_dllp_gen2. c2c_dllp_gen2 also transmits the flow control signal FC DLLP and the ACK DLLP or Nak DLLP retransmission control signals as second intermediate control signals DLLPs to the second physical layer C2C_PL2. That is, the second intermediate control signals include retransmission control signals and flow control signals.

[0080] The second physical layer C2C_PL2 also includes the sideband processing module c2c_pl_sideband2 of the PL2 layer and the control module c2c_pl_ctrl2 of the PL2 layer. c2c_pl_ctrl2 includes the second state machine LTSSM2 and the second active state power management ASPM2. c2c_pl_sideband2 also interacts with LTSSM2 in c2c_pl_ctrl2 at L0 / L0s / L1 / L2. c2c_pl_ctrl is connected to c2c_pl_rx.

[0081] The second physical layer C2C_PL2's c2c_pl_sideband2 receives the second intermediate control signal from the second data link layer C2C_DLL2 and performs bit-width conversion on the second intermediate control signal to obtain the control signal. The second physical layer C2C_PL2 also connects to the RX port of the radar chip 10 through the second link sideband. The second physical layer C2C_PL transmits low-speed control signals to the corresponding radar chip 10 through the second link sideband, including flow control signals for code rate control and retransmission control signals, i.e., ACK / NAK, etc., to provide feedback on the transmission of control service data in the radar chip 10.

[0082] In one communication unit, the second physical layer C2C_PL2 of the second processing module 201 is used to perform bit-width conversion on the second intermediate control signal to obtain a control signal. Since the bit width of the control signal transmitted on the GPIO link is different from that transmitted inside the second processor 201 (e.g., the bit width of the second link sideband, i.e., the GPIO link, is 1 bit, while the bit width transmitted inside the second processor 201 is 130 bits), the frequency of the clock signal used by the second processor 201 to send the low-speed control signal is different from the frequency of the clock signal used by the second processor 201 for operation. To convert the 130-bit second intermediate control signal into a 1-bit control signal, in one communication unit, the second physical layer C2C_PL2 of the second processing module 201 performs bit-width conversion on the second intermediate control signal to obtain the control signal.

[0083] like Figure 8 The diagram shown is a schematic of the transmission of control signals by the processor chip in this embodiment. The processor chip 20 also includes a second register module 204 connected to the second processing module 201.

[0084] The second register module 204 is used to receive the preset second configuration information cfg_sideband_clk_div2. The second configuration information cfg_sideband_clk_div2 is a set value of the second register module 204, which can be set according to actual needs. For example, the second configuration information cfg_sideband_clk_div2 can be set to 10. The second register module 204 also receives the third clock signal c2c_clk2, which is generated by the clock module inside the processor chip 20.

[0085] The second register module 204 generates a fourth clock signal div_clk2 based on the third clock signal c2c_clk2 and the preset second configuration information cfg_sideband_clk_div2. The second register module 204 reduces the frequency of the third clock signal c2c_clk2 to the frequency of the fourth clock signal div_clk2, that is, the frequency of the fourth clock signal div_clk2 is less than the frequency of the third clock signal c2c_clk2; for example, if the third clock signal c2c_clk2 is 200MHz, the second configuration information cfg_sideband_clk_div2 is set to 10, and the fourth clock signal div_clk2 output by the second register module 204 is 20MHz.

[0086] The second processing module 201 also sends a control signal Pkg_c through the second link, i.e., the GPIO chain. The control signal Pkg_c can be 1 bit, and the transmission bandwidth is 20 Mbps. The second processing module 201 is used to perform bit width conversion on the second intermediate control signal Pkg_c2 to obtain the control signal Pkg_c. The second intermediate control signal Pkg_c2 can be 130 bits. In this embodiment, the second processor module 201 sends a control signal to the second link under the action of the fourth clock signal div_clk2. The second processor module 201 is also used to perform bit width conversion and transmit the second intermediate control signal Pkg_c2 under the action of the third clock signal c2c_clk2.

[0087] In this embodiment, the processor chip 20 is connected to the radar chip 10 through a second conversion module 202 (i.e., a second SerDes module) of a communication unit 200 to form a first mainband link, and is connected to the radar chip 10 through a first processing module 201 of a communication unit 200 to form a second sideband link. This allows service data with high transmission speed requirements to be transmitted through the first mainband link, while control signals with lower transmission speed requirements are transmitted through the second sideband link. This reduces the area of ​​the second conversion module 202 of the processor chip 20, lowers power consumption, and improves energy efficiency. At the same time, the bidirectional transmission of control signals and service data also ensures the integrity of service data transmission.

[0088] In another aspect, this application provides a radar system, including the aforementioned processor chip and at least one radar chip. The processor chip includes at least one communication unit connected to the at least one radar chip in a one-to-one correspondence. A first conversion module of a radar chip is connected to a second conversion module of the corresponding communication unit to form a first link. The first conversion module of a radar chip transmits service data to the second conversion module of the corresponding communication unit through the first link. A first processing module of a radar chip is connected to the second processing module of the corresponding communication unit to form a second link. The first processing module of a radar chip receives control signals from the second processing module of the corresponding communication unit through the second link.

[0089] To facilitate a better understanding by those skilled in the art of radar technology of the radar system composed of the radar chip and processor chip provided in the above embodiments, the following will use... Figure 9 The structural diagram of the radar system shown is used for explanation.

[0090] The radar chip in this embodiment includes a processor chip 10 and at least one radar chip 20. Each radar chip 20 includes a first processing module 101 and a first conversion module 102 connected to the first processing module. The processor chip 10 includes at least one communication unit 200 connected to at least one radar chip 10 in a one-to-one correspondence. Each communication unit 200 includes a second processing module 201 and a second conversion module 202 connected to the second processing module 201. Specifically, the first conversion module 102 of one radar chip 10 is connected to the second conversion module 202 of the corresponding communication unit 200 to form a first link mainband. The first conversion module 102 of one radar chip 10 transmits service data to the second conversion module 202 of the corresponding communication unit through the first link mainband. The first processing module 101 of one radar chip 10 is connected to the second processing module 201 of the corresponding communication unit to form a second link sideband. The first processing module 101 of one radar chip 10 receives control signals from the second processing module 101 of the corresponding communication unit 200 through the second link sideband.

[0091] Specifically, the first end of the first link mainband is connected to the first TX (Transport) port of the first conversion module 102, and the second end of the first link mainband is connected to the first RX (Receive) port of the second conversion module 202; the first end of the second link sideband is connected to the second TX port of the second processing module 201, and the second end of the second link sideband is connected to the second RX port of the first processing module 101.

[0092] Specifically, the first conversion module 101 is a first SerDes module, which is used to convert parallel service data into serial service data and send the serial service data unidirectionally; the second conversion module 201 is a second SerDes module, which is used to receive serial service data unidirectionally and convert the serial service data into parallel service data.

[0093] In this embodiment, a first mainband is formed by connecting the first conversion module 102 of the radar chip 101 to the second conversion module 202 of a communication unit 200 of the processor chip 20. A second sideband is formed by connecting the first processing module 101 of the radar chip 10 to the second processing module 201 of a communication unit 200 of the processor chip 20. The radar chip 10 transmits service data to the processor chip 20 through the first mainband and receives control signals from the processor chip 20 through the second sideband. Thus, service data with high transmission speed requirements is transmitted through the first mainband, while control signals with lower transmission speed requirements are transmitted through the second sideband. The bidirectional transmission of control signals and service data also ensures the integrity of service data transmission. At the same time, the first processing module 101 of the radar chip 10 and the second processing module 201 of the processor chip 20 in this embodiment only need to provide unidirectional ports, resulting in a reduction in the area of ​​the radar chip 10 and the processor chip 20, a reduction in power consumption, and an improvement in energy efficiency.

[0094] like Figure 10 The diagram shown is a schematic representation of the specific structure of the radar system in this embodiment. The first processing module 101 of the radar chip 10 internally forms a first application layer C2C_AP1, a first transmission layer C2C_TL1, a first data link layer C2C_DLL1, and a first physical layer C2C_PL1 based on the C2C protocol. The second processing module 201 of the processor chip 20 internally forms a second transmission layer C2C_TL2, a second data link layer C2C_DLL2, and a second physical layer C2C_PL2 based on the C2C protocol. The processor chip 20 also forms a second application layer C2C_AP2 based on the C2C protocol. Multiple second processing modules 201 are connected to this second application layer C2C_AP2.

[0095] The radar chip 10 also includes a first processor Core1, a first global direct memory access module GDMA1, a first on-chip network NoC1, a first storage module Memory1, a first baseband processor BB1, and a first debugging module Debug1; the first application layer C2C_AP1 includes an interface AXI Master1, a first signal input interface AXI Stream In1, a first configuration file module Config1, and a first interconnect operation module Interconnect1; the initial service data Data is transmitted to AXI Stream In1 of the first application layer C2C_AP1 through the first storage module Memory1 and BB1. Afterwards, the initial service data Data is packaged into TLP messages through the first data link layer C2C_DLL1 and the first physical layer C2C_PL1, and sent to the processor chip 20 through the first link mainband.

[0096] Specifically, a processor chip 20 shares a cable Link with multiple radar chips 10 for the first link and the second link. The cable includes multiple Link Lanes, and each Lane is used to transmit different first link mainband and second link sideband.

[0097] The processor chip 20 also includes a second processor Core2, a second global direct memory access module GDMA2, a second on-chip network NoC2, a second storage module Memory2, a second baseband processor BB2, and a second debugging module Debug2; the second application layer C2C_AP2 includes an interface AXI Master2, a second configuration file module Config2, a second interconnect operation module Interconnect2, and a second load balancing scheduling module RR2; the initial service data Data arrives at the second application layer C2C_AP2, is transmitted to the second on-chip network NoC2 through RR2 and AXI Master2, and is stored in the second storage module Memory2.

[0098] Specifically, the control signal is generated by the second processing module 202 of the processor chip 20 and sent to the first physical layer C2C_PL1 of the first processing module 102 of the radar chip 10 through the second physical layer C2C_PL2 of the second processing module 202, thereby realizing feedback control of the business data. The specific implementation process is the same as that in the above embodiment, and will not be described again here to avoid repetition.

[0099] It should be noted that the specific structure of the radar chip in the radar system of this embodiment, the transmission of service data, and the reception of control signals are roughly the same as those in the radar chip embodiment described above. To avoid repetition, they will not be described again here. Similarly, the specific structure of the processor chip in the radar system of this embodiment, the reception of service data, and the transmission of control signals are roughly the same as those in the processor chip embodiment described above. To avoid repetition, they will not be described again here.

[0100] Another aspect of this application provides an electronic device, including: a radar chip, a processor chip, and a radar system as described in the above embodiments.

[0101] It is not difficult to see that this embodiment is a device embodiment corresponding to the radar chip, processor chip, and radar system embodiments described above, and the above embodiments can be implemented in conjunction with this embodiment. The relevant technical details mentioned in this embodiment are still valid in the above embodiments, and will not be repeated here to reduce repetition. Correspondingly, the relevant technical details mentioned in the above embodiments can also be applied to this embodiment.

[0102] It should be noted that radar chips can achieve functions such as target detection by transmitting and receiving radio signals, providing measurement information of the detected target to the main device, thereby assisting or even controlling the operation of the main device. Examples of measurement information include at least one of relative distance, relative speed, and relative angle.

[0103] In some embodiments, the device body described above can be a component or product applied in fields such as transportation, consumer electronics, monitoring, in-cabin detection, and healthcare. For example, the device body can be intelligent transportation equipment (such as automobiles, motorcycles, ships, subways, trains, etc.), security equipment (such as cameras), liquid level / flow rate detection equipment, smart wearable devices (such as wristbands, glasses, etc.), smart home devices (such as robot vacuum cleaners, door locks, televisions, air conditioners, smart lights, etc.), various communication devices (such as mobile phones, tablets, etc.), as well as devices such as barriers, intelligent traffic lights, intelligent signs, traffic cameras, and various industrial robotic arms (or robots). It can also be various instruments used to detect vital signs parameters and various devices equipped with such instruments, such as in-cabin detection in automobiles, indoor personnel monitoring, intelligent medical devices, and consumer electronic devices.

[0104] In some embodiments, when the aforementioned device body is applied to an Advanced Driving Assistance System (ADAS), the radar sensor, as an on-board sensor, can provide various functional safety guarantees for the ADAS system, such as Automatic Emergency Braking (AEB), Blind Spot Detection (BSD), Lane Changing Assist (LCA), and Rear CrossTraffic Alert (RCTA).

[0105] Furthermore, the examples mentioned in the above embodiments can be freely combined, and any combination can be understood as an embodiment. The terms "embodiment" or "example" appearing in various locations in the specification do not necessarily refer to the same embodiment, nor are they independent or alternative embodiments mutually exclusive with other embodiments. Those skilled in the art will understand that the embodiments described herein can be combined with other embodiments.

[0106] Those skilled in the art will understand that the above embodiments are specific embodiments for implementing this application, and in practical applications, various changes can be made to them in form and detail without departing from the spirit and scope of this application.

Claims

1. A radar chip, characterized in that, include: A first processing module and a first conversion module connected to the first processing module; The first conversion module is used to connect to the processor chip to form a first link; The first processing module is used to connect to the processor chip to form a second link; The first conversion module is used to obtain business data from the first processing module and transmit the business data to the processor chip through the first link; The first processing module is used to receive control signals from the processor chip via the second link.

2. The radar chip according to claim 1, characterized in that, The first processing module is further configured to perform bit-width conversion on the control signal to obtain a first intermediate control signal; the first intermediate control signal is used to provide feedback control over the transmission of the service data in the first processing module.

3. The radar chip according to claim 2, characterized in that, The radar chip also includes a first register module connected to the first processing module; The first register module is used to generate a second clock signal based on a first clock signal and preset first configuration information. The first clock signal is generated by the clock module inside the radar chip. The frequency of the second clock signal is less than the frequency of the first clock signal; The first processing module is used to receive the control signal from the second link under the action of the second clock signal; The first processor module is also configured to operate under the action of the first clock signal.

4. The radar chip according to claim 2 or 3, characterized in that, The first physical layer of the first processing module is used to receive the control signal from the processor chip through the second link, and to perform bit-width conversion on the control signal to obtain the first intermediate control signal.

5. The radar chip according to claim 4, characterized in that, The first intermediate control signal includes a retransmission control signal; the retransmission control signal indicates whether to retransmit the cached service data; wherein, the cached service data is cached by the radar chip during the transmission of the service data through the first data link layer of the first processing module; The first physical layer is also used to transmit the first intermediate control signal to the first data link layer; The first data link layer is configured to, upon receiving the retransmission control signal in the first intermediate control signal, determine whether to retransmit the cached service data based on the retransmission control signal; the first data link layer is further configured to, if it is determined that the cached service data should be retransmitted, retransmit the cached service data; the first data link layer is further configured to, if it is determined that the cached service data should not be retransmitted, release the cached service data.

6. The radar chip according to claim 5, characterized in that, The first intermediate control signal also includes a flow control signal, which represents the remaining storage space information of the second processing module; The first data link layer is also used to transmit the flow control signal in the first intermediate control signal to the first transport layer of the first processing module; The first transport layer is configured to, after receiving the flow control signal, determine whether to continue pushing the remaining service data based on the flow control signal, wherein the remaining service data is the service data that was not transmitted through the first link; the first transport layer is further configured to push the remaining service data if it is determined to continue pushing the remaining service data; the first transport layer is further configured to stop pushing the remaining service data if it is determined to stop pushing the remaining service data.

7. The radar chip according to claim 6, characterized in that, The first transport layer is further configured to obtain initial service data and corresponding packet headers from the first application layer of the first processing module, and package the initial service data and the packet headers into the service data; The first data link layer is further configured to add a sequence number and a data link layer cyclic redundancy check (LCRC) to the service data after receiving the service data from the first transport layer, and to cache the service data; The first physical layer is further configured to obtain the service data from the first data link layer, add a data header and a data trailer to the service data and indicate the boundary of the service data, and transmit the service data to the first conversion module; the first conversion module is further configured to convert the parallel service data into serial service data, and send the serial service data to the processor chip through the first link.

8. The radar chip according to any one of claims 1 to 3, 5, 6, and 7, characterized in that, The second link transmits the control signals via the GPIO protocol.

9. A processor chip, characterized in that, include: At least one second processing module and at least one second conversion module connected in a one-to-one correspondence with the at least one second processing module; One of the second processing modules and a corresponding second conversion module constitute a communication unit; One of the communication units is used to connect to a radar chip; wherein, the second conversion module of one of the communication units is connected to one of the radar chips to form a first link; The second processing module of one of the communication units is connected to one of the radar chips to form a second link; The second conversion module of one of the communication units is used to receive service data from one of the radar chips via the first link; The second processing module of one of the communication units is used to transmit control signals to one of the radar chips via the second link.

10. The processor chip according to claim 9, characterized in that, In one of the communication units, the second processing module is further configured to perform bit-width conversion on the second intermediate control signal to obtain the control signal; the second intermediate control signal is generated by the second processing module based on the service data, and the second intermediate control signal is used to provide feedback control over the transmission of the service data in the radar chip.

11. The processor chip according to claim 10, characterized in that, In one of the communication units, the processor chip further includes a second register module connected to the second processing module; The second register module is used to generate a fourth clock signal based on the third clock signal and preset second configuration information. The third clock signal is generated by the clock module inside the processor chip. The frequency of the fourth clock signal is less than the frequency of the third clock signal; The second processing module is used to send the control signal to the second link under the action of the fourth clock signal; The second processor module is also used to operate under the influence of the third clock signal.

12. The processor chip according to claim 10 or 11, characterized in that, In one of the communication units, the second physical layer of the second processing module is used to perform bit-width conversion on the second intermediate control signal to obtain the control signal.

13. The processor chip according to claim 12, characterized in that, The second control signal includes a retransmission control signal, which indicates whether to retransmit the cached service data; wherein the cached service data is cached by the radar chip during the transmission of the service data; The second physical layer is used to receive the retransmission control signal in the second intermediate control signal from the second data link layer of the second processing module; The second data link layer is used to detect the service data after receiving it, and generate a retransmission control signal indicating the release of the buffered service data if the service data is normal; the second data link layer is also used to generate a retransmission control signal indicating the retransmission of the buffered service data if the service data is abnormal.

14. The processor chip according to claim 12, characterized in that, The second intermediate control signal also includes a flow control signal; the flow control signal represents the remaining storage space information of the second processing module; The second data link layer is further configured to generate the flow control signal based on the remaining storage space information of the processor chip, and transmit the flow control signal and the retransmission control signal as the second control signal to the second physical layer.

15. The processor chip according to claim 14, characterized in that, The second conversion module is further configured to receive the serial service data through the first link and convert the serial service data into the parallel service data; The second physical layer is also used to receive the parallel service data from the second conversion module and remove the data header and data trailer from the service data; The second data link layer is further configured to perform LCRC detection on the service data after receiving the service data transmitted from the second physical layer. If the LCRC detection is normal, the sequence number and the LCRC in the service data are removed, the service data is transmitted to the second transport layer of the second processing module, and a retransmission control signal indicating the release of the buffered service data is generated. If the LCRC detection is abnormal, a retransmission control signal indicating the retransmission of the buffered service data is generated. The second transport layer is also used to perform transaction layer cyclic redundancy check (ECRC) on the service data after obtaining the service data from the second data link layer. If the ECRC check is normal, the initial service data in the service data is obtained, the initial service data is stored in the memory of the second transport layer, and the initial service data is transmitted to the second application layer of the processor chip. In the event of an ECRC check failure, the service data shall be discarded. The second application layer is used to store the initial service data in the memory of the processor chip after receiving the initial service data.

16. A radar system, characterized in that, include: Processor chip and at least one radar chip; Each radar chip includes a first processing module and a first conversion module connected to the first processing module; The processor chip includes at least one communication unit connected to at least one of the radar chips, and each communication unit includes a second processing module and a second conversion module connected to the second processing module. In this configuration, the first conversion module of one radar chip is connected to the second conversion module of the corresponding communication unit to form a first link; the first conversion module of one radar chip transmits service data to the second conversion module of the corresponding communication unit through the first link; the first processing module of one radar chip is connected to the second processing module of the corresponding communication unit to form a second link; and the first processing module of one radar chip receives the control signal from the second processing module of the corresponding communication unit through the second link.

17. The radar system according to claim 16, characterized in that, The first end of the first link is connected to the first transmit TX port of the first conversion module, and the second end of the first link is connected to the first receive RX port of the second conversion module. The first end of the second link is connected to the second transmit TX port of the second processing module, and the second end of the second link is connected to the second receive RX port of the first processing module.

18. The radar system according to claim 17, characterized in that, The first conversion module is a first SerDes module, which is used to convert the parallel service data into serial service data and send the serial service data unidirectionally; the second conversion module is a second SerDes module, which is used to receive the serial service data unidirectionally and convert the serial service data into parallel service data.

19. The radar system according to any one of claims 16-18, characterized in that, The first link and the second link between one of the processor chips and multiple radar chips share a single cable.

20. An electronic device, characterized in that, include: The radar chip as described in any one of claims 1-8, or the processor chip as described in any one of claims 9-15, or the radar system as described in any one of claims 16-19.

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