Silicon photonic interconnect integrated on-chip avionics edge intelligent actuation control device

Abstract

This invention provides an on-chip integrated intelligent actuation control device for aircraft based on a software-defined and hardware-accelerated collaborative paradigm using silicon photonic interconnects, belonging to the field of avionics and flight control technology. The device uses software-defined methods for functional configuration and reconfiguration, while hardware acceleration ensures link determinism and performance. Its core features include: achieving highly interference-resistant signal sensing and isolated transmission through a software-configurable silicon photonic interconnect intelligent interface; integrating a reconfigurable sensor computation and a hard real-time control law engine through a heterogeneous computing acceleration center, providing deterministic and high-performance sensor computation and control law execution; achieving efficient and safe energy conversion through a software-defined intelligent power drive module; and performing global collaborative configuration and online optimization of the above modules through an edge intelligent management unit. This invention resolves the contradiction between task adaptability, extreme real-time performance, and operational reliability in actuation control, and is applicable to distributed intelligent actuation systems for multi-electric / all-electric and hypersonic aircraft.

Description

Technical Field

[0001] This invention relates to the field of avionics and flight control technology, specifically to a distributed actuation control device for next-generation high-performance aircraft. More specifically, this invention relates to a silicon photonic interconnect-based on-chip intelligent actuation control device for aircraft edges, which provides top-level flexibility and intelligence through software definition, ensures ultimate performance, determinism, and reliability at the bottom level through hardware acceleration, and deeply integrates three enabling technologies: silicon photonic interconnect transmission, heterogeneous on-chip computing, and intelligent power drive. Background Technology

[0002] As aircraft evolve towards greater electrification, hypersonic speed, and intelligence, their flight control and actuation systems face unprecedented performance challenges and paradigm shifts. On the one hand, complex and ever-changing flight missions (such as efficient cruise, rapid maneuvering, and stealth penetration) require actuation systems to dynamically adjust their control bandwidth, accuracy modes, and robustness strategies. Traditional architectures based on fixed-function hardware or limited programmable processors are ill-suited to this due to insufficient flexibility and interconnectivity. On the other hand, to meet requirements such as flutter suppression and precise tracking, control loops must achieve microsecond-level deterministic latency and extremely high signal fidelity. This places stringent demands on the system's real-time computing power, anti-interference signal chain, and high-density power processing capabilities.

[0003] Existing technologies suffer from the following main contradictions: Solutions based on general-purpose microprocessors or digital signal processors, limited by serial computing architectures, struggle to meet microsecond-level hard real-time requirements under complex algorithms, and the flexibility of software-defined systems often comes at the cost of determinism and performance. While solutions using application-specific integrated circuits (ASICs) can achieve high performance, their functions are fixed and cannot respond to task changes and algorithm iterations. At the signal transmission level, traditional analog cables are susceptible to interference from strong airborne electromagnetic environments, becoming a bottleneck for system reliability. At the power drive level, fixed topologies and protection mechanisms struggle to achieve an optimal dynamic balance between efficiency, safety, and adaptability to various operating conditions.

[0004] Therefore, the industry urgently needs an innovative system architecture that can fundamentally unify the "flexibility" and "rigidity" of a system. Based on flexibility, it can be reconfigurable, adaptive, and intelligent; based on rigidity, it can have high performance, high reliability, and determinism, thereby providing aircraft with an actuation control solution that combines excellent mission adaptability with extreme performance indicators. Summary of the Invention

[0005] In view of the above problems, this application provides a silicon photonic interconnect-based on-chip intelligent actuation control device for aircraft edge based on software definition and hardware acceleration, so as to solve the technical problem that the flexibility and reliability of the prior art cannot be balanced.

[0006] According to the first aspect of this application, a silicon photonic interconnect-based on-chip integrated intelligent actuation control device for aircraft edge is provided, based on software definition and hardware acceleration. The device includes: a software-configurable silicon photonic interconnect intelligent interface for connecting external sensors. The sensor's excitation signal generation, analog front-end conditioning parameters, and optical interconnect transmission protocol are dynamically defined and configured through software instructions of the silicon photonic interconnect intelligent interface to achieve high-fidelity, interference-resistant conversion, and electrically isolated transmission from analog sensing signals to the digital domain; a heterogeneous computing acceleration center, with a heterogeneous on-chip system composed of an integrated processor system and a programmable logic unit as its core. The programmable logic unit contains a reconfigurable hardware acceleration resource pool, which includes a sensing signal processing acceleration engine and a hard real-time control law acceleration engine; the engine... The components are directly connected via an on-chip high-speed streaming interconnect bus, forming a deterministic data processing path free from processor intervention. The software-defined intelligent power drive module uses wide-bandgap semiconductor power devices to receive and execute instructions from the hard real-time control law acceleration engine to drive external actuators. The power conversion topology, drive timing, and multi-level hardware protection logic of the intelligent power drive module can all be defined and reconfigured online via software. The edge intelligent management unit runs on the processor system of the heterogeneous computing acceleration center. It is used to dynamically configure and coordinate the working modes, algorithm kernels, and performance parameters of the silicon photonics interconnect intelligent interface, the heterogeneous computing acceleration center, and the intelligent power drive module according to the flight mission and system status, so as to achieve software-defined optimization and adaptive operation of the entire system.

[0007] According to embodiments of this application, the software-configurable silicon photonic interconnect smart interface includes: a parameter-programmable direct digital frequency synthesis excitation generator, a differential analog front-end with configurable gain and filter characteristics, an analog-to-digital converter, and a silicon photonic interconnect isolation bridge with a defined transmission protocol; the silicon photonic interconnect isolation bridge supports software configuration and dynamic adaptation of optical modulation format, encoding method and transmission rate to adapt to different sensor types and electromagnetic environment requirements.

[0008] According to embodiments of this application, the sensor signal processing acceleration engine supports loading dedicated hardware acceleration intellectual property cores for different sensors via software. The digital filter link coefficients, nonlinear dynamic inverse model compensation lookup tables, and temperature drift correction models integrated within the dedicated hardware intellectual property cores can all be updated online via the software interface to achieve high-precision, deterministic signal processing.

[0009] According to embodiments of this application, the hard real-time control law acceleration engine loads dedicated hardware acceleration intellectual property cores for different cascaded pipeline hardware architectures through software, combines and cascades different basic control algorithm modules and loads them into dedicated hardware acceleration circuits; its control algorithm structure and parameters can be dynamically switched or merged through software configuration to achieve hard real-time execution of multiple control strategies, including at least one of dynamic inverse, incremental dynamic inverse, sliding mode control, and optimal adjustment.

[0010] According to an embodiment of this application, the intelligent power drive module includes a digitally programmable isolation driver, a wide-bandgap semiconductor power bridge with multiple topologies configurable, and a fast hardware protection circuit with software-configurable thresholds. The circuit topology of the wide-bandgap semiconductor power bridge can be configured in software according to efficiency and output ripple requirements. The fast hardware protection circuit has a multi-mode response strategy, which can be defined in software to perform shutdown, adaptive current limiting, or frequency reduction operations in the event of a fault.

[0011] According to embodiments of this application, the edge intelligent management unit diagnoses the system health status and predicts fault trends by analyzing sensor data, control error spectrum, drive current characteristics and module temperature in real time, so as to adjust hardware acceleration engine parameters online, reconstruct power drive protection strategy or trigger system degradation mode switching, thereby realizing the transformation from passive fault tolerance to active prediction and adaptation.

[0012] The second aspect of this application provides a software-defined and hardware-accelerated aircraft actuation control method, implemented based on the aforementioned device. The method includes: receiving and parsing task instructions through an edge intelligent management unit to generate a global system configuration strategy; dynamically configuring the transmission protocol and parameters of the silicon photonic interconnect intelligent interface through software according to the global system configuration strategy, and loading the corresponding sensor signal computation acceleration engine; compiling the control algorithm required for the task into a dedicated hardware acceleration intellectual property core based on the sensor signal computation acceleration engine, and loading it into the reconfigurable pipeline of the hard real-time control law acceleration engine; configuring the topology and protection strategy of the software-defined intelligent power drive module; enabling the system to operate within a software-defined framework, with sensor signals transmitted via an adapted optical interface, and processed in parallel pipelines by the loaded sensor signal computation acceleration engine and hard real-time control law acceleration engine to generate drive instructions, which are then executed by the intelligent power module, forming a high-precision, high-determinism, and high-reliability closed-loop control; and having the edge intelligent management unit continuously monitor the system status, and optimize the configuration of each module of the silicon photonic interconnect intelligent interface, heterogeneous computing acceleration center, and intelligent power drive module online based on real-time feedback to achieve adaptive, high-performance actuation control.

[0013] The above-described one or more embodiments achieve global flexible configuration, dynamic management, and intelligent optimization of the three core functions of system transmission, computing, and driving through software definition; transform high-level software-defined strategies into ultimate performance and reliability executed by dedicated circuits with deterministic time constraints through hardware acceleration; and fully realize this advanced concept at the physical level by relying on three hardware enabling technologies: silicon photonics interconnect, heterogeneous computing, and intelligent power drive. Based on the software-configurable silicon photonics interconnect intelligent interface, silicon photonics interconnect provides ultimate anti-interference protection for the software-defined signal chain; the heterogeneous computing acceleration center provides ultimate performance support for the software-defined algorithm chain; and the intelligent power drive module provides precise and safe execution for the software-defined energy chain. The three core technologies of silicon photonics interconnect, heterogeneous computing acceleration, and intelligent power drive are integrated at the cutting-edge hardware level, jointly supporting the physical realization of the software-defined architecture and hardware-accelerated execution. Thanks to the deep integration of silicon photonics interconnect, heterogeneous computing, and intelligent power drive on the same on-chip system, extremely low-latency communication and collaborative optimization between sensing, computing, and driving links are achieved, resulting in size, weight, power consumption, and reliability advantages that discrete systems cannot match. Thus, the contradiction between unified performance and flexibility is resolved: software-defined solutions meet the rapid reconfiguration needs of multiple tasks and scenarios, while hardware acceleration meets extreme performance targets, balancing both flexibility and rigidity requirements; a high degree of edge intelligent autonomy is achieved: intelligent management, decision-making, and optimization capabilities are pushed down to the actuators, enabling autonomous adjustment of control strategies based on real-time local information, significantly improving system response agility, resilience, and overall efficiency; an open and evolvable hardware platform is constructed: hardware acceleration intellectual property cores can be developed, upgraded, loaded, and reconfigured like software components, allowing device functions to continuously evolve with task requirements and technological developments, significantly reducing lifecycle costs and upgrade difficulty; and cross-level global optimization capabilities are provided: the edge intelligent management unit can take a system-wide perspective and collaboratively optimize the entire chain from signal perception and data processing to energy conversion, breaking through the comprehensive potential and performance breakthroughs that traditional isolated module designs cannot achieve. Attached Figure Description

[0014] The above-mentioned contents, other objects, features and advantages of this application will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:

[0015] Figure 1 This illustration schematically shows a module diagram of an on-chip integrated intelligent actuation control device for aircraft based on software-defined and hardware-accelerated silicon photonic interconnect according to an embodiment of this application;

[0016] Figure 2 This schematically illustrates the overall architecture of a silicon photonic interconnect-integrated on-chip intelligent actuation control device for aircraft based on software definition and hardware acceleration, according to an embodiment of this application.

[0017] Figure 3 This illustration schematically shows a closed-loop decision-making diagram of the edge intelligent management unit realizing dynamic configuration and optimization of the entire system according to an embodiment of this application;

[0018] Figure 4 This illustration schematically shows the modular structure and configuration data flow diagram of a software-configurable silicon photonic interconnect smart interface according to an embodiment of this application;

[0019] Figure 5 This illustration schematically shows the architecture and intellectual property core loading diagram of the reconfigurable hardware acceleration engine of the heterogeneous computing acceleration center according to an embodiment of this application;

[0020] Figure 6 This illustration schematically shows an example of a reconfigurable pipeline of a hard real-time control law acceleration engine according to an embodiment of this application, and a schematic diagram of its algorithm core dynamic switching.

[0021] Figure 7 This illustration schematically shows a multi-topology configuration and adaptive protection strategy logic diagram of a software-defined intelligent power drive module according to an embodiment of this application;

[0022] Figure 8 This illustration schematically shows an online optimization and health management diagram of the edge intelligent management unit according to an embodiment of this application;

[0023] Figure 9 The flowchart illustrates a software-defined and hardware-accelerated silicon photonic interconnect-based on-chip integrated intelligent actuation control method for aircraft edges according to an embodiment of this application. Detailed Implementation

[0024] The embodiments of this application will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of this application. In the following detailed description, numerous specific details are set forth to provide a thorough understanding of the embodiments of this application for ease of explanation. However, it will be apparent that one or more embodiments may be implemented without these specific details. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of this application.

[0025] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. The terms “comprising,” “including,” etc., as used herein indicate the presence of the stated features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0026] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein are to be interpreted in a manner consistent with the context of this specification, and not in an idealized or overly rigid way.

[0027] When using expressions such as "at least one of A, B and C", they should generally be interpreted in accordance with the meaning that is commonly understood by those skilled in the art (e.g., "a system having at least one of A, B and C" should include, but is not limited to, a system having A alone, a system having B alone, a system having C alone, a system having A and B, a system having A and C, a system having B and C, and / or a system having A, B and C, etc.).

[0028] To address the aforementioned technical problems, embodiments of this application provide a silicon photonic interconnect-based on-chip intelligent actuation control device for aircraft edges, based on software-defined and hardware-accelerated technologies. The following will combine... Figures 1-7 The device is described in detail.

[0029] Figure 1 The illustration shows a schematic diagram of a module of an on-chip integrated intelligent actuation control device 100 for aircraft based on software-defined and hardware-accelerated silicon photonic interconnect according to an embodiment of this application.

[0030] exist Figure 1In the illustrated embodiment, the device 100 includes: a software-configurable silicon photonic interconnect smart interface 110 for connecting external sensors. The sensor's excitation signal generation, analog front-end conditioning parameters, and optical interconnect transmission protocol are dynamically defined and configured through software instructions of the silicon photonic interconnect smart interface to achieve high-fidelity, interference-resistant conversion, and electrically isolated transmission from analog sensing signals to the digital domain; and a heterogeneous computing acceleration center 120, centered on a heterogeneous system-on-a-chip composed of an integrated processor system and programmable logic units. The programmable logic units contain a reconfigurable hardware acceleration resource pool, which includes a sensing signal processing acceleration engine and a hard real-time control law acceleration engine. The engines are directly connected via an on-chip high-speed streaming interconnect bus, forming a... A deterministic data processing path free from processor intervention is provided; the software-defined intelligent power drive module 130, employing wide-bandgap semiconductor power devices, is used to receive and execute instructions from the hard real-time control law acceleration engine to drive external actuators. The power conversion topology, drive timing, and multi-level hardware protection logic of the intelligent power drive module can all be defined and reconfigured online via software; the edge intelligent management unit 140, running on the processor system of the heterogeneous computing acceleration center, is used to dynamically configure and collaboratively manage the working modes, algorithm kernels, and performance parameters of the silicon photonic interconnect intelligent interface 110, the heterogeneous computing acceleration center 120, and the intelligent power drive module 130 according to the flight mission and system status, so as to achieve software-defined optimization and adaptive operation of the entire system.

[0031] In this embodiment, a silicon photonic interconnect-integrated on-chip intelligent actuation control device for aircraft edge is realized based on a software-defined and hardware-accelerated collaborative paradigm. The device includes four core modules: a software-configurable silicon photonic interconnect intelligent interface, a heterogeneous computing acceleration center, a software-defined intelligent power drive module, and an edge intelligent management unit. The overall architecture is divided into a software-defined architecture layer and a hardware-accelerated execution layer, which is suitable for multi-electric / all-electric aircraft, hypersonic aircraft, and distributed intelligent actuation system applications. The modules collaborate through an on-chip high-speed interconnect bus to achieve closed-loop collaboration between software-defined deployment and hardware-accelerated execution of flight mission commands.

[0032] Figure 2 The illustration shows a schematic diagram of the overall architecture of an on-chip integrated intelligent actuation control device for aircraft based on software-defined and hardware-accelerated silicon photonic interconnect according to an embodiment of this application.

[0033] Specifically, such as Figure 2As shown, the software-configurable silicon photonic interconnect smart interface 110 is a software-configurable silicon photonic interconnect smart interface. Its specific settings are as follows: One end connects to sensors, such as LVDT / NVDT, RVDT, strain gauges and other types of sensors, to complete three core configurations: software definition of excitation signal, software optimization of analog front-end, and software adaptation of optical transmission protocol. Through software instructions, the waveform, frequency and amplitude of the sensor excitation signal are dynamically defined, the gain, filtering characteristics and common mode rejection ratio of the analog front-end are adjusted, and the optical modulation format, transmission rate and encoding protocol of the silicon photonic interconnect isolation bridge are set to achieve high-fidelity, anti-interference conversion and electrical isolation transmission of analog sensing signals to the digital domain, providing a clean digital signal for the back-end hardware acceleration layer.

[0034] Heterogeneous Computing Acceleration Center 120: As the core of the hardware acceleration execution layer, it is based on a heterogeneous system-on-a-chip integrating a multi-core processor system and a programmable logic unit. The programmable logic unit builds a dynamically reconfigurable hardware acceleration resource pool, solidifies the sensor signal processing acceleration engine and the hard real-time control law acceleration engine. The two engines are directly connected by on-chip high-speed streaming interconnect bus, forming a deterministic data processing path free from processor intervention. The sensor signal processing acceleration engine achieves a sensor processing latency of ≤10μs, and the hard real-time control law acceleration engine achieves a control law execution latency of ≤1μs, with a data bandwidth of ≥10Gbps, completing the hard real-time processing from sensor digital signals to actuation control commands.

[0035] The software-defined intelligent power drive module 130 receives control commands from the hard real-time control law acceleration engine, drives external actuators, and completes three major functions: power topology software reconfiguration, impedance characteristic software definition, and intelligent protection strategy reconfiguration. It adopts silicon carbide / gallium nitride wide bandgap semiconductor power devices, supports software switching of power topologies such as H-bridge and three-level, can define the stiffness and damping characteristics of the output impedance, and configure the threshold and fault response strategy of the fast hardware protection circuit to achieve efficient, safe, and reconfigurable energy conversion. The switching frequency is ≤500kHz, the efficiency is ≥98%, and the output accuracy is ≤0.1%.

[0036] Figure 3 This illustration shows a closed-loop decision-making diagram of the edge intelligent management unit realizing dynamic configuration and optimization of the entire system according to an embodiment of this application.

[0037] like Figure 2 , Figure 3As shown, the edge intelligent management unit 140 serves as the decision-making hub of the software-defined architecture layer. Running on the processor system of the heterogeneous computing acceleration center, it does not intervene in the hard real-time control loop. It obtains system-wide operational data through the status feedback of the software-defined intelligent power drive module, and executes a closed-loop decision-making cycle of perception, evaluation, decision-making, and execution based on flight mission instructions, with a decision cycle ≤1ms. It completes global task analysis, system status perception, and resource configuration optimization. Through software dynamic configuration and collaborative management of the working modes, algorithm kernels, performance parameters, and collaborative relationships of the silicon photonics interconnect intelligent interface, heterogeneous computing acceleration center, and software-defined intelligent power drive module, it achieves software-defined optimization and adaptive operation of the entire system. Simultaneously, it performs online optimization, module refactoring, predictive maintenance, and adaptive fault tolerance functions.

[0038] The above four modules form a collaborative paradigm of software-defined and hardware-accelerated systems: software-defined systems provide system-level intelligence, flexibility, and adaptability; hardware acceleration provides circuit-level speed, determinism, and efficiency; and three hardware enabling technologies—silicon photonic interconnect, heterogeneous computing, and intelligent power drive—provide the physical realization of this paradigm. Silicon photonic interconnect provides ultimate anti-interference protection for the signal chain of software-defined systems, heterogeneous computing provides ultimate performance support for the algorithm chain of software-defined systems, and intelligent power drive provides precise and safe execution for the energy chain of software-defined systems.

[0039] In a more specific example, regarding the configuration of this silicon photonic interconnect smart interface: the management unit, i.e., the edge smart management unit, identifies the current sensor as a high-precision LVDT / NVDT and issues a configuration command: setting the direct digital frequency synthesizer to generate low harmonic distortion at a frequency of... The sinusoidal excitation is used; the analog front end is configured with high gain and narrowband filtering mode to improve the signal-to-noise ratio; and the silicon photonic interconnect isolation bridge is set to use intensity modulation and non-return-to-zero coding to optimize power consumption and transmission reliability.

[0040] For the heterogeneous computing acceleration center, a heterogeneous computing acceleration core is loaded: the management unit selects and loads a high-precision LVDT / NVDT solution core from non-volatile memory into the sensor signal solution acceleration engine. This core embeds a complex vector zero-point compensation algorithm and a high-order piecewise linearized lookup table for specific sensors. Simultaneously, to meet the stability and efficiency requirements of the "cruise mode," a "linear quadratic optimal regulator core" is loaded into the hard real-time control law acceleration engine. This core, after hardware synthesis, has been transformed into a highly efficient pipelined circuit structure.

[0041] For the software-defined intelligent power drive module, a power drive strategy is set, and the management unit configures the power drive module as a high-efficiency synchronous rectification H-bridge topology to reduce conduction losses. The software protection threshold is set to a more lenient level, and the response mode is set to hierarchical current limiting to prioritize continuous and smooth output rather than frequent shutdown.

[0042] Based on this, the configuration process is completed quickly, and the system immediately enters hardware-accelerated operation mode. Dedicated circuitry ensures high-performance and deterministic execution of the sensing, computing, and driving links. Specifically, sensor signals are transmitted losslessly through an optimized optical interface; the loaded hardware acceleration core runs at full speed in a parallel pipeline manner; the power module efficiently and smoothly drives the load; software-defined high-level deployment is completed, and hardware acceleration ensures efficient and deterministic execution at lower levels.

[0043] Thus, the following technical problems are addressed: Traditional aircraft actuation control architectures are divided into fixed-function hardware or limited programmable processor architectures, which cannot balance flexibility and rigidity. The flexibility of software-defined systems often comes at the cost of determinism and performance, while the high performance of application-specific integrated circuits is accompanied by the problem of functional rigidity, making them unsuitable for the complex and variable flight missions of multi-electrified and hypersonic aircraft; Signal transmission relies on traditional analog cables, which are susceptible to interference from the strong electromagnetic environment on board, becoming a bottleneck for system reliability and unable to provide high-fidelity signals for the control loop; The topology and protection mechanisms of power drive modules are fixed, making it difficult to achieve a dynamic balance between efficiency, safety, and multi-condition adaptability, and unable to match the actuation requirements of different flight phases; Each control module is designed in isolation, lacking a globally coordinated intelligent management unit, and unable to achieve end-to-end optimization from signal perception, data processing to energy conversion, thus limiting the overall performance of the system; Discrete systems have high communication latency between sensing, computing, and drive links, and poor performance in terms of size, weight, and power consumption, failing to meet the integration requirements of distributed intelligent actuation systems.

[0044] This yields the following beneficial effects: It establishes a closed-loop collaborative paradigm of software-defined architecture and hardware-accelerated execution, fundamentally unifying the system's flexibility and rigidity. Software-defined architecture meets the rapid reconfiguration requirements of multiple tasks and scenarios, while hardware acceleration ensures extreme performance indicators at the microsecond or even nanosecond level, balancing task adaptability and real-time performance. It deeply integrates three major hardware enabling technologies: silicon photonics interconnect, heterogeneous computing, and intelligent power drive, achieving on-chip integration of sensing, computing, and drive links, gaining advantages in size, weight, power consumption, and reliability that discrete systems cannot match. It achieves highly autonomous edge intelligence, integrating intelligent management, decision-making, and optimization capabilities. By sinking down to the actuator, the control strategy can be autonomously adjusted based on real-time local information, reducing the central computing load and significantly improving the system's response agility, resilience, and overall performance. The edge intelligent management unit provides cross-level global optimization capabilities, coordinating the optimization of the complete link of the signal chain, algorithm chain, and energy chain from a system-wide perspective, breaking through the comprehensive potential and performance breakthroughs that traditional isolated module designs cannot achieve. It is adapted to the actuation control requirements of next-generation high-performance aircraft such as multi-electric / all-electric aircraft, hypersonic aircraft, and distributed intelligent actuation systems, providing an innovative system architecture solution for the fields of avionics and flight control technology.

[0045] In this embodiment, the software-configurable silicon photonic interconnect smart interface 110 includes: a parameter-programmable direct digital frequency synthesis excitation generator, a differential analog front-end with configurable gain and filter characteristics, an analog-to-digital converter, and a silicon photonic interconnect isolation bridge with a defined transmission protocol; the silicon photonic interconnect isolation bridge supports software configuration and dynamic adaptation of optical modulation format, encoding method and transmission rate to adapt to different sensor types and electromagnetic environment requirements.

[0046] Figure 4 The illustration schematically shows the modular structure and configuration data flow diagram of a software-configurable silicon photonic interconnect smart interface according to an embodiment of this application.

[0047] exist Figure 4 In the example shown, the software-configurable silicon photonic interconnect smart interface is the first key component of the hardware-accelerated execution layer. Its core is to extend the software-defined flexibility to the physical layer. The overall system comprises four modular components: a parameter-programmable direct digital frequency synthesis excitation generator, a differential analog front-end with configurable gain and filter characteristics, an analog-to-digital converter, and a silicon photonic interconnect isolation bridge with a definable transmission protocol. The configuration data flow follows the logic of "excitation generation, analog conditioning, analog-to-digital conversion, and optical interconnect transmission," adapting to different sensor types and complex electromagnetic environments. The specific configuration process is as follows:

[0048] For a programmable direct digital frequency synthesis excitation generator, also known as a programmable DDS excitation generator, the edge intelligent management unit sends commands to the generator via a configuration bus according to the type of connected sensor, such as LVDT / NVDT, RVDT, strain gauge, etc., to dynamically set the frequency, amplitude, and waveform of the excitation signal to match the specific resonant frequency and sensitivity requirements of the sensor, thereby optimizing the signal-to-noise ratio from the source. For example, for high-precision LVDT / NVDT sensors, it generates a sinusoidal excitation signal with low harmonic distortion. The frequency of this generator can be programmable from 1Hz to 10MHz, the waveform can be selected as sine or square wave, the amplitude is dynamically adjustable, and the phase can be precisely controlled.

[0049] The differential analog front-end with configurable gain and filter characteristics can be configured online by the edge intelligent management unit based on the current electromagnetic environment assessment results and signal-to-noise ratio requirements. This amplifies and filters the analog signal output by the sensor, suppressing electromagnetic interference at the source and improving signal quality. For example, in a strong electromagnetic interference environment, the gain and common-mode rejection ratio can be increased, and a narrowband filtering mode can be configured. The gain of this configurable differential analog front-end is adjustable from 1 to 1000 times, the bandwidth is software-configurable, the common-mode rejection ratio is greater than or equal to 100 dB, and the filtering characteristics are programmable.

[0050] Analog-to-digital converter: Converts the analog sensing signal conditioned by the differential analog front end into a digital signal, completing the conversion from analog domain to digital domain, and providing digital signal input for the silicon photonics interconnect isolation bridge;

[0051] A silicon photonic interconnect isolation bridge with a definable transmission protocol: As the core anti-interference component of the interface, its optical modulation format, encoding method, and transmission rate can all be dynamically configured and adapted through software commands. For example, in high-intensity electromagnetic interference environments, it automatically switches to an anti-interference coding mode and increases optical transmission power, employing formats such as intensity modulation, non-return-to-zero coding, or phase modulation to adjust the transmission rate to balance power consumption and reliability, ensuring reliable electrically isolated transmission in harsh airborne environments. This silicon photonic interconnect isolation bridge provides an optical transmission sensitivity of less than or equal to -20 dBm, a bandwidth greater than 10 GHz, and a bit error rate of less than or equal to 10^6 dBm for silicon photonic interconnect isolated transmission silicon photonic transmitter modules. -12 The dynamic range is 40dB. The silicon photonics emission module associated with this silicon photonics interconnect isolation bridge has a wavelength of 1310 / 1550nm, a configurable modulation format, a data rate of 1-10Gbps, and an isolation voltage of ≥3000V. The digital interface module associated with this silicon photonics interconnect isolation bridge includes digital output interfaces, high-speed serial interfaces, and parallel buses. The high-precision ADC involved has a resolution of 16-24 bits, a sampling rate of 10MSPS, an SNR of ≥100dB, and a linearity of 0.001%.

[0052] Through the software collaborative configuration of the above four components, a single hardware interface platform can dynamically reconstruct its signal sensing and transmission characteristics, enabling adaptation to various sensors such as LVDT / NVDT, RVDT, and strain gauges. At the same time, it can optimize the transmission strategy in real time according to the airborne electromagnetic environment, providing a clean and reliable digital signal source for the back-end heterogeneous computing acceleration center, and completing the modular structure and configuration data flow of the software-configurable silicon photonic interconnect intelligent interface.

[0053] Based on this, the technical problem of traditional sensor interfaces being fixed hardware configurations with no software configurability, one interface only adapting to one type of sensor, resulting in poor hardware versatility and inability to meet the multi-sensor adaptation requirements of distributed intelligent actuation systems is addressed. The solution achieves software configurability of the sensor interface physical layer, integrating three major configuration functions—excitation signal software definition, analog front-end software optimization, and optical transmission protocol software adaptation—into a single hardware interface. This allows for dynamic reconfiguration to adapt to multiple sensors, significantly improving hardware versatility and reducing system hardware costs. Furthermore, the parameters of the direct digital frequency synthesis excitation generator are programmable, enabling precise matching of the operating characteristics of different sensors, optimizing the signal-to-noise ratio from the source, and improving sensor signal-to-noise ratio. The original quality of the signal; the software optimization capability of the differential analog front end, which can adjust the conditioning parameters in real time according to the electromagnetic environment, actively suppress interference, and ensure signal fidelity, providing high-quality analog signals for analog-to-digital conversion; the transmission protocol software adaptation capability of the silicon photonics interconnect isolation bridge, which provides ultimate anti-interference guarantee for the signal chain, can achieve reliable electrical isolation transmission in complex airborne electromagnetic environments, solving the interference bottleneck of traditional analog cables; the construction of a standardized modular structure and configuration data flow, realizing the collaborative software configuration of various interface components, fast reconfiguration response speed, and improving the high adaptability of the interface to sensor types and electromagnetic environments, laying a high-quality signal foundation for back-end hardware acceleration processing.

[0054] In this embodiment, the sensor signal processing acceleration engine supports loading dedicated hardware acceleration intellectual property cores for different sensors through software. The digital filter link coefficients, nonlinear dynamic inverse model compensation lookup tables, and temperature drift correction models integrated within the dedicated hardware intellectual property cores can all be updated online through the software interface to achieve high-precision, deterministic signal processing.

[0055] Figure 5 The illustration shows the architecture and intellectual property core loading diagram of the reconfigurable hardware acceleration engine of the heterogeneous computing acceleration center according to an embodiment of this application.

[0056] exist Figure 5 In the example shown, the reconfigurable hardware acceleration engine in the hardware acceleration resource pool includes a sensor signal processing acceleration engine and a hard real-time control law acceleration engine. The hardware acceleration and dynamic reconfiguration of the sensor signal processing acceleration engine in the heterogeneous computing acceleration center is implemented. This engine is one of the core components of the hardware acceleration resource pool. Its core function is to perform high-precision, deterministic processing of digital signals transmitted through the silicon photonics interconnect smart interface, with a sensor processing latency ≤10μs. It supports loading dedicated hardware acceleration intellectual property cores (IP cores) for different sensors via software, and the internal parameters of the IP cores can be updated online through a software interface. The specific implementation process is as follows:

[0057] Hardware acceleration resource pool and IP core loading: The programmable logic area of ​​the heterogeneous computing acceleration center is a dynamically reconfigurable hardware acceleration resource pool. The edge intelligent management unit selects a dedicated hardware acceleration IP core that matches the current sensor from the IP core library through software-defined loading and loads it into the sensor signal calculation acceleration engine. For example, a high-precision calculation IP core is loaded for LVDT / NVDT sensors, and a strain signal calculation IP core is loaded for strain gauges. The reconstruction time is ≤1ms.

[0058] Online software updates for internal IP core parameters: The loaded dedicated hardware-accelerated IP core integrates three core configurable parameters: digital filter link coefficients, nonlinear dynamic inverse model compensation lookup table, and temperature drift correction model. All of these parameters can be updated online via the software interface.

[0059] Digital filter link coefficients: Configure the coefficients of the Finite Impulse Response (FIR) filter, adjust the filter bandwidth and filter characteristics, and adapt to the signal and noise characteristics of different sensors;

[0060] Nonlinear dynamic inverse model compensation lookup table: constructed based on piecewise polynomial fitting data calibrated by laser interferometer, and updated online to match the nonlinear characteristics of the sensor and eliminate the inherent nonlinear error of the sensor;

[0061] Temperature drift correction model: Load a gain coefficient based on temperature feedback and update it online to compensate for the impact of ambient temperature changes on the sensor and suppress temperature drift;

[0062] Deterministic microsecond-level signal processing: The sensor signal processing acceleration engine receives digital sequences from the silicon photonics interconnect smart interface. After loading the IP core, the hardware resources are reconfigured into a dedicated data processing path, sequentially performing operations such as feedforward synchronous demodulation, digital mixing and filtering, complex plane vector zero compensation, and nonlinear compensation. The entire processing is completed within a fixed microsecond-level clock cycle: a direct digital frequency synthesis module generates an orthogonal reference signal with the same frequency as the excitation, completing feedforward synchronous demodulation; digital mixing and low-pass filtering are performed through a configurable coefficient finite-length impulse response filter; complex plane vector zero compensation is performed to eliminate the residual voltage of the sensor; the nonlinear compensation lookup table of piecewise polynomial fitting is consulted, and combined with the gain coefficient of the temperature drift correction model, the final sensor physical quantities (displacement, strain, etc.) are obtained.

[0063] By loading IP cores and updating parameters online through the aforementioned software, the sensor signal processing acceleration engine achieves high-precision, deterministic microsecond-level processing of signals from different sensors, providing accurate sensor data input for the hard real-time control law acceleration engine.

[0064] In a more concrete example, the programmable logic region of a heterogeneous computing acceleration center is a dynamically reconfigurable pool of hardware resources. The sensor signal processing acceleration engine receives digital sequences from the silicon photonics interface. After loading the high-precision solution IP core, the hardware resources are reconfigured for dedicated data processing paths, filtering, compensation, and other operations, all completed within a fixed microsecond clock cycle. This path performs feedforward synchronous demodulation, first generating an orthogonal reference signal with the same frequency as the excitation by the direct digital frequency synthesis module:

[0065] ;

[0066] in The sampling period is [number]. Digital mixing and filtering are then performed.

[0067] ;

[0068] Here, FILTER represents a low-pass filter implemented using a configurable coefficient finite-length impulse response filter. Subsequently, complex plane vector zero compensation is performed to eliminate residual voltage.

[0069] ;

[0070] The final displacement is obtained by querying the nonlinear compensation generated by piecewise polynomial fitting:

[0071] ;

[0072] in This represents the gain coefficient based on temperature feedback. The entire calculation process is completed within a fixed clock cycle, with a delay of [missing information]. This enables deterministic microsecond-level signal processing.

[0073] Based on this, a software loading approach using hardware-accelerated IP cores is adopted to achieve dynamic reconfiguration of the sensor signal processing engine. This allows for compatibility with various sensors such as LVDT / NVDT, RVDT, and strain gauges, enhancing the reconfigurability and scalability of the hardware and constructing an open and evolvable hardware platform. The digital filter link coefficients, nonlinear dynamic inverse model compensation lookup table, and temperature drift correction model within the IP cores support online software updates, enabling real-time compensation for non-ideal errors such as sensor nonlinearity and temperature drift, achieving high-precision signal processing and improving the accuracy of the results. The dedicated hardware-accelerated IP cores construct a fixed processing hardware path, completing the entire processing within microsecond-level clock cycles, with a sensor processing latency ≤10μs, achieving deterministic microsecond-level signal processing and meeting the latency requirements of hard real-time control. The design of the hardware acceleration resource pool and IP core library enables the hardware-accelerated IP cores to achieve... The core can be developed, upgraded, loaded, and refactored like a software component, reducing the system's total lifecycle cost and upgrade difficulty; the sensor signal processing acceleration engine and the hard real-time control law acceleration engine are directly connected by on-chip high-speed streaming interconnect bus, forming a direct path without software intervention, reducing data transmission latency and improving the processing efficiency of the entire heterogeneous computing acceleration center.

[0074] In this embodiment, the hard real-time control law acceleration engine loads dedicated hardware acceleration intellectual property cores for different cascaded pipeline hardware architectures through software, combines and cascades different basic control algorithm modules and loads them into dedicated hardware acceleration circuits; its control algorithm structure and parameters can be dynamically switched or merged through software configuration to achieve hard real-time execution of multiple control strategies, including at least one of dynamic inverse, incremental dynamic inverse, sliding mode control, and optimal adjustment.

[0075] Figure 6 The illustration schematically shows an example of a reconfigurable pipeline of a hard real-time control law acceleration engine according to an embodiment of this application, and a schematic diagram of dynamic switching of its algorithm cores.

[0076] exist Figure 6 The example shown illustrates the hardware acceleration and dynamic reconfiguration of the hard real-time control law acceleration engine in the heterogeneous computing acceleration center. This engine is a core component of the hardware acceleration resource pool, with a control law execution latency of ≤1μs. It employs a reconfigurable pipeline architecture, loading dedicated hardware acceleration intellectual property cores (IP cores) for different cascaded pipeline hardware architectures via software. This allows for the combination and cascading of different basic control algorithm modules into dedicated hardware acceleration circuits, with an algorithm switching time of <1ms. The control algorithm structure and parameters can be dynamically switched or merged via software, enabling hard real-time execution of various control strategies such as dynamic inversion, incremental nonlinear dynamic inversion (INDI), sliding mode control, and optimal adjustment. The specific implementation is as follows:

[0077] Basic configuration of the reconfigurable pipeline architecture: The engine's pipeline has 4-8 configurable stages, 32-bit floating-point accuracy, and a control cycle of <10μs. The edge intelligent management unit configures the pipeline slots into different cascaded architectures based on flight mission instructions, enabling hardware execution of the control algorithm. For example, in cruise flight mode, the pipeline slots are configured as: State Observer → LQR Controller → Integrator → PWM Generator, loading the optimal adjustment IP core to achieve high-precision, low-power control for smooth cruise. In maneuvering flight mode, the edge intelligent management unit triggers reconfiguration, reconfiguring the pipeline within milliseconds to: Nonlinear Disturbance Observer → Sliding Mode Controller → PWM Generator, loading the sliding mode control IP core to achieve highly dynamic maneuverable disturbance rejection control.

[0078] IP cores of basic control algorithms, such as dynamic inversion, incremental nonlinear dynamic inversion (INDI), sliding mode control, and optimal adjustment, are selected from the IP core library and combined, cascaded, and loaded into a dedicated hardware acceleration circuit through software. For complex requirements such as chatter suppression and load-sensitive control, multiple control algorithm cores are integrated and loaded. For example, the incremental nonlinear dynamic inversion (INDI) algorithm core is integrated with the sliding mode control core to achieve synergy between disturbance and chatter suppression and hard real-time disturbance rejection, thereby realizing the combination and integration of basic control algorithm modules.

[0079] Hardware implementation of Incremental Nonlinear Dynamic Inverse (INDI): To combat model uncertainties and external aerodynamic disturbances, the incremental nonlinear dynamic inverse algorithm is implemented in hardware. The hardware engine executes the following steps in each control cycle through a hardware parallel matrix operation unit, taking less than 1 microsecond. For example: obtaining the control quantity from the previous moment and the state derivative estimate estimated by the state observer; receiving the expected state derivative increment; calculating the control increment in parallel using the estimated value of the control performance matrix; and calculating the current control command, achieving a disturbance rejection response on the order of hundreds of nanoseconds.

[0080] Software-defined implementation of load-sensitive impedance control: The actuator is equivalent to a virtual mass-spring-damping system through software definition. The edge intelligent management unit dynamically configures the impedance parameters according to the flight mission (such as flutter suppression requiring high damping and precise tracking requiring high stiffness). The engine is loaded with a load-sensitive impedance control IP core to achieve flexible actuation, so that the actuator output behavior can be dynamically reconstructed from a high-stiffness "position source" to a high-damping "force source".

[0081] Dynamic software adjustment of control algorithm parameters: In addition to the switching and fusion of algorithm cores, the core parameters of the control algorithm, such as the weight matrix of the LQR controller, the switching gain of the sliding mode controller, and the estimated value of the control performance matrix of the incremental dynamic inverse, can be dynamically adjusted by software without reloading the entire IP core, thus achieving online optimization of control performance.

[0082] Through the loading and combination of the aforementioned reconfigurable pipeline architecture and hardware acceleration IP cores, the hard real-time control law acceleration engine achieves nanosecond to microsecond-level hard real-time execution of various control strategies, providing precise control instructions for software-defined intelligent power drive modules.

[0083] In a more specific example, the control law acceleration engine employs a reconfigurable pipeline architecture. In "cruise mode," the pipeline slots are configured as [State Observer] → [LQR Controller] → [Integrator]. If the mission switches to "maneuvering flight," the edge intelligent management unit triggers reconfiguration, reconfiguring the pipeline within milliseconds to [Nonlinear Disturbance Observer] → [Sliding Mode Controller] → [PWM Generator]. Within the control law acceleration engine, the incremental nonlinear dynamic inverse algorithm is implemented in hardware to combat disturbances. Its core is to utilize incremental information from sensor feedback to cancel disturbances in real time. Specifically, combining the control quantity from the previous cycle with the current state feedback increment, the disturbance compensation is calculated in real time using a hardware parallel matrix operation unit, and the current control command is generated. This calculation process is executed entirely in hardware logic in a pipelined manner, achieving disturbance rejection responses on the order of hundreds of nanoseconds, significantly improving the system's accuracy and robustness under model uncertainty and external disturbances. The incremental nonlinear dynamic inverse (INDI) algorithm is implemented in hardware to achieve nanosecond-level disturbance rejection.

[0084] Let the approximate model of the system be:

[0085] ;

[0086] in For state variables, For control variables. The hardware engine executes the following steps in each control cycle:

[0087] 1. Obtain the control quantity from the previous moment. and the state derivative estimate by the state observer .

[0088] 2. Increment of the expected state derivative before reception .

[0089] 3. Using the estimated value of the control effectiveness matrix The control increment is calculated in parallel by a hardware matrix multiplication and addition unit. :

[0090] ;

[0091] in This is the increment caused by the disturbance in the sensor feedback.

[0092] 4. Calculate the current control command: .

[0093] The calculation is performed entirely in a pipelined manner within a dedicated logic circuit, taking less than 1 microsecond. Therefore, by utilizing feedback increments in real time, the incremental nonlinear dynamic inverse hardware module can effectively compensate for model uncertainties and external aerodynamic disturbances, significantly enhancing the accuracy and robustness of the actuation control system.

[0094] To achieve safe and efficient interaction between the aircraft's actuation system and the external environment (such as airflow and structure), this invention implements load-sensitive impedance control through software definition. Its core is to treat the actuator as an equivalent virtual mass-spring-damped system, whose dynamic characteristics are described by the following impedance model:

[0095] ;

[0096] in To output force commands to the actuator. These are the software-defined expected virtual inertia, damping, and stiffness, respectively. The actual position, velocity, and acceleration of the actuator. For reference position, The observed external disturbances.

[0097] The software-defined implementation mechanism comprises three parts: dynamic impedance parameter configuration, hardware-coordinated execution, and disturbance feedforward compensation. During the dynamic impedance parameter configuration process, the edge intelligent management unit dynamically calculates and distributes the optimal impedance parameters based on the flight mission (e.g., "flutter suppression" requires high damping, and "precise tracking" requires high stiffness) and real-time load identification results. Parameter set. During hardware co-execution, the updated impedance parameters are configured into the hard real-time control law acceleration engine, enabling it to output the basic force command. On the one hand, it satisfies virtual dynamics; on the other hand, it is configured to a software-defined intelligent power drive module, which adjusts the equivalent closed-loop gain of the current loop to enable the actual output force of the power stage. Track quickly and accurately During the disturbance feedforward compensation process, the "incremental nonlinear dynamic inverse" engine is used to estimate in real time... As a feedforward quantity injection control command, it enables active disturbance rejection.

[0098] In this way, a single hardware platform can dynamically reconstruct its output behavior from a high-stiffness "position source" to a high-damping "force source" or any impedance characteristic in between through software instructions, fundamentally realizing the flexible adjustability of the actuation mode and the self-adaptation to complex loads.

[0099] In this embodiment, the intelligent power drive module includes a digitally programmable isolation driver, a wide-bandgap semiconductor power bridge with multiple configurable topologies, and a fast hardware protection circuit with software-configurable thresholds. The circuit topology of the wide-bandgap semiconductor power bridge can be configured by software according to efficiency and output ripple requirements. The fast hardware protection circuit has a multi-mode response strategy, which can be defined by software to perform shutdown, adaptive current limiting, or frequency reduction operation in the event of a fault.

[0100] Figure 7 The illustration shows a schematic diagram of the multi-topology configuration and adaptive protection strategy logic of a software-defined intelligent power drive module according to an embodiment of this application.

[0101] exist Figure 7 In the example shown, the software-defined intelligent power drive module is the final execution unit for impedance control and energy conversion. This module not only completes efficient energy conversion but also achieves disturbance suppression from external airflow and control surface flutter through software definition. Its intelligent and flexible adjustable output impedance and protection strategy are key to realizing advanced control algorithms such as "incremental nonlinear dynamic inverse hard real-time disturbance rejection" and "load-sensitive impedance control flexible actuation" in this device. The main functions of the software-defined intelligent power drive module include power topology software reconstruction, impedance characteristic software definition, and intelligent protection strategy reconstruction.

[0102] In power topology software reconfiguration, the module incorporates multi-topology power bridges (such as H-bridges and three-level bridges) based on wide-bandgap semiconductors (such as SiC). The edge intelligent management unit can dynamically switch power topologies according to task requirements (such as low ripple for high-precision positioning and high efficiency for fast response) to achieve global performance optimization.

[0103] In the software definition of impedance characteristics, to achieve flexible actuation and precise force control, the equivalent output impedance of this module (manifested as stiffness, damping, and other characteristics) can be defined via software. In impedance loop control, the module receives force commands from the control law engine. The system performs closed-loop tracking control based on software-defined current loop parameters (proportional gain, integral time), and its closed-loop transfer function is equivalent to a programmable force impedance. The management unit adjusts the current loop control parameters in real time according to the load status and task instructions, enabling the actuator to exhibit the required impedance characteristics. This process borrows from the concept of load-sensitive impedance control, translating high-level interaction strategies into low-level driving behaviors through software, allowing the system to interact smoothly and safely with the environment while outputting precise force and position.

[0104] In the intelligent protection strategy reconfiguration, the thresholds (such as overcurrent and overtemperature) of the module's fast hardware protection circuits (response time ≤ 100ns) and fault response strategies (such as immediate shutdown, adaptive current limiting, and frequency reduction operation) are all defined online by software. This allows the protection mechanism to dynamically adjust according to the mission phase (such as takeoff, cruise, and landing) and the system health status, maximizing mission continuity while ensuring absolute safety.

[0105] Therefore, this module, through software definition, unifies the contradiction between the high efficiency and high safety of power drive and task adaptability, and is the embodiment of "hardware accelerated execution" in the energy domain.

[0106] exist Figure 7 In a specific example, the hardware implementation and software reconfiguration of the software-defined intelligent power drive module are illustrated. This module is the final execution unit of the hardware acceleration execution layer, providing precise and safe execution for the software-defined energy chain. Its core comprises three main components: a digitally programmable isolation driver, a multi-topology configurable wide-bandgap semiconductor power bridge, and a software-settable threshold fast hardware protection circuit. This enables software reconfiguration of the power topology, software definition of impedance characteristics, and intelligent protection strategy reconfiguration. The topology switching time is < 10μs, and the protection response time is < 100ns. The specific implementation is as follows:

[0107] Configurable wide-bandgap semiconductor power bridge with multiple topologies: Employing wide-bandgap semiconductor devices such as silicon carbide (SiC) / gallium nitride (GaN), it integrates multiple power conversion topologies including H-bridge and three-level topologies. The edge intelligent management unit dynamically configures the topologies via software based on efficiency and output ripple requirements: High-precision positioning actuation tasks: Configured as a three-level topology to reduce output ripple, achieving an output accuracy of ≤0.1% to meet precise tracking requirements; Fast-response actuation tasks: Configured as an H-bridge topology to improve power conversion efficiency, achieving an efficiency of ≥98% and a switching frequency of ≤500kHz to meet high dynamic response requirements; Digitally programmable isolated driver: Receives control commands from the hard real-time control law acceleration engine to drive the switching transistors of the wide-bandgap semiconductor power bridge. Its isolation voltage and drive timing can be configured via software programming, achieving precise transmission and electrical isolation of control commands and ensuring the electrical safety of the module; Software-configurable threshold fast hardware protection circuit: This circuit is the core of the module's safety, with a protection response time < The 100ns overcurrent, overtemperature, and short-circuit protection thresholds can all be defined online via software, and it features multi-mode protection strategies. Fault response strategies can be selected from immediate shutdown, adaptive current limiting, and frequency reduction operation based on software definition: Takeoff phase (high load): Overcurrent and overtemperature thresholds are set to high levels, and the fault response strategy is set to adaptive current limiting, prioritizing operational continuity; Cruise phase (low load): Protection thresholds are lowered, and the fault response strategy is set to frequency reduction operation, optimizing power consumption while ensuring safety; Short-circuit fault: Immediately triggers the immediate shutdown strategy to quickly protect power devices and actuators; Impedance characteristics are software-defined: To achieve load-sensitive impedance control and flexible actuation, the module's equivalent output impedance (manifested as stiffness, damping, etc.) can be defined via software; The edge intelligent management unit adjusts parameters such as the proportional gain and integral time of the current loop based on flight mission and load identification results. The module receives force commands from the control law engine and executes closed-loop tracking control. Its closed-loop transfer function is equivalent to a programmable force impedance, enabling the actuator to exhibit the required impedance characteristics and achieving safe and efficient interaction with the external environment (airflow, structure);

[0108] Through the coordinated software configuration of the above three components, the module realizes the energy conversion from control commands to actuator drive, taking into account efficiency, safety and task adaptability, and completes the final execution of interference and chatter suppression and flexible actuation. It is the key to the device to realize advanced control algorithms such as incremental nonlinear dynamic inverse hard real-time disturbance rejection and load-sensitive impedance control flexible actuation.

[0109] Based on this, wide-bandgap semiconductor power devices are used to achieve high-efficiency energy conversion with a switching frequency ≤500kHz and an efficiency ≥98%. Compared with traditional silicon-based devices, this significantly improves power density and conversion efficiency while reducing power consumption, meeting the integration requirements of distributed intelligent actuation systems. A multi-topology configurable power bridge supports software switching between H-bridge, three-level, and other topologies, with a topology switching time <10μs. It can achieve global optimization between efficiency and output ripple according to mission requirements, balancing high-precision positioning and rapid response actuation needs. A software-configurable threshold fast hardware protection circuit with a protection response time <100ns is included. Overcurrent, overtemperature, and short-circuit protection thresholds and multi-mode protection strategies (immediate shutdown, adaptive current limiting, and frequency reduction operation) can be dynamically defined in software, adapting to the load characteristics of different flight phases and maximizing mission continuity while ensuring absolute safety. The software-defined impedance characteristics enable load-sensitive impedance control and flexible actuation, allowing the actuator to be dynamically reconfigured into a high-stiffness position source or a high-damping force source. This enables safe and efficient interaction with the external environment and is key to achieving advanced control algorithms such as flutter suppression and precise tracking. The digitally programmable isolation driver allows for software configuration of drive timing and isolation parameters, improving the transmission accuracy of control commands and the safety of electrical isolation, ensuring reliable operation of the module under high-voltage airborne environments. The software-defined reconfiguration of power drives reconciles the contradiction between high efficiency, high safety, and task adaptability in power drives. This is a concrete manifestation of "hardware-accelerated execution" in the energy domain, providing a precise and safe execution standard for software-defined energy chains.

[0110] In this embodiment, the edge intelligent management unit diagnoses the system health status and predicts fault trends by analyzing sensor data, control error spectrum, drive current characteristics and module temperature in real time. This allows for online adjustment of hardware acceleration engine parameters, reconstruction of power drive protection strategies or triggering of system degradation mode switching, thus achieving a shift from passive fault tolerance to active prediction and adaptation.

[0111] Figure 8 The illustration shows a schematic diagram of online optimization and health management of the edge intelligent management unit according to an embodiment of this application.

[0112] exist Figure 8 In the example shown, the edge intelligent management unit is the intelligent hub of the software-defined paradigm, responsible for the system's global perception, decision-making, and optimization. It operates within a continuous "perception-evaluation-decision-execution" closed loop, not only performing health management but also achieving cross-module collaborative optimization. This edge intelligent unit collects deep operational data from each hardware module through a non-intrusive dedicated monitoring channel, including calculating the signal-to-noise ratio and control error statistics. Power module drive efficiency and chip junction temperature And so on, and accordingly provide incoming line optimization and health management functions.

[0113] In terms of performance optimization, when the management unit detects that the airflow is stable during the current flight segment and the control error is far below the threshold, it can fine-tune the filter bandwidth of the calculation engine online to reduce noise, or adjust the LQR weight matrix in the control law engine. Energy consumption is further optimized while ensuring performance. The management unit monitors the error spectrum in real time. When error characteristics caused by model uncertainty or external disturbances (such as aerodynamic disturbances) are detected, key parameters (such as the estimated value of the control performance matrix) in the "incremental nonlinear dynamic inverse" hardware acceleration engine can be fine-tuned online. This optimization draws on the idea of ​​using error increments to compensate for disturbances in real time in nonlinear control. By fine-tuning the parameters of the hardware algorithm core through software, the disturbance rejection algorithm deployed in the hardware pipeline can maintain optimal performance without reloading the entire intellectual property core, achieving continuous optimization of nanosecond-level disturbance rejection response. The management unit evaluates the dynamic characteristics of the load (such as inertia and damping changes) in real time by analyzing data such as drive current and position tracking error. Based on this evaluation, it can dynamically adjust the impedance parameters (equivalent stiffness and damping) of the software-defined intelligent power drive module, or send commands to the hard real-time control law acceleration engine to fine-tune its control algorithm output, so that the output impedance of the entire actuation system is optimally matched with the real-time load and task requirements (such as the need for specific damping for flutter suppression), thereby significantly reducing unnecessary force fluctuations and energy consumption.

[0114] In terms of health prediction and fault tolerance, the management unit can predict actuator bearing wear trends by analyzing the harmonic spectrum characteristics of the drive current. Once the health assessment falls below a threshold, a more robust control algorithm core is pre-loaded, and the power drive module is instructed to enter protection mode. If a sensor coil fault is diagnosed, the management unit can switch to an observer mode based on redundant information such as motor back EMF and trigger a degraded operation strategy. The sensor coil fault is detected by monitoring the secondary voltage and... Does it deviate from a constant value? Judgment, that is This deep-perception-based online intelligent management transforms the system from passively responding to faults to proactively predicting and adaptively adjusting, achieving a higher level of intelligent autonomy and adaptive fault tolerance. The management unit predicts faults through deep data analysis. Its advanced functionality lies not only in triggering degradation modes but also in proactively initiating system refactoring. For example, when a sensor's performance degradation is predicted, an observer-based fault-tolerant control algorithm core can be pre-loaded into the hardware acceleration engine, and the parameters of the signal processing engine can be adjusted simultaneously, achieving seamless migration of system functions and graceful performance degradation, demonstrating a high degree of edge intelligent autonomy. Through these closed-loop optimizations, the edge intelligent management unit ensures that the synergy between the "software-defined architecture" and "hardware-accelerated execution" is optimal, enabling the system to evolve from passive response to proactive prediction and adaptive adjustment.

[0115] After repeated testing, Figure 3 , Figure 8 In the specific example shown, the online optimization and health management of the edge intelligent management unit is implemented. This unit is the intelligent hub of the software-defined architecture, running on the processor system of the heterogeneous computing acceleration center. It does not intervene in the hard real-time control loop, but collects the entire system's operating data through a non-intrusive dedicated monitoring channel. It operates in a closed-loop decision-making cycle of perception-evaluation-decision-execution, with a decision cycle of ≤1ms. It realizes the transformation from passive fault tolerance to active prediction and adaptation, with a fault prediction accuracy of ≥95%, optimization convergence time <10ms, and system reconfiguration time ≤5ms. The specific implementation is as follows:

[0116] Perception: Real-time data acquisition: Deep operational data of each hardware module is collected through a dedicated monitoring channel, including sensor data, control error spectrum, drive current characteristics, module temperature, calculated signal-to-noise ratio, control error statistics, power module drive efficiency, chip junction temperature, etc., to provide a data foundation for system status assessment and health diagnosis;

[0117] Assessment: System health diagnosis and performance indicator evaluation: In-depth analysis of collected operational data to complete four major assessment functions: system health diagnosis, fault trend prediction, performance indicator evaluation, and load characteristic identification.

[0118] Performance evaluation: Analyze control errors, calculate signal-to-noise ratio, power conversion efficiency, etc., and evaluate the current control performance, signal processing performance and energy conversion performance of the system;

[0119] Load characteristic identification: By analyzing data such as drive current and position tracking error, the dynamic characteristics of the actuator (such as inertia and damping changes) can be identified in real time.

[0120] System health diagnosis: Analyze the harmonic spectrum characteristics of the drive current, sensor secondary voltage, module temperature, etc., to diagnose the health status of core components such as sensor coils, actuator bearings, and power devices;

[0121] Fault trend prediction: A fault prediction model is established based on health diagnosis data, with a fault prediction accuracy of ≥95%. For example, the wear trend of actuator bearings can be predicted by the harmonic spectrum of the drive current, and the fault trend of coils can be judged by the deviation of the secondary voltage of the sensor from a constant value.

[0122] Decision-making: Configuration strategy generation: Based on the evaluation results, a global configuration strategy is generated, including algorithm kernel selection, hardware acceleration IP core loading, power topology configuration, protection strategy settings, parameter fine-tuning schemes, fault response strategies, etc.

[0123] Execution: Online optimization, module refactoring, and adaptive fault tolerance: Execute corresponding operations according to the configuration policy to achieve online optimization and health management of the entire system, specifically including:

[0124] Online optimization: Optimize convergence time < 10ms. If stable airflow is detected and control error is far below the threshold, fine-tune the filter bandwidth of the calculation engine to reduce noise and adjust the LQR weight matrix of the control law engine to optimize energy consumption. If aerodynamic disturbance is detected, fine-tune the control performance matrix estimate of the incremental nonlinear dynamic inverse engine to continuously optimize disturbance rejection performance. Based on the load characteristic identification results, adjust the impedance parameters (equivalent stiffness, damping) of the power drive module to match the actuation system with the load in real time, reducing force fluctuation and energy consumption.

[0125] Module Reconfiguration: System reconfiguration time ≤ 5ms. If sensor performance degradation is predicted, the fault-tolerant control algorithm core based on the observer is loaded into the hardware acceleration engine in advance, and the configuration of the silicon photonic interconnect intelligent interface and the parameters of the signal processing engine are adjusted synchronously. If the task is switched, the pipeline architecture of the hard real-time control law acceleration engine and the topology of the power drive module are reconfigured.

[0126] Adaptive fault tolerance and predictive maintenance: If the health assessment is below the threshold, a more robust control algorithm core is loaded in advance, and the power drive module is instructed to enter a high-safety-level protection mode; if a sensor coil fault is diagnosed, the system switches to an observer mode based on redundant information such as motor back EMF, triggering a degradation mode switch; a comprehensive equipment status word is generated to provide data support for predictive maintenance.

[0127] Closed-loop optimization: The system state after execution is collected again through state feedback and enters the next "perception, evaluation, decision-making, execution" cycle to ensure that the collaboration between "software-defined architecture" and "hardware accelerated execution" is in the optimal state, so that the system has the evolutionary ability to move from passive response to active prediction and adaptive adjustment.

[0128] Based on this, a closed-loop decision-making cycle of "perception-evaluation-decision-execution" is constructed, with a decision cycle of ≤1ms, achieving global collaborative optimization of the entire system. This breaks through the limitations of traditional isolated module design, improving the overall performance, efficiency, and reliability of actuation control at the system level. It realizes a shift from passive fault tolerance to active prediction and adaptation, enabling fault prediction accuracy of ≥95%. It predicts the failure trends of core components such as sensors, actuators, and power devices in advance, allowing for proactive protective measures and significantly improving the system's resilience and task continuity. The online optimization function enables real-time fine-tuning of parameters for each module, optimizing convergence time. With a 10ms response time, the system configuration can be dynamically adjusted according to the flight environment and load characteristics, continuously optimizing control performance, disturbance rejection performance, and energy efficiency to ensure the system is always in optimal operating condition. Millisecond-level system reconfiguration capability (system reconfiguration time ≤ 5ms) enables rapid reconfiguration such as algorithm kernel loading, interface reconfiguration, and power topology switching. In the event of a fault, it can achieve seamless migration and graceful degradation of system functions, ensuring the continuity of actuation control. A non-intrusive dedicated monitoring channel enables interference-free acquisition of deep operational data from each module, providing a precise data foundation for system health diagnosis and fault prediction, improving the accuracy and real-time performance of health management. Intelligent management, decision-making, and optimization capabilities are decentralized to the actuators, achieving highly edge-based intelligent autonomy, reducing the central computing load, improving system responsiveness, and adapting to the development needs of distributed intelligent actuation systems. Predictive maintenance capabilities are provided, generating integrated equipment status words, providing data support for the maintenance of the aircraft actuation system, reducing maintenance costs, and improving the system's reliability throughout its entire lifecycle.

[0129] In summary, the silicon photonics interconnect-based on-chip intelligent actuation control device for aircraft, based on software-defined and hardware-accelerated technologies, creatively constructs a collaborative paradigm of "software-defined architecture and hardware-accelerated execution," and deeply integrates three core technologies: silicon photonics interconnect, heterogeneous computing, and intelligent power drive. This results in a novel intelligent actuation control device for aircraft edges. It not only achieves breakthroughs in performance indicators but also revolutionizes the system architecture paradigm, providing a crucial hardware platform and design methodology for the development of future adaptive, high-performance aircraft.

[0130] Based on the aforementioned silicon photonics interconnect-based on-chip integrated intelligent actuation control device for aircraft using software-defined and hardware-accelerated methods, embodiments of this application also provide a silicon photonics interconnect-based on-chip integrated intelligent actuation control method for aircraft using software-defined and hardware-accelerated methods. The following will combine... Figure 9 The device is described in detail.

[0131] Figure 9 The flowchart illustrates a software-defined and hardware-accelerated silicon photonic interconnect-based on-chip integrated intelligent actuation control method for aircraft edges according to an embodiment of this application.

[0132] like Figure 9 As shown in the embodiments of this application, the silicon photonic interconnect-based on-chip integrated intelligent actuation control method for aircraft edges, based on software-defined and hardware-accelerated technologies, is implemented using the sensing device described above. The method includes:

[0133] S910: Receive and parse task instructions through the edge intelligent management unit to generate a global system configuration strategy; S920: Based on the global system configuration strategy, dynamically configure the transmission protocol and parameters of the silicon photonic interconnect intelligent interface through software, and load the corresponding sensor signal calculation acceleration engine; S930: Based on the sensor signal calculation acceleration engine, compile the control algorithm required by the task into a dedicated hardware acceleration intellectual property core, and load it into the reconfigurable pipeline of the hard real-time control law acceleration engine; S940: Configure the topology and protection strategy of the software-defined intelligent power drive module; S950: Enable the system to run under the software-defined framework. Sensor signals are transmitted through the adapted optical interface and processed in parallel pipeline by the loaded sensor signal calculation acceleration engine and hard real-time control law acceleration engine to generate drive instructions, which are then executed by the intelligent power module, forming a high-precision, high-determinism, and high-reliability closed-loop control; S960: Enable the edge intelligent management unit to continuously monitor the system status and optimize the configuration of each module of the silicon photonic interconnect intelligent interface, heterogeneous computing acceleration center, and intelligent power drive module online based on real-time feedback, achieving adaptive and high-performance actuation control.

[0134] In this embodiment, the method essentially enables: the edge intelligent management unit to receive and parse task instructions, and generate a global system configuration strategy; based on the configuration strategy, to dynamically configure the transmission protocol and parameters of the silicon photonic interconnect intelligent interface through software, and load the corresponding sensor signal calculation acceleration engine intellectual property core; to compile the control algorithm required by the task into a hardware acceleration intellectual property core, and load it into the reconfigurable pipeline of the hard real-time control law acceleration engine; to configure the topology and protection strategy of the software-defined intelligent power drive module; the system operates under a software-defined framework, the sensor signals are transmitted through the adapted optical interface, and are processed in parallel pipeline by the loaded hardware acceleration engine to generate drive instructions and execute them through the intelligent power module, forming a closed-loop control with high precision, high determinism and high reliability; the edge intelligent management unit continuously monitors the system status, and optimizes the configuration of each module online based on real-time feedback to achieve adaptive and high-performance actuation control.

[0135] In this embodiment, the software-configurable silicon photonic interconnect smart interface includes: a parameter-programmable direct digital frequency synthesis excitation generator, a differential analog front-end with configurable gain and filter characteristics, an analog-to-digital converter, and a silicon photonic interconnect isolation bridge with a defined transmission protocol; the silicon photonic interconnect isolation bridge supports software configuration and dynamic adaptation of optical modulation format, encoding method and transmission rate to adapt to different sensor types and electromagnetic environment requirements.

[0136] In this embodiment, the sensor signal processing acceleration engine supports loading dedicated hardware acceleration intellectual property cores for different sensors through software. The digital filter link coefficients, nonlinear dynamic inverse model compensation lookup tables, and temperature drift correction models integrated within the dedicated hardware intellectual property cores can all be updated online through the software interface to achieve high-precision, deterministic signal processing.

[0137] In this embodiment, the hard real-time control law acceleration engine loads dedicated hardware acceleration intellectual property cores for different cascaded pipeline hardware architectures through software, combines and cascades different basic control algorithm modules and loads them into dedicated hardware acceleration circuits; its control algorithm structure and parameters can be dynamically switched or merged through software configuration to achieve hard real-time execution of multiple control strategies, including at least one of dynamic inverse, incremental dynamic inverse, sliding mode control, and optimal adjustment.

[0138] In this embodiment, the intelligent power drive module includes a digitally programmable isolation driver, a wide-bandgap semiconductor power bridge with multiple configurable topologies, and a fast hardware protection circuit with software-configurable thresholds. The circuit topology of the wide-bandgap semiconductor power bridge can be configured by software according to efficiency and output ripple requirements. The fast hardware protection circuit has a multi-mode response strategy, which can be defined by software to perform shutdown, adaptive current limiting, or frequency reduction operation in the event of a fault.

[0139] In this embodiment, the edge intelligent management unit diagnoses the system health status and predicts fault trends by analyzing sensor data, control error spectrum, drive current characteristics and module temperature in real time. This allows for online adjustment of hardware acceleration engine parameters, reconstruction of power drive protection strategies or triggering of system degradation mode switching, thus achieving a shift from passive fault tolerance to active prediction and adaptation.

[0140] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems and methods according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram or flowchart, and combinations of blocks in a block diagram or flowchart, may be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0141] Those skilled in the art will understand that the features described in the various embodiments of this application can be combined and / or combined in various ways, even if such combinations or combinations are not explicitly described in this application. In particular, the features described in the various embodiments of this application can be combined and / or combined in various ways without departing from the spirit and teachings of this application. All such combinations and / or combinations fall within the scope of this application.

Claims

1. A silicon photonic interconnect-based on-chip intelligent actuation control device for aircraft edges, characterized in that, include: The software-configurable silicon photonic interconnect smart interface is used to connect external sensors. The sensor's excitation signal generation, analog front-end conditioning parameters, and optical interconnect transmission protocol are dynamically defined and configured through the software instructions of the silicon photonic interconnect smart interface to achieve high-fidelity, interference-resistant conversion and electrically isolated transmission from analog sensing signals to the digital domain. The heterogeneous computing acceleration center is centered on a heterogeneous system-on-a-chip (SoC) composed of an integrated processor system and a programmable logic unit (PLU). The PLU contains a reconfigurable hardware acceleration resource pool, which includes a sensor signal processing acceleration engine and a hard real-time control law acceleration engine. The engines are directly connected to each other via an on-chip high-speed streaming interconnect bus, forming a deterministic data processing path that is free from processor intervention. The software-defined intelligent power drive module uses wide-bandgap semiconductor power devices to receive and execute instructions from the hard real-time control law acceleration engine to drive external actuators. The power conversion topology, drive timing and multi-level hardware protection logic of the intelligent power drive module can be defined and reconfigured online through software. The edge intelligent management unit, running on the processor system of the heterogeneous computing acceleration center, is used to dynamically configure and collaboratively manage the working modes, algorithm kernels, and performance parameters of the silicon photonic interconnect intelligent interface, the heterogeneous computing acceleration center, and the intelligent power drive module according to the flight mission and system status, so as to achieve software-defined optimization and adaptive operation of the entire system.

2. The apparatus according to claim 1, characterized in that, The software-configurable silicon photonic interconnect smart interface includes: a parameter-programmable direct digital frequency synthesis excitation generator, a differential analog front-end with configurable gain and filter characteristics, an analog-to-digital converter, and a silicon photonic interconnect isolation bridge with a defined transmission protocol. The silicon photonic interconnect isolation bridge supports software configuration and dynamic adaptation of optical modulation format, encoding method and transmission rate to adapt to different sensor types and electromagnetic environment requirements.

3. The apparatus according to claim 1, characterized in that, The sensor signal processing acceleration engine supports loading dedicated hardware acceleration intellectual property cores for different sensors via software. The digital filter link coefficients, nonlinear dynamic inverse model compensation lookup tables, and temperature drift correction models integrated within the dedicated hardware intellectual property cores can all be updated online via the software interface to achieve high-precision, deterministic signal processing.

4. The apparatus according to claim 1, characterized in that, The hard real-time control law acceleration engine loads dedicated hardware acceleration intellectual property cores for different cascaded pipeline hardware architectures through software, combining and cascading different basic control algorithm modules and loading them into a dedicated hardware acceleration circuit; its control algorithm structure and parameters can be dynamically switched or merged through software configuration to achieve hard real-time execution of multiple control strategies, including at least one of dynamic inverse, incremental dynamic inverse, sliding mode control, and optimal adjustment.

5. The apparatus according to claim 1, characterized in that, The intelligent power drive module includes a digitally programmable isolation driver, a multi-topology configurable wide bandgap semiconductor power bridge, and a software-settable threshold fast hardware protection circuit. The circuit topology of the wide bandgap semiconductor power bridge can be configured in software according to efficiency and output ripple requirements; The fast hardware protection circuit has a multi-mode response strategy, which can perform shutdown, adaptive current limiting, or frequency reduction operation in the event of a fault, according to software definition.

6. The apparatus according to claim 1, characterized in that, The edge intelligent management unit diagnoses the system's health status and predicts fault trends by analyzing sensor data, control error spectrum, drive current characteristics, and module temperature in real time. It then adjusts hardware acceleration engine parameters online, reconstructs power drive protection strategies, or triggers system degradation mode switching, thus achieving a shift from passive fault tolerance to active prediction and adaptation.

7. A software-defined and hardware-accelerated aircraft actuation control method, characterized in that, The method is implemented based on the apparatus according to any one of claims 1 to 6, and includes: The edge intelligent management unit receives and parses task instructions to generate a global system configuration policy. Based on the global system configuration strategy, the transmission protocol and parameters of the silicon photonic interconnect smart interface are dynamically configured by software, and the corresponding sensor signal processing acceleration engine is loaded. Based on the sensor signal processing acceleration engine, the control algorithm required for the task is compiled into a dedicated hardware acceleration intellectual property core and loaded into the reconfigurable pipeline of the hard real-time control law acceleration engine. Configure the topology and protection strategy of the software-defined intelligent power drive module; enable the system to run under the software-defined framework, the sensor signal is transmitted through the adapted optical interface, and the loaded sensor signal calculation acceleration engine and the hard real-time control law acceleration engine are processed in parallel pipeline to generate drive commands and execute them through the intelligent power module, forming a closed-loop control with high precision, high determinism and high reliability. The edge intelligent management unit continuously monitors the system status and optimizes the configuration of each module, including the silicon photonic interconnect intelligent interface, the heterogeneous computing acceleration center, and the intelligent power drive module, based on real-time feedback, thereby achieving adaptive and high-performance actuation control.

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