Display device

Abstract

This disclosure provides a display device. The display device includes: a substrate including an effective region and an ineffective region; an encapsulation layer disposed on the substrate; a plurality of pseudo-lines disposed in the ineffective region; and an amplifier connected to some of the pseudo-lines, wherein some of the pseudo-lines are disposed outside the encapsulation layer in the ineffective region, and the remaining pseudo-lines are disposed on the encapsulation layer in the ineffective region. Therefore, by connecting the amplifier to the pseudo-lines, the signal radiation of the pseudo-lines can be increased, and touch signal noise caused by electromagnetic interference can be reduced.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0201366, filed on December 30, 2024, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference. Technical Field

[0003] This disclosure relates to a display device, and more particularly to a display device having a built-in touch unit. Background Technology

[0004] Electroluminescent displays are self-emissive displays. Unlike liquid crystal displays (LCDs), electroluminescent displays do not require a separate light source and can be manufactured in a lightweight, thin design. Furthermore, electroluminescent displays offer advantages in power consumption due to their low-voltage operation, and exhibit excellent color performance, response time, viewing angle, and contrast ratio (CR), and are being researched as next-generation displays.

[0005] Among electroluminescent display devices, there are touchscreen integrated display devices that include touch units capable of recognizing user touches. Touchscreen integrated display devices allow for direct input of information using fingers or pens and are widely used in navigation systems, portable terminals, and home appliances. Summary of the Invention

[0006] One objective of this disclosure is to provide a display device with a built-in touch unit.

[0007] Another objective of this disclosure is to provide a display device with improved performance of the touch unit.

[0008] Another objective of this disclosure is to provide a display device that reduces electromagnetic interference in the touch unit.

[0009] Another objective of this disclosure is to provide a display device for suppressing the discontinuity of lines in the area of ​​dam components.

[0010] Another objective of this disclosure is to provide a display device with reduced capacitance variation in the touch line.

[0011] Another objective of this disclosure is to provide a display device that improves touch sensing performance by forming dummy touch electrodes between multiple touch electrodes.

[0012] Another objective of this disclosure is to provide a display device that minimizes the transmission delay of touch signals.

[0013] Another objective of this disclosure is to provide a display device that suppresses radiation loss due to pseudo-lines caused by coupling with the housing cover.

[0014] Another objective of this disclosure is to provide a display device that improves the noise reduction effect of pseudo-lines.

[0015] The purpose of this disclosure is not limited to the foregoing objectives, and other objectives not mentioned above will be clearly understood by those skilled in the art from the following description.

[0016] An exemplary embodiment of the present disclosure provides a display device comprising: a substrate including an effective region and an ineffective region; an encapsulation layer disposed on the substrate; a plurality of pseudo-lines disposed in the ineffective region; and an amplifier connected to some of the pseudo-lines, wherein some of the pseudo-lines are disposed outside the encapsulation layer in the ineffective region, and the remaining pseudo-lines are disposed on the encapsulation layer in the ineffective region. Therefore, by connecting the amplifier to the pseudo-lines, the signal radiation of the pseudo-lines can be increased, and touch signal noise caused by electromagnetic interference can be improved.

[0017] A display device according to another exemplary embodiment of the present disclosure includes: a substrate including an effective area and an ineffective area; a plurality of light-emitting diodes disposed on the substrate; an encapsulation layer disposed on the plurality of light-emitting diodes and extending from the effective area to a portion of the ineffective area; and a touch unit disposed on the encapsulation layer and the substrate, wherein the touch unit includes a plurality of touch electrodes on the encapsulation layer, a plurality of touch lines connected to the plurality of touch electrodes, and a plurality of pseudo-lines disposed in the ineffective area, and wherein the plurality of pseudo-lines are configured to surround the plurality of touch lines and the plurality of touch electrodes. Therefore, by forming pseudo-lines that suppress electromagnetic interference from external signals, the performance of the touch unit can be improved.

[0018] Further details of the exemplary embodiments are included in the detailed description and accompanying drawings.

[0019] According to this disclosure, a display device with a built-in touch unit can be provided.

[0020] According to this disclosure, a display device with improved performance of the touch unit can be provided.

[0021] According to this disclosure, electromagnetic interference in the touch unit can be reduced by including pseudo-lines.

[0022] According to this disclosure, the discontinuity of touch wires in dam components can be suppressed.

[0023] According to this disclosure, capacitance variation in the touch line can be reduced by changing the width of the touch line.

[0024] According to this disclosure, touch sensing performance can be improved by forming dummy touch electrodes among multiple touch electrodes.

[0025] According to this disclosure, the transmission delay of touch signals can be minimized.

[0026] According to this disclosure, the radiation reduction of pseudo-lines due to coupling between the pseudo-line and the cover can be suppressed.

[0027] According to this disclosure, the noise reduction effect of pseudo-lines can be improved.

[0028] The effects of this disclosure are not limited to those exemplified above, and include a variety of other effects. Attached Figure Description

[0029] The above and other aspects, features and advantages of this disclosure will become clearer from the following detailed description taken in conjunction with the accompanying drawings, wherein:

[0030] Figure 1 This is a schematic diagram of a display device according to an exemplary embodiment of the present disclosure;

[0031] Figure 2 This is a schematic plan view of a display device according to exemplary embodiments of the present disclosure;

[0032] Figure 3 This is a cross-sectional view of a sub-pixel of a display device according to an exemplary embodiment of the present disclosure;

[0033] Figure 4 yes Figure 2 An enlarged plan view of region A1;

[0034] Figure 5A It is along Figure 2 A cross-sectional view taken from line A-A';

[0035] Figure 5B It is along Figure 2 A cross-sectional view taken from line B-B';

[0036] Figures 6A to 6C This is a schematic cross-sectional view of a dam component of a display device according to an exemplary embodiment of the present disclosure;

[0037] Figure 7 yes Figure 2 An enlarged plan view of region A2;

[0038] Figure 8 and Figure 9 This is a schematic plan view of the touch unit of a display device according to exemplary embodiments of the present disclosure;

[0039] Figure 10This is a schematic enlarged plan view of the touch unit of a display device according to an exemplary embodiment of the present disclosure;

[0040] Figure 11 and Figure 12 This is a schematic enlarged plan view of the touch unit of a display device according to an exemplary embodiment of the present disclosure;

[0041] Figure 13 This is a schematic plan view of a display device according to exemplary embodiments of the present disclosure;

[0042] Figure 14 and 15 yes Figure 13 An enlarged plan view of area A3;

[0043] Figure 16 yes Figure 14 An enlarged plan view of area A4;

[0044] Figure 17 It is along Figure 16 A cross-sectional view taken from line C-C';

[0045] Figure 18 yes Figure 16 An enlarged plan view of area A5;

[0046] Figure 19 yes Figure 13 Enlarged plan view of area A6;

[0047] Figure 20 It is along Figure 19 A cross-sectional view taken from line D-D';

[0048] Figure 21 yes Figure 14 An enlarged plan view of area A7;

[0049] Figure 22A yes Figure 14 An enlarged plan view of area A8;

[0050] Figure 22B It is along Figure 22A A cross-sectional view taken from line E-E';

[0051] Figure 23A yes Figure 14 An enlarged plan view of area A8;

[0052] Figure 23B It is along Figure 23A A cross-sectional view taken by line F-F';

[0053] Figure 24 This is a schematic plan view of a display device according to another exemplary embodiment of the present disclosure;

[0054] Figure 25 It is along Figure 24 A cross-sectional view taken from line G-G';

[0055] Figure 26 This is a schematic diagram of a display device according to another exemplary embodiment of the present disclosure;

[0056] Figure 27A It is a graph showing the noise of the touch signal caused by electromagnetic interference in the display device according to the comparative example; and

[0057] Figure 27B It is a graph measuring the noise of a touch signal caused by electromagnetic interference from a display device according to another exemplary embodiment of the present disclosure. Detailed Implementation

[0058] The advantages and features of this disclosure, as well as methods for implementing these advantages and features, will become clear from the exemplary embodiments described in detail below and the accompanying drawings. However, this disclosure is not limited to the exemplary embodiments disclosed herein, but will be implemented in various forms. The exemplary embodiments are provided by way of example only so that those skilled in the art can fully understand the disclosure and scope of this disclosure.

[0059] The shapes, dimensions, ratios, angles, quantities, etc., shown in the accompanying drawings used to describe exemplary embodiments of this disclosure are merely examples, and this disclosure is not limited thereto. In this disclosure, the same reference numerals generally denote the same elements. Furthermore, in the following description of this disclosure, detailed explanations of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of this disclosure. Terms such as “comprising,” “having,” and “consisting of” as used herein are generally intended to allow for the addition of additional components, unless these terms are used in conjunction with the word “only.” Unless otherwise expressly stated, any reference to the singular may include the plural.

[0060] Even without explicit explanation, components are interpreted as including the normal tolerance range.

[0061] When using terms such as “above,” “over,” “below,” and “next” to describe the positional relationship between two parts, one or more parts may be located between the two parts unless these terms are used with “immediately following” or “directly.”

[0062] When one element or layer is placed "on" another element or layer, other layers or other elements can be directly inserted onto or between the other element.

[0063] Although the terms "first," "second," etc., are used to describe various components, these components are not limited to these terms. These terms are only used to distinguish one component from others. Therefore, the first component mentioned below may be the second component in the technical concept of this disclosure.

[0064] In this disclosure, the same reference numerals generally denote the same elements.

[0065] For ease of description, the dimensions and thickness of each component shown in the figures are illustrated, and this disclosure is not limited to the dimensions and thickness of the components shown.

[0066] Features of the various embodiments of this disclosure may be combined or integrated with each other in part or in whole, and may be interlocked and operated in various technical ways, and the embodiments may be performed independently or in association with each other.

[0067] In the following, a display device according to exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0068] Figure 1 This is a schematic diagram of a display device according to an embodiment of the present disclosure. For ease of explanation, in... Figure 1 The image shows only the display panel PN, gate driver GD, data driver DD, touch driver TD, and timing controller TC among the various components of the display device 100.

[0069] refer to Figure 1 The display device 100 includes a display panel PN, which includes a plurality of sub-pixels SP, a gate driver GD and a data driver DD that supply various signals to the display panel PN, a timing controller TC that controls the gate driver GD and the data driver DD, and a touch driver TD for sensing touch input.

[0070] The display panel PN is configured to display an image to the user and includes multiple subpixels SP. In the display panel PN, multiple scan lines SL and multiple data lines DL intersect each other, and each of the multiple subpixels SP is connected to both scan lines SL and data lines DL. Furthermore, although not shown in the figure, each of the multiple subpixels SP can be connected to a high-potential power line, a low-potential power line, a reference line, etc.

[0071] Multiple subpixels SP are the smallest units constituting a screen, and each of the multiple subpixels SP includes a light-emitting diode (LED) and pixel circuitry for driving the LED. Depending on the type of display device 100, the multiple LEDs can be defined differently. For example, when the display device 100 is an organic light-emitting display device 100, the LEDs can be organic light-emitting diodes (OLEDs).

[0072] The gate driver GD supplies multiple scan signals SCAN to multiple scan lines SL based on multiple gate control signals GCS provided by the timing controller TC. Figure 1 In the diagram, a gate driver GD is shown spaced apart from one side of the display panel PN, but the number and arrangement of gate drivers GD are not limited to this.

[0073] The data driver DD converts the image data (RGB) transmitted from the timing controller TC into a data voltage (Vdata) using a reference gamma voltage, based on multiple data control signals (DCS) provided by the timing controller TC. The data driver DD can then supply the converted data voltage (Vdata) to multiple data lines DL.

[0074] The timing controller TC aligns the externally input image data (RGB) and supplies the RGB data to the data driver DD. The timing controller TC can use externally input synchronization signals (such as dot clock signals, data enable signals, and horizontal / vertical synchronization signals) to generate the gate control signal GCS and the data control signal DCS. Furthermore, the timing controller TC can control the gate driver GD and the data driver DD by supplying the generated gate control signal GCS and data control signal DCS to the gate driver GD and the data driver DD, respectively.

[0075] The touch driver TD is connected to the display panel PN via the touch line TL, and drives the touch unit 150 included in the display panel PN (reference) based on a touch enable signal input from the timing controller TC or an external component during the touch sensing period. Figure 3 The touch driver TD can sense touch input based on signals from the touch unit 150.

[0076] Figure 2 This is a schematic plan view of a display device according to an exemplary embodiment of the present disclosure. Figure 3 This is a cross-sectional view of a sub-pixel of a display device according to an exemplary embodiment of the present disclosure. Figure 4 yes Figure 2 An enlarged plan view of region A1. Figure 5A It is along Figure 2 A cross-sectional view taken from line A-A'. Figure 5B It is along Figure 2 The cross-sectional view taken by line B-B'. Figures 6A to 6C This is a schematic cross-sectional view of a dam component of a display device according to an exemplary embodiment of the present disclosure. Figure 7 yes Figure 2 An enlarged plan view of region A2. For ease of explanation, in... Figure 4 Only the low-potential power line VSSL, the high-potential power line VDDL, the reference line RL, the LOG line LOG, and the data line DL are shown among the multiple lines.

[0077] refer to Figure 2 The display panel PN of the display device 100 includes an effective area AA and an inactive area NA. The effective area AA can be an area for displaying an image. Multiple sub-pixels SP can be formed in the effective area AA to display an image. The inactive area NA can be an area where no image is displayed. Various lines and circuits for driving the multiple sub-pixels SP in the effective area AA can be provided in the inactive area NA. For example, a gate driver GD can be mounted in the inactive area NA, or a pad portion PAD on which a flexible film COF and a printed circuit board PCB are bonded can be provided in the inactive area NA. Furthermore, wiring for driving the multiple sub-pixels SP, the gate driver GD, the touch unit 150, etc., can be provided in the inactive area NA.

[0078] Multiple flexible film-on-film (COF) connections are attached to the pad portions (PADs) of the display panel PN. The multiple flexible film-on-film (COFs) can be films in which various components are disposed on a flexible base film. For example, a driver integrated circuit (IC) can be disposed on the multiple flexible film-on-film (COFs). The driver IC can be a component that processes data and drive signals for displaying images. The multiple flexible film-on-film (COFs) can be attached or bonded to multiple pad electrodes (PEs) via a conductive adhesive layer, but embodiments of this disclosure are not limited thereto.

[0079] A printed circuit board (PCB) is connected to multiple flexible film coils (COFs). The PCB is electrically connected to the COFs and can be a component that supplies signals to a driver IC. Various components for supplying various signals to the driver IC can be disposed on the PCB. For example, timing controllers (TCs), power management integrated circuits (PMICs), memory, processors, and other components can be disposed on the PCB, but embodiments of this disclosure are not limited thereto.

[0080] refer to Figure 3 The substrate 110 is a support component for supporting other components of the display device 100, and may be made of an insulating material. For example, the substrate 110 may be made of glass, resin, etc.

[0081] The substrate 110 can be formed from one or more layers. For example, the substrate 110 can be formed from a double-layer structure including a first substrate 110a and a second substrate 110b on the first substrate 110a. For example, the first substrate 110a and the second substrate 110b can be formed from polyimide (PI). Furthermore, although not shown in the figure, an insulating layer can be further disposed on the first substrate 110a and the second substrate 110b.

[0082] A multi-buffer layer 111 is disposed on the substrate 110. The multi-buffer layer 111 can reduce the penetration of moisture or impurities through the substrate 110. For example, the multi-buffer layer 111 may consist of a single layer or multiple layers of insulating materials such as silicon nitride (SiNx), silicon oxide (SiOx), and silicon oxynitride (SiON), but is not limited thereto.

[0083] A light-blocking layer BSM is disposed on the multi-buffer layer 111. The light-blocking layer BSM minimizes the leakage current of the multiple transistors TR by blocking light incident from the lower part of the substrate 110 onto the active layer ACT of the transistor TR. Furthermore, the light-blocking layer BSM minimizes damage to the multiple transistors TR caused by charge trapped in the substrate 110. The light-blocking layer BSM can be connected to the source electrode SE or drain electrode DE of the transistor TR to minimize its influence on the threshold voltage of the transistor TR. The light-blocking layer BSM can be formed as a single layer or multiple layers made of, but is not limited to, one of, molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd) or alloys thereof.

[0084] An active buffer layer 112 is disposed on the light-blocking layer BSM. The active buffer layer 112 can protect the transistor TR from impurities such as alkali ions leaking from the substrate 110. In addition, the active buffer layer 112 can improve the adhesion between the layer formed above the active buffer layer 112 and the substrate 110. For example, the active buffer layer 112 can be formed of a single layer or multiple layers of insulating materials such as silicon nitride (SiNx), silicon oxide (SiOx), and silicon oxynitride (SiON), but is not limited thereto.

[0085] Transistor TR is disposed on active buffer layer 112. Transistor TR includes active layer ACT, gate electrode GE, source electrode SE, and drain electrode DE.

[0086] First, an active layer ACT is formed on the active buffer layer 112. The active layer ACT can be made of semiconductor materials such as oxide semiconductor, amorphous silicon or polycrystalline silicon, but is not limited to these.

[0087] A gate insulating layer 113 is disposed on the active layer ACT. The gate insulating layer 113 is an insulating layer used to insulate the active layer ACT and the gate electrode GE, and may consist of a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0088] The gate electrode GE is disposed on the gate insulating layer 113. The gate electrode GE may be a single layer or multiple layers made of a conductive material such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) or an alloy thereof, but is not limited thereto.

[0089] A first interlayer insulating layer 114 is disposed on the gate electrode GE, and a second interlayer insulating layer 115 is disposed on the first interlayer insulating layer 114. The first interlayer insulating layer 114 and the second interlayer insulating layer 115 are insulating layers used to protect the underlying structure, and can be composed of a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx), but are not limited thereto. Figure 3 As shown, the multi-buffer layer 111, the active buffer layer 112, the gate insulating layer 113, the first interlayer insulating layer 114, and the second interlayer insulating layer 115 can be collectively referred to as the insulating layer group IL.

[0090] The source electrode SE and drain electrode DE are disposed on the second interlayer insulating layer 115. The source electrode SE and drain electrode DE can be electrically connected to the active layer ACT through contact holes formed in the second interlayer insulating layer 115, the first interlayer insulating layer 114, and the gate insulating layer 113. The source electrode SE and drain electrode DE can be formed of a single layer or multiple layers of conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), gold (Au), chromium (Cr), or alloys thereof, but are not limited thereto.

[0091] A capacitor Cst is disposed on the gate insulating layer 113. The capacitor Cst may include a first capacitor electrode C1 and a second capacitor electrode C2. The first capacitor electrode C1 may be disposed on the gate insulating layer 113, and the second capacitor electrode C2 may be disposed on the first interlayer insulating layer 114. The first capacitor electrode C1 and the second capacitor electrode C2 may overlap each other, with the first interlayer insulating layer 114 interposed between them. For example, the first capacitor electrode C1 and the second capacitor electrode C2 may be a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), or their alloys, but are not limited thereto.

[0092] Simultaneously, various conductive layers can be disposed on the substrate 110. These conductive layers can constitute any one of multiple wirings, multiple transistors TR, and multiple capacitors Cst. For example, a first source-drain conductive layer SDL1 and a second source-drain conductive layer SDL2 can be disposed on the second interlayer insulating layer 115. The first source-drain conductive layer SDL1 can be connected to the first capacitor electrode C1, and the second source-drain conductive layer SDL2 can be connected to the second capacitor electrode C2. Each of the first source-drain conductive layer SDL1 and the second source-drain conductive layer SDL2 can be used as an electrode to connect the first capacitor electrode C1 and the second capacitor electrode C2 to other components of the sub-pixel SP.

[0093] A planarization layer 116 is disposed on the transistor TR. The planarization layer 116 is an insulating layer that planarizes the upper part of the substrate 110. The planarization layer 116 may be made of organic materials and may consist of a single layer or multiple layers of organic materials such as polyimide or photoacrylic acid, but is not limited thereto.

[0094] A light-emitting diode 120 is disposed on a planarization layer 116. The light-emitting diode 120 may be an organic light-emitting diode (OLED). The light-emitting diode 120 includes an anode 121, a light-emitting layer 122, and a cathode 123.

[0095] Anode 121 is disposed on planarization layer 116. Anode 121 can be connected to the drain electrode DE of transistor TR. Anode 121 can be formed of a conductive material with a high work function to supply holes to light-emitting layer 122. For example, anode 121 can be formed of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), but is not limited thereto.

[0096] Meanwhile, the display device 100 can be implemented in either a top-emitting or bottom-emitting manner. In the case of a top-emitting manner, a reflective layer can be disposed below the anode 121 to reflect light emitted from the light-emitting layer 122 toward the cathode 123. For example, the reflective layer may include a material with excellent reflectivity, such as aluminum (Al) or silver (Ag), but is not limited thereto. Conversely, in the case of a bottom-emitting manner, the anode 121 may be formed solely of a transparent conductive material. Hereinafter, the display device 100 according to exemplary embodiments of the present disclosure will be described assuming that the display device 100 is implemented in a top-emitting manner.

[0097] A barrier 117 is disposed on the anode 121 and the planarization layer 116. The barrier 117 may cover the edge of the anode 121. The barrier 117 may divide multiple sub-pixels SP and suppress color mixing between multiple sub-pixels SP. The barrier 117 may be an organic insulating material. For example, the barrier 117 may be made of any of, but is not limited to, polyimide, acrylic, and benzocyclobutene (BCB) based resins.

[0098] Spacer 130 is disposed on barrier 117. Spacer 130 can suppress potential damage to the light-emitting diode 120 when the fine metal mask (FMM) used to form the light-emitting layer 122 of the light-emitting diode 120 directly contacts barrier 117 or anode 121. Spacer 130 can be made of the same material as barrier 117, or it can be made of a different insulating material than barrier 117, but is not limited thereto. Furthermore, spacer 130 and barrier 117 can be integrally formed at one time. Since spacer 130 is disposed on barrier 117, cathode 123 can be configured to cover spacer 130 and barrier 117.

[0099] A light-emitting layer 122 is disposed on the anode 121 and the spacer 117. The light-emitting layer 122 can be an organic layer for emitting light of a specific color. The light-emitting layer 122 can further include various layers, such as a hole transport layer, a hole injection layer, a hole blocking layer, an electron injection layer, an electron blocking layer, and an electron transport layer. The light-emitting layer 122 can be formed individually for each sub-pixel SP, allowing each sub-pixel SP to emit a different color. For example, a red light-emitting layer 122, a green light-emitting layer 122, and a blue light-emitting layer 122 can be formed for each sub-pixel SP. Simultaneously, a light-emitting layer 122 for emitting white light can be formed together for multiple sub-pixels SP, and light conversion components for converting white light into various colors can be provided individually; however, the embodiments disclosed herein are not limited to this.

[0100] A cathode 123 is disposed on the light-emitting layer 122. The cathode 123 can be formed as a single layer spanning the entire surface of the substrate 110. That is, the cathode 123 can be a common layer formed for multiple sub-pixels SP. Since the cathode 123 supplies electrons to the light-emitting layer 122, the cathode 123 can be formed of a conductive material with a low work function. The cathode 123 can be formed of transparent conductive materials such as indium tin oxide (ITO) or indium zinc oxide (IZO), metal alloys such as MgAg, ytterbium (Yb) alloys, etc., and may further include metal doping layers, but is not limited thereto.

[0101] A protective layer 118 is disposed on the cathode 123. The protective layer 118 can protect the light-emitting diode 120 from foreign matter or moisture penetration. For example, the material of the protective layer 118 can be made of inorganic materials such as aluminum oxide (Al2O3) or silicon nitride (SiNx).

[0102] An encapsulation layer 140 is disposed on the protective layer 118. The encapsulation layer 140 can protect the light-emitting diode 120 from moisture and other substances that penetrate from the outside of the display device 100. The encapsulation layer 140 includes a first inorganic encapsulation layer 141, an organic encapsulation layer 142, and a second inorganic encapsulation layer 143.

[0103] A first inorganic encapsulation layer 141 is disposed on the protective layer 118, and a second inorganic encapsulation layer 143 is disposed on the first inorganic encapsulation layer 141. The first inorganic encapsulation layer 141 and the second inorganic encapsulation layer 143 can be used to block the penetration of moisture or oxygen. The first inorganic encapsulation layer 141 and the second inorganic encapsulation layer 143 can be made of inorganic materials, and for example, they can be made of inorganic materials such as silicon nitride (SiNx), silicon oxide (SiOx), or aluminum oxide (AlOx), but are not limited thereto.

[0104] An organic encapsulation layer 142 is disposed between the first inorganic encapsulation layer 141 and the second inorganic encapsulation layer 143. The organic encapsulation layer 142 may be formed to be thicker than the first inorganic encapsulation layer 141 and the second inorganic encapsulation layer 143 to adsorb and block foreign matter (particles) that may occur during the manufacturing process of the display device 100. The organic encapsulation layer 142 may fill cracks that may appear in the first inorganic encapsulation layer 141 and the second inorganic encapsulation layer 143, and cover foreign matter on the first inorganic encapsulation layer 141 to flatten the upper portion. The organic encapsulation layer 142 may be made of organic materials, and may be made of, for example, epoxy-based polymers or acrylic-based polymers, but is not limited thereto.

[0105] Touch unit 150 is disposed on encapsulation layer 140. Touch unit 150 can sense external touch input using a user's finger or stylus. Touch unit 150 includes touch buffer layer 151, bridging electrode BE, touch electrode TE, touch insulating layer 152, touch passivation layer 153, and touch protective layer 154.

[0106] First, a touch buffer layer 151 is disposed on the encapsulation layer 140. The touch buffer layer 151 is an insulating layer used to protect peripheral components such as the encapsulation layer 140 and the light-emitting diode 120 during the formation of the touch unit 150. The touch buffer layer 151 can minimize the penetration of moisture from the outside, materials used in the manufacturing process of the touch unit 150, etc., into the light-emitting diode 120. For example, the touch buffer layer 151 can be made of an insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0107] Multiple bridging electrodes BE are disposed on the touch buffer layer 151. The multiple bridging electrodes BE are electrodes made of bridging metal BM and can connect multiple touch electrodes TE to each other. For example, a pair of adjacent touch electrodes TE can be electrically connected to each other through bridging electrodes BE. For example, the multiple bridging electrodes BE can be formed from metals such as copper (Cu), aluminum (Al), titanium (Ti), chromium (Cr), nickel (Ni), or a laminated structure of metal materials such as titanium / aluminum / titanium (Ti / Al / Ti), for example, but not limited to these.

[0108] A touch insulating layer 152 is disposed on the bridging electrodes BE. The touch insulating layer 152 is disposed between the plurality of bridging electrodes BE and the plurality of touch electrodes TE, and can insulate some of the bridging electrodes BE from some of the touch electrodes TE. The touch insulating layer 152 may be made of an insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0109] Multiple touch electrodes TE are disposed on the touch insulating layer 152. The multiple touch electrodes TE are electrodes made of sensor metal SM and are used for sensing touch input. For example, when the touch unit 150 senses touch input using mutual capacitance, the multiple touch electrodes TE can be made of a touch driving electrode to which a touch driving signal is applied and a touch sensing electrode that forms a capacitance with the touch driving electrode. Furthermore, touch input can be sensed based on the capacitance change between the touch driving electrode and the touch sensing electrode. Here, the bridging metal BM and the sensor metal SM can be collectively referred to as touch metal TM.

[0110] However, the touch sensing method of the touch unit 150 is exemplary, and the touch unit 150 may use a self-capacitance method to sense touch input, but is not limited thereto.

[0111] A touch passivation layer 153 is disposed on multiple touch electrodes TE. The touch passivation layer 153 is an insulating layer used to protect the multiple touch electrodes TE and multiple bridging electrodes BE, and can suppress corrosion of the multiple touch electrodes TE and multiple bridging electrodes BE caused by external moisture, etc. For example, the touch passivation layer 153 can be made of an insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0112] A touch protection layer 154 is disposed on the touch passivation layer 153. The touch protection layer 154, together with the touch passivation layer 153, can protect multiple touch electrodes TE and multiple bridging electrodes BE from external moisture or impact. For example, the touch protection layer 154 can be made of organic materials such as epoxy-based or acrylic-based polymers, but is not limited thereto.

[0113] Meanwhile, in the figure, the touch passivation layer 153 is depicted as being disposed below the touch protection layer 154, but the touch passivation layer 153 may also be formed on the touch protection layer 154, and is not limited thereto.

[0114] refer to Figure 4 The pads (PAD) and multiple wirings are located in the non-active area (NA).

[0115] The pad portion (PAD) is the part electrically connected to multiple flexible film COFs and may include multiple pad electrodes (PE) and multiple touch pad electrodes (TPE) (see reference). Figure 8 Each of the multiple pad electrodes PE can transmit signals from the printed circuit board (PCB) and flexible film COF to various wirings of the display panel PN. Additionally, multiple touch pad electrodes TPE can transmit signals from the PCB and flexible film COF to the touch line TL of the touch unit 150. Pad portions PAD can be exposed from the encapsulation layer 140 to connect with the flexible film COF. The pad portions PAD can be disposed on the outside of the encapsulation layer 140.

[0116] The wiring associated with driving the display device 100 (i.e., image display) is located in the non-active area NA. For example, multiple low-potential power lines VSSL, LOG (Line On Glass) lines LOG, multiple high-potential power lines VDDL, multiple reference lines RL, and multiple data lines DL can be located in the non-active area NA.

[0117] Multiple low-potential power lines (VSSLs) are positioned within the non-active area NA. These VSSLs are lines used to apply low-potential power voltages to multiple sub-pixels (SPs). Some of the VSSLs extending from the pad portion (PAD) can extend to surround the perimeter of the active area AA. Furthermore, other VSSLs extending from the pad portion (PAD) can be configured to cover the data line (DL), thus acting as a protective layer to suppress the influence of the data line (DL) on other lines.

[0118] Multiple high-potential power lines VDDL are disposed in the inactive area NA. These multiple high-potential power lines VDDL are wirings used to apply high-potential power voltages to multiple sub-pixels SP. A short strip of high-potential power lines VDDL is provided extending along a first direction D1 between the active area AA and the pad portion PAD. Furthermore, multiple high-potential power lines VDDL extending from the pad portion PAD along a second direction D2 can be connected to the short strip of high-potential power lines VDDL. In this case, a portion of the multiple high-potential power lines VDDL extending from the pad portion PAD along the second direction D2 can be disposed between multiple low-potential power lines VSSL. Therefore, by forming a short strip of high-potential power lines VDDL connecting multiple high-potential power lines VDDL in the inactive area NA, the resistance deviation between the multiple high-potential power lines VDDL can be reduced, and brightness uniformity can be improved.

[0119] In the inactive region NA, a reference line RL is positioned between a high-potential power line VDDL and a low-potential power line VSSL. A short strip reference line RL extending along a first direction D1 can be positioned between the active region AA and the pad portion PAD, and multiple reference lines RL extending from the pad portion PAD along a second direction D2 can be connected to the short strip reference line RL. At this time, the high-potential power line VDDL, on the same layer as the reference line RL, is positioned between the short strip reference line RL and the reference line RL connected to the pad portion PAD. Therefore, at the point where the reference line RL and the high-potential power line VDDL intersect, an auxiliary reference line RLa located on a different layer than the high-potential power line VDDL can be used to connect the short strip reference line RL and the reference line RL connected to the pad portion PAD. Therefore, by forming a short strip reference line RL connecting multiple reference lines RL in the inactive region NA, the resistance deviation between the multiple reference lines RL can be reduced, and brightness uniformity can be improved.

[0120] In the non-active region NA, the LOG line LOG is positioned between the low-potential power line VSSL and the high-potential power line VDDL. The LOG line LOG is used to transmit various signals to the gate driver GD. For example, if the gate driver GD is mounted in the non-active region NA, the LOG line LOG extends from the pad portion PAD to the gate driver GD to transmit various signals to the gate driver GD.

[0121] Multiple data lines DL can be configured to extend from the pad portion PAD. Multiple data lines DL can also be configured to extend radially from the pad portion PAD. Multiple data lines DL can extend from the pad portion PAD to the active area AA, thereby transmitting the data voltage Vdata to multiple sub-pixels SP within the active area AA.

[0122] At the same time, also refer to Figure 17 Between the short reference line RL and the effective area AA, a multiplexer circuit MUX, an electrostatic discharge protection circuit ESD, and an optical inspection transistor AP can also be installed. The multiplexer circuit MUX is used to distribute signals to multiple wirings, and can be used to control the output of each wiring. The electrostatic discharge protection circuit ESD protects the internal configuration of the display device 100 by releasing static electricity introduced from the outside. When checking whether the light-emitting diode 120 is on during the manufacturing process of the display device 100, the optical inspection transistor AP can be used to temporarily apply a signal to the light-emitting diode 120.

[0123] Simultaneously, the wiring located between the pad portion PAD and the active area AA can also be called a link line LL. That is, some wiring located in the inactive area NA can be defined as link lines LL. For example, to distinguish some data lines DL located in the active area AA from the remaining data lines DL located in the inactive area NA, the remaining data lines DL located in the inactive area NA can be called data link lines LL. Similarly, some high-potential power lines VDDL, low-potential power lines VSSL, and reference lines RL located in the inactive area NA can also be called high-potential power lines LL, low-potential power lines LL, reference link lines LL, etc. Therefore, the following description will assume that link lines LL define some wiring located in the inactive area NA.

[0124] Next, let's refer to... Figure 3 and Figure 5A Some configurations for the effective region AA can be set to extend to the ineffective region NA.

[0125] At the same time, Figure 5A For ease of explanation, the multi-buffer layer 111, active buffer layer 112, gate insulating layer 113, first interlayer insulating layer 114, and second interlayer insulating layer 115 are simply referred to as insulating layer group IL. However, in practice, the multi-buffer layer 111, active buffer layer 112, gate insulating layer 113, first interlayer insulating layer 114, and second interlayer insulating layer 115 can be disposed between the substrate 110 and the low-potential power line VSSL.

[0126] Encapsulation layer 140 may be configured to cover the entire effective region AA and a portion of the ineffective region NA extending from the effective region AA. For example, the organic encapsulation layer 142 of encapsulation layer 140 may be configured in the region from the effective region AA to the dam member DAM in the ineffective region NA. Furthermore, the first inorganic encapsulation layer 141 and the second inorganic encapsulation layer 143 may extend to the region outside the dam member DAM. The first inorganic encapsulation layer 141 and the second inorganic encapsulation layer 143 extending to the region outside the dam member DAM may contact each other to seal the organic encapsulation layer 142.

[0127] Simultaneously, the second inorganic encapsulation layer 143 can be configured to cover the entire first inorganic encapsulation layer 141 in at least a portion of the ineffective region NA. The second inorganic encapsulation layer 143 can cover the edge of the first inorganic encapsulation layer 141, thereby minimizing the lifting of the first inorganic encapsulation layer 141.

[0128] Compared to inorganic insulating layers, organic insulating layers, such as the spacer 117 and planarization layer 116, made of organic materials, are relatively susceptible to moisture penetration. Therefore, the edges of the spacer 117 and planarization layer 116 can be located in regions within the encapsulation layer 140. For example, the edges of the spacer 117 and planarization layer 116 can be located in regions within the encapsulation layer 140 and can be located on the low-potential power line VSSL.

[0129] At least some of the multiple insulating layers of the touch unit 150 may be configured to extend from the active region AA to the inactive region NA. For example, touch buffer layer 151, touch insulating layer 152, etc., may extend to the outside of encapsulation layer 140 and cover the edge of encapsulation layer 140. For example, touch passivation layer 153 may extend from the active region AA to a region inside the dam member DAM. For example, touch protective layer 154 may extend from the active region AA to a region outside the dam member DAM. However, touch protective layer 154 may only be provided in the region overlapping with organic encapsulation layer 142, but is not limited thereto.

[0130] Furthermore, the active touch area TAA, where the touch electrode TE is located, can be set to be a portion extending from the active area AA to the inactive area NA. Within the active touch area TAA, the touch electrode TE and the bridging electrode BE are configured to sense touch input. The active touch area TAA can be formed to be larger than the active area AA.

[0131] Outside the active touch area TAA within the non-active area NA, i.e., in the area where touch input is not sensed, a ground wire GND and a pseudo-wire PS can also be set. The ground wire GND and pseudo-wire PS can reduce noise such as electromagnetic interference and improve touch performance, which will be described in more detail later.

[0132] Multiple crack suppression patterns (CSPs) are disposed in the non-effective region NA. During the manufacture of the display device 100, the configuration of the display device 100 is formed on a mother substrate, and the mother substrate can be cut into multiple pieces to manufacture multiple display devices 100. However, during the cutting of the mother substrate, cracks may occur in the substrate 110 or in the configuration on the substrate 110 at its edge due to impact. Multiple crack suppression patterns (CSPs) are disposed along the edge of the substrate 110 and can suppress crack propagation into the display device 100. Multiple crack suppression patterns (CSPs) can be formed by patterning some of the multiple insulating layers on the substrate 110. For example, the multiple crack suppression patterns (CSPs) can be formed from a multilayer structure of organic and inorganic insulating layers, but are not limited thereto.

[0133] A dam member DAM is disposed outside the organic encapsulation layer 142 in the non-active region NA. The dam member DAM is configured to suppress overflow of the organic encapsulation layer 142 of the encapsulation layer 140. The dam member DAM can be configured to surround the active region AA. The dam member DAM can be configured to surround the organic encapsulation layer 142 of the encapsulation layer 140. The dam member DAM can be formed into a closed loop shape that closes the active region AA and the organic encapsulation layer 142. The dam member DAM can be disposed on the low-potential power line VSSL while surrounding the organic encapsulation layer 142.

[0134] The dam component DAM may include a first dam component DAM1 and a second dam component DAM2. The first dam component DAM1 may be disposed between the second dam component DAM2 and the organic encapsulation layer 142. The first dam component DAM1 and the second dam component DAM2 may be formed from each of a plurality of insulating layers on the substrate 110.

[0135] For example, refer to Figure 6A The first dam component DAM1 can be formed by a planarization layer pattern 116a made of the same material as the planarization layer 116 and a spacer pattern 130a made of the same material as the spacer 130. The second dam component DAM2 can be formed by the planarization layer pattern 116a, a dike pattern 117a made of the same material as the dike 117 and a spacer pattern 130a.

[0136] refer to Figure 6B Each of the first dam component DAM1 and the second dam component DAM2 can be formed by a planarization layer pattern 116a, a dike pattern 117a, and a spacer pattern 130a. The dike pattern 117a of the second dam component DAM2 can be configured to cover the side surface of the planarization layer pattern 116a.

[0137] refer to Figure 6C The first dam component DAM1 can be formed by a planarization layer pattern 116a and a spacer pattern 130a, and the second dam component DAM2 can be formed by a planarization layer pattern 116a, a dike pattern 117a, and a spacer pattern 130a. In this case, the spacer pattern 130a of the second dam component DAM2 can be formed by a plurality of slit patterns.

[0138] Therefore, as Figures 6A to 6C As shown, the dam component DAM can be composed of a combination of various insulating layers.

[0139] Next, refer to Figure 5BThe pad electrode PE is positioned in the non-active area NA. The pad electrode PE can transmit signals from the flexible film COF and the printed circuit board (PCB) to the link line LL and the wiring. For example, the link line LL is positioned on the insulating layer group IL in the non-active area NA, and the pad electrode PE is positioned on the link line LL. The link line LL can transmit signals from the pad electrode PE to the wiring in the active area AA.

[0140] Multiple gate conductive layers (GATs) can be disposed between insulating layer groups (ILs) in the non-active region (NA). Multiple gate conductive layers (GATs) can be included in various configurations and, for example, can form link lines (LLs), gate drivers (GDs), etc.

[0141] A planarization layer dam 116P is disposed between the pad electrode PE and the dam member DAM in the non-effective region NA. Since the planarization layer dam 116P is spaced apart from the planarization layer 116 in the effective region AA, moisture penetration into the effective region AA via the planarization layer dam 116P can be suppressed. Furthermore, the planarization layer dam 116P can compensate for steps in the dam member DAM, thereby minimizing disconnections such as those caused by steps in the touch line TL.

[0142] And refer to them together Figure 2 and Figure 7 The dam component DAM is configured as a closed-loop shape surrounding the effective area AA, such that at least some of the wiring extending from the pad portion PAD to the effective area AA can intersect with the dam component DAM. Specifically, the encapsulation layer 140 and the touch unit 150 can be formed after the dam component DAM is formed. Furthermore, the wiring of the touch unit 150 (e.g., the link line LL as touch line TL, pseudo line PS, and ground line GND) can pass through the dam component DAM. In this case, the link line LL passing through the dam component DAM may be prone to disconnection due to the step of the dam component DAM. Therefore, the width of the link line LL overlapping with the dam component DAM can be formed to suppress disconnection of the link line LL in the dam component DAM.

[0143] In the following text, reference will be made to Figures 8 to 23B The touch unit 150 of the display device 100 according to an exemplary embodiment of the present disclosure will be described in more detail.

[0144] Figure 8 and Figure 9 This is a schematic plan view of the touch unit of a display device according to an exemplary embodiment of the present disclosure. Figure 10 This is a schematic enlarged plan view of the touch unit of a display device according to an exemplary embodiment of the present disclosure. Figure 11 and Figure 12 This is a schematic enlarged plan view of the touch unit of a display device according to an exemplary embodiment of the present disclosure.

[0145] First, the touch unit 150 can sense touch input using either the mutual capacitance method or the self-capacitance method. The mutual capacitance method senses touch input based on the capacitance change between the touch driving electrode and the touch sensing electrode. The self-capacitance method senses touch input based on the capacitance change between an external input and the touch electrode.

[0146] In the following explanation, it will be assumed that the touch unit 150 of the display device 100 according to the exemplary embodiments of the present disclosure is a touch unit 150 that uses a combination of mutual capacitance method and self capacitance method.

[0147] refer to Figure 8 and Figure 9 The touch unit 150 includes multiple touch lines TL and multiple touch electrodes TE. The multiple touch lines TL include multiple first touch lines TL1 and multiple second touch lines TL2, and the multiple touch electrodes TE include multiple first touch electrodes TE1 and multiple second touch electrodes TE2. In this case, as... Figure 8 and Figure 9 As shown, the shape and arrangement of the multiple touch electrodes TE of the touch unit 150, as well as the connection structure between the touch electrodes TE and the touch line TL, can be configured in various ways.

[0148] For example, refer to Figure 8 Multiple first touch electrodes TE1 can be arranged in a matrix at predetermined intervals. Each of the multiple first touch electrodes TE1 can be formed as a rhombus. Furthermore, among the multiple first touch electrodes TE1, the first touch electrodes TE1 arranged along the same line along the first direction D1 can be connected to each other. For example, the first touch electrodes TE1 in the nth row can be electrically connected to each other to form a line of first touch electrodes TE1.

[0149] Multiple second touch electrodes TE2 can be arranged in a matrix at predetermined intervals. Each of the multiple second touch electrodes TE2 can be formed as a rhombus. The multiple second touch electrodes TE2 can be staggered with multiple first touch electrodes TE1. Among the multiple second touch electrodes TE2, second touch electrodes TE2 arranged on the same line along the second direction D2 can be connected. For example, the second touch electrodes TE2 in the nth column can be electrically connected to each other to form a line of second touch electrodes TE2. Therefore, the lines of the first touch electrodes TE1 and the lines of the second touch electrodes TE2 can intersect each other.

[0150] Multiple first touch lines TL1 are electrically connected to multiple first touch electrodes TE1. The multiple first touch lines TL1 are electrically connected to the first touch pad electrode TPE1 among multiple touch pad electrodes TPE1, and can transmit touch signals from the first touch pad electrode TPE1 to the multiple first touch electrodes TE1. For example, the first touch lines TL1 can be connected to both ends of a line of a single first touch electrode TE1 composed of multiple first touch electrodes TE1 arranged in the same row. By supplying touch signals to both ends of the line of the first touch electrode TE1, signal delay can be minimized.

[0151] Multiple second touch lines TL2 are electrically connected to multiple second touch electrodes TE2. These multiple second touch lines TL2 are electrically connected to second touch pad electrodes TPE2 among multiple touch pad electrodes TPE, and the second touch pad electrodes TPE2 and the multiple second touch electrodes TE2 can be electrically connected to each other. For example, a second touch line TL2 can be connected to one end of a line of a single second touch electrode TE2, which is composed of multiple second touch electrodes TE2 arranged in the same row.

[0152] Figure 8 The touch unit 150 may be configured with a dual-feeding structure that simultaneously applies signals to both ends of a line of a touch electrode TE. For example, as the size of the display device 100 increases, the length of a line of touch electrodes TE formed by the same line may increase, and signal transmission may be delayed depending on the position of the touch electrode TE. Therefore, in order to reduce the time deviation between sending and receiving touch signals, one or more touch lines TL may be connected to the same line constituting the touch electrode TE to minimize signal delay.

[0153] Next, refer to Figure 9 Multiple first touch electrodes TE1 can be arranged in a matrix at predetermined intervals. Each of the multiple first touch electrodes TE1 can have a rectangular shape. Among the multiple first touch electrodes TE1, the first touch electrodes TE1 arranged along the same line along the first direction D1 can receive signals simultaneously. For example, multiple first touch pad electrodes TPE1 are arranged in an inactive area NA, and the nth first touch line TL1 electrically connected to the nth first touch pad electrode TPE1 among the multiple first touch pad electrodes TPE1 can be connected to the multiple first touch electrodes TE1 arranged on the same line.

[0154] Multiple second touch electrodes TE2 can be disposed between multiple first touch electrodes TE1. Each of the multiple second touch electrodes TE2 can have a rectangular shape. For example, the multiple first touch electrodes TE1 and multiple second touch electrodes TE2 can be alternately disposed in a first direction D1. The first touch electrodes TE1 and the second touch electrodes TE2 can be disposed in the same row, and the first touch electrodes TE1 and the second touch electrodes TE2 can be disposed in different columns. Among the multiple second touch electrodes TE2, the second touch electrodes TE2 disposed along the same line in the second direction D2 can receive signals simultaneously. For example, multiple second touch pad electrodes TPE2 are disposed in an inactive area NA, and the nth second touch line TL2 electrically connected to the nth second touch pad electrode TPE2 among the multiple second touch pad electrodes TPE2 can be connected to the multiple second touch electrodes TE2 disposed on the same line.

[0155] Multiple first touch lines TL1 are electrically connected to multiple first touch electrodes TE1. Multiple first touch lines TL1 are electrically connected to the first touch pad electrode TPE1 among multiple touch pad electrodes TPE, and can transmit touch signals from the first touch pad electrode TPE1 to the multiple first touch electrodes TE1.

[0156] Multiple second touch lines TL2 are electrically connected to multiple second touch electrodes TE2. The multiple second touch lines TL2 can be electrically connected to the second touch pad electrodes TPE2 in multiple touch pad electrodes TPE, and the second touch pad electrodes TPE2 and the multiple second touch electrodes TE2 can be electrically connected to each other.

[0157] at the same time, Figure 9 The touch unit 150 can be configured with a multi-feeding structure that simultaneously applies signals to multiple touch electrodes TE. For example, as the size of the display device 100 increases, the length of a single touch electrode TE formed by touch electrodes TE on the same line may increase, and signal transmission may be delayed depending on the position of the touch electrode TE. Therefore, in order to reduce the time deviation between sending and receiving touch signals, the touch line TL can be connected to each of the multiple touch electrodes TE on the same line constituting the touch electrode TE, thereby allowing signals to be applied simultaneously. Therefore, by connecting multiple touch lines TL to each of the multiple touch electrodes TE in a one-to-one correspondence, the delay of touch signals can be reduced, and the touch performance of the entire area of ​​the display device 100 can be improved.

[0158] Furthermore, the multiple first touch electrodes TE1 can be touch driving electrodes, and the multiple second touch electrodes TE2 can be touch sensing electrodes. Further, the multiple first touch lines TL1 can be touch driving lines, and the multiple second touch lines TL2 can be touch sensing lines. In this case, the touch driver TD can send touch driving signals to the first touch electrodes TE1 through the first touch lines TL1, and receive touch sensing signals from the second touch electrodes TE2 through the second touch lines TL2.

[0159] However, the first touch electrode TE1 and the first touch line TL1 can both be touch sensing electrodes and touch sensing lines, and the second touch electrode TE2 and the second touch line TL2 can both be touch driving electrodes and touch driving lines, and the embodiments of this disclosure are not limited thereto.

[0160] refer to Figure 10 The multiple touch electrodes TE can further include multiple dummy touch electrodes DTE. The dummy touch electrodes DTE can be positioned between the multiple first touch electrodes TE1 and the multiple second touch electrodes TE2. For example, the dummy touch electrodes DTE can be positioned between the first touch electrodes TE1 and the second touch electrodes TE2. For example, the multiple touch electrodes TE and the multiple dummy touch electrodes DTE can be positioned at equal intervals. By setting the dummy touch electrodes DTE, the distance between the first touch electrodes TE1 and the second touch electrodes TE2 can be ensured, and the initial capacitance value between the first touch electrodes TE1 and the second touch electrodes TE2 can be reduced.

[0161] Touch input can be sensed by sensing the capacitance between the first touch electrode TE1 and the second touch electrode TE2. In this case, as the first touch electrode TE1 and the second touch electrode TE2 get closer, the initial capacitance value between the first touch electrode TE1 and the second touch electrode TE2 may increase, making it somewhat difficult to sense the capacitance change.

[0162] For example, when the first touch electrode TE1 and the second touch electrode TE2 are set with a first interval that does not have a dummy touch electrode DTE, it can be assumed that the initial capacitance value between the first touch electrode TE1 and the second touch electrode TE2 is 100, and the capacitance change upon touch input is 10. As a result, the capacitance value after touch input is 110. In this case, the difference between the initial capacitance value 100 and the capacitance value 110 after touch input is very small, so it may be difficult to detect the touch to some extent.

[0163] Furthermore, when a dummy touch electrode (DTE) is formed between the first touch electrode TE1 and the second touch electrode TE2, the gap between them increases. Therefore, the initial capacitance value between the first touch electrode TE1 and the second touch electrode TE2 can be reduced. For example, when the dummy touch electrode DTE is positioned between the first touch electrode TE1 and the second touch electrode TE2, the gap between them can be increased by the width of the first gap and the dummy touch electrode DTE. Therefore, the initial capacitance value can be reduced to a value less than 100, such as 50. When the capacitance change during touch input is 10, the capacitance value after touch input is 60. In this case, the difference between the initial capacitance value of 50 and the capacitance value after touch input is relatively large, making touch detection easier.

[0164] Therefore, by placing the dummy touch electrode DTE between the first touch electrode TE1 and the second touch electrode TE2, the gap between the first touch electrode TE1 and the second touch electrode TE2 can be ensured, and the initial capacitance value between the first touch electrode TE1 and the second touch electrode TE2 can be reduced. Thus, the performance of the touch unit 150 can be improved.

[0165] Next, refer to Figure 9 and Figure 11 In the multi-feed structure touch unit 150, multiple first touch lines TL1 are arranged around multiple second touch electrodes TE2, and parasitic capacitance may be formed between the multiple first touch lines TL1 and the second touch electrodes TE2. When the parasitic capacitance between the multiple first touch lines TL1 and the second touch electrodes TE2 changes, the touch performance may be degraded. Therefore, in the display device 100 according to an exemplary embodiment of the present disclosure, the gap D between the second touch electrodes TE2 and the first touch lines TL1 can be uniformly formed, thereby minimizing the change in parasitic capacitance.

[0166] Specifically, multiple first touch lines TL1 can extend in the second direction D2 and be electrically connected to multiple first touch electrodes TE1 through contact holes. In this case, by offsetting the first touch line TL1 by one line in the first direction D1, the distance or gap D between the contact hole connecting the first touch electrode TE1 and the first touch line TL1 and the second touch electrode TE2 can be configured to be constant.

[0167] First, the regions of multiple first touch electrodes TE1 in the second direction D2, such as the region between the first touch electrode TE1(n) in the nth row and the first touch electrode TE1(n-1) in the (n-1)th row, and the region between the first touch electrode TE1(n) in the nth row and the first touch electrode TE1(n+1) in the (n+1)th row, can be defined as the offset regions where the first touch line TL1 is offset.

[0168] In the nth row, the nth first touch line TL1(n) can be set to be closest to the second touch electrode TE2. In the nth row, the contact hole connecting the nth first touch line TL1(n) and the first touch electrode TE1(n) and the second touch electrode TE2 can be set to be spaced apart from each other by a gap D.

[0169] Furthermore, the contact holes of the first touch electrode TE1(n) and the first touch line TL1(n) located to the right of the second touch electrode TE2 and the contact holes of the first touch electrode TE1(n) and the first touch line TL1(n) located to the left of the second touch electrode TE2 can be symmetrically arranged with respect to the second touch electrode TE2.

[0170] Furthermore, the first touch line TL1(n) of the nth row, used for transmitting signals to the first touch electrode TE1(n) of the nth row, is electrically connected to the nth first touch electrode TE1(n). Therefore, the first touch line TL1(n) is positioned to reach only the offset region between the nth first touch electrode TE1(n) and the (n-1)th first touch electrode TE1(n-1), and does not extend into the region of the (n-1)th first touch electrode TE1(n-1).

[0171] Furthermore, the first touch line TL1 to the (n-1)th first touch line TL1(n-1) can be offset in the first direction D1 within the offset region and extend again to the (n-1)th first touch electrode TE1(n-1). In the (n-1)th row, the (n-1)th first touch line TL1(n-1) is electrically connected to the first touch electrode TE1(n-1). Also, in the (n-1)th row, the contact hole connecting the (n-1)th first touch line TL1(n-1) to the first touch electrode TE1(n-1) and the second touch electrode TE2 can be spaced apart by a gap D.

[0172] Therefore, by offsetting the remaining first touch lines TL1 in the offset region, except for the nth first touch line TL1(n) connected to the nth first touch electrode TE1(n) and extending in the second direction D2, the gap D between the contact hole connecting the first touch electrode TE1 and the first touch line TL1 and the second touch electrode TE2 can be configured to be the same.

[0173] Meanwhile, multiple touch electrodes TE can have, for example Figure 11 The plate-like structure shown can also be formed with multiple touch electrodes TE as shown. Figure 12 The grid structure shown. Even when multiple touch electrodes TE are formed as... Figure 12 When the grid structure shown is used, an offset region can also be formed.

[0174] refer to Figure 12 Multiple touch electrodes TE can be formed into a grid structure, and the openings of the grid structure can overlap with each of the multiple sub-pixels SP. The metal of the multiple touch electrodes TE can be disposed in the region between the multiple sub-pixels SP. For example, the metal of the multiple touch electrodes TE can be disposed in an octagonal shape in the region between the sub-pixels SP.

[0175] The first touch line TL1 can extend along the metal forming the first touch electrode TE1 in the second direction D2. The first touch lines TL1 (such as touch lines TL1(n-3), TL1(n-2), and TL1(n-1)) can be electrically connected to the metal of the first touch electrode TE1 via contact holes in a region with a first gap to the second touch electrode TE2. Furthermore, multiple first touch lines TL1 can be offset in the first direction D1 in an offset region and then extend upwards again.

[0176] Therefore, the offset region can be formed in the touch unit 150 of various structures, thereby forming a constant gap between the contact hole connecting the first touch electrode TE1 and the first touch line TL1 and the second touch electrode TE2.

[0177] Figure 13 This is a schematic plan view of a display device according to an exemplary embodiment of the present disclosure. Figure 14 and Figure 15 yes Figure 13 A magnified plan view of region A3. Figure 16 yes Figure 14 An enlarged plan view of area A4. Figure 17 It is along Figure 16 The cross-sectional view taken from line C-C'. Figure 18 yes Figure 16 An enlarged plan view of area A5. Figure 19 yes Figure 13 An enlarged plan view of area A6. Figure 20 It is along Figure 19 The cross-sectional view taken by line D-D'. Figure 21 yes Figure 14 Enlarged plan view of area A7. Figure 22A yes Figure 14 An enlarged plan view of area A8. Figure 22B It is along Figure 22A The cross-sectional view taken from line E-E'. Figure 23A yes Figure 14 An enlarged plan view of area A8. Figure 23B It is along Figure 23A The cross-sectional view taken by line F-F'. For ease of explanation, in Figure 14 In the diagram, among the multiple wiring lines, the touch line TL, ground line GND, and pseudo line PS are drawn as solid lines, while the reference line RL, LOG line LOG, data line DL, and low-potential power line VSSL are drawn as dashed lines.

[0178] Please refer to the above. Figure 13 and Figure 14 The wiring associated with the touch unit 150 is located in the non-active area NA. For example, pseudo-line PS, multiple touch lines TL, and multiple ground lines GND can be located in the non-active area NA.

[0179] Meanwhile, the display device 100 according to an exemplary embodiment of the present disclosure has a TOE (Touch On Encap) structure in which the touch unit 150 is disposed on the encapsulation layer 140, and most of the wiring associated with the touch unit 150 can extend to the encapsulation layer 140. Therefore, Figure 4 The wiring associated with driving the display device 100 shown is... Figure 14 The wiring associated with the touch unit 150 shown can be disposed on different layers, and at least some of the wiring can be configured to be spaced apart from each other, with the encapsulation layer 140 inserted therebetween.

[0180] For ease of explanation, Figure 4 and Figure 14 In the wiring of the non-effective area NA, the wiring related to the driving display device 100 and the wiring related to the touch unit 150 are drawn as solid lines, but... Figure 4 and Figure 14 The wiring of the ineffective area NA shown in the figure actually overlaps with each other.

[0181] Furthermore, for ease of explanation, in Figure 4 and Figure 14 Each wire is represented as a single wire, but each wire can also consist of at least one group of wires. For example, in Figure 14 In the diagram, each of the touch lines TL and pseudo lines PS is depicted as a single wiring, but touch lines TL and pseudo lines PS can be composed of a set of multiple touch lines TL and a set of multiple pseudo lines PS.

[0182] refer to Figure 14 The multiple first touch lines TL1 include a portion extending from the pad portion PAD in a second direction D2 and another portion extending from that portion in a first direction D1 and configured as a closed loop. For example, this portion of the multiple first touch lines TL1 can be... Figure 9 The first touch pad electrode TPE1 of the pad portion PAD shown extends. For example, in the non-active area NA, multiple first touch lines TL1 can be formed by vertical line portions extending from the pad portion PAD toward the package layer 140 and horizontal line portions disposed on the package layer 140 having annular loops and empty spaces therein. Furthermore, the multiple first touch lines TL1 can branch from the horizontal line portions of the multiple first touch lines TL1 in the second direction D2 and can be connected to multiple first touch electrodes TE1 in the active area AA.

[0183] In this case, in the non-active area NA, the vertical line portions of multiple first touch lines TL1 can be connected to at least one area of ​​the pad portion PAD. For example, in Figure 14 In the middle, the vertical lines of multiple first touch lines TL1 are connected to two areas of the pad portion PAD, and in Figure 15 In the middle, the vertical line portion of multiple first touch lines TL1 can be connected to an area of ​​the pad portion PAD.

[0184] Furthermore, in the non-effective area NA, the horizontal portions of multiple first touch lines TL1 can form at least one loop. For example, in Figure 14 In the middle, the horizontal portion of multiple first touch lines TL1 can form a loop, and in Figure 15 In the middle, the horizontal section of multiple first touch lines TL1 can form two loops.

[0185] The multiple second touch lines TL2 include a portion extending from the pad portion PAD in a second direction D2, and another portion extending from that portion in a first direction D1 and configured as a strip. For example, this portion of the multiple second touch lines TL2 can be... Figure 9 The second touch pad electrode TPE2 extends from the pad portion PAD shown. For example, in the non-active area NA, multiple second touch lines TL2 can be formed by vertical line portions extending from the pad portion PAD toward the package layer 140 and horizontal line portions arranged in a strip shape on the package layer 140. The horizontal line portions of the multiple second touch lines TL2 can be arranged in the blank space within the horizontal line portions of the multiple first touch lines TL1. That is, the horizontal line portions of the multiple first touch lines TL1 arranged in a ring can be configured to surround the horizontal line portions of the multiple second touch lines TL2. Furthermore, the multiple second touch lines TL2 can branch from the horizontal line portions of the multiple second touch lines TL2 in the second direction D2 and connect to the multiple second touch electrodes TE2 of the active area AA.

[0186] Meanwhile, at least a portion of the multiple touch lines TL in the non-effective area NA can be located outside the encapsulation layer 140. In this case, in the area where the encapsulation layer 140 is not located, the touch lines TL and data lines DL are located relatively close to each other, so their signals may interfere with each other. Therefore, a constant voltage line capable of shielding the signal can be provided at the intersection of the data line DL and the touch line TL in the area outside the encapsulation layer 140 to minimize signal interference.

[0187] For example, a low-potential power line VSSL can be placed between multiple first touch lines TL1 and multiple data lines DL in the area outside the package layer 140, as well as between multiple second touch lines TL2 and multiple data lines DL, thereby minimizing signal interference between the touch signal and the data voltage Vdata and improving touch sensing performance.

[0188] For example, in the non-effective area NA, the horizontal line portions of multiple second touch lines TL2 extending in the second direction D2 can be configured to overlap with the short strip reference line RL. Therefore, the short strip reference line RL can be positioned between the horizontal line portions of multiple data lines DL and multiple second touch lines TL2, thereby serving as a protective layer to minimize signal interference between the multiple data lines DL and the second touch lines TL2.

[0189] Next, refer to Figure 14 Multiple pseudo-lines PS are positioned within the non-active area NA. The multiple pseudo-lines PS can be configured to surround the active area AA. When the display device 100 transmits and receives wireless signals with other devices, electromagnetic interference to the touch signal may occur, and the transmission and reception performance of the wireless signal, as well as the touch sensing performance, may deteriorate. The multiple pseudo-lines PS are wiring used to eliminate electromagnetic interference between the wireless signal and the touch signal, and electromagnetic interference can be eliminated by supplying pseudo-touch signals with a phase opposite to the touch drive signal to the multiple pseudo-lines PS.

[0190] refer to Figure 14 Multiple grounding wires GND are set between multiple touch lines TL and multiple pseudo lines PS. By releasing noise charges and other substances flowing into the display panel PN to the grounding voltage of the grounding wires GND, the touch lines TL and pseudo lines PS can be protected, and the touch sensing performance can be improved.

[0191] Some of the multiple grounding wires GND can extend along multiple touch lines TL and can be arranged adjacent to each of the multiple touch lines TL. For example, some of the multiple grounding wires GND can be arranged along the vertical and horizontal portions of multiple first touch lines TL1, and other grounding wires GND can be arranged along the vertical and horizontal portions of multiple second touch lines TL2. For example, other grounding wires GND can be arranged in a ring between the horizontal portions of the multiple first touch lines TL1 and the horizontal portions of the multiple second touch lines TL2, and can be formed in a ring. For example, other grounding wires GND can extend along multiple pseudo-lines PS and can be arranged adjacent to each of the multiple pseudo-lines PS.

[0192] In addition, refer to Figure 13 , Figure 14 , Figure 19 and Figure 20 In the non-active region NA, some of the multiple pseudo-lines PS and multiple ground lines GND can be disposed on the encapsulation layer 140, and the rest can be disposed in the region outside the encapsulation layer 140. For example, the multiple pseudo-lines PS may include a first pseudo-line PS1, a second pseudo-line PS2, a third pseudo-line PS3, a fourth pseudo-line PS4, and a fifth pseudo-line PS5. Among the multiple pseudo-lines PS, the first pseudo-line PS1 can be disposed in the region outside the encapsulation layer 140, and the second pseudo-line PS2, the third pseudo-line PS3, the fourth pseudo-line PS4, and the fifth pseudo-line PS5 can be disposed on the encapsulation layer 140.

[0193] The ground line GND can be positioned on both sides of the second pseudo-line PS2, the third pseudo-line PS3, the fourth pseudo-line PS4, and the fifth pseudo-line PS5 on the package layer 140. The ground line GND between the first pseudo-line PS1 and the second pseudo-line PS2 can alleviate the need for a configuration below multiple pseudo-lines PS (e.g., the gate driver GD (reference...)). Figure 5A Electromagnetic interference between the fifth pseudo-line PS5 and multiple pseudo-lines PS5. The grounding wire GND between the fifth pseudo-line PS5 and the effective area AA can act as a protective film, which suppresses the interaction between the configuration of the effective area AA and the pseudo-line PS, thereby reducing electromagnetic interference.

[0194] Furthermore, one or more pseudo-lines PS can be positioned in the area outside the package layer 140, and the ground line GND can be further positioned outside the pseudo-lines PS. For example, refer to Figure 5AOne or more dummy lines PS can be disposed in the area outside the encapsulation layer 140, and the ground wire GND can be disposed in the area outside the dummy lines PS. In addition, the outermost ground wire GND can discharge static electricity to protect other components inside the display device 100, including the dummy lines PS.

[0195] At the same time, Figure 13 , Figure 19 and Figure 20 The diagram shows five pseudo-lines PS1 to PS5, with only the first pseudo-line PS1 located outside the encapsulation layer 140. However, the arrangement and number of pseudo-lines PS can be varied taking into account the size of the ineffective region NA, the formation area of ​​the encapsulation layer 140, etc., and the embodiments of this disclosure are not limited thereto.

[0196] Next, refer to Figure 16 In the upper region of the first ineffective region NA, the width of the multiple first touch lines TL1 can be narrowed at the points where the multiple first touch lines TL1 intersect with the multiple second touch lines TL2. The width of the portion of the multiple first touch lines TL1 intersecting with the multiple second touch lines TL2 can be narrower than the width of the other portion not intersecting with the multiple second touch lines TL2. By configuring the width of the multiple first touch lines TL1 to be narrow at the points where the multiple first touch lines TL1 intersect with the multiple second touch lines TL2, interference between the multiple first touch lines TL1 and the multiple second touch lines TL2 can be minimized.

[0197] Please refer to the above. Figure 16 and Figure 17 The first touch line TL1, the second touch line TL2, and the ground line GND can be formed as a dual-wire structure. For example, each of the first touch line TL1, the second touch line TL2, and the ground line GND can be formed as a dual-layer structure of a bridging metal BM on the touch buffer layer 151 and a sensor metal SM on the touch insulating layer 152. Furthermore, the bridging metal BM and the sensor metal SM of each of the first touch line TL1, the second touch line TL2, and the ground line GND can be connected to each other through contact holes in the touch insulating layer 152.

[0198] In this case, at the intersection of the first touch line TL1 and the second touch line TL2, the first touch line TL1 and the second touch line TL2 can use different metals. For example, at the intersection of the first touch line TL1 and the second touch line TL2, the first touch line TL1 can be composed only of the bridging metal BM on the touch insulating layer 152, and the second touch line TL2 can be composed only of the sensor metal SM between the touch buffer layer 151 and the touch insulating layer 152.

[0199] Simultaneously, in the non-active region NA, the cathode 123 can be electrically connected to the low-potential power line VSSL using the anode pattern 121a. For example, in the non-active region NA, the anode pattern 121a, made of the same material as the anode 121, can be connected to the low-potential power line VSSL. Furthermore, an opening exposing the anode pattern 121a can be formed in the dike 117, and the cathode 123 can extend from the active region AA to this opening. Therefore, the cathode 123, the anode pattern 121a, and the low-potential power line VSSL can be electrically connected to each other.

[0200] Furthermore, in the non-active area NA, the multiplexer circuit MUX, the optical inspection transistor AP, and the electrostatic discharge protection circuit ESD are located below the touch unit 150. Additionally, [further details can be added]. Figure 4 The short strip reference line RL, the high-potential power line VDDL, and the low-potential power line VSSL are described in the text.

[0201] Next, refer to Figure 18 In the region below the first ineffective region NA, the width of the multiple second touch lines TL2 can be changed at the point where the multiple first touch lines TL1 intersect with the multiple second touch lines TL2 to compensate for the capacitance change of each of the multiple touch lines TL.

[0202] For example, depending on the shape of the display device 100, the position of the touch electrodes TE, etc., each of the multiple touch lines TL can have a different length. For example, when the display device 100 has a non-rectangular shape, the length of the multiple touch lines TL can vary with the area. When the lengths of the touch lines TL are different, the capacitance can change depending on the difference in the overlap size between the touch lines TL. For example, when the lengths of the multiple second touch lines TL2 are different, the overlap size between each of the multiple second touch lines TL2 and the first touch line TL1 is not the same, and the capacitance value between each of the multiple second touch lines TL2 and the first touch line TL1 can also vary. Therefore, by changing the width of the second touch lines TL2, the overlap size between the first touch line TL1 and the second touch lines TL2 and the resulting capacitance value can be controlled.

[0203] For example, when the leftmost second touch line TL2 among the three second touch lines TL2 has a shorter length, the width of the second touch line TL2 can be widened in three regions of the intersection area between the leftmost second touch line TL2 and the multiple first touch lines TL1. Therefore, the overlap between the first touch lines TL1 and the second touch lines TL2 can be increased, and the capacitance can be increased. For example, when the rightmost second touch line TL2 among the three second touch lines TL2 has a longer length, the width of the second touch line TL2 can be widened only in one region of the intersection area between the second touch line TL2 and the multiple first touch lines TL1. Furthermore, the width of the second touch line TL2 can vary in the intersection areas with different first touch lines TL1. Therefore, by changing the width of the second touch line TL2 at the intersection of the first touch lines TL1 and the second touch line TL2, the capacitance variation of each of the multiple touch lines TL can be reduced.

[0204] Also refer to Figure 21 and Figure 5A The area where the LOG line is set is the area where the gate driver GD is set, and the scan signal driver SCAN driver or the light emission signal driver EM driver that constitutes the gate driver GD can be set together. For example, in the inactive area NA, the light emission signal driver EM driver and the scan signal driver SCAN driver can be set, and the LOG line LOG, such as the transmit clock signal line EM CLK, can be set between the light emission signal driver EM driver and the scan signal driver SCAN driver.

[0205] In this case, multiple pseudo-lines PS can be set in the inactive region NA and can overlap with the gate driver GD (see reference). Figure 5ATherefore, electromagnetic interference may occur between the multiple pseudo-lines PS and the gate driver GD. Thus, the width of the ground line GND, which is adjacent to the multiple pseudo-lines PS and overlaps with the gate driver GD, can be made relatively wide. For example, the ground line GND can be configured to cover all scan signal drivers (SCAN Driver) and light emission signal drivers (EM Driver) of the gate driver GD and the LOG line LOG. For example, the width of the ground line GND overlapping with the gate driver GD can be wider than the width of the gate driver GD. For example, the width of the ground line GND overlapping with the gate driver GD is greater than the sum of the widths of the scan signal driver SCAN Driver and the light emission signal driver EM Driver. The ground line GND can act as a protective film that shields the signal of the gate driver GD from affecting the multiple pseudo-lines PS. Therefore, by forming a ground line GND with a wide width that overlaps with the gate driver GD and is located on one side of the multiple pseudo-lines PS, electromagnetic interference between the gate driver GD and the pseudo-lines PS can be minimized.

[0206] Next, refer to Figure 22A and Figure 22B In addition to the multiple pad electrodes PE connected to the wiring associated with the touch unit 150, the pad portion PAD may further include multiple touch pad electrodes TPE connected to the wiring associated with the driving display panel PN. The multiple touch pad electrodes TPE can be formed in various structures.

[0207] For example, refer to Figure 22A and Figure 22B The touch pad electrode (TPE) is disposed on the pad portion (PAD). A flexible film (COF) can be bonded to the touch pad electrode (TPE) to connect the touch driver (TD) and the touch unit 150. The touch pad electrode (TPE) includes a first pad conductive layer (TPEa) and a second pad conductive layer (TPEb) located on the first pad conductive layer (TPEa).

[0208] The first pad conductive layer TPEa is disposed between the second interlayer insulating layer 115 and the planarization layer 116, and the planarization layer 116 includes an opening 116O through which the first pad conductive layer TPEa is exposed. The opening 116O of the planarization layer 116 may have a smaller size than the first pad conductive layer TPEa.

[0209] The second pad conductive layer TPEb is disposed on the planarization layer 116. The second pad conductive layer TPEb can contact the first pad conductive layer TPEa at the opening 116O of the planarization layer 116. The second pad conductive layer TPEb can be formed using the same material and the same process as the conductive layer of the touch electrode TE. The second pad conductive layer TPEb can have a smaller size than the opening 116O of the planarization layer 116.

[0210] refer to Figure 23A and Figure 23B The touch pad electrode TPE includes a first pad conductive layer TPEa and a second pad conductive layer TPEb on the first pad conductive layer TPEa.

[0211] The first pad conductive layer TPEa is disposed between the second interlayer insulating layer 115 and the planarization layer 116, and the planarization layer 116 includes an opening 116O through which the first pad conductive layer TPEa is exposed. The opening 116O of the planarization layer 116 may have a smaller size than the first pad conductive layer TPEa.

[0212] At least one insulating layer of the touch unit 150 is disposed on the planarization layer 116, and a second pad conductive layer TPEb is disposed on the insulating layer of the touch unit 150. For example, a touch buffer layer 151 may be disposed between the planarization layer 116 and the second pad conductive layer TPEb. The touch buffer layer 151 may overlap with an opening 1160 of the planarization layer 116 and has an opening smaller than the opening 1160 of the planarization layer 116. The second pad conductive layer TPEb can contact the first pad conductive layer TPEa through the opening of the touch buffer layer 151 and the opening 1160 of the planarization layer 116.

[0213] However, in addition to the touch buffer layer 151 between the planarization layer 116 and the second pad conductive layer TPEb, a touch insulating layer 152 may be additionally provided, or a touch insulating layer 152 may be provided to replace the touch buffer layer 151, but this disclosure is not limited thereto.

[0214] In this configuration, multiple link lines LL can be positioned beneath multiple touch pad electrodes TPE. These link lines LL can be composed of various conductive layers. For example, see reference... Figure 22B Multiple interconnect lines LL can be disposed between the gate insulating layer 113 and the first interlayer insulating layer 114, and can be connected to another touch pad electrode TPE or another pad electrode PE. As another example, refer to... Figure 23B Some of the multiple link lines LL can be disposed between the gate insulating layer 113 and the first interlayer insulating layer 114, and some of the other multiple link lines LL can be disposed between the first interlayer insulating layer 114 and the second interlayer insulating layer 115.

[0215] Therefore, in the display device 100 according to an exemplary embodiment of the present disclosure, the touch unit 150 is disposed on the encapsulation layer 140, and various configurations can be provided to improve the performance of the touch unit 150. For example, offset regions can be formed in which multiple first touch lines TL1 are offset and extended between multiple first touch electrodes TE1. Therefore, the gap between the contact hole connecting the first touch line TL1 and the first touch electrode TE1 and the second touch electrode TE2 can be formed to be constant, and the parasitic capacitance between the first touch line TL1 and the second touch electrode TE2 can be configured to be uniform. For example, the delay of the touch signal can be minimized by applying a dual-feed structure that connects one or more touch lines TL to a single touch electrode TE, or a multi-feed structure that connects touch lines TL to each of the touch electrodes TE.

[0216] As another example, multiple pseudo-lines PS, to which a signal with a phase opposite to that of the touch line TL is applied, can be placed in the inactive area NA to suppress electromagnetic interference that occurs during the transmission and reception of wireless signals. For example, a ground line GND can be placed around the multiple pseudo-lines PS to minimize interference between the signals of the multiple pseudo-lines PS and the gate driver GD, and to protect other components of the display device 100, including the multiple pseudo-lines PS, from electrostatic discharge. For example, in the inactive area NA, various lines for driving the display panel PN and various wiring for driving the touch unit 150 can overlap each other. Therefore, the data line DL and the touch line TL can overlap each other, and a low-potential power line VSSL or a reference line RL, acting as a shielding film, can be placed between the touch line TL and the data line DL to suppress their signals from interfering with each other.

[0217] Therefore, in the display device 100 according to the exemplary embodiments of the present disclosure, by applying the above configuration, the capacitance changes of the touch electrode TE and the touch line TL, signal interference or electromagnetic interference between the touch unit 150 and other configurations can be reduced, thereby improving the touch sensing performance of the touch unit 150.

[0218] Figure 24 This is a schematic plan view of a display device according to another exemplary embodiment of the present disclosure. Figure 25 It is along Figure 24 A cross-sectional view taken from line G-G'. Figure 26 This is a schematic diagram of the configuration of a display device according to another exemplary embodiment of the present disclosure. Figure 27A It is a graph measuring the noise of the touch signal caused by electromagnetic interference in the display device according to the comparative example. Figure 27B This is a graph measuring the noise of a touch signal due to electromagnetic interference in a display device according to another exemplary embodiment of the present disclosure. Aside from a different arrangement of the pseudo-lines PS and the further inclusion of an amplifier OPAMP, Figures 24 to 26 The display device 200 and Figures 1 to 23B The display device 100 is basically the same as that of the other device. Therefore, its repeated description will be omitted.

[0219] refer to Figure 24 and Figure 25 According to another exemplary embodiment of the present disclosure, the display device 200 includes a plurality of pseudo lines PS disposed in a non-functional area NA. For example, the plurality of pseudo lines PS may include a first pseudo line PS1, a second pseudo line PS2, a third pseudo line PS3, a fourth pseudo line PS4, and a fifth pseudo line PS5.

[0220] Furthermore, some of the multiple pseudo-lines PS can be disposed on the encapsulation layer 140, while the remainder can be disposed in the area outside the encapsulation layer 140. Since there is not enough space on the encapsulation layer 140 to accommodate all the multiple pseudo-lines PS, some pseudo-lines PS can be disposed outside the encapsulation layer 140. For example, the first pseudo-line PS1 and the second pseudo-line PS2 can be disposed outside the encapsulation layer 140, while the third pseudo-line PS3, the fourth pseudo-line PS4, and the fifth pseudo-line PS5 can be disposed on the encapsulation layer 140.

[0221] A set cover (SET) is configured to surround the outer surface of the display device 200. The set cover (SET) can be configured to cover all surfaces of the display device 200 except the surface displaying the image. The set cover (SET) can be combined with the display device 200 to manufacture the display device 200. In this case, the set cover (SET) can form a grounded surface in a grounded state.

[0222] Simultaneously, the signal radiation of the pseudo-line PS can be increased to reduce touch signal noise. The width of the pseudo-line PS can be increased to increase the signal radiation. However, as the width of the pseudo-line PS increases, coupling between the pseudo-line PS and the grounded cover SET is more likely to occur. The radiation of the pseudo-line PS is weakened by the capacitance between the pseudo-line PS and ground, making it difficult to improve touch signal noise.

[0223] In this configuration, among the multiple pseudo-lines PS, the third pseudo-line PS3, the fourth pseudo-line PS4, and the fifth pseudo-line PS5, located on the encapsulation layer 140, are positioned relatively far from the housing cover SET. Therefore, the coupling between the pseudo-lines PS and the housing cover SET may be relatively weak. However, among the multiple pseudo-lines PS, the first pseudo-line PS1 and the second pseudo-line PS2 are located in the region outside the encapsulation layer 140 and are positioned relatively close to the housing cover SET. Therefore, the coupling between the pseudo-lines PS and the housing cover SET is stronger, potentially significantly reducing radiation.

[0224] refer to Figure 26In a display device 200 according to another exemplary embodiment of the present disclosure, an amplifier OPAMP is connected to a first pseudo-line PS1 and a second pseudo-line PS2 disposed below the encapsulation layer 140 to amplify the signals transmitted to the first pseudo-line PS1 and the second pseudo-line PS2. The amplifier OPAMP is connected to the first pseudo-line PS1 and the second pseudo-line PS2, which are disposed relatively close to the housing cover SET among a plurality of pseudo-lines PS, to amplify the signal and increase the radiation of the first pseudo-line PS1 and the second pseudo-line PS2.

[0225] The touch integrated circuit (IC) that constitutes the touch driver TD is mounted on a printed circuit board (PCB). For example... Figure 26 As shown, multiple pseudo-lines PS and multiple touch lines TL can be connected between the touch driver TD and the display panel PN. An amplifier OPAMP can be mounted on the printed circuit board (PCB) and connected to the first pseudo-line PS1 and the second pseudo-line PS2. The first pseudo-line PS1 and the second pseudo-line PS2, extending from the touch driver TD, can be connected to the input terminals of the amplifier OPAMP, and the output terminals of the amplifier OPAMP can be connected to the first pseudo-line PS1 and the second pseudo-line PS2 of the display panel PN. Therefore, the amplifier OPAMP can amplify the pseudo-signal from the touch driver TD and output the amplified pseudo-signal to the first pseudo-line PS1 and the second pseudo-line PS2 of the display panel PN.

[0226] Figure 27A and Figure 27B It is a graph that measures the noise of touch signals caused by electromagnetic interference.

[0227] refer to Figure 27A Except that display device 200 does not include an amplifier OPAMP, display device 20 according to the comparative example is the same as in all other configurations. Figures 24 to 26 The display device 200 is the same. In the display device 20 according to the comparative example, due to the coupling of the first pseudo-line PS1 and the second pseudo-line PS2 with the housing cover SET, the signal radiation of the first pseudo-line PS1 and the second pseudo-line PS2 is reduced. Therefore, it can be confirmed that the peak value of the touch signal noise caused by electromagnetic interference exceeds the target peak value specification PKSpec, and the average value of the noise also exceeds the target average value specification AVSpec.

[0228] refer to Figure 27BAccording to another exemplary embodiment of this disclosure, the display device 200 may include an amplifier OPAMP to compensate for the reduction in signal radiation of the first pseudo-line PS1 and the second pseudo-line PS2 due to coupling with the housing cover SET. The amplifier OPAMP can increase the signal radiation of the first pseudo-line PS1 and the second pseudo-line PS2. Therefore, it can be confirmed that the peak of the touch signal noise is formed within the range of the target peak specification PK Spec, and the average noise is also within the range of the average specification AV Spec.

[0229] Therefore, in a display device 200 according to another exemplary embodiment of the present disclosure, an amplifier OPAMP is connected to a first pseudo-line PS1 and a second pseudo-line PS2, which are disposed outside the encapsulation layer 140 and are strongly affected by coupling with the housing cover SET. Thus, the reduction in signal radiation from the first pseudo-line PS1 and the second pseudo-line PS2 can be compensated, and noise in the touch signal due to electromagnetic interference can be reduced.

[0230] Exemplary embodiments of this disclosure can also be described as follows:

[0231] According to one aspect of this disclosure, a display device is provided. The display device includes a substrate, the substrate including an effective region and an ineffective region. The display device further includes an encapsulation layer disposed on the substrate. The display device further includes a plurality of pseudo-lines disposed in the ineffective region. The display device further includes an amplifier connected to some of the plurality of pseudo-lines. Some of the plurality of pseudo-lines are disposed outside the encapsulation layer in the ineffective region, and the remaining portions of the plurality of pseudo-lines are disposed on the encapsulation layer in the ineffective region.

[0232] Multiple pseudolines can be set to enclose the valid area.

[0233] Multiple pseudo-lines may include: a first pseudo-line disposed on the outside of the package layer, a second pseudo-line disposed on the outside of the package layer, a third pseudo-line disposed on the package layer, a fourth pseudo-line disposed on the package layer, and a fifth pseudo-line disposed on the package layer. The amplifier may be connected to the first and second pseudo-lines.

[0234] The display device may further include a housing disposed beneath the substrate. The housing may be coupled to at least some of the pseudo-lines.

[0235] The display device may further include: a plurality of flexible films connected to a substrate, and a printed circuit board connected to the plurality of flexible films and including a touch driver. An amplifier may be disposed on the printed circuit board.

[0236] The first and second pseudo-lines extending from the touch driver can be connected to the input terminals of the amplifier, and the output terminals of the amplifier can be connected to the first and second pseudo-lines on the substrate.

[0237] The display device may further include multiple ground wires disposed on the encapsulation layer. One of the multiple ground wires may be disposed between the edge of the encapsulation layer and the third pseudo-line, and another of the multiple ground wires may be disposed between the effective area and the fifth pseudo-line.

[0238] The display device may further include a gate driver that overlaps with any one of the multiple ground lines.

[0239] According to another aspect of this disclosure, a display device is provided. The display device includes a substrate, the substrate including an active region and an inactive region. The display device further includes a plurality of light-emitting diodes (LEDs) disposed on the substrate. The display device further includes an encapsulation layer disposed on the plurality of LEDs and extending from the active region to a portion of the inactive region. The display device further includes a touch unit disposed on the encapsulation layer and the substrate. The touch unit includes: a plurality of touch electrodes on the encapsulation layer, a plurality of touch lines connected to the plurality of touch electrodes, and a plurality of pseudo-lines disposed in the inactive region. The plurality of pseudo-lines are configured to surround the plurality of touch lines and the plurality of touch electrodes.

[0240] The signals supplied to multiple touch lines and the signals supplied to multiple pseudo lines can be signals with opposite phases.

[0241] The display device may further include multiple grounding wires disposed in non-active areas. Some of the multiple pseudo-wires may be disposed in areas outside the encapsulation layer, the remaining pseudo-wires may be disposed on the encapsulation layer, and the multiple grounding wires may be disposed adjacent to the multiple pseudo-wires.

[0242] The display device may further include an amplifier connected to some of the pseudolines disposed outside the encapsulation layer. The amplifier may be configured to amplify the signal and output the amplified signal to some of the pseudolines.

[0243] The display device may further include a gate driver disposed in an inactive region and include a scan signal driver and a light emission signal driver. One of the multiple ground lines may overlap with the gate driver and may be disposed adjacent to multiple pseudo-lines.

[0244] While exemplary embodiments of the present disclosure have been described in detail with reference to the accompanying drawings, the present disclosure is not limited thereto and may be embodied in many different forms without departing from the technical concept of the present disclosure. Therefore, the exemplary embodiments of the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above exemplary embodiments are illustrative in all respects and do not limit the present disclosure.

Claims

1. A display device, comprising: The substrate includes both effective and ineffective regions; An encapsulation layer disposed on the substrate; Multiple pseudo-lines are set in the non-valid area; as well as The amplifier connected to some of the pseudo-lines, Among them, some of the multiple pseudo lines are disposed outside the encapsulation layer in the non-effective area, and the remaining pseudo lines are disposed on the encapsulation layer in the non-effective area.

2. The display device according to claim 1, wherein, The multiple pseudo-lines are configured to surround the effective region.

3. The display device according to claim 1, wherein, The multiple pseudo-lines include: The first pseudo-line is disposed on the outside of the encapsulation layer. The second pseudoline is disposed on the outside of the encapsulation layer. The third pseudo-line is disposed on the encapsulation layer. The fourth pseudo-line is disposed on the encapsulation layer, and A fifth pseudoline is set on the encapsulation layer, and The amplifier is connected to the first pseudoline and the second pseudoline.

4. The display device according to claim 3, further comprising: A cover disposed beneath the substrate. The cover is coupled to one or more of the multiple pseudo-lines.

5. The display device according to claim 3, further comprising: Multiple flexible films connected to the substrate; as well as A printed circuit board, connected to the plurality of flexible films and including a touch driver, is provided. The amplifier is mounted on the printed circuit board.

6. The display device according to claim 5, wherein, The first and second pseudowires extending from the touch driver are connected to the input terminals of the amplifier, and The output terminal of the amplifier is connected to the first pseudo-line and the second pseudo-line on the substrate.

7. The display device according to claim 3, further comprising: Multiple grounding wires are disposed on the encapsulation layer; Among them, the first grounding wire of the plurality of grounding wires is disposed between the edge of the encapsulation layer and the third pseudo-wire, and The second grounding wire among the multiple grounding wires is located between the effective area and the fifth pseudo-wire.

8. The display device according to claim 7, further comprising: A gate driver that overlaps with one of the multiple grounding lines.

9. A display device, comprising: The substrate includes both effective and ineffective regions; Multiple light-emitting diodes disposed on the substrate; An encapsulation layer is disposed on the plurality of light-emitting diodes and extends from the effective region to a portion of the ineffective region; as well as Touch units disposed on the encapsulation layer and the substrate; The touch unit includes: Multiple touch electrodes on the encapsulation layer; Multiple touch lines connected to the plurality of touch electrodes; and Multiple pseudo-lines are set in the non-valid area, and The multiple pseudo-lines are configured to surround the multiple touch lines and the multiple touch electrodes.

10. The display device according to claim 9, wherein, The first phase of the first signal supplied to the plurality of touch lines is opposite to the second phase of the second signal supplied to the plurality of pseudo lines.

11. The display device according to claim 9, further comprising: Multiple grounding wires are installed in the non-effective area; Some of the multiple pseudo-lines are located in the area outside the encapsulation layer, while the remaining pseudo-lines are located on the encapsulation layer, and the multiple grounding lines are located adjacent to the multiple pseudo-lines.

12. The display device according to claim 11, further comprising: An amplifier, wherein the amplifier is connected to some of the plurality of pseudolines disposed in a region outside the encapsulation layer. The amplifier is configured to amplify the signal and output the amplified signal to some of the multiple pseudolines.

13. The display device according to claim 11, further comprising: A gate driver, disposed in the inactive region, includes a scan signal driver and a light emission signal driver. One of the multiple grounding lines overlaps with the gate driver and is arranged adjacent to the multiple pseudo-lines.

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