Display device

Abstract

A display device is provided. The display device includes a substrate, the substrate including a display area and a non-display area surrounding the display area and including a dam area, wherein at least one dam is disposed in the dam area. The display device further includes an encapsulation layer disposed on the substrate in the display area and the dam area. The display device further includes a first touch buffer layer disposed on the encapsulation layer in the dam area. The display device further includes a first touch electrode line disposed on the first touch buffer layer in the dam area. The display device further includes a second touch buffer layer disposed on the first touch electrode line in the dam area. The display device further includes a touch interlayer insulating layer disposed on the second touch buffer layer in the dam area. The display device further includes a second touch electrode line disposed on the touch interlayer insulating layer in the dam area. The second touch buffer layer comprises an inorganic insulating material, and the touch interlayer insulating layer comprises an organic insulating material.

Description

[0001] Cross-references to related applications This application claims priority to Korean Patent Application No. 10-2024-0200139, filed on December 30, 2024, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference. Technical Field

[0002] This disclosure relates to a display device, and more particularly to a display device in which touch electrodes are disposed on an encapsulation layer. Background Technology

[0003] With the development of the information society, the demand for display devices for displaying images is increasing, and various types of display devices, such as liquid crystal displays and organic light-emitting displays, are being utilized.

[0004] The display device can recognize user touches on the display panel and perform input processing based on the recognized touches to provide users with a wider range of functions. For example, multiple touch electrodes can be provided in the display area of ​​the display panel.

[0005] In addition, the display device can sense touch by detecting changes in the capacitance of the touch electrodes caused by the user's touch.

[0006] In particular, when the touch electrode is applied to an organic light-emitting display device, the elements constituting the touch element can be formed above or below the encapsulation layer used to protect the light-emitting element of the organic light-emitting display device.

[0007] During the process of forming the touch element on the encapsulation layer, components located beneath the touch element may be damaged, potentially creating a pathway for moisture penetration. Consequently, the lifespan of the light-emitting element may be shortened. Summary of the Invention

[0008] The purpose of this disclosure is to provide a display device that can suppress moisture penetration from non-display areas in a structure in which touch electrodes are disposed on an encapsulation layer.

[0009] The purpose of this disclosure is not limited to the above-described purposes, and other purposes not mentioned above will be clearly understood by those skilled in the art from the following description.

[0010] According to one aspect of this disclosure, a display device is provided. The display device includes a substrate, the substrate including a display area and a non-display area surrounding the display area and including a dam area, wherein at least one dam is disposed in the dam area. The display device further includes an encapsulation layer disposed on the substrate in the display area and the dam area. The display device further includes a first touch buffer layer disposed on the encapsulation layer in the dam area. The display device further includes a first touch electrode line disposed on the first touch buffer layer in the dam area. The display device further includes a second touch buffer layer disposed on the first touch electrode line in the dam area. The display device further includes a touch interlayer insulating layer disposed on the second touch buffer layer in the dam area. The display device further includes a second touch electrode line disposed on the touch interlayer insulating layer in the dam area. The second touch buffer layer comprises an inorganic insulating material, and the touch interlayer insulating layer comprises an organic insulating material.

[0011] According to another aspect of this disclosure, a display device is provided. The display device includes a substrate, the substrate including a display area and a dam area, the dam area being located around the display area and having at least one dam disposed in the dam area. The display device further includes an encapsulation layer disposed on the substrate in the display area and the dam area. The display device further includes a first touch buffer layer disposed on the encapsulation layer. The display device further includes a first touch electrode line disposed on the first touch buffer layer. The display device further includes a second touch buffer layer disposed on the first touch electrode line. The display device further includes a touch interlayer insulating layer disposed on the second touch buffer layer. The display device further includes a second touch electrode line disposed on the touch interlayer insulating layer. The encapsulation layer, the first touch buffer layer, the first touch electrode line, the second touch buffer layer, the touch interlayer insulating layer, and the second touch electrode line each overlap with a side surface and a top surface of the at least one dam.

[0012] Further details of the exemplary embodiments are included in the detailed description and the accompanying drawings.

[0013] According to embodiments of this disclosure, multiple touch electrode lines and multiple insulating layers are disposed in the non-display area. Therefore, defects in the encapsulation layer disposed in the non-display area can be suppressed, the lifespan of the light-emitting diode can be improved, and a display device capable of low-power operation can be provided.

[0014] The effects of this disclosure are not limited to those described above, and other effects not mentioned above will be clearly understood by those skilled in the art based on the following description.

[0015] The objectives to be achieved by this disclosure, the means to achieve these objectives, and the effects of this disclosure do not specify the essential features of the claims; therefore, the scope of the claims is not limited to the content of this disclosure. Attached Figure Description

[0016] The above and other aspects, features and advantages of this disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which: Figure 1 This is a system configuration diagram of a display device according to an embodiment of the present disclosure.

[0017] Figure 2 This is a schematic diagram of a display panel of a light-emitting display device integrating a touch screen according to an embodiment of the present disclosure.

[0018] Figure 3 This is an exemplary diagram illustrating a structure in which a touch panel is embedded in a display panel according to an embodiment of the present disclosure.

[0019] Figure 4 It is along Figure 2 The sectional view taken by line AB.

[0020] Figure 5 It is along Figure 2 The sectional view taken from the line CD.

[0021] Figure 6 This diagram illustrates the process steps for forming components disposed on the encapsulation layer in a non-display area.

[0022] Figure 7 This is a cross-sectional view of the non-display area of ​​a display device according to another embodiment of the present disclosure.

[0023] Figure 8 This is an image showing a portion of the dam area of ​​the display device according to the comparative example.

[0024] Figure 9 This is an image showing a portion of the dam area of ​​the display device according to an embodiment. Detailed Implementation

[0025] The advantages and features of this disclosure, as well as methods for achieving such advantages and features, will become clear from the exemplary embodiments described in detail below with reference to the accompanying drawings. However, this disclosure is not limited to the exemplary embodiments disclosed herein, but will be implemented in various forms. The exemplary embodiments are provided by way of example only, so that those skilled in the art can fully understand the disclosure and scope of this disclosure.

[0026] The shapes, dimensions, ratios, angles, quantities, etc., shown in the accompanying drawings used to describe exemplary embodiments of this disclosure are merely examples, and this disclosure is not limited thereto. Throughout the specification, the same reference numerals generally denote the same elements. Furthermore, in the following description of this disclosure, detailed explanations of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of this disclosure. Terms such as “comprising,” “having,” and “consisting of” as used herein are generally intended to allow for the addition of additional components, unless these terms are used in conjunction with the term “only.” Unless otherwise expressly stated, any reference to the singular may include the plural.

[0027] Even without explicit explanation, components are interpreted as including the normal tolerance range.

[0028] When using terms such as “above,” “over,” “below,” and “near” to describe the positional relationship between two parts, one or more parts may be located between the two parts, unless these terms are used with the terms “immediately adjacent” or “directly.”

[0029] When one element or layer is placed "on" another element or layer, another layer or element can be directly inserted on or between the other element.

[0030] Although the terms "first," "second," etc., are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from other components. Therefore, the first component referred to below may be the second component in the technical concept of this disclosure.

[0031] Throughout the specification, the same reference numerals generally denote the same elements.

[0032] For ease of description, the dimensions and thicknesses of the various components shown in the accompanying drawings are illustrated, and this disclosure is not limited to the dimensions and thicknesses of the components shown.

[0033] The features of the various embodiments of this disclosure may be combined or integrated with each other in part or in whole, and may be associated and operated in a variety of technical ways, and the embodiments may be implemented independently or in association with each other.

[0034] In the following, a display device according to exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0035] Figure 1 This is a system configuration diagram of a display device according to an embodiment of the present disclosure.

[0036] Reference Figure 1 The display device 100 may include a display panel 110 and a display driving circuit as components for displaying images.

[0037] The display driving circuit is a circuit used to drive the display panel 110, and may include a data driving circuit 120, a gate driving circuit 130, a display controller 140, etc.

[0038] The display panel 110 may include a display area AA for displaying images and a non-display area NA for not displaying images.

[0039] The non-display area NA can be the outer area of ​​the display area AA, also known as the border area. All or part of the non-display area NA can be an area visible from the front of the display device 100, or it can be a curved area that is not visible from the front of the display device 100.

[0040] The display panel 110 may include a substrate 101 and a plurality of sub-pixels SP disposed on the substrate 101. In addition, the display panel 110 may also include various types of signal lines for driving the plurality of sub-pixels SP.

[0041] The display device 100 according to embodiments of the present disclosure may be a liquid crystal display device or the like, or it may be a light-emitting display device in which the display panel 110 is self-emissive. When the display device 100 according to embodiments of the present disclosure is a self-emissive display device, each of the plurality of sub-pixels SP may include a light-emitting diode.

[0042] For example, the display device 100 according to an embodiment of the present disclosure may be an organic light-emitting display device, wherein the light-emitting diode is implemented as an organic light-emitting diode OLED.

[0043] For example, the display device 100 according to an embodiment of the present disclosure may be an inorganic light-emitting display device, wherein the light-emitting diode is implemented as an inorganic-based light-emitting diode. For example, the display device 100 according to an embodiment of the present disclosure may be a quantum dot display device, wherein the light-emitting diode is implemented as a quantum dot, and a quantum dot is a self-emissive semiconductor crystal.

[0044] Depending on the type of display device 100, the structure of each of the plurality of sub-pixels SP can vary. For example, when the display device 100 is a self-emissive display device in which the sub-pixels SP emit their own light, each sub-pixel SP may include a self-emissive light-emitting diode, one or more transistors, and one or more capacitors.

[0045] For example, various types of signal lines may include multiple data lines DL carrying data signals (also known as data voltages or image signals) and multiple gate lines GL carrying gate signals (also known as scan signals).

[0046] Multiple data lines DL and multiple gate lines GL can intersect each other. Each of the multiple data lines DL can be configured to extend in a first direction. Each of the multiple gate lines GL can be configured to extend in a second direction.

[0047] Here, the first direction can be the column direction, and the second direction can be the row direction.

[0048] The data driving circuit 120 is configured to drive multiple data lines DL and output data signals to the multiple data lines DL. The gate driving circuit 130 is configured to drive multiple gate lines GL and output gate signals to the multiple gate lines GL.

[0049] The display controller 140 may be a device configured to control the data drive circuit 120 and the gate drive circuit 130. The display controller 140 may control the driving timing of multiple data lines DL and multiple gate lines GL.

[0050] The display controller 140 can supply a data drive control signal DCS to the data drive circuit 120 to control the data drive circuit 120. The display controller 140 can also supply a gate drive circuit control signal GCS to the gate drive circuit 130 to control the gate drive circuit 130.

[0051] The display controller 140 can receive input image data from the host system 150 and supply image data Data to the data drive circuit 120 based on the input image data.

[0052] The data drive circuit 120 can control the driving timing of the display controller 140 to supply data signals to multiple data lines DL.

[0053] The data drive circuit 120 can receive digital image data Data from the display controller 140, convert the received image data Data into analog data signals, and output the converted data signals to multiple data lines DL.

[0054] The gate driving circuit 130 can supply gate signals to multiple gate lines GL according to the timing control of the display controller 140. The gate driving circuit 130 can receive a first gate voltage corresponding to the on-level voltage and a second gate voltage corresponding to the off-level voltage, as well as various gate driving circuit control signals GCS, generate gate signals, and supply the generated gate signals to the multiple gate lines GL.

[0055] For example, the data drive circuit 120 can be connected to the display panel 110 via a tape-on-board (TAB) method, to the bonding pads of the display panel 110 via a chip-on-glass (COG) or chip-on-panel (COP) method, or implemented and connected to the display panel 110 via a chip-on-film (COF) method.

[0056] The gate drive circuit 130 can be connected to the display panel 110 via the tape-on-board (TAB) method, to the bonding pads of the display panel 110 via the chip-on-glass (COG) or chip-on-panel (COP) method, or to the display panel 110 via the chip-on-film (COF) method.

[0057] Alternatively, the gate driving circuit 130 can be formed in the non-display area NA of the display panel 110 as a gate in panel (GIP) type. The gate driving circuit 130 can be disposed on or connected to the substrate 101.

[0058] In other words, when the gate driving circuit 130 is a gate in-panel (GIP) type, the gate driving circuit 130 can be disposed in the non-display area NA of the substrate 101. When the gate driving circuit 130 is a chip on glass (COG) type, chip on film (COF) type, etc., the gate driving circuit 130 can be connected to the substrate.

[0059] Meanwhile, at least one of the data driving circuit 120 and the gate driving circuit 130 can be disposed in the display area AA of the display panel 110. For example, at least one of the data driving circuit 120 and the gate driving circuit 130 can be configured not to overlap with the sub-pixel SP, or can be configured to partially or completely overlap with the sub-pixel SP.

[0060] The data driving circuit 120 can be connected to one side of the display panel 110 (e.g., the top or bottom side). Depending on the driving method, panel design method, etc., the data driving circuit 120 can be connected to both sides of the display panel 110 (e.g., the top and bottom sides), or it can be connected to two or more of the four side surfaces of the display panel 110.

[0061] The gate driving circuit 130 can be connected to one side of the display panel 110 (e.g., the left or right side). Depending on the driving method, panel design method, etc., the gate driving circuit 130 can be connected to both sides of the display panel 110 (e.g., the left and right sides), or it can be connected to two or more of the four side surfaces of the display panel 110.

[0062] The display controller 140 can be implemented as a component separate from the data drive circuit 120, or it can be implemented as an integrated circuit integrated with the data drive circuit 120.

[0063] The display controller 140 may be a timing controller used in conventional display technology, or it may be a control device that includes a timing controller and can perform other control functions, or it may be a control device other than a timing controller, or it may be a circuit within a control device. The display controller 140 may be implemented using various circuits or electronic components, such as integrated circuits (ICs), field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), or processors.

[0064] The display controller 140 can be electrically connected to the data drive circuit 120 and the gate drive circuit 130 via a printed circuit board (PCB), a flexible printed circuit board (FPCB), or the like.

[0065] The display controller 140 can send signals to and receive signals from the data drive circuit 120 according to one or more predetermined interfaces. Here, for example, the interface may include a low-voltage differential signaling (LVDS) interface, an EPI interface, a serial peripheral interface (SPI), etc.

[0066] The display device 100 according to an embodiment of the present disclosure may include a touch sensor and a touch sensing circuit, the touch sensing circuit sensing the touch sensor to detect whether a touch object (e.g., a finger or a pen) has been touched, or to detect the touch position, so as to provide touch sensing functionality in addition to image display functionality.

[0067] The touch sensing circuit may include a touch driver circuit 160 that drives and senses touch sensors to generate and output touch sensing data, a touch controller 170 that can use touch sensing data to detect touch occurrence or touch location, etc.

[0068] A touch sensor may include multiple touch electrodes. The touch sensor may also include multiple touch lines for electrically connecting the multiple touch electrodes and the touch driving circuitry 160.

[0069] The touch sensor can exist on the outside of the display panel 110 in the form of a touch panel, or it can exist inside the display panel 110.

[0070] When a touch sensor exists outside the display panel 110 in the form of a panel, the touch sensor is referred to as an external type.

[0071] When the touch sensor is external, the touch panel and display panel 110 can be manufactured and assembled separately during the assembly process. The external touch panel may include a touch panel substrate, multiple touch electrodes on the touch panel substrate, etc.

[0072] When a touch sensor is present inside the display panel 110, the touch sensor can be formed on the substrate 101 together with signal lines and electrodes related to display driving during the manufacturing process of the display panel 110.

[0073] The touch driving circuit 160 can supply a touch driving signal to at least one of the plurality of touch electrodes and generate touch sensing data by sensing at least one of the plurality of touch electrodes.

[0074] Touch sensing circuits can use self-capacitance sensing or mutual capacitance sensing to perform touch sensing.

[0075] When a touch sensing circuit performs touch sensing in a self-capacitance sensing manner, it can perform touch sensing based on the capacitance between each touch electrode and the touch object (e.g., a finger, a pen, etc.).

[0076] According to the self-capacitance sensing method, each of the plurality of touch electrodes can act as both a driving touch electrode and a sensing touch electrode. The touch driving circuit 160 can drive all or some of the plurality of touch electrodes and sense all or some of the plurality of touch electrodes.

[0077] When the touch sensing circuit performs touch sensing in a mutual capacitance sensing manner, the touch sensing circuit can perform touch sensing based on the capacitance between the touch electrodes.

[0078] According to the mutual capacitance sensing method, multiple touch electrodes are divided into driving touch electrodes and sensing touch electrodes. The touch driving circuit 160 can drive the driving touch electrodes and sense the sensing touch electrodes.

[0079] The touch driver circuit 160 and touch controller 170 included in the touch sensing circuit can be implemented as separate devices or as a single device. Furthermore, the touch driver circuit 160 and data driver circuit 120 can be implemented as separate devices or as a single device.

[0080] The display device 100 may also include a power supply circuit that supplies various types of power to the display driving circuit and / or touch sensing circuit, etc.

[0081] The display device 100 according to embodiments of this disclosure may be a mobile terminal such as a smartphone or tablet computer, or a display or television (TV) of various sizes, but is not limited thereto. That is, the display device 100 may be a display device of various types and sizes capable of displaying information or images.

[0082] Hereinafter, for ease of explanation, an example is given of a display device 100 according to an embodiment of the present disclosure where the touch panel TSP is built-in.

[0083] Figure 2 This is a schematic diagram of a display panel of a light-emitting display device integrating a touch screen according to an embodiment of the present disclosure.

[0084] Reference Figure 2 The display panel 110 may include a display area AA for displaying images and a non-display area NA that is the outer region of the outer boundary line BL of the display area AA.

[0085] In the display area AA of the display panel 110, multiple sub-pixels for image display are provided, and various electrodes and signal lines for display driving are provided.

[0086] In addition, multiple touch electrodes for touch sensing and multiple touch routing wires electrically connected to them can be arranged in the display area AA of the display panel 110. Therefore, the display area AA can also be referred to as a touch sensing area capable of touch sensing.

[0087] In the non-display area NA of the display panel 110, there may be connecting lines for various signal lines provided in the display area AA through their extensions, or connecting lines electrically connected to various signal lines provided in the display area AA, and pads electrically connected to these connecting lines.

[0088] Display driver circuits (DDC, GDC, etc.) can be coupled or electrically connected to pads located in the non-display area NA.

[0089] Additionally, in the non-display area NA of the display panel 110, there may be connecting lines extending from or electrically connected to multiple touch wires provided in the display area AA, as well as pads electrically connected to these connecting lines.

[0090] The touch drive circuit (TDC) can be bonded or electrically connected to pads located in the non-display area NA.

[0091] In the non-display area NA, there may be an extension of a portion of the outermost touch electrode among the multiple touch electrodes disposed in the display area AA. Furthermore, one or more electrodes (touch electrodes) having the same material as the multiple touch electrodes disposed in the display area AA may be further disposed in the non-display area NA.

[0092] In other words, all touch electrodes disposed in the display panel 110 may exist within the display area AA. Alternatively, a portion of the multiple touch electrodes disposed in the display panel 110 (e.g., the outermost touch electrode) may exist in the non-display area NA, or a portion of the multiple touch electrodes disposed on the display panel 110 (e.g., the outermost touch electrode) may span both the display area AA and the non-display area NA.

[0093] At the same time, refer to Figure 2 According to embodiments of the present disclosure, the display panel 110 of the integrated touch screen light-emitting display device may include a dam region DA in which a dam DAM is provided to suppress the collapse of any layer (e.g., an encapsulation layer in an organic light-emitting display panel) within the display region AA.

[0094] In other words, dam DAM can be used to suppress the outward overflow of organic layers contained in the encapsulation layer ENCAP.

[0095] The dam region DA can be located at the boundary point between the display region AA and the non-display region NA, or at any point in the non-display region NA that is an outer region of the display region AA.

[0096] The dam set in the dam area DA can be set to surround all directions of the display area AA, or it can be set only on the periphery of one or more parts of the display area AA, such as the part where the easily collapsed layer is located.

[0097] A dam set in the dam area DA can be a single connected pattern, or it can include two or more disconnected patterns.

[0098] In addition, a dam area (DA) may have only one dam, two dams, or three or more dams.

[0099] When two dams are set in the dam area DA, it can include a first dam and a second dam spaced apart from the first dam. The second dam can be set further away from the display area AA than the first dam.

[0100] Additionally, when three dams are set in the dam area DA, it can include a first dam, a second dam spaced apart from the first dam, and a third dam spaced apart from the second dam. The second dam can be set further away from the display area AA than the first dam, and the third dam can be set further away from the display area AA than the second dam.

[0101] In addition, only the first dam can be set in one direction, while the second and third dams can be set in another direction.

[0102] Figure 3 This is an exemplary diagram illustrating a structure in which a touch panel is embedded in a display panel according to an embodiment of the present disclosure.

[0103] Reference Figure 3 In the display area AA of the display panel 110, multiple sub-pixels SP are disposed on the substrate 101.

[0104] Each sub-pixel SP may include a light-emitting diode ED, a first transistor T1 for driving the light-emitting diode ED, a second transistor T2 for transmitting the data voltage VDATA to a first node N1 of the first transistor T1, a storage capacitor Cst for maintaining a constant voltage within a frame, etc.

[0105] The first transistor T1 may include a first node N1 to which a data voltage VDATA can be applied, a second node N2 electrically connected to a light-emitting diode ED, and a third node N3 to which a drive voltage VDD is applied from a drive voltage line.

[0106] The first node N1 can be a gate node, the second node N2 can be a source node or a drain node, and the third node N3 can be a drain node or a source node. The first transistor T1 is also referred to as the driving transistor for driving the light-emitting diode ED.

[0107] A light-emitting diode (ED) may include a first electrode (e.g., an anode), a light-emitting layer, and a second electrode (e.g., a cathode).

[0108] The first electrode can be electrically connected to the second node N2 of the first transistor T1, and the second electrode can be subjected to a base voltage VSS.

[0109] In a light-emitting diode (ED), the light-emitting layer can be an organic light-emitting layer containing organic materials. In this case, the ED can be an organic light-emitting diode (OLED).

[0110] The second transistor T2 can be turned on and off by the scan signal SCAN applied through the gate line GL, and can be electrically connected between the first node N1 of the first transistor T1 and the data line DL. The second transistor T2 is also referred to as a switching transistor.

[0111] When the second transistor T2 is turned on by the scan signal SCAN, the second transistor T2 will transfer the data voltage VDATA supplied from the data line DL to the first node N1 of the first transistor T1.

[0112] The storage capacitor Cst can be electrically connected between the first node N1 and the second node N2 of the first transistor T1.

[0113] like Figure 3 As shown, each sub-pixel SP can have a 2T1C structure including two transistors T1 and T2 and a capacitor Cst, and in some cases, it can further include one or more transistors or one or more capacitors.

[0114] The storage capacitor Cst can be an external capacitor intentionally designed outside the first transistor T1, rather than a parasitic capacitor (e.g., Cgs, Cgd) that can exist as an internal capacitor between the first node N1 and the second node N2 of the first transistor T1.

[0115] Each of the first transistor T1 and the second transistor T2 can be an n-type transistor or a p-type transistor.

[0116] Meanwhile, as described above, circuit elements such as light-emitting diodes ED, two or more transistors T1 and T2, and one or more capacitors Cst are disposed in the display panel 110.

[0117] Since these circuit components (especially light-emitting diodes ED) are susceptible to external moisture or oxygen, the display panel 110 may be provided with an encapsulation layer ENCAP to prevent external moisture or oxygen from penetrating into the circuit components (especially light-emitting diodes ED).

[0118] The ENCAP encapsulation layer can be a single layer or multiple layers.

[0119] Meanwhile, in the light-emitting display device integrating a touch screen according to embodiments of the present disclosure, the touch panel TSP can be formed on the encapsulation layer ENCAP.

[0120] In other words, in a light-emitting display device with an integrated touch screen, the touch sensor structure (e.g., multiple touch electrodes TE forming the touch panel TSP) can be disposed on the encapsulation layer ENCAP.

[0121] During touch sensing, a touch drive signal or a touch sensing signal can be applied to the touch electrode TE.

[0122] Therefore, during touch sensing, a potential difference may be formed between the touch electrode TE and the cathode (an encapsulation layer ENCAP is provided between the touch electrode TE and the cathode), and unwanted parasitic capacitance may be formed.

[0123] Parasitic capacitance can reduce touch sensitivity. Therefore, in order to reduce parasitic capacitance, taking into account panel thickness, panel manufacturing process, display performance, etc., the distance between the touch electrode TE and the cathode can be designed to be equal to or greater than a certain value.

[0124] Next, the structure of the display area AA and the non-display area NA of a display device according to an embodiment of the present disclosure will be described in detail.

[0125] Figure 4 It is along Figure 2 The sectional view taken by line AB.

[0126] Reference Figure 4The substrate 101 may include a first substrate 101a, an intermediate film 101b, and a second substrate 101c. The intermediate film 101b may be located between the first substrate 101a and the second substrate 101c. Since the substrate 101 includes the first substrate 101a, the intermediate film 101b, and the second substrate 101c, moisture penetration can be suppressed. For example, the first substrate 101a and the second substrate 101c may be polyimide (PI) substrates. The first substrate 101a may be referred to as the main PI substrate, and the second substrate 101c may be referred to as the secondary PI substrate.

[0127] The first transistor T1, the second transistor T2, and the storage capacitors 125 and 126 can be disposed on the second substrate 101c.

[0128] The second transistor T2 may include a first display layer 121, a first gate 122, a first source 123, and a first drain 124.

[0129] The first transistor T1 may include a second display layer 131, a second gate 132, a second source 133, and a second drain 134.

[0130] Storage capacitors 125 and 126 may include a first storage capacitor electrode 125 and a second storage capacitor electrode 126.

[0131] Specifically, the multi-buffer layer 103 can be disposed on the second substrate 101c, and the first display buffer layer 104a can be disposed on the multi-buffer layer 103.

[0132] The first metal layer 102 can be disposed on the first display buffer layer 104a. Here, the first metal layer 102 can be a light-blocking layer (LS).

[0133] The second display buffer layer 104b can be disposed on the first metal layer 102.

[0134] The first display layer 121 of the second transistor T2 can be disposed on the second display buffer layer 104b.

[0135] The first display layer 121 can be configured to overlap with the first metal layer 102.

[0136] The first gate insulating layer 105 may be disposed on the first display layer 121. The first gate insulating layer 105 may be configured to cover the first display layer 121.

[0137] The first gate 122 of the second transistor T2 can be disposed on the first gate insulating layer 105. The first gate 122 can be configured to overlap with the first display layer 121.

[0138] In addition, the first storage capacitor electrode 125 may be disposed on the first gate insulating layer 105.

[0139] The first storage capacitor electrode 125 can be located in a region different from the region where the first gate 122 is located.

[0140] The first interlayer insulating layer 106 may be disposed on the first gate 122 and the first storage capacitor electrode 125. The first interlayer insulating layer 106 may be configured to cover the first gate 122 and the first storage capacitor electrode 125.

[0141] The second storage capacitor electrode 126 and the second metal layer 127 can be disposed on the first interlayer insulating layer 106.

[0142] The second storage capacitor electrode 126 can be configured to overlap with the first storage capacitor electrode 125.

[0143] The second metal layer 127 can be configured to be spaced apart from the second storage capacitor electrode 126. Here, the second metal layer 127 can be a light-blocking layer (LS).

[0144] The second interlayer insulating layer 107 can be disposed on the second storage capacitor electrode 126 and the second metal layer 127.

[0145] The second interlayer insulating layer 107 can be configured to cover the second storage capacitor electrode 126 and the second metal layer 127.

[0146] The thickness of the second interlayer insulation layer 107 may be greater than the thickness of the first interlayer insulation layer 106, but is not limited thereto.

[0147] The second display layer 131 of the first transistor T1 can be disposed on the second interlayer insulating layer 107.

[0148] Each of the first display layer 121 of the second transistor T2 and the second display layer 131 of the first transistor T1 can be formed of an oxide semiconductor, or can be formed of amorphous silicon (a-Si), polycrystalline silicon (poly-Si), organic semiconductor, etc.

[0149] The second display layer 131 can be configured to overlap with the second metal layer 127.

[0150] The second gate insulating layer 108 may be disposed on the second display layer 131. The second gate insulating layer 108 may be configured to cover the second display layer 131.

[0151] The second gate 132 of the first transistor T1 can be disposed on the second gate insulating layer 108. The second gate 132 can be configured to overlap with the second display layer 131.

[0152] The third interlayer insulating layer 109 can be disposed on the second gate 132.

[0153] The third interlayer insulating layer 109 can be configured to cover the second gate 132.

[0154] The first source 123 and the first drain 124 of the second transistor T2 can be spaced apart from each other on the third interlayer insulating layer 109. Furthermore, the second source 133 and the second drain 134 of the first transistor T1 can be spaced apart from each other on the third interlayer insulating layer 109.

[0155] Meanwhile, reference numeral 123 in the second transistor T2 is referred to as the first source, and reference numeral 124 is referred to as the first drain, but not limited thereto. For example, reference numeral 123 can be the first drain of the second transistor T2, and reference numeral 124 can be the first source of the second transistor T2.

[0156] Furthermore, although reference numeral 133 in the first transistor T1 is referred to as the second source and reference numeral 134 as the second drain, this is not a limitation. For example, reference numeral 133 can be the second drain of the first transistor T1, and reference numeral 134 can be the second source of the first transistor T1.

[0157] The first source 123 and the first drain 124 of the second transistor T2 can be electrically connected to one end and the other end of the first display layer 121 through contact holes provided in the third interlayer insulating layer 109, the second gate insulating layer 108, the second interlayer insulating layer 107, the first interlayer insulating layer 106 and the first gate insulating layer 105.

[0158] The portion of the first display layer 121 that overlaps with the first gate 122 is a channel region. The first source 123 can be connected to one end of the channel region of the first display layer 121, and the first drain 124 can be connected to the other end of the channel region of the first display layer 121.

[0159] The second source 133 and the second drain 134 of the first transistor T1 can be electrically connected to one end and the other end of the second display layer 131 through contact holes disposed in the third interlayer insulating layer 109 and the second gate insulating layer 108.

[0160] The portion of the second display layer 131 that overlaps with the second gate 132 is a channel region. The second source 133 can be connected to one end of the channel region of the second display layer 131, and the second drain 134 can be connected to the other end of the channel region of the second display layer 131.

[0161] In addition, the second source 133 of the first transistor T1 can overlap with the first storage capacitor electrode 125 and the second storage capacitor electrode 126.

[0162] The second source electrode 133 can be electrically connected to the second storage capacitor electrode 126 through contact holes disposed in the third interlayer insulating layer 109, the second gate insulating layer 108, and the second interlayer insulating layer 107.

[0163] The first planarization layer 111 can be disposed on the first source 123 and the first drain 124 of the second transistor T2 and the second source 133 and the second drain 134 of the first transistor T1.

[0164] The first planarization layer 111 can be used to planarize the top surface of the substrate 101 on which the first source 123 and the first drain 124 of the second transistor T2 and the second source 133 and the second drain 134 of the first transistor T1 are disposed.

[0165] The connecting electrode 135 can be disposed on the first planarization layer 111.

[0166] The connecting electrode 135 can be electrically connected to the second source 133 of the second transistor T1 through a contact hole provided in the first planarization layer 111.

[0167] The second planarization layer 112 can be disposed on the connecting electrode 135.

[0168] The second planarization layer 112 can be used to planarize the top surface of the substrate 101 on which the connecting electrode 135 is disposed.

[0169] The light-emitting diode (ED) can be disposed on the second planarization layer 112.

[0170] A light-emitting diode (ED) may include a first electrode 141, an organic layer 142, and a second electrode 143.

[0171] The first electrode 141 can be disposed on the second planarization layer 112.

[0172] The first electrode 141 can be electrically connected to the connecting electrode 135 through the contact holes of the second planarization layer 112.

[0173] The dam 113 can be disposed on a portion of the top surface of the first electrode 141 and on the second planarization layer 112.

[0174] The dam 113 may be configured to cover a portion of the first electrode 141. The dam 113 may include a dam hole (or an opening in the dam) that exposes the top surface of the first electrode 141 in the light-emitting region EA of the sub-pixel SP.

[0175] An organic layer 142, including at least one light-emitting layer, may be disposed on the side surface of the dam 113 and in the holes of the dam 113.

[0176] In other words, the organic layer 142 can be disposed on the top surface of the first electrode 141 exposed by the dam 113. Therefore, the organic layer 142 can contact the top surface of the first electrode 141 in the holes of the dam 113.

[0177] The area where the dam 113 is set in the sub-pixel SP can correspond to the non-light-emitting area NEA.

[0178] At least one spacer 114 may be provided on the embankment 113 in the non-luminous area NEA.

[0179] Additionally, in some cases, at least one reverse spacer 115 may be disposed on the dam 113 in the non-light-emitting area NEA. The reverse spacer 115 can reduce undesirable leakage current between sub-pixels SP by disconnecting the connection between the organic layer 142 and the second electrode 143. Therefore, since color mixing is suppressed even at low brightness, degradation of the image quality of the display device can be suppressed. Furthermore, when the display device 100 is flexible or foldable, the reverse spacer 115 can prevent the encapsulation layer ENCAP disposed on the second electrode 143 from lifting due to bending or folding.

[0180] Spacer 114 and reverse spacer 115 may be integrally formed with dam 113. However, this is not a limitation, and spacer 114 and reverse spacer 115 may be formed by a process different from that used to form dam 113, such that boundaries may exist between dam 113 and spacer 114 and between dam 113 and reverse spacer 115.

[0181] The second electrode 143 can be disposed on the organic layer 142, the dam 113, the spacer 114, and the reverse spacer 115.

[0182] The encapsulation layer ENCAP can be disposed on the second electrode 143.

[0183] The encapsulation layer ENCAP can have a single-layer structure or a multi-layer structure. For example, the encapsulation layer ENCAP may include a first encapsulation layer 151, a second encapsulation layer 152, and a third encapsulation layer 153.

[0184] The first encapsulation layer 151 and the third encapsulation layer 153 can be inorganic films, and the second encapsulation layer 152 can be an organic film. Among the first encapsulation layer 151, the second encapsulation layer 152, and the third encapsulation layer 153, the second encapsulation layer 152, being an organic film, is the thickest and can be used as a planarization layer.

[0185] The first encapsulation layer 151 can be disposed on the cathode (CE) and closest to the light-emitting diode (ED). The first encapsulation layer 151 can be formed of an inorganic insulating material that can be deposited at low temperatures.

[0186] For example, the first encapsulation layer 151 may be silicon nitride (SiN). x ), silicon oxide (SiO) x The first encapsulation layer 151 is made of silicon oxynitride (SiON) or aluminum oxide (Al2O3). Because the first encapsulation layer 151 is deposited in a low-temperature atmosphere, it can suppress damage to the light-emitting layer (EL) containing organic materials that are susceptible to high-temperature atmospheres during the deposition process.

[0187] The second encapsulation layer 152 can be formed with a smaller area than the first encapsulation layer 151. In this case, the second encapsulation layer 152 can be formed to expose both ends of the first encapsulation layer 151.

[0188] The second encapsulation layer 152 serves as a buffer to reduce the stress between layers caused by the bending of the display device 100, and can also be used to improve planarization performance.

[0189] For example, the second encapsulation layer 152 can be formed of an organic insulating material, such as acrylic resin, epoxy resin, polyimide, polyethylene, or silicon carbide (SiOC). For example, the second encapsulation layer 152 can be formed using an inkjet printing method.

[0190] The second encapsulation layer 152, also known as the particle cover layer (PCL), has excellent planarization capabilities. Therefore, the second encapsulation layer 152 can compensate for step differences in the underlying layers and is suitable for providing planarization functionality.

[0191] The third encapsulation layer 153 may be formed on the substrate 101 on which the second encapsulation layer 152 may be formed, to cover the top and side surfaces of each of the second encapsulation layer 152 and the first encapsulation layer 151.

[0192] The third encapsulation layer 153 can minimize or block external moisture or oxygen from penetrating into the first encapsulation layer 151 and the second encapsulation layer 152. For example, the third encapsulation layer 153 can be made of materials such as silicon nitride (SiN). x ), silicon oxide (SiO) x Inorganic insulating materials such as silicon oxynitride (SiON) or aluminum oxide (Al2O3) are formed.

[0193] The touch electrode TE can be disposed on the encapsulation layer ENCAP. The touch electrode TE may include a first touch electrode 181 and a second touch electrode 182.

[0194] The first touch electrode 181 and the second touch electrode 182 can be disposed on different layers. The structure of the touch electrode TE is described in detail below.

[0195] The first touch buffer layer 161 can be set on the encapsulation layer ENCAP.

[0196] The first touch electrode 181 can be disposed on the first touch buffer layer 161. Here, the first touch electrode 181 can also be referred to as a bridging electrode.

[0197] The second touch buffer layer 162 can be disposed on the first touch electrode 181.

[0198] The second touch buffer layer 162 can be configured to cover the first touch electrode 181.

[0199] The second touch buffer layer 162 may comprise an inorganic insulating material. For example, the second touch buffer layer 162 may be made of silicon nitride (SiN). x ) or silicon oxide (SiO) x Monolayer or silicon nitride (SiN) x ) or silicon oxide (SiO) x It is composed of multiple layers, but is not limited to this.

[0200] The interlayer insulation layer 163 can be disposed on the second touch buffer layer 162.

[0201] The second touch electrode 182 can be disposed on the interlayer insulating layer 163. The second touch electrode 182 can be electrically connected to the first touch electrode 181 through contact holes disposed in the second touch buffer layer 162 and the interlayer insulating layer 163.

[0202] The first touch electrode 181 and the second touch electrode 182 can be disposed in the non-light-emitting region NEA of the sub-pixel SP. That is, the first touch electrode 181 and the second touch electrode 182 can be disposed to overlap with the embankment 113.

[0203] On the other hand, when the touch electrode TE is formed on the display panel 110, the chemical solution (developing solution or etching solution, etc.) used in the process may flow into the interior, or moisture may flow in from the outside.

[0204] By placing the touch electrode TE on the first touch buffer layer 161, chemicals or moisture can be prevented from penetrating into the organic layer 142, including the light-emitting layer, during the manufacturing process of the touch electrode TE. Therefore, the first touch buffer layer 161 can prevent damage to the organic layer 142, which is susceptible to chemicals or moisture.

[0205] The first touch buffer layer 161 may be formed at a low temperature below a certain temperature (e.g., 100°C) to suppress damage to the organic layer 142 which is susceptible to high temperatures, and may be formed of an organic insulating material having a low dielectric constant of 1 to 3, but is not limited thereto.

[0206] Furthermore, a second touch buffer layer 162 may be disposed between the first touch electrode 181 and the second touch electrode 182, and may be used to separate the first touch electrode 181 and the second touch electrode 182. The second touch buffer layer 162 may include at least one contact hole, and the first touch electrode 181 and the second touch electrode 182 may be connected through the contact hole disposed in the second touch buffer layer 162.

[0207] The interlayer insulation layer 163 may contain an organic insulating material. For example, the interlayer insulation layer 163 may contain acrylic, epoxy, or siloxane materials.

[0208] On the other hand, when the display device 100 is bent, the encapsulation layer ENCAP may be damaged, and the touch electrode TE located on the touch interlayer insulation layer 163 may be damaged. Even when the display device 100 is bent, the touch interlayer insulation layer 163, which contains organic insulating material and has planarization properties, can suppress damage to the encapsulation layer ENCAP and / or breakage of the first touch electrode 181 and the second touch electrode 182 constituting the touch electrode TE.

[0209] Furthermore, the interlayer insulating layer 163 can reduce signal interference by lowering the dielectric constant between the touch electrode TE and the various electrodes and wiring disposed below the touch electrode TE. Therefore, the interlayer insulating layer 163 can improve the performance of the touch electrode TE.

[0210] A protective layer 164 may be disposed on the second touch electrode 182. The protective layer 164 may be configured to cover the second touch electrode 182.

[0211] The protective layer 164 may be an organic insulating layer. For example, the organic insulating layer may contain the same material as the first planarization layer 111 and the second planarization layer 112 described above. Furthermore, the organic insulating layer may be formed of a different material than the second encapsulation layer 152. For example, the protective layer 164 may include a thermosetting resin.

[0212] Color buffer layer 171 can be set on protective layer 164.

[0213] A black matrix 175 can be disposed on the color buffer layer 171. The black matrix 175 can be configured to overlap with a portion of the non-emitting region NEA of the sub-pixel SP. Furthermore, the black matrix 175 may include an opening that exposes the emitting region EA of the sub-pixel SP and a portion of the non-emitting region NEA surrounding a portion of the emitting region EA.

[0214] Color filter 176 can be disposed on a portion of the top surface of black matrix 175 and on color buffer layer 171.

[0215] Color filter 176 can be set in the luminous region EA of sub-pixel SP, and can also be set in a portion of the non-luminous region NEA. Color filter 176 can be set inside the opening of black matrix 175, and can be set to cover the edge of black matrix 175.

[0216] In addition, the black matrix 175 can overlap with the first touch electrode 181 and the second touch electrode 182.

[0217] Figure 5 It is along Figure 2 The sectional view taken from the line CD.

[0218] Figure 5 This is a diagram illustrating a portion of a non-display area NA, including a dam area DA and an additional area A1, in a display panel 110 according to an embodiment of the present disclosure.

[0219] Reference Figure 5 The non-display area NA may include a dam area DA in which at least one of dams DAM1 and DAM2 is provided.

[0220] Additionally, the non-display area NA may include an additional area A1 located between the display area AA and the dam area DA.

[0221] Specifically, the multiple buffer layer 103, the first display buffer layer 104a, the second display buffer layer 104b, the first gate insulating layer 105, the first interlayer insulating layer 106, the second interlayer insulating layer 107, the second gate insulating layer 108 and the third interlayer insulating layer 109 disposed on the substrate 101 can be disposed in the non-display area NA of the display panel 110.

[0222] Each of the multiple buffer layer 103, the first display buffer layer 104a, the second display buffer layer 104b, the first gate insulating layer 105, the first interlayer insulating layer 106, the second interlayer insulating layer 107, the second gate insulating layer 108, and the third interlayer insulating layer 109 can be configured to extend from the display area AA to the non-display area NA.

[0223] In the non-display area NA, multiple first wirings 125a can be disposed on the first gate insulating layer 105. The multiple first wirings 125a can be disposed on the same layer as the first gate 122 and the first storage capacitor electrode 125 in the display area AA.

[0224] Additionally, multiple second wirings 126a can be provided on the first interlayer insulating layer 106 in the non-display area NA. These multiple second wirings 126a can be disposed on the same layer as the second storage capacitor electrode 126 and the second metal layer 127 in the display area AA.

[0225] Multiple first wirings 125a and multiple second wirings 126a can be detection wirings for detecting cracks in the display panel 110.

[0226] The first basic wiring 131a can be disposed on the third interlayer insulating layer 109 in the non-display area NA. The first basic wiring 131a can be disposed on the same layer as the first source 123, the first drain 124, the second source 133 and the second drain 134 in the display area AA.

[0227] The first planarization layer 111 may be disposed on a portion of the top surface of the first base wiring 131a and on the third interlayer insulating layer 109. The first planarization layer 111 may be configured to extend from the display area AA.

[0228] The first planarization layer 111 can be configured to expose a portion of the top surface of the first base wiring 131a.

[0229] The second basic wiring 135a can be disposed on the first planarization layer 111 and the first basic wiring 131a. The second basic wiring 135a can be disposed on the same layer as the connection electrode 135 in the display area AA.

[0230] The first base wiring 131a and the second base wiring 135a set in the non-display area NA can be low-potential voltage wiring or connection wiring (or connection electrode) connected to the low-potential voltage wiring.

[0231] The second planarization layer 112 may be disposed on a portion of the top surface of the second base wiring 135a and on the first planarization layer 111.

[0232] The second planarization layer 112 may be configured to cover at least a portion of the edge of the second base wiring 135a. The second planarization layer 112 may be configured to extend from the display area AA to at least a portion of the non-display area NA.

[0233] Specifically, the second planarization layer 112 may cover the first planarization layer 111 and the second base wiring 135a disposed on the first planarization layer 111. The second planarization layer 112 may also be disposed on the portion of the top surface of the second base wiring 135a that contacts the first base wiring 131a.

[0234] Additionally, the second planarization layer pattern 112a disposed on the same layer as the second planarization layer 112 can be configured to cover the end of each of the first base wiring 131a and the second base wiring 135a that does not overlap with the first planarization layer 111.

[0235] The second planarization layer pattern 112a can also be disposed on a portion of the top surface of the third interlayer insulation layer 109.

[0236] The dam 113 can be disposed on the second planarization layer 112 in the non-display area NA. The dam 113 can be configured to extend from the display area AA to at least a portion of the non-display area NA.

[0237] The dam 113 can be configured to cover the second planarization layer 112 disposed in the non-display area NA. The dam 113 can also be disposed on a portion of the top surface of the second base wiring 135a.

[0238] In addition, the first dam pattern 113a and the second dam pattern 113b, prepared by the same process as dam 113, can be set in the non-display area NA.

[0239] The first embankment pattern 113a can be set on the top surface of the second base wiring 135a.

[0240] The first spacer pattern 114a can be set on the first embankment pattern 113a.

[0241] The first dam pattern 113a and the first spacer pattern 114a disposed on the first dam pattern 113a can constitute the first dam DAM1. In other words, the first dam DAM1 may include the first dam pattern 113a and the first spacer pattern 114a disposed on the first dam pattern 113a.

[0242] The second embankment pattern 113b can be set on the second planarization layer pattern 112a.

[0243] The second spacer pattern 114b can be set on the second embankment pattern 113b.

[0244] The second planarization layer pattern 112a, the second embankment pattern 113b disposed on the second planarization layer pattern 112a, and the second spacer pattern 114b disposed on the second embankment pattern 113b can form the second dam DAM2.

[0245] In other words, the second dam DAM2 may include a second planarization layer pattern 112a, a second embankment pattern 113b disposed on the second planarization layer pattern 112a, and a second spacer pattern 114b disposed on the second embankment pattern 113b.

[0246] At the same time, Figure 5 In the diagram, the first dam DAM1 is shown having a structure including a first dam pattern 113a and a first spacer pattern 114a disposed on the first dam pattern 113a, but is not limited thereto. For example, the first dam pattern 113a and the first spacer pattern 114a may be integrally formed.

[0247] Furthermore, although the second dam DAM2 is shown as having a structure including a second dam pattern 113b and a second spacer pattern 114b disposed on the second dam pattern 113b, it is not limited thereto. For example, the second dam pattern 113b and the second spacer pattern 114b can be integrally formed.

[0248] The first dam DAM1 and the second dam DAM2 can be used to suppress the outward spillage of material from the second encapsulation layer 152, which is included in the encapsulation layer ENCAP.

[0249] The height of the second dam DAM2 can be higher than the height of the first dam DAM1. Therefore, even if the first dam DAM1 cannot suppress the overflow of the material of the second encapsulation layer 152, the second dam DAM2 can suppress the overflow of the material of the second encapsulation layer 152.

[0250] Furthermore, the second dam DAM2 can be configured to surround at least one end of each of the first base wiring 131a and the second base wiring 135a, thereby protecting at least one end of each of the first base wiring 131a and the second base wiring 135a.

[0251] In the non-display area NA, the first encapsulation layer 151 can be disposed on the substrate 101 on which the first dam DAM1 and the second dam DAM2 are disposed.

[0252] The first encapsulation layer 151 can be configured to extend from at least a portion of the display area AA to the non-display area NA. The first encapsulation layer 151 can be configured to cover the dam 113, the second base wiring 135a, the first dam DAM1, the second dam DAM2, and the third interlayer insulation layer 109.

[0253] In other words, the first encapsulation layer 151 can be disposed on the side and top surfaces of the first dam DAM1, and can be disposed on the side and top surfaces of the second dam DAM2.

[0254] The second encapsulation layer 152 may be disposed on a portion of the top surface of the first encapsulation layer 151.

[0255] The second encapsulation layer 152 can be configured to extend from the display area AA and can extend to the area between the dike 113 and the first dam DAM1.

[0256] Meanwhile, the second encapsulation layer 152 is shown as having a structure in which the second encapsulation layer 152 is spaced apart from the first encapsulation layer 151 disposed on the side surface of the first dam DAM1, but is not limited thereto. For example, the second encapsulation layer 152 may be configured to contact at least a portion of the first encapsulation layer 151 disposed on the side surface of the first dam DAM1.

[0257] In this way, the second encapsulation layer 152 can be set without exceeding the non-display area NA via the first dam DAM1.

[0258] The third encapsulation layer 153 can be disposed on the second encapsulation layer 152 and the first encapsulation layer 151.

[0259] The third encapsulation layer 153 can be configured to extend from the display area AA and be configured to extend to at least a portion of the non-display area NA.

[0260] The third encapsulation layer 153 can be configured to cover the second encapsulation layer 152. Alternatively, the third encapsulation layer 153 can also be disposed on the first encapsulation layer 151 in the non-display area NA that does not overlap with the second encapsulation layer 152.

[0261] The third encapsulation layer 153 can be disposed on the first encapsulation layer 151 disposed on the side surface and top surface of the first dam DAM1, and can also be disposed on the first encapsulation layer 151 disposed on the side surface and top surface of the second dam DAM2.

[0262] The first touch buffer layer 161 can be disposed on the third encapsulation layer 153 in the non-display area NA.

[0263] The first touch buffer layer 161 can be configured to extend from the display area AA and extend to at least a portion of the non-display area NA.

[0264] The first touch buffer layer 161 can be configured to overlap with the first encapsulation layer 151 and the third encapsulation layer 153 disposed on the side surface and top surface of the first dam DAM1. Furthermore, the first touch buffer layer 161 can be configured to overlap with the first encapsulation layer 151 and the third encapsulation layer 153 disposed on the side surface and top surface of the second dam DAM2.

[0265] The first touch electrode line 181a can be disposed on the first touch buffer layer 161.

[0266] The first touch electrode line 181a may be a line connected to the first touch electrode 181 disposed in the display area AA.

[0267] The first touch electrode line 181a may contain the same material as the first touch electrode 181.

[0268] The first touch electrode line 181a can be configured to overlap with the first encapsulation layer 151, the third encapsulation layer 153, and the first touch buffer layer 161 disposed on the side and top surfaces of the first dam DAM1. Furthermore, the first touch electrode line 181a can be configured to overlap with the first encapsulation layer 151, the third encapsulation layer 153, and the first touch buffer layer 161 disposed on the side and top surfaces of the second dam DAM2.

[0269] The second touch buffer layer 162 can be disposed on the first touch electrode line 181a.

[0270] The second touch buffer layer 162 can be configured to extend from the display area AA and extend to at least a portion of the non-display area NA.

[0271] The second touch buffer layer 162 can be disposed on the first encapsulation layer 151, the third encapsulation layer 153, the first touch buffer layer 161, and the first touch electrode line 181a disposed on the side surface and the top surface of the first dam DAM1.

[0272] In addition, the second touch buffer layer 162 can be disposed on the first encapsulation layer 151, the third encapsulation layer 153, the first touch buffer layer 161 and the first touch electrode line 181a disposed on the side surface and the top surface of the second dam DAM2.

[0273] The interlayer insulating layer 163 can be disposed on the top surface of the second touch buffer layer 162 in the non-display area NA.

[0274] A portion of the touch interlayer insulating layer 163 may be configured to overlap with the top and side surfaces of the second encapsulation layer 152 disposed in the non-display area NA. Specifically, a portion of the touch interlayer insulating layer 163 may be configured to extend from the display area AA and be disposed in the area between the second encapsulation layer 152 and the first dam DAM1 disposed in the non-display area NA.

[0275] Additionally, a portion of the interlayer insulation layer 163 may be configured to overlap with the first encapsulation layer 151, the third encapsulation layer 153, the first touch buffer layer 161, the first touch electrode line 181a, and the second touch buffer layer 162 disposed on the top and side surfaces of the first dam DAM1.

[0276] Additionally, another portion of the interlayer insulating layer 163 can be configured to overlap with the first encapsulation layer 151, the third encapsulation layer 153, the first touch buffer layer 161, the first touch electrode line 181a, and the second touch buffer layer 162, which are configured to overlap with the top and side surfaces of the second dam DAM2.

[0277] The interlayer insulating layer 163 may be arranged to expose a portion of the top surface of the second touch buffer film 162 in the non-display area NA, but is not limited thereto.

[0278] The second touch electrode line 182a can be disposed on the touch interlayer insulating layer 163.

[0279] The second touch electrode line 182a can be a line connected to the second touch electrode 182 disposed in the display area AA.

[0280] The second touch electrode line 182a may contain the same material as the second touch electrode 182.

[0281] The second touch electrode line 182a can be disposed on the first encapsulation layer 151, the third encapsulation layer 153, the first touch buffer layer 161, the first touch electrode line 181a, the second touch buffer layer 162, and the touch layer insulation layer 163 disposed on the side and top surfaces of the first dam DAM1.

[0282] In addition, the second touch electrode line 182a can be configured to overlap with the first encapsulation layer 151, the third encapsulation layer 153, the first touch buffer layer 161, the first touch electrode line 181a, the second touch buffer layer 162 and the touch layer insulation layer 163 disposed on the side surface and the top surface of the second dam DAM2.

[0283] In other words, the first encapsulation layer 151, the third encapsulation layer 153, the first touch buffer layer 161, the first touch electrode line 181a, the second touch buffer layer 162, the touch interlayer insulation layer 163, and the second touch electrode line 182a can be sequentially stacked on the surface of the first dam DAM1.

[0284] In addition, the first encapsulation layer 151, the third encapsulation layer 153, the first touch buffer layer 161, the first touch electrode line 181a, the second touch buffer layer 162, the touch interlayer insulating layer 163, and the second touch electrode line 182a can be sequentially stacked on the surface of the second dam DAM2.

[0285] On the other hand, the display device 100, which includes multiple touch electrodes TE or color filters 176, has the problem of damaging remaining components during the process of patterning various insulating layers, electrodes, or wiring. As a result, gaps are created, moisture penetration paths are formed, and defects are caused in the light-emitting diodes (EDs).

[0286] Specifically, in the process of forming the first touch electrode 181 and the first touch electrode line 181a, the process of forming the second touch buffer layer 162, or the process of forming the second touch electrode 182 and the second touch electrode line 182a, at least one of the first encapsulation layer 151 and the third encapsulation layer 153 disposed on the first dam DAM1 or the second dam DAM2 is damaged.

[0287] Therefore, due to damage to the first encapsulation layer 151 and the third encapsulation layer 153, a moisture penetration path is created, and the light-emitting diodes (EDs) disposed in the display area AA have a problem of shortened lifespan due to the effect of moisture penetration.

[0288] A display device 100 according to an embodiment of the present disclosure may include a first touch electrode line 181a, which overlaps with a first dam DAM1 and a second dam DAM2, such that no defects occur in the first encapsulation layer 151 and the third encapsulation layer 153 during the process of forming the first touch electrode 181 and the first touch electrode line 181a and the process of forming the second touch buffer layer 162.

[0289] When the first touch electrode line 181a is not disposed on the first dam DAM1 and the second dam DAM2, plasma or wet etching solution may damage the first encapsulation layer 151 and the third encapsulation layer 153 during the process of forming the first touch electrode 181 and the first touch electrode line 181a and the process of forming the second touch buffer layer 162.

[0290] Additionally, a display device 100 according to an embodiment of the present disclosure may include a second touch electrode line 182a on a first dam DAM1 and a second dam DAM2, such that no defects occur in the first encapsulation layer 151 and the third encapsulation layer 153 during the process of forming the second touch electrode 182 and the second touch electrode line 182a, and may include a second touch buffer layer 162 and an inter-touch layer insulating layer 163 overlapping the first dam DAM1 and the second dam DAM2.

[0291] When the first touch electrode line 181a is not disposed on the first dam DAM1 and the second dam DAM2, plasma or wet etching solution may damage the first encapsulation layer 151 and the third encapsulation layer 153 during the process of forming the second touch electrode 182 and the second touch electrode line 182a.

[0292] Furthermore, a second touch buffer layer 162 and an interlayer insulating layer 163 are disposed between the first dam DAM1 and the second dam DAM2 and the second touch electrode line 182a. By disposing the second touch buffer layer 162 and the interlayer insulating layer 163 between the first dam DAM1 and the second dam DAM2 and the second touch electrode line 182a, damage to the first encapsulation layer 151 and the third encapsulation layer 153 due to plasma or wet etching solution during the formation of the second touch electrode 182 and the second touch electrode line 182a can be further suppressed.

[0293] Next, refer to Figure 6 The following details the process of forming the component disposed on the encapsulation layer ENCAP in the non-display area NA.

[0294] Figure 6 This diagram illustrates the process steps for forming a component disposed on the encapsulation layer in a non-display area.

[0295] Reference Figure 6The first touch buffer layer 161 can be deposited on the third encapsulation layer 153 in the non-display area NA.

[0296] Subsequently, a first touch electrode line material can be deposited on the first touch buffer layer 161. Using the first touch electrode line material, a first touch electrode line 181a disposed in the non-display area NA and a first touch electrode 181 disposed in the display area AA can be formed. However, the following description will focus on the process of forming the first touch electrode line 181a disposed in the non-display area NA.

[0297] Specifically, a photoresist can be formed on the material of the first touch electrode line.

[0298] Subsequently, a photoresist can be patterned on the first touch electrode line material using a mask and an exposure process.

[0299] A patterned photoresist can be used as a mask to etch the first touch electrode line material. In this case, a dry etching process using plasma can be employed to etch the first touch electrode line material.

[0300] Subsequently, the material of the first touch electrode line in the area where no photoresist is applied can be removed to form the first touch electrode line 181a in the non-display area NA.

[0301] During the process of forming the first touch electrode line 181a, the dry etching process using plasma may damage the first encapsulation layer 151, the third encapsulation layer 153, and the first touch buffer layer 161 (which are components disposed below the first touch electrode line 181a).

[0302] In this case, gaps may appear in the first encapsulation layer 151 and the third encapsulation layer 153. These gaps are used to prevent moisture from penetrating into the multiple light-emitting diodes (EDs) disposed in the display area AA of the display panel 110.

[0303] The gaps formed in the first encapsulation layer 151 and the third encapsulation layer 153 can serve as pathways for moisture or oxygen to permeate. Therefore, moisture or oxygen permeating from the non-display area NA may reach the light-emitting diode ED disposed in the display area AA.

[0304] Therefore, the lifespan of the light-emitting diode (ED) may be shortened, and the reliability of the display panel 110 may be reduced.

[0305] Specifically, the second encapsulation layer 152 in the encapsulation layer ENCAP that inhibits moisture or oxygen penetration into the light-emitting diode ED may not be provided in at least a portion of the dam region DA in the non-display area NA.

[0306] For example, such as Figure 5 As shown, the second encapsulation layer 152 may not be disposed on the first dam DAM1 and the second dam DAM2. Therefore, in the dam region DA of the non-display region NA, the penetration of moisture and oxygen should be suppressed only by the first encapsulation layer 151 and the third encapsulation layer 153. Therefore, damage to the first encapsulation layer 151 and the third encapsulation layer 153 should be suppressed.

[0307] Meanwhile, in the non-display area NA, in the region where the first touch electrode line 181a is not provided, there is no photoresist to block the plasma during the dry etching process. Therefore, in the region where the first touch electrode line 181a is not provided, damage to the first encapsulation layer 151, the third encapsulation layer 153, and the first touch buffer layer 161 may occur.

[0308] Furthermore, when the material used to form the first touch electrode line 181a is over-etched, the possibility of damaging the first encapsulation layer 151, the third encapsulation layer 153, and the first touch buffer layer 161 will further increase.

[0309] However, in a display device 100 according to an embodiment of the present disclosure, a first touch electrode line 181a is disposed on a first encapsulation layer 151, a third encapsulation layer 153, and a first touch buffer layer 161 disposed on a first dam DAM1 and a second dam DAM2. Therefore, damage to the first encapsulation layer 151, the third encapsulation layer 153, and the first touch buffer layer 161 can be suppressed during the process of forming the first touch electrode line 181a.

[0310] Specifically, since the photoresist disposed on the first touch electrode line 181a is used to block plasma during the dry etching process that forms the first touch electrode line 181a, the components disposed below the first touch electrode line 181a are not affected by the plasma. Therefore, damage to the first encapsulation layer 151, the third encapsulation layer 153, and the first touch buffer layer 161 can be suppressed, thereby extending the lifespan of the light-emitting diode (ED).

[0311] In this way, by improving the lifespan of the light-emitting diodes (EDs) included in the display device 100, which includes multiple touch electrodes (TEs), a display device 100 with improved reliability and low-power operation can be provided.

[0312] Reference Figure 6 A second touch buffer layer material can be formed on a substrate 101 on which the first touch electrode line 181a is formed.

[0313] The second touch buffer layer material may contain inorganic insulating materials.

[0314] Subsequently, an interlayer insulating layer material can be formed on the second touch buffer layer material.

[0315] Interlayer insulation materials for touch can include organic insulating materials.

[0316] Photoresist can be formed on the interlayer insulating material of the touch layer.

[0317] Subsequently, a photoresist can be patterned onto the interlayer insulating material using a mask and an exposure process.

[0318] Patterned photoresist can be used as a mask to cure interlayer insulating materials.

[0319] The photoresist can be removed after the interlayer insulating material has cured.

[0320] Afterwards, the uncured portion of the interlayer insulation material can be removed, and the unremoved portion can become the interlayer insulation layer 163.

[0321] Subsequently, the second touch buffer layer material can be etched using the interlayer insulating layer 163 as a mask. The second touch buffer layer material can be etched using a dry etching process employing plasma.

[0322] Then, the second touch buffer layer material in the area where the touch interlayer insulation layer 163 is not provided can be removed, and the remaining second touch buffer layer material can become the second touch buffer layer 162.

[0323] During the process of forming the second touch buffer layer 162, gaps are created in the first encapsulation layer 151, the third encapsulation layer 153, and the first touch buffer layer 161 (which are components disposed below the second touch buffer layer 162) during a dry etching process using plasma. Therefore, pathways may be created for moisture or oxygen to penetrate into the light-emitting diodes (EDs) disposed in the display area AA.

[0324] In this situation, there may be a problem where power consumption increases as the lifespan of the light-emitting diode (ED) decreases.

[0325] However, in a display device 100 according to an embodiment of the present disclosure, during the process of forming the second touch buffer layer 162, the first touch electrode line 181a can suppress the influence of plasma on the first encapsulation layer 151, the third encapsulation layer 153 and the first touch buffer layer 161 disposed below the first touch electrode line 181a.

[0326] Therefore, the reliability of the first encapsulation layer 151, the third encapsulation layer 153, and the first touch buffer layer 161 disposed in the dam area DA of the non-display area NA is improved. Furthermore, the shortened lifespan of the light-emitting diodes (EDs) disposed in the display area AA due to moisture penetration can be suppressed.

[0327] The second touch electrode line material can be deposited on the touch interlayer insulating layer 163. Using the second touch electrode line material, a second touch electrode line 182a disposed in the non-display area NA and a second touch electrode 182 disposed in the display area AA can be formed. However, the following description will focus on the process of forming the second touch electrode line 182a disposed in the non-display area NA.

[0328] A photoresist can be formed on the material of the second touch electrode line.

[0329] Subsequently, a photoresist can be patterned on the second touch electrode line material using an exposure process and a mask.

[0330] A patterned photoresist can be used as a mask to etch the second touch electrode line material. In this case, a dry etching process using plasma can be employed to etch the second touch electrode line material.

[0331] Then, the material of the second touch electrode line in the area where no photoresist is applied can be removed to form the second touch electrode line 182a in the non-display area NA.

[0332] During the process of forming the second touch electrode line 182a, a dry etching process using plasma may damage the first encapsulation layer 151, the third encapsulation layer 153, and the first touch buffer layer 161 (which are components disposed below the second touch electrode line 182a).

[0333] In particular, when the interlayer insulation layer 163 and the second touch buffer layer 162 disposed below the second touch electrode line 182a are not provided, damage may occur to the insulation layer disposed below the second touch electrode line 182a.

[0334] However, in a display device 100 according to an embodiment of the present disclosure, a second touch buffer layer 162 and an inter-touch layer insulating layer 163 are disposed between the second touch electrode line 182a and the first dam DAM1, and between the second touch electrode line 182a and the second dam DAM2. Therefore, damage to the first encapsulation layer 151, the third encapsulation layer 153, and the first touch buffer layer 161 disposed below the second touch electrode line 182a can be suppressed.

[0335] Specifically, the interlayer insulation layer 163 comprises an organic insulating material. Therefore, even when moisture or oxygen penetrates, the interlayer insulation layer 163 can delay the movement of moisture or oxygen.

[0336] The second touch buffer layer 162 contains an inorganic insulating material. Therefore, even when moisture or oxygen penetrates the interlayer insulation layer 163, it can inhibit the penetration of moisture or oxygen into the component located below the second touch buffer layer 162.

[0337] Furthermore, the second touch electrode line 182a is disposed in the dam region DA. Therefore, damage to the first encapsulation layer 151, the third encapsulation layer 153, and the first touch buffer layer 161, as well as damage to the second touch buffer layer 162 and the touch layer interlayer insulating layer 163 disposed below the second touch electrode line 182a, can be suppressed.

[0338] Specifically, in the non-display area NA, in the region where the second touch electrode line 182a is not provided, there is no photoresist to block the plasma during the dry etching process. Therefore, damage to the second touch buffer layer 162 and the interlayer insulation layer 163 may occur in the region where the second touch electrode line 182a is not provided.

[0339] When the second touch buffer layer 162 and the interlayer insulation layer 163 are damaged and moisture or oxygen permeates, the likelihood of moisture or oxygen permeating into the first encapsulation layer 151, the third encapsulation layer 153 and the first touch buffer layer 161 disposed below the second touch buffer layer 162 increases.

[0340] However, in a display device 100 according to an embodiment of the present disclosure, the second touch electrode line 182a is disposed on the first encapsulation layer 151, the third encapsulation layer 153, and the first touch buffer layer 161 disposed on the first dam DAM1, the second dam DAM2, the second touch buffer layer 162, and the touch interlayer insulation layer 163. Therefore, in the process of forming the second touch electrode line 182a, defects such as moisture or oxygen penetrating through the first encapsulation layer 151, the third encapsulation layer 153, the first touch buffer layer 161, the second touch buffer layer 162, and the touch interlayer insulation layer 163 can be suppressed.

[0341] Furthermore, as described above, the first touch electrode line 181a is disposed on the first dam DAM1 and the second dam DAM2 between the first touch buffer layer 161 and the second touch buffer layer 162. Therefore, even when a gap is generated in the second touch buffer layer 162 or the interlayer insulation layer 163 and moisture or oxygen permeates, the first touch electrode line 181a can be used to inhibit moisture or oxygen from permeating into the first encapsulation layer 151, the third encapsulation layer 153, and the first touch buffer layer 161 disposed below the first touch electrode line 181a.

[0342] Figure 7 This is a cross-sectional view of the non-display area of ​​a display device according to another embodiment of the present disclosure.

[0343] Figure 7 The display device 200 and Figure 5 The difference of the display device 100 is that the third dam DAM3 is further set in the dam area DA, and the other components are basically the same, so repeated descriptions are omitted.

[0344] Reference Figure 7 The dam area DA can be set in the non-display area NA of the display device 200.

[0345] The third dam, DAM3, can be located between the first dam, DAM1, and the second dam, DAM2, within the dam area DA.

[0346] In this way, by placing the third dam DAM3 between the first dam DAM1 and the second dam DAM2, the second dam DAM2 can suppress the overflow of the material of the second encapsulation layer 152 into the dam region DA, even if the first dam DAM1 cannot suppress the overflow of the material of the second encapsulation layer 152 into the dam region DA.

[0347] The third dam DAM3 can be formed by the process of forming the dike 113 and the spacer 114.

[0348] The third dam DAM3 may include a third dam pattern 113c disposed on the second base wiring 135a and a third spacer pattern 114c disposed on the third dam pattern 113c.

[0349] exist Figure 7 In the diagram, the third dam DAM3 is shown as having a structure including a third dam pattern 113c and a third spacer pattern 114c, but is not limited thereto. For example, the third dam pattern 113c and the third spacer pattern 114c can be formed integrally.

[0350] On the third dam DAM3, the first encapsulation layer 151, the third encapsulation layer 153, the first touch buffer layer 161, the first touch electrode line 181a, the second touch buffer layer 162, the touch interlayer insulation layer 163, and the second touch electrode line 182a can be stacked sequentially.

[0351] Furthermore, the first touch electrode line 181a is disposed on the third dam DAM3. Therefore, during the process of forming the first touch electrode line 181a and the first touch electrode 181, damage to the first encapsulation layer 151, the third encapsulation layer 153, and the first touch buffer layer 161 can be suppressed.

[0352] Additionally, a second touch buffer layer 162 and an inter-touch layer insulating layer 163 are disposed on the third dam DAM3. Therefore, the second touch buffer layer 162 and the inter-touch layer insulating layer 163 can serve as additional encapsulation layers to prevent moisture or oxygen from penetrating from the outside.

[0353] Furthermore, the second touch electrode line 182a is disposed on the third dam DAM3. Therefore, during the process of forming the second touch electrode line 182a and the second touch electrode 182, damage to the first encapsulation layer 151, the third encapsulation layer 153, the first touch buffer layer 161, the second touch buffer layer 162 and the touch interlayer insulating layer 163 can be suppressed.

[0354] Therefore, since moisture or oxygen can be prevented from penetrating into the multiple light-emitting diodes (EDs) disposed in the display area AA, the lifespan of the EDs is extended. Therefore, the display device 200 can be driven with low power.

[0355] Figure 8 This is an image showing a portion of the dam area of ​​the display device according to the comparative example.

[0356] Figure 9 This is an image showing a portion of the dam area of ​​the display device according to an embodiment.

[0357] according to Figure 8 The comparative example display device has a structure in which an encapsulation layer is disposed on the dam. Here, the display device according to the comparative example may include a plurality of touch electrodes disposed in the display area.

[0358] Figure 9 yes Figure 5 An enlarged view of only a portion of the structure of the dam area DA. Specifically, Figure 9 The structure shown is formed by a first encapsulation layer 151, a third encapsulation layer 153, a first touch buffer layer 161, and a first touch electrode line 181a disposed on a first dam DAM1.

[0359] First, refer to Figure 8 As can be seen, damage occurred on the surface of the encapsulation layer ENCAP located on the dam DAM. Specifically, the encapsulation layer ENCAP located on the dam DAM may have been damaged during the process of forming multiple touch electrodes.

[0360] In this situation, moisture penetration paths may form in the encapsulation layer, and moisture may seep in due to the formation of moisture penetration paths in the encapsulation layer.

[0361] Moisture that has seeped through the moisture penetration path formed in the encapsulation layer ENCAP on the dam DAM reaches the light-emitting diode (ED) in the display area AA, and the lifespan of the ED may be shortened. As a result, it may become difficult for the display device to operate at low power consumption.

[0362] At the same time, refer to Figure 9As can be seen, the encapsulation layer ENCAP is disposed on the first dam DAM1, the first touch buffer layer 161 is disposed on the encapsulation layer ENCAP, and the first touch electrode line 181a is disposed on the first touch buffer layer 161. Accordingly, it can be seen that the encapsulation layer ENCAP is not damaged.

[0363] Therefore, moisture penetration through the encapsulation layer ENCAP located in the non-display area NA can be suppressed, thus preventing a shortened lifespan of the light-emitting diode (ED). This results in the ability to drive the display device with low power consumption.

[0364] Exemplary embodiments of this disclosure can also be described as follows: According to one aspect of this disclosure, a display device is provided. The display device includes a substrate, the substrate including a display area and a non-display area surrounding the display area and including a dam area, wherein at least one dam is disposed in the dam area. The display device further includes an encapsulation layer disposed on the substrate in the display area and the dam area. The display device further includes a first touch buffer layer disposed on the encapsulation layer in the dam area. The display device further includes a first touch electrode line disposed on the first touch buffer layer in the dam area. The display device further includes a second touch buffer layer disposed on the first touch electrode line in the dam area. The display device further includes a touch interlayer insulating layer disposed on the second touch buffer layer in the dam area. The display device further includes a second touch electrode line disposed on the touch interlayer insulating layer in the dam area. The second touch buffer layer comprises an inorganic insulating material, and the touch interlayer insulating layer comprises an organic insulating material.

[0365] The non-display area may also include an additional area disposed between the display area and the dam area, and the first touch buffer layer may also be disposed in the display area and the additional area.

[0366] The encapsulation layer may include a first encapsulation layer and a third encapsulation layer. The first encapsulation layer may be disposed on at least one dam in the dam area, and the third encapsulation layer may be disposed on the first encapsulation layer in the dam area. The first touch buffer layer may be disposed on at least one dam, the first encapsulation layer and the third encapsulation layer in the dam area.

[0367] The non-display area may also include an additional area disposed between the display area and the dam area, and the first touch electrode line may also be disposed in the additional area. The first touch electrode is disposed in the display area and is connected to the first touch electrode line.

[0368] The encapsulation layer may include a first encapsulation layer and a third encapsulation layer. The first encapsulation layer may be disposed on at least one dam in the dam region, and the third encapsulation layer may be disposed on the first encapsulation layer in the dam region. The first touch electrode line may be disposed on at least one dam, the first encapsulation layer, the third encapsulation layer, and the first touch buffer layer in the dam region.

[0369] The non-display area may also include an additional area disposed between the display area and the dam area, and the second touch buffer layer may also be disposed in the display area and the additional area.

[0370] The encapsulation layer may include a first encapsulation layer and a third encapsulation layer. The first encapsulation layer may be disposed on at least one dam in the dam region, and the third encapsulation layer may be disposed on the first encapsulation layer in the dam region. The second touch buffer layer may be disposed on at least one dam, the first encapsulation layer, the third encapsulation layer, the first touch buffer layer, and the first touch electrode line in the dam region.

[0371] The non-display area may also include an additional area disposed between the display area and the dam area, and the touch interlayer insulation layer may also be disposed in the display area and the additional area.

[0372] The encapsulation layer may include a first encapsulation layer and a third encapsulation layer. The first encapsulation layer may be disposed on at least one dam in the dam region, and the third encapsulation layer may be disposed on the first encapsulation layer in the dam region. The interlayer insulation layer may be disposed on at least one dam, the first encapsulation layer, the third encapsulation layer, the first touch buffer layer, the first touch electrode line, and the second touch buffer layer in the dam region.

[0373] The non-display area may also include an additional area disposed between the display area and the dam area, and the second touch electrode line may also be disposed in the additional area. The second touch electrode is disposed in the display area and is connected to the second touch electrode line.

[0374] The encapsulation layer may include a first encapsulation layer and a third encapsulation layer. The first encapsulation layer may be disposed on at least one dam in the dam region, and the third encapsulation layer may be disposed on the first encapsulation layer in the dam region. The second touch electrode line may be disposed on at least one dam, the first encapsulation layer, the third encapsulation layer, the first touch buffer layer, the first touch electrode line, the second touch buffer layer, and the touch layer interlayer insulating layer in the dam region.

[0375] The display device may further include at least one basic wiring disposed on a substrate in a non-display area, wherein at least one dam is disposed on the at least one basic wiring in the dam area.

[0376] The dam may include a first dam and a second dam spaced apart from the first dam. The first dam may be disposed on a substrate and may contain the same material as the dike disposed in the display area. The second dam may include a planarization layer pattern disposed on the substrate and containing the same material as the planarization layer disposed in the display area, and a dike pattern disposed on the planarization layer pattern and containing the same material as the dike disposed in the display area.

[0377] The dam may also include a third dam disposed between the first dam and the second dam, and the third dam may be disposed on the substrate and disposed on the same layer as the dam disposed in the display area.

[0378] The height of the second dam can be higher than that of the first dam.

[0379] According to another aspect of this disclosure, a display device is provided. The display device includes a substrate, the substrate including a display area and a dam area, the dam area being located around the display area and having at least one dam disposed in the dam area. The display device further includes an encapsulation layer disposed on the substrate in the display area and the dam area. The display device further includes a first touch buffer layer disposed on the encapsulation layer. The display device further includes a first touch electrode line disposed on the first touch buffer layer. The display device further includes a second touch buffer layer disposed on the first touch electrode line. The display device further includes a touch interlayer insulating layer disposed on the second touch buffer layer. The display device further includes a second touch electrode line disposed on the touch interlayer insulating layer. The encapsulation layer, the first touch buffer layer, the first touch electrode line, the second touch buffer layer, the touch interlayer insulating layer, and the second touch electrode line each overlap with a side surface and a top surface of the at least one dam.

[0380] The encapsulation layer may include a first encapsulation layer and a third encapsulation layer. The first encapsulation layer may be disposed on at least one dam in the dam region, and the third encapsulation layer may be disposed on the first encapsulation layer in the dam region. The first touch buffer layer may be disposed on the third encapsulation layer in at least a portion of the dam region.

[0381] The second touch buffer layer may contain inorganic insulating material, and the interlayer insulation layer may contain organic insulating material.

[0382] Although exemplary embodiments of the present disclosure have been described in detail with reference to the accompanying drawings, the present disclosure is not limited thereto and may be embodied in many different forms without departing from the technical concept of the present disclosure. Therefore, the exemplary embodiments of the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above exemplary embodiments are illustrative in all respects and do not limit the present disclosure. All technical concepts within the equivalent scope of the present disclosure should be construed as falling within the scope of the present disclosure.

Claims

1. A display device, comprising: A substrate, the substrate including a display area and a non-display area located around the display area and including a dam area, wherein at least one dam is disposed in the dam area; An encapsulation layer is disposed on the substrate in the display area and the dam area; A first touch buffer layer is disposed on the encapsulation layer in the dam area; The first touch electrode line is disposed on the first touch buffer layer in the dam area; A second touch buffer layer is disposed on the first touch electrode line in the dam area; An interlayer insulating layer is provided on the second touch buffer layer in the dam area; as well as The second touch electrode line is disposed on the interlayer insulating layer in the dam region. The second touch buffer layer contains an inorganic insulating material, and the interlayer insulation layer contains an organic insulating material.

2. The display device according to claim 1, wherein The non-display area further includes an additional area disposed between the display area and the dam area, and The first touch buffer layer is further disposed in the display area and the additional area.

3. The display device according to claim 2, wherein, The encapsulation layer includes a first encapsulation layer and a third encapsulation layer. The first encapsulation layer is disposed on the at least one dam in the dam area. The third encapsulation layer is disposed on the first encapsulation layer in the dam area, and The first touch buffer layer is disposed in the dam area on the at least one dam, the first encapsulation layer and the third encapsulation layer.

4. The display device according to claim 1, wherein, The non-display area further includes an additional area disposed between the display area and the dam area, and The first touch electrode line is further disposed in the additional region, wherein a first touch electrode is disposed in the display area, and the first touch electrode is connected to the first touch electrode line.

5. The display device according to claim 4, wherein, The encapsulation layer includes a first encapsulation layer and a third encapsulation layer. The first encapsulation layer is disposed on at least one dam in the dam region, and the third encapsulation layer is disposed on the first encapsulation layer in the dam region. The first touch electrode line is disposed in the dam region on the at least one dam, the first encapsulation layer, the third encapsulation layer, and the first touch buffer layer.

6. The display device according to claim 1, wherein, The non-display area further includes an additional area disposed between the display area and the dam area, and The second touch buffer layer is further disposed in the display area and the additional area.

7. The display device according to claim 6, wherein, The encapsulation layer includes a first encapsulation layer and a third encapsulation layer. The first encapsulation layer is disposed on the at least one dam in the dam region, and the third encapsulation layer is disposed on the first encapsulation layer in the dam region. The second touch buffer layer is disposed in the dam area on the at least one dam, the first encapsulation layer, the third encapsulation layer, the first touch buffer layer, and the first touch electrode line.

8. The display device according to claim 1, wherein, The non-display area further includes an additional area disposed between the display area and the dam area, and The interlayer insulating layer for touch is further disposed in the display area and the additional area.

9. The display device according to claim 8, wherein, The encapsulation layer includes a first encapsulation layer and a third encapsulation layer. The first encapsulation layer is disposed on at least one dam in the dam region, and the third encapsulation layer is disposed on the first encapsulation layer in the dam region. The interlayer insulation layer is disposed in the dam region on the at least one dam, the first encapsulation layer, the third encapsulation layer, the first touch buffer layer, the first touch electrode line, and the second touch buffer layer.

10. The display device according to claim 1, wherein, The non-display area further includes an additional area disposed between the display area and the dam area, and The second touch electrode line is further disposed in the additional area, and the second touch electrode is disposed in the display area, and the second touch electrode is connected to the second touch electrode line.

11. The display device according to claim 10, wherein, The encapsulation layer includes a first encapsulation layer and a third encapsulation layer. The first encapsulation layer is disposed on the at least one dam in the dam region, and the third encapsulation layer is disposed on the first encapsulation layer in the dam region. The second touch electrode line is disposed in the dam area on the at least one dam, the first encapsulation layer, the third encapsulation layer, the first touch buffer layer, the first touch electrode line, the second touch buffer layer, and the touch layer interlayer insulation layer.

12. The display device according to claim 1, further comprising at least one basic wiring disposed on the substrate in the non-display area. in, The at least one dam is located on the at least one basic wiring in the dam area.

13. The display device according to claim 1, wherein, The dam includes a first dam and a second dam spaced apart from the first dam. The first dam is disposed on the substrate and comprises the same material as the dike disposed in the display area, and The second dam includes a planarization layer pattern disposed on the substrate and containing the same material as the planarization layer disposed in the display area, and a dam pattern disposed on the planarization layer pattern and containing the same material as the dam disposed in the display area.

14. The display device according to claim 13, wherein, The dam further includes a third dam disposed between the first dam and the second dam, and The third dam is disposed on the substrate and is disposed on the same layer as the dike disposed in the display area.

15. The display device according to claim 13, wherein, The height of the second dam is higher than that of the first dam.

16. A display device, comprising: A substrate, the substrate including a display area and a dam area, the dam area being located around the display area and having at least one dam disposed in the dam area; An encapsulation layer is disposed on the substrate in the display area and the dam area; A first touch buffer layer is disposed on the encapsulation layer; The first touch electrode line is disposed on the first touch buffer layer; A second touch buffer layer is disposed on the first touch electrode line; An interlayer insulating layer is disposed on the second touch buffer layer; as well as The second touch electrode line is disposed on the interlayer insulating layer of the touch layer. The encapsulation layer, the first touch buffer layer, the first touch electrode line, the second touch buffer layer, the interlayer insulation layer, and the second touch electrode line each overlap with the side surface and top surface of the at least one dam.

17. The display device according to claim 16, wherein, The encapsulation layer includes a first encapsulation layer and a third encapsulation layer. The first encapsulation layer is disposed on at least one dam in the dam region, and the third encapsulation layer is disposed on the first encapsulation layer in the dam region. The first touch buffer layer is disposed on the third encapsulation layer in at least a portion of the dam area.

18. The display device according to claim 16, wherein, The second touch buffer layer contains an inorganic insulating material, and The interlayer insulation layer of the touch panel contains organic insulating material.

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