HLS code generation method and system for Xilinx FPGA environment

Abstract

This invention provides an HLS code generation method and system for Xilinx FPGA environments, comprising: Step S1: Based on the target task description, obtain the hardware optimization instructions most relevant to the target task description, generate HLS code for the FPGA kernel side according to the current hardware optimization instructions, and iteratively optimize the current HLS code based on code performance to obtain the optimal FPGA kernel HLS code; Step S2: Verify the functional correctness of the optimal FPGA kernel HLS code according to the target task description. If a functional error occurs, repair the current FPGA kernel HLS code to obtain the repaired FPGA kernel HLS code; Step S3: Generate FPGA host side code based on the repaired FPGA kernel HLS code and the target task description, and call Xilinx tools to perform emulation compilation on the repaired FPGA kernel HLS code and the FPGA host side code to generate an FPGA executable program.

Description

Technical Field

[0001] This invention relates to the field of computer application technology, and more specifically, to an HLS code generation method and system for Xilinx FPGA environments. Background Technology

[0002] Field-Programmable Gate Arrays (FPGAs) are a type of logic chip that can be reprogrammed after manufacturing using a Hardware Description Language (HDL). Compared to Application Specific Integrated Circuits (ASICs), FPGAs offer significant advantages such as high flexibility, shorter development cycles, and lower initial costs. Xilinx FPGAs are a family of programmable logic devices developed by AMD Xilinx. Their development process is based on toolchains such as Vivado and Vitis, supporting complete logic synthesis, placement and routing, hardware-software co-design, and High-Level Synthesis (HLS). They play a crucial role in several key industries, including communication base stations, automotive electronics, aerospace and defense, data center acceleration, and embedded intelligent systems.

[0003] In modern integrated circuit design, including FPGAs, designers need to specify the hardware architecture and model the behavioral logic of the digital system by writing hardware description language (HDL) code (such as Verilog, VHDL) or high-level code (such as C, SystemC) and then using high-level synthesis. Due to the increasing complexity of Very Large Scale Integration (VLSI) circuit design, manually writing HDL or HLS code is time-consuming and error-prone, requiring multiple iterations to debug functional correctness. Therefore, reducing design costs and the workload required for designers to complete hardware specifications has become a critical requirement.

[0004] With the remarkable capabilities of large language models (LLMs) in natural language generation and understanding, increasing research is focusing on using LLMs for automatic code generation. In the field of integrated circuit design, the main research areas for LLM-based code generation methods are as follows: 1) generating HLS or RTL code through LLM reasoning; 2) detecting and correcting syntax and functional errors through self-feedback optimization based on LLMs or external tools.

[0005] During the implementation of this invention, it was found that existing LLM-based HLS code generation methods have at least the following technical problems: 1. Existing HLS code generation methods only verify the HLS code at the simulation and synthesis level, but do not verify the HLS code in the actual hardware environment. Hardware simulation usually runs in the transaction-level model (TLM) or QEMU environment, which has a relatively lenient handling of memory model and resource management, and is difficult to fully reflect the running of HLS code in the actual hardware environment. 2. Existing methods only evaluate the syntactic and functional correctness of the generated code, while ignoring the impact of code performance on the actual execution process: functionally correct but low-efficiency code may cause excessive unnecessary resource overhead, resulting in placement and routing failures, timing construction failures, or resource allocation failures when executing in a real hardware environment.

[0006] Therefore, it can be seen that the existing methods have technical problems such as lack of code verification in a real hardware environment and ignoring the impact of code performance on the actual execution process. Summary of the Invention

[0007] In view of the shortcomings of the prior art, the purpose of this invention is to provide an HLS code generation method and system for Xilinx FPGA environment.

[0008] The present invention provides an HLS code generation method for Xilinx FPGA environments, comprising: Step S1: Based on the target task description, obtain the hardware optimization instructions that are most relevant to the target task description, generate HLS code for the FPGA kernel based on the current hardware optimization instructions, and iteratively optimize the current HLS code based on code performance to obtain the optimal FPGA kernel HLS code. Step S2: Verify the functional correctness of the optimal FPGA kernel HLS code according to the target task description. If a functional error occurs, repair the current FPGA kernel HLS code to obtain the repaired FPGA kernel HLS code. Step S3: Generate FPGA host code based on the repaired FPGA kernel HLS code and the target task description, and call Xilinx tools to compile the repaired FPGA kernel HLS code and FPGA host code to generate the FPGA executable program.

[0009] Preferably, step S1 includes: Step S1.1: Obtain the target task description and vectorize the obtained target task description to obtain the target task vector; Step S1.2: Perform similarity matching between the target task vector and the vector database to obtain the hardware optimization instructions most relevant to the target task; wherein, the vector database is a vector generated based on all hardware optimization instructions provided by Vitis HLS; Step S1.3: Based on the hardware optimization instructions that are most relevant to the target task, generate HLS code for the FPGA kernel using a large language model; Step S1.4: Call the Vitis HLS tool to simulate the generated FPGA kernel HLS code and perform performance evaluation. If the performance evaluation does not meet the preset requirements, optimize the HLS code and repeat the process until the optimal FPGA kernel HLS code is obtained.

[0010] Preferably, step S1.2 includes:

[0011] in, For vector databases, A vectorized representation of the target task. The results obtained after similarity retrieval from a vector database One "#pragma" hardware optimization directive; For similarity matching.

[0012] Preferably, step S2 includes: Step S2.1: Use a large language model to generate the task input and its corresponding expected output based on the target task description; Step S2.2: Remove hardware optimization instructions from the optimal kernel HLS code and convert them into kernel functions that are logically equivalent at the C++ level; Step S2.3: Construct a C++ functional verification program based on kernel functions that are logically equivalent at the C++ level; Step S2.4: Compile and execute the C++ functional verification program using the g++ compiler. If the program displays kernel output that matches the expected output, it means that the current kernel HLS code is functionally correct; otherwise, it means that there is a functional error at the C / C++ level in the kernel HLS code. Analyze the cause of the error using the large language model based on the kernel HLS code, input, output, and expected output, and provide a solution. Based on the kernel HLS code error analysis feedback, repair the FPGA kernel HLS code to obtain the repaired FPGA kernel HLS code.

[0013] Preferably, step S3 includes: Step S3.1: Generate FPGA host code based on the repaired FPGA kernel HLS code and the target task description using a large language model; Step S3.2: After obtaining the FPGA host code, call the Vitis HLS tool to compile the repaired FPGA kernel HLS code and FPGA host code for the hardware environment, and obtain the executable programs for the FPGA kernel and host. Step S3.3: Execute the executable program on the host side. The program generates input and calls the executable program on the FPGA kernel side to calculate the output, obtaining the running results of the repaired FPGA kernel HLS code and FPGA host side code in the real FPGA hardware environment; when the program execution reports an error, check the error and repair the host program code.

[0014] The present invention provides an HLS code generation system for Xilinx FPGA environments, comprising: Module M1: Based on the target task description, obtain the hardware optimization instructions that are most relevant to the target task description, generate HLS code for the FPGA kernel based on the current hardware optimization instructions, and iteratively optimize the current HLS code based on code performance to obtain the optimal FPGA kernel HLS code; Module M2: Verifies the functional correctness of the optimal FPGA kernel HLS code based on the target task description. If a functional error occurs, it repairs the current FPGA kernel HLS code to obtain the repaired FPGA kernel HLS code. Module M3: Generates FPGA host code based on the repaired FPGA kernel HLS code and the target task description, and calls Xilinx tools to compile the repaired FPGA kernel HLS code and FPGA host code to generate the FPGA executable program.

[0015] Preferably, the module M1 includes: Module M1.1: Obtains the target task description and performs vectorization processing on the obtained target task description to obtain the target task vector; Module M1.2: Performs similarity matching between the target task vector and the vector database to obtain the hardware optimization instructions most relevant to the target task; wherein, the vector database is a vector generated based on all hardware optimization instructions provided by Vitis HLS; Module M1.3: Based on the hardware optimization instructions most relevant to the target task, generate HLS code for the FPGA kernel using a large language model; Module M1.4: Calls the Vitis HLS tool to simulate the generated FPGA kernel HLS code and perform performance evaluation. If the performance evaluation does not meet the preset requirements, the HLS code is optimized and the process is repeated until the optimal FPGA kernel HLS code is obtained.

[0016] Preferably, the module M1.2 includes:

[0017] in, For vector databases, A vectorized representation of the target task. The results obtained after similarity retrieval from a vector database One "#pragma" hardware optimization directive; For similarity matching.

[0018] Preferably, the module M2 includes: Module M2.1: Utilizes a large language model to generate task inputs and their corresponding expected outputs based on the target task description; Module M2.2: Removes hardware optimization instructions from the optimal kernel HLS code and converts them into kernel functions that are logically equivalent at the C++ level; Module M2.3: Constructs a C++ functional verification program based on logically equivalent kernel functions at the C++ level; Module M2.4: Calls the g++ compiler to compile and execute the C++ functional verification program. When the program displays kernel output that matches the expected output, it means that the current kernel HLS code is functionally correct; otherwise, it means that there is a functional error at the C / C++ level in the kernel HLS code. Using the large language model, it analyzes the cause of the error based on the kernel HLS code, input, output, and expected output, and provides a solution. Based on the kernel HLS code error analysis feedback, it repairs the FPGA kernel HLS code to obtain the repaired FPGA kernel HLS code.

[0019] Preferably, the module M3 includes: Module M3.1: Generates FPGA host code based on the repaired FPGA kernel HLS code and the target task description using a large language model; Module M3.2: After obtaining the FPGA host code, it calls the Vitis HLS tool to compile the repaired FPGA kernel HLS code and FPGA host code for the hardware environment, resulting in executable programs for the FPGA kernel and host. Module M3.3: Executes an executable program on the host side. The program generates input and calls the executable program on the FPGA kernel side to calculate the output, obtaining the running results of the repaired FPGA kernel HLS code and FPGA host side code in the real FPGA hardware environment; when the program execution reports an error, it checks the error and repairs the host program code.

[0020] Compared with the prior art, the present invention has the following beneficial effects: 1. This invention constructs an end-to-end generation framework from task description to FPGA executable program, realizing end-to-end generation from task description to executable program, and providing an efficient executability verification process for HLS design; 2. The HLS code generated by LLM in this invention has significant improvements in compilability, synthesizability, and functional correctness; 3. Compared with other LLM-based HLS code generation methods, this invention ensures the executableness of the generated HLS code in a real FPGA environment, while significantly improving the compilability, synthesizability and functional accuracy of the generated HLS code. 4. This invention aims to solve the technical problems of current LLM-based HLS code generation methods lacking code verification in a real hardware environment and ignoring the impact of code performance on the actual execution process. It proposes an HLS code generation method for Xilinx FPGA environment.

[0021] 5. This invention addresses the technical problems of current LLM-based HLS code generation methods, which lack code verification in a real hardware environment and ignore the impact of code performance on the actual execution process. 6. Compared with other HDL (Hardware Description Language) generation methods, this invention improves the success rate of code generation and functional accuracy, while realizing end-to-end generation from task description to executable program, and provides an efficient execution and verification framework for HLS design. Attached Figure Description

[0022] Other features, objects, and advantages of the present invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings: Figure 1This is a flowchart of the HLS code generation method for Xilinx FPGA environments. Detailed Implementation

[0023] The present invention will now be described in detail with reference to specific embodiments. These embodiments will help those skilled in the art to further understand the present invention, but do not limit the invention in any way. It should be noted that those skilled in the art can make several changes and improvements without departing from the concept of the present invention. These all fall within the protection scope of the present invention.

[0024] Example 1 According to the present invention, an HLS code generation method for Xilinx FPGA environment is provided, such as... Figure 1 As shown, it includes: Step S1: Based on the target task description, obtain the hardware optimization instructions that are most relevant to the target task description, generate HLS code for the FPGA kernel based on the current hardware optimization instructions, and iteratively optimize the current HLS code based on code performance to obtain the optimal FPGA kernel HLS code. Specifically, step S1 includes: selecting a suitable HLS code optimization method according to the task description; prompting the large language model to adopt the corresponding optimization method to generate FPGA kernel HLS code; calling Xilinx tools to simulate and evaluate the performance of the generated HLS code, and storing the best one into the HLS code pool; performing multiple iterations and selecting the kernel HLS code with the best performance through the principle of evolution. More specifically, the HLS tool provides dedicated hardware directives "#pragma" to guide optimizations during code compilation and synthesis, such as loop unrolling, pipelining, memory partitioning, and data flow. For all hardware optimization directives provided by Vitis HLS, we have compiled their official documentation, including usage instructions and code examples, and built a vector database based on this.

[0025] After receiving the task description input, the task description is vectorized and matched against a vector database for similarity.

[0026] in, For vector databases, A vectorized representation of the task description. The results obtained after similarity retrieval from a vector database A "#pragma" hardware optimization directive.

[0027] After obtaining the hardware optimization instructions most relevant to the task, the large language model is prompted to use these instructions to generate HLS code for the FPGA kernel. The Vitis HLS tool is then called to perform C simulation and HLS synthesis tests on the generated code. If the code can be correctly synthesized, the HLS code and its simulation performance (latency, resource consumption, etc.) are added to the code population. When the code population reaches its maximum size, the best code is selected based on its simulation performance. The code serves as the initial population for the next iteration. After a specified number of iterations, the FPGA kernel HLS code that can be correctly synthesized and achieves optimal simulation performance is obtained.

[0028] Step S2: Verify the functional correctness of the optimal FPGA kernel HLS code according to the target task description. If a functional error occurs, repair the current FPGA kernel HLS code to obtain the repaired FPGA kernel HLS code. Specifically, step S2 includes: prompting the large language model to construct appropriate input and expected output based on the task description, and generating a C++ verification program that calls the kernel function based on this; compiling and executing the verification program, and judging whether the kernel code is functionally correct based on whether the program output is the same as the expected output; if the function is incorrect, analyzing the cause of the error based on the actual program output, feeding back the error code and the cause of the error to the large language model, and performing iterative optimization of the kernel code; More specifically, after obtaining a set of FPGA kernel HLS code that can be correctly synthesized and has optimal simulation performance, its functional correctness is checked to verify whether it can meet the task requirements.

[0029] First, the large language model is prompted to generate appropriate task inputs and their corresponding expected outputs based on the task description. Hardware optimization instructions in the kernel HLS code are removed and transformed into kernel functions that are logically equivalent at the C++ level. Based on this, a C++ functional verification program is built, in which the main function is responsible for generating inputs, calling kernel functions, and verifying function outputs.

[0030] After obtaining the C++ functional verification program, the g++ compiler is called to compile and execute the program. If the program displays kernel output that matches the expectations, it means that the kernel HLS code is functionally correct; otherwise, it means that there is a functional error at the C / C++ level in the HLS code. At this time, the system prompts the large language model to analyze the error cause based on the HLS code, input, output and expected output and provide a solution. Finally, the kernel HLS code-error analysis is fed back to the kernel code generation module for code repair.

[0031] Step S3: Generate FPGA host code based on the repaired FPGA kernel HLS code and the target task description, and call Xilinx tools to compile the repaired FPGA kernel HLS code and FPGA host code to generate the FPGA executable program.

[0032] Specifically, step S3 includes: calling Xilinx tools to compile HLS code and generate an FPGA executable program; executing the program on an actual FPGA platform and verifying the program output; if the program execution encounters an error, collecting error logs and feeding back the host code and error logs to the large language model for host code error repair. More specifically, after functional correctness verification, the FPGA kernel code that can be correctly synthesized, has good simulation performance, and is functionally correct is obtained, and its execution on real FPGA hardware is tested.

[0033] First, the large language model is prompted to generate FPGA host code based on the current FPGA kernel code and task description. At the same time, the large language model is given an example of host code based on XRT, including the control execution flow, parameter initialization, memory allocation and data transmission.

[0034] After obtaining the host-side code, the Vitis HLS tool is used to compile all HLS code for the hardware environment, resulting in an FPGA kernel-side (.xclbin) and a host-side executable program. The executable program is executed on the host side; it generates inputs and calls the FPGA kernel program to calculate the outputs, thus obtaining the running results of the HLS code in a real FPGA hardware environment.

[0035] If an error occurs during program execution, the error is checked. If the error is due to incorrect parameter settings or memory allocation in the host program, the error is reported back to the host code generation module for code repair in the host program.

[0036] The present invention also provides an HLS code generation system for Xilinx FPGA environment. The HLS code generation system for Xilinx FPGA environment can be implemented by executing the process steps of the HLS code generation method for Xilinx FPGA environment. That is, those skilled in the art can understand the HLS code generation method for Xilinx FPGA environment as a preferred embodiment of the HLS code generation system for Xilinx FPGA environment.

[0037] Table 1 shows a comparison of the performance of this invention across multiple models. This invention (LLM4FPGA) achieves effective performance improvements on all basic models. Compared to the zero-shot method, this invention improves synthesability by an average of 16.9%, executability by 26.7%, and functional accuracy by 30.6%.

[0038] Based on Gemini 3.1 Pro, this invention achieved a maximum functional accuracy of 92.3%, fully demonstrating the strong synergy between the basic model and the LLM4FPGA end-to-end verification process.

[0039] On qwen3-coder-30B-A3B, the present invention still achieved a functional accuracy of 66.7%; this shows that the framework is not only effective for high-performance closed-source models, but also significantly improves the usability and feasibility of medium-sized open-source models in HLS generation tasks.

[0040] Table 1

[0041] Those skilled in the art will understand that, in addition to implementing the system, apparatus, and their modules provided by this invention in purely computer-readable program code, the same program can be implemented in the form of logic gates, switches, application-specific integrated circuits, programmable logic controllers, and embedded microcontrollers by logically programming the method steps. Therefore, the system, apparatus, and their modules provided by this invention can be considered a hardware component, and the modules included therein for implementing various programs can also be considered structures within the hardware component; alternatively, modules for implementing various functions can be considered both software programs implementing the method and structures within the hardware component.

[0042] Specific embodiments of the present invention have been described above. It should be understood that the present invention is not limited to the specific embodiments described above, and those skilled in the art can make various changes or modifications within the scope of the claims, which do not affect the essence of the present invention. Unless otherwise specified, the embodiments and features described in this application can be arbitrarily combined with each other.

Claims

1. A HLS code generation method for Xilinx FPGA environment, characterized in that, include: Step S1: Based on the target task description, obtain the hardware optimization instructions that are most relevant to the target task description, generate HLS code for the FPGA kernel based on the current hardware optimization instructions, and iteratively optimize the current HLS code based on code performance to obtain the optimal FPGA kernel HLS code. Step S2: Verify the functional correctness of the optimal FPGA kernel HLS code according to the target task description. If a functional error occurs, repair the current FPGA kernel HLS code to obtain the repaired FPGA kernel HLS code. Step S3: Generate FPGA host code based on the repaired FPGA kernel HLS code and the target task description, and call Xilinx tools to compile the repaired FPGA kernel HLS code and FPGA host code to generate the FPGA executable program.

2. The HLS code generation method for Xilinx FPGA environment according to claim 1, characterized in that, Step S1 includes: Step S1.1: Obtain the target task description and vectorize the obtained target task description to obtain the target task vector; Step S1.2: Perform similarity matching between the target task vector and the vector database to obtain the hardware optimization instructions most relevant to the target task; wherein, the vector database is a vector generated based on all hardware optimization instructions provided by Vitis HLS; Step S1.3: Based on the hardware optimization instructions that are most relevant to the target task, generate HLS code for the FPGA kernel using a large language model; Step S1.4: Call the Vitis HLS tool to simulate the generated FPGA kernel HLS code and perform performance evaluation. If the performance evaluation does not meet the preset requirements, optimize the HLS code and repeat the process until the optimal FPGA kernel HLS code is obtained.

3. The HLS code generation method for Xilinx FPGA environment according to claim 2, characterized in that, Step S1.2 includes: in, For vector databases, A vectorized representation of the target task. The results obtained after similarity retrieval from the vector database One "#pragma" hardware optimization directive; For similarity matching.

4. The HLS code generation method for Xilinx FPGA environment according to claim 1, characterized in that, Step S2 includes: Step S2.1: Use a large language model to generate the task input and its corresponding expected output based on the target task description; Step S2.2: Remove hardware optimization instructions from the optimal kernel HLS code and convert them into kernel functions that are logically equivalent at the C++ level; Step S2.3: Construct a C++ functional verification program based on kernel functions that are logically equivalent at the C++ level; Step S2.4: Compile and execute the C++ functional verification program using the g++ compiler. If the program displays kernel output that matches the expected output, it means that the current kernel HLS code is functionally correct; otherwise, it means that there is a functional error at the C / C++ level in the kernel HLS code. Analyze the cause of the error using the large language model based on the kernel HLS code, input, output, and expected output, and provide a solution. Based on the kernel HLS code error analysis feedback, repair the FPGA kernel HLS code to obtain the repaired FPGA kernel HLS code.

5. The HLS code generation method for Xilinx FPGA environment according to claim 1, characterized in that, Step S3 includes: Step S3.1: Generate FPGA host code based on the repaired FPGA kernel HLS code and the target task description using a large language model; Step S3.2: After obtaining the FPGA host code, call the Vitis HLS tool to compile the repaired FPGA kernel HLS code and FPGA host code for the hardware environment, and obtain the executable programs of the FPGA kernel and host. Step S3.3: Execute the executable program on the host side. The program generates input and calls the executable program on the FPGA kernel side to calculate the output, obtaining the running results of the repaired FPGA kernel HLS code and FPGA host side code in the real FPGA hardware environment; when the program execution reports an error, check the error and repair the host program code.

6. An HLS code generation system for Xilinx FPGA environments, characterized in that, include: Module M1: Based on the target task description, obtain the hardware optimization instructions that are most relevant to the target task description, generate HLS code for the FPGA kernel based on the current hardware optimization instructions, and iteratively optimize the current HLS code based on code performance to obtain the optimal FPGA kernel HLS code; Module M2: Verifies the functional correctness of the optimal FPGA kernel HLS code based on the target task description. If a functional error occurs, it repairs the current FPGA kernel HLS code to obtain the repaired FPGA kernel HLS code. Module M3: Generates FPGA host code based on the repaired FPGA kernel HLS code and the target task description, and calls Xilinx tools to compile the repaired FPGA kernel HLS code and FPGA host code to generate the FPGA executable program.

7. The HLS code generation system for Xilinx FPGA environment according to claim 6, characterized in that, The module M1 includes: Module M1.1: Obtains the target task description and performs vectorization processing on the obtained target task description to obtain the target task vector; Module M1.2: Performs similarity matching between the target task vector and the vector database to obtain the hardware optimization instructions most relevant to the target task; wherein, the vector database is a vector generated based on all hardware optimization instructions provided by Vitis HLS; Module M1.3: Based on the hardware optimization instructions most relevant to the target task, generate HLS code for the FPGA kernel using a large language model; Module M1.4: Calls the Vitis HLS tool to simulate the generated FPGA kernel HLS code and perform performance evaluation. If the performance evaluation does not meet the preset requirements, the HLS code is optimized and the process is repeated until the optimal FPGA kernel HLS code is obtained.

8. The HLS code generation system for Xilinx FPGA environment according to claim 7, characterized in that, The module M1.2 includes: in, For vector databases, A vectorized representation of the target task. The results obtained after similarity retrieval from the vector database One "#pragma" hardware optimization directive; For similarity matching.

9. The HLS code generation system for Xilinx FPGA environment according to claim 6, characterized in that, The module M2 includes: Module M2.1: Utilizes a large language model to generate task inputs and their corresponding expected outputs based on the target task description; Module M2.2: Removes hardware optimization instructions from the optimal kernel HLS code and converts them into kernel functions that are logically equivalent at the C++ level; Module M2.3: Constructs a C++ functional verification program based on logically equivalent kernel functions at the C++ level; Module M2.4: Calls the g++ compiler to compile and execute the C++ functional verification program. When the program displays kernel output that matches the expected output, it means that the current kernel HLS code is functionally correct; otherwise, it means that there is a functional error at the C / C++ level in the kernel HLS code. Using the large language model, it analyzes the cause of the error based on the kernel HLS code, input, output, and expected output, and provides a solution. Based on the error analysis feedback of the kernel HLS code, it repairs the FPGA kernel HLS code to obtain the repaired FPGA kernel HLS code.

10. The HLS code generation system for Xilinx FPGA environment according to claim 6, characterized in that, The module M3 includes: Module M3.1: Generates FPGA host code based on the repaired FPGA kernel HLS code and the target task description using a large language model; Module M3.2: After obtaining the FPGA host code, it calls the Vitis HLS tool to compile the repaired FPGA kernel HLS code and FPGA host code for the hardware environment, resulting in executable programs for the FPGA kernel and host. Module M3.3: Executes an executable program on the host side. The program generates input and calls the executable program on the FPGA kernel side to calculate the output, obtaining the running results of the repaired FPGA kernel HLS code and FPGA host side code in the real FPGA hardware environment; when the program execution reports an error, it checks the error and repairs the host program code.

Images