Method for raid striping and apparatus therefor

Abstract

In some aspects, a memory system is provided. The memory system may include a memory device and a memory controller. The memory device may include one or more dies, each comprising multiple facets. Each of the multiple facets may include a subset of pages to form a striped group in the one or more dies, and one word line of multiple word lines may be coupled to R strings in each facet to form R pages. The striped group may form J stripes. The ratio of J to R may be a value greater than 1 and less than 2. The memory controller may be coupled to the memory device and configured to: receive data portions corresponding to the J stripes; generate J parity data portions based on the data portions; and control the memory device to store the J parity data portions.

Description

Technical Field

[0001] This disclosure generally relates to data storage methods and apparatus, and more specifically, to techniques and related apparatus for striping redundant arrays of independent disks (RAID). Background Technology

[0002] With the rapid development of the Internet and the increasing reliance on mission-critical applications, the need to protect data integrity and ensure uninterrupted access to critical information has become paramount. To meet these requirements, RAID algorithms have been developed to improve performance and reliability, reduce power consumption, and increase the scalability of data storage, especially in NAND-based memory devices. These algorithms utilize techniques such as data striping, mirroring, and parity-based error correction to build highly reliable and efficient storage systems capable of storing large amounts of data while minimizing the risk of data loss or corruption. Summary of the Invention

[0003] In some aspects, a memory system is provided. The memory system may include a memory device and a memory controller. The memory device may include one or more dies, each comprising multiple faces. Each of the multiple faces may include a subset of pages to form a striped group in the one or more dies, and one of the multiple word lines may be coupled to R strings in each face to form R pages. The striped group may form J stripes. The ratio of J to R may be a value greater than 1 and less than 2. The memory controller may be coupled to the memory device and configured to: receive data portions corresponding to the J stripes; generate J parity data portions based on the data portions; and control the memory device to store the J parity data portions.

[0004] In some implementations, the ratio of J to R can be equal to 1.5.

[0005] In some implementations, the ratio of J to R can be equal to 1.25.

[0006] In some implementations, the ratio of J to R can be equal to 1.75.

[0007] In some implementations, the memory controller may also be configured to determine the ratio of J to R based on the distribution of programming faults associated with the memory device.

[0008] In some implementations, within a subset of pages, two i-th pages of two adjacent word lines coupled to multiple word lines in the same string can belong to two stripes in J stripes, 1≤i≤R.

[0009] In some implementations, within a subset of pages, two adjacent pages coupled to the same word line among multiple word lines may belong to two of J stripes.

[0010] In some implementations, within a subset of pages, each of the first, second, and third pages coupled to the same word line may belong to a corresponding strip in J strips. The second and third pages may be adjacent to the first page corresponding to the same word line.

[0011] In some implementations, within a subset of pages, each of the fourth, fifth, and sixth pages, respectively coupled to the first, second, and third word lines, can belong to a corresponding strip among J strips. The first and third word lines can be adjacent to the second word line. The fourth, fifth, and sixth pages can correspond to the same string.

[0012] In some implementations, the first strip of the J strips may include a first set of pages and a second set of pages. The first set of pages may include the i-th page from each subset of pages coupled to a first word line in the plurality of word lines, 1≤i≤R; and the second set of pages may include the j-th page from each subset of pages coupled to a second word line adjacent to the first word line, 1≤j≤R and j≠i.

[0013] In some implementations, the first strip of the J strips may include a third set of pages and a fourth set of pages. The third set of pages may include the i-th page from each subset of pages coupled to the first word line in the multiple word lines, 1≤i≤R; and the fourth set of pages may include the i-th page from each subset of pages coupled to the third word line, which may not be adjacent to the first word line.

[0014] In some implementations, the memory controller may also be configured to perform encoding operations on the data portions to generate J parity data portions.

[0015] In some implementations, the memory controller may also be configured to: receive a first data portion of a first page corresponding to a subset of pages and a second data portion of a second page corresponding to a subset of pages; and perform an XOR operation on the first data portion and the second data portion.

[0016] In some implementations, one of the J stripes corresponds to one of the J parity data portions; and the memory controller may also be configured to control the memory device to store the parity data portion of the J parity data portions in the last page of the stripe.

[0017] In some implementations, the memory controller may also be configured to, in response to a read fault associated with the third data portion: locate the third data portion corresponding to the read fault in the memory device; obtain the remaining data portion and the first parity data portion in a stripe having the third data portion; generate a reconstructed data portion based on the first parity data portion and the remaining data portion; and replace the third data portion with the reconstructed data portion.

[0018] In some implementations, the memory controller may be configured to perform an XOR operation on the remaining data portion and the first parity data portion to generate the reconstructed data portion.

[0019] In some implementations, the memory controller may also be configured to send a notification signal to a host coupled to the memory controller when no read fault is associated with J stripes.

[0020] In some implementations, the memory device may include NAND memory cells, and the memory controller may include a flash memory controller.

[0021] In some aspects, a memory controller is provided, including a processor and interface (I / F) circuitry coupled to a memory device. The memory device may include one or more dies, each comprising multiple faces. Each of the multiple faces may include a subset of pages corresponding to multiple word lines to form a striped group in the one or more dies. One word line of the multiple word lines may be coupled to R strings in each face to form R pages. The striped group may form J stripes. Each of R and J may be an integer, and the ratio of J to R may be a value greater than 1 and less than 2. The processor may be coupled to the I / F interface and configured to: receive data portions corresponding to the J stripes; generate J parity data portions based on the data portions; and control the I / F circuitry to send write commands, data portions, and the J parity data portions to the memory device to store the J parity data portions and the data portions in the memory device.

[0022] In some implementations, the ratio of J to R can be equal to 1.5.

[0023] In some implementations, the ratio of J to R can be equal to 1.25.

[0024] In some implementations, the ratio of J to R can be equal to 1.75.

[0025] In some implementations, the processor may also be configured to determine the ratio of J to R based on the distribution of programming faults associated with the memory device.

[0026] In some implementations, within a subset of pages, two i-th pages of two adjacent word lines coupled to multiple word lines in the same string can belong to two stripes in J stripes, 1≤i≤R.

[0027] In some implementations, within a subset of pages, two adjacent pages coupled to the same word line among multiple word lines may belong to two of J stripes.

[0028] In some implementations, within a subset of pages, each of the first, second, and third pages coupled to the same word line may belong to a corresponding strip in J strips. The second and third pages may be adjacent to the first page corresponding to the same word line.

[0029] In some implementations, within a subset of pages, each of the fourth, fifth, and sixth pages, respectively coupled to the first, second, and third word lines, can belong to a corresponding strip among J strips. The first and third word lines can be adjacent to the second word line. The fourth, fifth, and sixth pages can correspond to the same string.

[0030] In some implementations, the first strip of the J strips may include a first set of pages and a second set of pages. The first set of pages may include the i-th page from each subset of pages coupled to a first word line in the plurality of word lines, 1≤i≤R; and the second set of pages may include the j-th page from each subset of pages coupled to a second word line adjacent to the first word line, 1≤j≤R and j≠i.

[0031] In some implementations, the first strip of the J strips may include a third set of pages and a fourth set of pages. The third set of pages may include the i-th page from each subset of pages coupled to the first word line in the multiple word lines, 1≤i≤R; and the fourth set of pages may include the i-th page from each subset of pages coupled to the third word line, which may not be adjacent to the first word line.

[0032] In some implementations, the processor may also be configured to perform encoding operations on the data portions to generate J parity data portions.

[0033] In some implementations, the processor may also be configured to: control the I / F circuitry to receive a first data portion of a first page corresponding to a subset of pages and a second data portion of a second page corresponding to a subset of pages; and perform an XOR operation on the first data portion and the second data portion.

[0034] In some implementations, one of the J stripes may correspond to one of the J parity data portions. The processor may also be configured to: generate a write command; and control the I / F circuitry to send the write command and the parity data portion to the memory device to store the parity data portion in the last page of the stripe.

[0035] In some implementations, the processor may also be configured to, in response to a read fault associated with the third data portion: locate the third data portion corresponding to the read fault in the memory device; obtain the remaining data portion and the first parity data portion in the stripe having the third data portion; generate a reconstructed data portion based on the first parity data portion and the remaining data portion; and control the I / F circuitry to send the reconstructed data portion to the memory device for storing the reconstructed data portion in the memory device.

[0036] In some implementations, the processor can also be configured to generate J parity data portions in parallel.

[0037] In some aspects, a method for striping a Redundant RAID (RAID) array is provided. The method can be implemented in a memory device comprising one or more dies, each comprising multiple faces. Each face may include a subset of pages corresponding to multiple word lines to form a striped group in the one or more dies. One word line may be coupled to R strings in each face to form R pages. The striped group may form J stripes. Each of R and J may be an integer, and the ratio of J to R may be a value greater than 1 and less than 2. The method may include: receiving data portions corresponding to the J stripes; generating J parity data portions based on the data portions; and controlling the memory device to store the J parity data portions.

[0038] In some implementations, the ratio of J to R can be equal to 1.5.

[0039] In some implementations, the ratio of J to R can be equal to 1.25.

[0040] In some implementations, the ratio of J to R can be equal to 1.75.

[0041] In some implementations, the method may further include determining the ratio of J to R based on the distribution of programming faults associated with the memory device.

[0042] In some implementations, within a subset of pages, two i-th pages of two adjacent word lines coupled to multiple word lines in the same string can belong to two stripes in J stripes, 1≤i≤R.

[0043] In some implementations, within a subset of pages, two adjacent pages coupled to the same word line among multiple word lines may belong to two of J stripes.

[0044] In some implementations, within a subset of pages, each of the first, second, and third pages coupled to the same word line may belong to a corresponding strip in J strips. The second and third pages may be adjacent to the first page corresponding to the same word line.

[0045] In some implementations, within a subset of pages, each of the fourth, fifth, and sixth pages, respectively coupled to the first, second, and third word lines, can belong to a corresponding strip among J strips. The first and third word lines can be adjacent to the second word line. The fourth, fifth, and sixth pages can correspond to the same string.

[0046] In some implementations, the first strip of the J strips may include a first set of pages and a second set of pages. The first set of pages may include the i-th page from each subset of pages coupled to a first word line in the plurality of word lines, 1≤i≤R; and the second set of pages may include the j-th page from each subset of pages coupled to a second word line adjacent to the first word line, 1≤j≤R and j≠i.

[0047] In some implementations, the first strip of the J strips may include a third set of pages and a fourth set of pages. The third set of pages may include the i-th page from each subset of pages coupled to the first word line of the multiple word lines, 1≤i≤R; and the fourth set of pages may include the i-th page from each subset of pages coupled to the third word line that is not adjacent to the first word line.

[0048] In some implementations, generating J parity data portions based on the data portions may include performing an encoding operation on the data portions to generate J parity data portions.

[0049] In some implementations, generating J parity data portions based on the data portions may include receiving a first data portion of a first page corresponding to a subset of pages and a second data portion of a second page corresponding to a subset of pages; and performing an XOR operation on the first data portion and the second data portion.

[0050] In some implementations, one of the J stripes may correspond to one of the J parity data portions; and controlling the memory device to store the J parity data portions may include controlling the memory device to store the parity data portions in the last page of the stripe.

[0051] In some embodiments, the method may further include, in response to a read failure associated with the third data portion: locating the third data portion corresponding to the read failure in the memory device; obtaining the remaining data portion and a first parity data portion in a stripe having the third data portion; generating a reconstructed data portion based on the first parity data portion and the remaining data portion; and replacing the third data portion with the reconstructed data portion.

[0052] In some implementations, generating the reconstructed data portion may include performing an XOR operation on the remaining data portion and the first parity data portion to generate the reconstructed data portion.

[0053] In some implementations, the method may further include sending a notification signal to the host when no read fault is associated with J stripes.

[0054] In some aspects, a nontransitory storage medium coupled to a memory device and a processor is provided. The memory device may include one or more dies, each comprising multiple faces. Each of the multiple faces may include a subset of pages corresponding to multiple word lines to form a striped group in the one or more dies. One word line of the multiple word lines may be coupled to R strings in each face to form R pages. The striped group may form J stripes. Each of R and J may be an integer, and the ratio of J to R may be a value greater than 1 and less than 2. The nontransitory storage medium may be configured to store instructions that, when executed by a processor, cause the processor to: receive data portions corresponding to the J stripes; generate J parity data portions based on the data portions; and control the memory device to store the J parity data portions. Attached Figure Description

[0055] The accompanying drawings, which are incorporated herein and form part of the specification, illustrate some embodiments of the present disclosure and, together with the specification, further serve to explain the principles of the present disclosure and enable those skilled in the art to make and use the present disclosure.

[0056] Figure 1A A schematic diagram illustrating an example hierarchy of a memory device according to some aspects of this disclosure is shown.

[0057] Figure 1B A circuit diagram of an example memory device including peripheral circuitry according to some aspects of this disclosure is shown.

[0058] Figure 1C A schematic diagram of an example physical structure of a memory cell array according to some aspects of this disclosure is shown.

[0059] Figure 2AA schematic diagram of example data structures and striping configurations for implementing a RAID algorithm in a memory device according to some aspects of this disclosure is shown.

[0060] Figure 2B A schematic diagram illustrating multiple storage strings in two storage blocks according to some aspects of this disclosure is shown.

[0061] Figure 2C Some aspects of this disclosure are shown. Figure 2A A schematic diagram of an example striped configuration from another perspective.

[0062] Figure 3A A schematic diagram of another example data structure and striping configuration for a RAID algorithm implemented in a memory device according to some aspects of this disclosure is shown.

[0063] Figure 3B Some aspects of this disclosure are shown. Figure 3A A schematic diagram of an example striped configuration from another perspective.

[0064] Figure 4A A schematic diagram of an example system implementing non-integer striping configuration according to some aspects of this disclosure is shown.

[0065] Figure 4B A diagram of an example memory card having a memory device according to some aspects of this disclosure is shown.

[0066] Figure 4C A diagram of an example solid-state drive (SSD) having a memory device according to some aspects of this disclosure is shown.

[0067] Figure 5A A schematic diagram of an example memory controller for use in a RAID process, in cooperation with a host and a memory device, is shown, according to some aspects of this disclosure.

[0068] Figure 5B A schematic diagram of an example memory device including a memory cell array and peripheral circuitry is shown, according to some aspects of this disclosure.

[0069] Figure 6A A schematic diagram of a first example data structure and non-integer striping configuration for a RAID algorithm implemented in a memory device, according to some aspects of this disclosure, is shown.

[0070] Figure 6B Some aspects of this disclosure are shown. Figure 6A The first example of a striped configuration is illustrated from another perspective.

[0071] Figure 7A flowchart illustrating an example method for operating a memory device according to some aspects of this disclosure is shown.

[0072] Figure 8 A bar graph is shown illustrating the distribution of programming faults in different strings in a memory device according to some aspects of this disclosure.

[0073] Figure 9A and Figure 9B A flowchart illustrating an example method for determining stripes according to some aspects of this disclosure is shown.

[0074] Figure 10 A schematic diagram of a second example data structure and non-integer striping configuration for a RAID algorithm implemented in a memory device, according to some aspects of this disclosure, is shown.

[0075] Figure 11 A schematic diagram of a third example data structure and non-integer striping configuration for a RAID algorithm implemented in a memory device, according to some aspects of this disclosure, is shown.

[0076] Figure 12 A schematic diagram of a fourth example data structure and non-integer striping configuration for a RAID algorithm implemented in a memory device, according to some aspects of this disclosure, is shown.

[0077] Figure 13 A schematic diagram of a fifth example data structure and non-integer striping configuration for a RAID algorithm implemented in a memory device, according to some aspects of this disclosure, is shown.

[0078] Figure 14A A schematic diagram of a sixth example data structure and non-integer striping configuration for a RAID algorithm implemented in a memory device, according to some aspects of this disclosure, is shown.

[0079] Figure 14B Some aspects of this disclosure are shown. Figure 14A The sixth example of a striped configuration is illustrated from another perspective.

[0080] Figure 15 A schematic diagram of a seventh example data structure and non-integer striping configuration for a RAID algorithm implemented in a memory device, according to some aspects of this disclosure, is shown.

[0081] Figure 16 A schematic diagram illustrating an example non-integer striped configuration of data recovery protection is shown, according to some aspects of this disclosure.

[0082] Some embodiments of this disclosure will be described with reference to the accompanying drawings. Detailed Implementation

[0083] Although specific configurations and arrangements have been discussed, it should be understood that this is done for illustrative purposes only. Those skilled in the art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of this disclosure. It will be apparent to those skilled in the art that this disclosure can also be used in a variety of other applications.

[0084] Note that references to "some implementations," "exemplary implementations," "other implementations," "some examples," etc., in the specification indicate that the described implementations may include specific features, structures, or characteristics, but not every implementation necessarily includes that specific feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same implementation. Additionally, when a specific feature, structure, or characteristic is described in connection with an implementation, whether explicitly stated or not, incorporating other implementations to affect such feature, structure, or characteristic will be within the knowledge of those skilled in the art.

[0085] Generally, terms can be understood at least partly from their use in context. For example, depending at least partly on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or it can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, depending at least partly on the context, terms such as "a," "an," or "the" can again be understood to convey either a singular or a plural usage. Furthermore, the terms "based on" and "according to" can be understood not necessarily to convey an exclusive set of factors, and can alternatively allow for additional factors that are not necessarily explicitly described, again depending at least partly on the context.

[0086] As used herein, the terms “nominal / nominally” and “substantially / basically” refer to the expected or target values ​​of characteristics or parameters of a component or process operation set during the design phase of a product or process, and the range of values ​​higher and / or lower than the expected values. The range of values ​​may be due to slight variations in manufacturing processes or tolerances. As used herein, the terms “approximately” and “roughly” indicate the value of a given quantity that may vary based on a specific technology node associated with the subject semiconductor device. Based on a specific technology node, the terms “approximately” and “roughly” may indicate the value of a given quantity that varies within, for example, 10-30% of the value (e.g., ±10%, ±20%, or ±30% of the value).

[0087] As used herein, the term "three-dimensional (3D) memory device" refers to a semiconductor device comprising vertically oriented strings of memory cells on a laterally oriented substrate, wherein the strings of interconnects extend in a vertical direction relative to the substrate. The term "string of interconnects" refers to a vertically oriented and series connection of memory cells on a laterally oriented substrate, such that the string of interconnects of memory cells extends in a vertical direction relative to the substrate. Furthermore, the term "vertically" refers to a direction perpendicular to the lateral plane of the substrate.

[0088] To increase storage capacity, memory devices typically include multiple dies, each with multiple faces. In some instances, each face can be divided into one or more memory blocks, and each block can include multiple laterally extending gate conductive layers. The gate conductive layers can be vertically arranged in several layers, and each gate conductive layer can be coupled to memory cells in multiple pages laterally distributed within the memory block.

[0089] Figure 1A A schematic diagram illustrating an example hierarchical structure of a memory device 10 according to some aspects of this disclosure is shown. In some instances, the memory device 10 may be a three-dimensional NAND memory device. Figure 1A As shown, the NAND memory cells in the NAND memory device 10 can be organized into pages 12 (e.g., physical pages), which are further organized into multiple memory blocks 14 (e.g., from B0 to B1). k-1 (K storage blocks). Each NAND storage cell can be electrically connected to a third party (i.e., Figure 1A The corresponding bit lines (BLs) extend in the z-direction (or bit line direction) of the NAND memory device 10. Memory cells located at the same physical level in the NAND memory device 10 can be electrically connected by word lines WL (i.e., corresponding conductive gate layers) through their respective control gates. Each word line can be electrically coupled to memory cells spanning multiple pages 12.

[0090] In some implementations, a certain number of storage blocks 14 can further form a surface 16. Therefore, as... Figure 1A As shown, the NAND memory device 10 may include multiple faces 16 (e.g., from P0 to P1 in each die). M-1 (M faces). Face 16 can be an independent storage unit within the NAND memory device 10, responsible for storing and managing data. Each face 16 may include one or more storage blocks 14 and can independently perform read, write, and erase operations. By performing these operations simultaneously across multiple faces 16, the NAND memory device 10 with multiple faces 16 can significantly improve its performance, especially by reducing latency and increasing data throughput through parallel processing.

[0091] Each gate conductive layer (corresponding to a word line at a circuit level) can be in a first direction (i.e., Figure 1A It extends laterally in the x-direction (or bit line direction) of the memory. In memory block 14, memory cells connected by a single gate conductive layer form a page 12. A single memory block 14 may include multiple pages 12 connected by multiple word lines. In some embodiments, such as... Figure 1A As shown, the NAND memory device 10 may also include a plurality of dies 18 (e.g., from Die0 to Die1). N-1 The memory consists of N dies, each comprising one or more facets 16. Dividing the memory cells into multiple facets 16 allows the memory controller to perform parallel access, enabling synchronous operations across different facets and improving overall data access speed. Furthermore, data distribution across multiple facets can optimize erase operations and lifetime management due to the application of wear leveling.

[0092] Figure 1B A circuit diagram of an example memory device 100 including peripheral circuitry 102 is shown according to some aspects of this disclosure. The memory device 100 may include a memory cell array 104 and peripheral circuitry 102 coupled to the memory cell array 104. The memory device 100 may be an example of a memory device 10. In some embodiments, the memory cell array 104 may be a NAND flash memory cell array including NAND memory cells 106 arranged in rows and columns in a memory block. The memory cells 106 in the columns of the memory cell array 104 may be stacked vertically (in the z-direction) and coupled in series. The memory cells 106 in the rows of the memory cell array 104 may be coupled to and controlled by word lines 108. Each memory cell 106 may hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped within the memory cell 106. The logic state (i.e., data) of each memory cell 106 may be based on a threshold voltage V of the memory cell 106. th Confirmed. Each memory cell 106 can be a floating-gate type memory cell including a floating-gate transistor or a charge-trapping type memory cell including a charge-trapping transistor.

[0093] In some implementations, each memory cell 106 may be a single-level cell (SLC) having two possible storage states capable of storing one bit of data. For example, a first storage state "1" (e.g., erase state) may correspond to a first voltage range, and a second storage state "0" (e.g., programmable state) may correspond to a second voltage range. The first and second voltage ranges may not overlap. In some implementations, to increase storage capacity, each memory cell 106 may be a multi-level cell (MLC), a three-level cell (TLC), or a four-level cell (QLC). An MLC may store two bits of data and includes four logic states {11, 10, 01, and 00} (i.e., a fully erased state, and programmable states P1, P2, and P3). A TLC may store three bits of data and includes eight logic states {111, 110, 101, 100, 011, 010, 001, and 000} (i.e., a fully erased state, and programmable states P1-P7). QLC can store 4 bits of data and includes 16 logical states {1111, 1110, 1101, 1100, 1011, 1010, 1001, 1000, 0111, 0110, 0101, 0100, 0011, 0010, 0001, 0000} (i.e., the fully erased state and the programmed states P1-P15).

[0094] In some implementations, memory cell 106 may be an SLC (Single-Level Cell), and each word line 108 is coupled to one or more physical pages 110 of memory cell 106. A physical page is a basic unit of data used for programming operations. The size of a physical page 110 is associated with the number of columns of memory cells 106 coupled to a word line 108 in the memory block. Based on the number of bits that memory cell 106 can store, a physical page 110 may be associated with one or more logical pages. For example, when memory cell 106 is an SLC that can store one bit of data, a physical page 110 may be associated with one logical page. When memory cell 106 is an MLC that can store two bits of data, a physical page 110 may be associated with two logical pages. When memory cell 106 is a TLC that can store three bits of data, a physical page 110 may be associated with three logical pages (i.e., the next page, the middle page, and the previous page). When memory cell 106 is a QLC that can store four bits of data, a physical page 110 may be associated with four logical pages. Logical pages associated with the same physical page 110 can share the same physical address.

[0095] In some implementations, peripheral circuitry 102 can be coupled to memory cell array 104 via bit lines, word lines, and source lines. Memory cells 106 in a column of memory cell array 104 can be coupled to a source-select-gate (SSG) transistor at their source end and to a drain-select-gate (DSG) transistor at their drain end. The SSG and DSG transistors can be configured to activate that column of memory cell array 104 when it is selected during read and program operations.

[0096] Figure 1C A schematic diagram of an example physical structure of a memory cell array 101 according to some aspects of this disclosure is shown. The memory cell array 101 may be... Figure 1B An example of storage cell array 104. For example... Figure 1C As shown, the memory cell array 101 may include multiple rows of memory cells separated by parallel gate isolation structures (e.g., first gate isolation structure 105, second gate isolation structure 107, and third gate isolation structure 109) extending in the x-direction, such as... Figure 1C As shown. In some embodiments, the first gate isolation structure 105 may be configured to organize the memory cell array 101 into a plurality of memory blocks 111, and the second gate isolation structure 107 may further divide a memory block into a plurality of memory fingers 113. A memory finger 113 may be further divided into a plurality of memory strings 115 by a third gate isolation structure 109 (e.g., a top-select gate isolation structure). In some embodiments, the third gate isolation structure 109, which acts as a top-select gate isolation structure, may have a different configuration than the first gate isolation structure 105 and the second gate isolation structure 107. For example, in some examples, the first gate isolation structure 105 and the second gate isolation structure 107 may extend through the entire memory stack of the memory cell array 101 to divide the memory stack into different regions, while the third gate isolation structure 109 may cut through (e.g.) a top-select gate layer without penetrating the entire memory stack to control different portions of the memory cells via the divided top-select gate layer.

[0097] In storage string 115, storage cells coupled to the same word line can be referred to as a "page," typically meaning a physical page. In some implementations, such as... Figure 1C As shown, a memory block 111 may include multiple memory strings 115. In some embodiments, the SSG transistors of memory strings 115 in the same memory finger 113 may be coupled to the same SSG line.

[0098] In this disclosure, the terms "word line coupled to a memory string" and "a page" can, to some extent, represent similar concepts because both terms can refer to a set of memory cells connected / controlled by the same word line. While "word line coupled to a memory string" generally means a physical subset of memory cells coupled to the same word line within a memory block at the semiconductor level, "memory page" can represent an access unit that includes all memory cells along a specific word line at the circuit level. Therefore, both terms can broadly express a group of memory cells connected / controlled by a single word line.

[0099] To improve data integrity in storage cells, RAID algorithms are widely used in NAND flash memory. Different RAID levels typically utilize various striping techniques across storage pages or blocks to divide data into multiple data portions. Encoding operations are performed on these data portions to generate corresponding parity information, and this parity information is stored for subsequent data recovery when necessary. In striping methods, a data portion within a stripe can represent data to be stored in a single page, and a stripe can include data portions arranged in two dimensions: horizontally across different storage blocks, faces, and dies, and vertically across multiple levels (word lines) within the same storage block.

[0100] In some implementations, certain RAID algorithms (such as RAID 4 or RAID 5) can be applied to UFS (Universal Flash Storage) and SSD (Solid State Drive) products to recover portions of data within a stripe. These RAID algorithms can provide block-level data striping across multiple faces and dies to ensure data redundancy. For this purpose, they can be configured to output and store parity information (i.e., redundant data used for recovery) generated as the result of encoding operations on striped pages. In some instances, the parity information may need to be reserved for storage space (i.e., reserved space, OP). Additionally, a certain amount of swap buffer (or "RAID buffer") may also be required. The terms "swap buffer" and "RAID buffer" are used to refer to a storage area used to cache redundant data (e.g., parity data) generated from the data during the programming operation. In the event of a read failure, the stored parity information can be used to reconstruct the erroneous data portion, ensuring data integrity and fault tolerance.

[0101] Figure 2A Schematic diagrams illustrating example data structures and striping configurations for implementing a RAID algorithm in a memory device 200 according to some aspects of this disclosure are shown. In some instances, the memory device 200 may be, for example... Figure 1B The memory device 100 in the memory device is a NAND memory device. For ease of illustration, Figure 2AThe NAND memory device 200 is represented in tabular format. Furthermore, the NAND memory device 200 is simplified to show two sides of a die, with four memory strings on each side. In this example, data is to be stored in two dies ("Die0" and "Die1"), each with two sides ("Plane0" and "Plane1"). Each side may include one or more memory blocks configured to store data. Figure 2A The memory device 200 can correspond to four vertically arranged word lines (“WL0” to “WL3”). In one plane, each word line can be coupled to four memory strings (“STR0”, “STR1”, “STR2”, and “STR3”) to form four pages.

[0102] In some implementations, the memory device may have more than two dies, and each die may have more than two faces. Each memory block may include more than four word lines, and each word line may be coupled to more than four pages in one face. Therefore, it can be understood that Figure 2A This can describe part or all of the data to be stored in the memory device 200. In other words, Figure 2A It is possible to describe only one striped group. Furthermore, Figure 2A An example striped configuration implementing SLC technology can be shown. It is clear that... Figure 2A The striping configuration can also be applied to MLC, TLC, or QLC. For example, when applying TLC technology, each physical page can correspond to three logical pages used to store the previous page (UP) data portion, the middle page (MP) data portion, and the next page (LP) data portion.

[0103] exist Figure 2A In the striping configuration described herein, stripe 204 (shown in larger bold boxes) may include multiple pages 206 (shown in smaller bold boxes) spanning different faces of each die. More specifically, to form stripe 204 according to this striping configuration, pages 206 corresponding to strings (e.g., “STR0” – string 0) with the same index in a subset 202 of pages on each face can be striped. Laterally, stripe 204 may include data portions located in the same segment (i.e., corresponding to the i-th page of each word line) across different faces of each die. Vertically, stripe 204 may include data portions at different levels (i.e., corresponding to pages of different word lines). Figure 2A In order to keep the illustration clear, the logo is only attached to the part of the strip.

[0104] In this disclosure, the terms "pages located in the same segment" and "pages in the same string" are used to refer to pages corresponding to strings with the same index in a striped group. To explain the terms "pages located in the same segment" and "same string," the following are provided and referenced. Figure 2B . Figure 2B A schematic diagram illustrating multiple memory strings in memory blocks 201 and 203 according to some aspects of this disclosure is shown. Memory blocks 201 and 203 may belong to different facets. Figure 2B As shown, the string in storage block 201 may include SRT0, STR1, and others, and the same applies to storage block 203. PAGE1 and PAGE2 in storage block 201 may correspond to the same string (i.e., STR0), even though PAGE1 is coupled to word line WL0 and PAGE2 to word line WL1. In another example, PAGE3 and PAGE4 also correspond to the same string (i.e., STR0), even though these pages are in different faces. As a result, PAGE1, PAGE2, PAGE3, and PAGE4 are located in the same segment. In other words, in this disclosure, the term "same string" can refer to pages corresponding to strings with the same index / located in the same segment, whether in the same face or different faces.

[0105] In some implementations... Figure 2A The parity data portion for stripe 204 shown can be derived from the encoding operation. In some implementations, a series of XOR operations can be performed on the data to be stored in stripe 204. For example, for data portions D0, D1, ..., D14 in 15 pages of stripe 204, parity data Parity0 can be generated as follows:

[0106] Parity0 = (D0) XOR (D1) XOR (D2)…XOR (D14) (1).

[0107] In some implementations, the XOR operation for generating the parity data portion according to equation (1) can be performed sequentially. For example, after receiving data portions D0 and D1, the result of the XOR operation on data portions D0 and D1 can be obtained. Subsequently, after receiving data portion D2, another XOR operation can be performed on data portion D2 and the result of the XOR operation.

[0108] In some implementations, the parity data itself can be stored in a page of stripe 204, for example, the last page of stripe 204 (corresponding to...). Figure 2A Parity0 in [the context of parity data]. In some implementations, parity data may be stored in a dedicated storage block instead of in the stripe, but this disclosure is not limited thereto. Figure 2AIn the example, 15 data portions (e.g., from D0 to D14) are used to generate a parity data portion (e.g., Parity0) using an XOR operation, resulting in a 15:1 data to parity ratio. This ratio represents the proportion of space occupied by the data portions to the space occupied by the parity data portion.

[0109] For a striping group with this striping configuration, four stripes can be generated, each corresponding to a parity data portion. When the parameter J represents the number of stripes generated, J becomes 4. When another parameter R represents the number of strings coupled in the face by the word lines, in this example, R also equals 4. This makes both J and R equal to 4. The four parity data portions generated can be stored in four pages (e.g., in a...). Figure 2A (As shown in Plane 1 of Die 1). In some implementations, the parity data portion may require temporary storage in the RAID buffer before being written to the corresponding memory location (e.g., the four last pages of the four stripes), which may also occupy the space of four physical pages in the RAID buffer.

[0110] Figure 2C Some aspects of this disclosure are shown. Figure 2A A schematic diagram of an exemplary striped configuration from another viewpoint 205. Figure 2C A different perspective shows Figure 2A The subset of pages 202 and stripe 204.

[0111] Figure 2A and Figure 2C This striping configuration can be called "1-WL RAID protection". The resulting four parity data portions are stored (for example) in four pages all coupled to a single word line. Figure 2B It can be understood that in this striping strategy, data portions stored in pages corresponding to the same segment participate in the XOR operation used to generate a stripe. In the event of a read failure associated with a data portion of the stripe (e.g., D0), recovery can be achieved by performing a decoding operation using the parity data portion (e.g., Parity0) and the remaining data portions (e.g., from D1 to D14). For example, refer to... Figure 2A When the read operation of data section D0 fails, it can be recovered through the following:

[0112] (D0) = Parity0 XOR (D1) XOR (D2)…XOR (D14) (2).

[0113] Similarly, for Figure 2AThe second stripe (shown as a diagonal stripe texture), parity data Parity1, can be generated by performing another encoding operation using data sections DD0 to DD14. As described, 1-WL RAID protection can have the advantage of efficient storage. That is, a relatively small RAID buffer is needed and utilized to store the parity data before it is written to the corresponding stripe. It can use storage space more efficiently because this striped configuration minimizes the need for a large space for storing parity data.

[0114] On the other hand, while parity data can prevent failure of a single data segment, it cannot prevent multiple simultaneous failures within the same band, leading to potential data loss. For example, when two data segments in the same band fail, recovery becomes impossible even using parity data and the remaining data segments during decoding. One situation that can result in more than one faulty data segment in the same band is a "multifaceted failure," which can be caused by programming errors when multiple faces are programmed in parallel. Data segments located in the same segment on different faces can fail simultaneously (e.g., Figure 2B Both data D0 to be stored in PAGE1 and data D1 to be stored in PAGE3 fail. In another case, more than one faulty data segment in a strip can be caused by a "source-select gate (SSG) leakage fault" (i.e., current leakage in the SSG). An SSG leakage fault can lead to faulty data segments coupled to the same SSG, for example, faulty data segments located in the same segment on the same face of different layers (e.g., Figure 2B Both data D0, which was to be stored in PAGE1, and data D4, which was to be stored in PAGE2, failed.

[0115] In this disclosure, the terms "erroneous data portion" and "faulty data portion" are used to refer to a portion of data in a memory device that cannot be correctly accessed or read due to an error or fault. An erroneous data portion can be caused by a variety of reasons, such as physical defects in the memory cell and / or programming errors. In some examples, these terms may refer not only to corrupted or inaccessible data but also to missing data, where the fault has resulted in data either never being written correctly or being completely lost.

[0116] It should be noted that interference between two adjacent word lines within a block can be quite significant. When a location experiences a fault, it can typically affect the validity of data in adjacent word lines (e.g., word line-to-word line short-circuit faults). To address this issue, this application proposes an alternative striping configuration called "2-WL striping protection." The term "2-WL striping" refers to placing two pages coupled to two adjacent word lines in the same segment on the same face in different stripes. Therefore, when both the page coupled to the two adjacent word lines and another page experience a fault, recovery can be achieved through multiple RAID stripes.

[0117] Figure 3A A schematic diagram of another example data structure and striping configuration for implementing a RAID algorithm in a memory device 300 according to some aspects of this disclosure is shown. In some instances, the memory device 300 may be a NAND memory device, such as... Figure 1B The memory device 100 is shown in the image. For ease of illustration, Figure 3A The NAND memory device 300 can also be represented in tabular format. Furthermore, the NAND memory device 300 is simplified to show two sides of a die, with four memory strings on each side. In this example, data is to be stored in two dies ("Die0" and "Die1"), each with two sides ("Plane0" and "Plane1"). Each side may include one or more memory blocks configured to store data. Figure 3A The diagram shows a subset 302 of pages in a face, which can represent pages to be striped in a striping group of this face. The subset 302 of pages can correspond to eight word lines (“WL0” to “WL7”) arranged vertically. In this example, each face in the memory device 300 corresponds to four memory strings (“STR0”, “STR1”, “STR2”, and “STR3”), and therefore, each word line can be coupled to four pages. Thus, with... Figure 3A The associated R is 4.

[0118] like Figure 3A As shown, 2-WL striping protection can place data portions to be stored in pages with two adjacent word lines in different stripes 304. More specifically, in this striping configuration, laterally, stripes 304 can include data portions located in the same segment across different faces (e.g., Figure 2B The data D0 to be stored in PAGE1 and the data D1 to be stored in PAGE3). Vertically, strip 304 may include data portions located in the same segment on the same plane and corresponding to two non-adjacent word lines (e.g., Figure 2B (Data D0 to be stored in PAGE1 and data D4 to be stored in PAGE5). Figure 3AIn order to keep the illustration clear, the identifier is only attached to the portion of the strip.

[0119] like Figure 3A As shown, a stripe 304 may include data portions D0, D1, ..., D14, such that parity data Parity0 can be derived by performing a series of XOR operations on the data portions D0, D1, ..., D14. In some embodiments, the parity data Parity0 may be stored in a format such as... Figure 3A In the stripe 304 shown, although in some embodiments, parity data may be stored in other memory locations such as dedicated memory blocks. Similarly, for Figure 3A Another stripe in the stripe can generate parity data Parity1 by performing a series of XOR operations using the corresponding data portion. Therefore, eight stripes can be generated based on a subset 302 of pages in this striped group, resulting in J equal to 8. In the event of a read failure associated with a data portion of a stripe (e.g., D0 in the first stripe 304), recovery can be achieved by performing XOR operations using parity data (e.g., Parity0) and the remaining data portions (e.g., from D1 to D14).

[0120] Figure 3B Some aspects of this disclosure are shown. Figure 3A A schematic diagram of an exemplary striped configuration from another perspective 301. Figure 3B China shows from different perspectives Figure 3A The subset of pages 302 and stripe 304.

[0121] By arranging two pages coupled to adjacent word lines in different stripes, 2-WL striping configurations can provide a higher level of data protection against various faults compared to 1-WL striping configurations. For example, 2-WL striping can be used to recover certain NAND fault types that cannot be handled in 1-WL striping configurations, such as word line and word line short-circuit faults (i.e., programming faults in two adjacent word lines within the same block / face). On the other hand, 2-WL striping configurations may require larger RAID buffers due to the increased amount of data that needs to be temporarily buffered and managed, resulting in higher memory overhead. During recovery requests, parity data may need to be read from memory devices and buffered in the RAID buffer for XOR recovery calculations, leading to frequent data exchanges and higher memory overhead.

[0122] More specifically, according to Figure 3A The example described herein is for the purpose of maintaining consistency with Figure 2AThe same 15:1 data-to-parity ratio can generate eight stripes, each corresponding to a parity data portion (“Parity0” to “Parity7”). That is, J equals 8. The eight parity data portions can be stored in eight corresponding pages, either within the stripes or in other memory locations. Figure 3A In a subset 302 of the pages, each word line can be coupled to four pages. Therefore, eight parity data portions can occupy spaces coupled to two word lines (e.g., as shown below). Figure 3A The diagram shows eight pages ("WL6" and "WL7") in Plane 1 of Die 1. This is twice the size of 1-WL striped protection. Due to the need for managing and exchanging data, this increased resource requirement can lead to higher RAID buffer usage and longer latency during data transactions.

[0123] As the number of layers in NAND technology increases, the likelihood of word line failures may also rise. Data protection in 1-WL RAID striped configurations is relatively weak, thus posing challenges to data integrity. However, implementing 2-WL RAID protection can also become challenging when the buffer size of the memory controller is limited.

[0124] Given these striped configurations, alternative striped configurations are being investigated that can provide robust protection for data integrity by generating large volumes of parity data. In particular, the increased level of redundancy can provide a higher degree of fault tolerance, ensuring that the system can recover data in the event of a failure. However, these configurations also come with trade-offs, especially when the large volume of parity data generated may require significant uptime. Therefore, while these configurations are very effective in improving reliability, they are not always candidates for systems with limited memory resources.

[0125] To address one or more of the aforementioned issues, this disclosure proposes a solution in which a non-integer RAID striping configuration is implemented to recover from failures. This approach balances robust data protection with minimal impact on performance and cost. In particular, current NAND technology faces the challenge of word line leakage, which causes leakage current to occur between two adjacent word lines in a NAND memory device. Word line leakage can be a significant problem in NAND technology, and addressing it becomes critical for maintaining data integrity and extending the lifespan of the memory device.

[0126] According to some embodiments of this disclosure, protection strategies with reasonable costs can be adopted based on the distribution of defective parts per million units (DPPM) while minimizing the impact on performance. Therefore, striping based on integer multiples of word lines may not be necessary. Striping configurations can be customized to meet specific needs. According to some embodiments of this disclosure, non-integer striping configurations covering most word line leakage issues are proposed. Non-integer striping configurations can provide coverage of most DPPM issues with relatively reasonable RAID buffer usage while reducing buffer occupancy in terms of performance.

[0127] Figure 4A A schematic diagram of an example system 40 implementing a non-integer striping configuration according to some aspects of this disclosure is shown. System 40 may include a memory system 400 or a system including memory devices. Figure 4A As shown, system 40 may include host 402, memory controller 404, processing memory 406, and memory device 408. In some embodiments, memory system 400 may include memory controller 404 and memory device 408.

[0128] It is understood that system 40 may include any other suitable components. For ease of illustration, from Figure 4A These components are omitted. In some instances, host 402, memory controller 404, processing memory 406, and memory device 408 may be arranged on a printed circuit board (PCB). In some embodiments, each of host 402, memory controller 404, processing memory 406, and memory device 408 may be designed and implemented as a discrete chip with its package and mounted on the PCB. In some instances, memory controller 404, processing memory 406, and memory device 408 may be implemented on the same chip (e.g., UFS / SSD), and host 402 may be an external device to the chip; this disclosure is not limited thereto.

[0129] Host 402 may include a dedicated processor for performing data processing on memory device 408. For example, host 402 may include a central processing unit (CPU) and / or a system-on-a-chip (SoC) such as an application processor. Data can be transferred between host 402 and memory controller 404, between host 402 and processing memory 406, and between memory controller 404 and memory device 408 via corresponding connections such as processor buses 410, 411, and 413. In some examples, connections 410, 411, and 413 may use the same or different communication protocols. Therefore, host 402 can control the operation of processing memory 406 and memory controller 404.

[0130] The host 402 can coordinate the operations of different modules / parts in the system 40 based on data and / or signals transmitted from the memory controller 404. The host 402 can control the operation of the processing memory 406 based on data and / or signals transmitted from the memory controller 404.

[0131] Memory device 408 may include an array of memory cells configured to implement a RAID algorithm following the core of this disclosure. The RAID algorithm may use a non-integer striping configuration according to some embodiments of this disclosure. Memory device 408 may include, for example, 3D NAND memory that transfers data with memory controller 404 via corresponding links 410, 411, and 413. In some embodiments, memory device 408 may include a 3D NAND memory having an array of 3D NAND memory cells. The array of 3D NAND memory cells may be formed by the intersection of word lines and connection strings. Connection strings extend vertically through the memory stack above the substrate. NAND memory cells may be organized into pages, and pages may then be organized into memory blocks. In a memory block, each NAND memory cell is electrically connected to a bit line (BL). Memory cells having the same horizontal level may be electrically connected by word lines via control gates.

[0132] Processing memory 406 can act as a system cache, serving as immediate access space for frequently used data and / or auxiliary operations as instructed by host 402 during a task. In some embodiments, processing memory 406 may include random access memory (RAM), and it may be any suitable static random access memory (SRAM) and / or dynamic random access memory (DRAM). It is understood that processing memory 406 in system 40 may be selective.

[0133] According to some embodiments, a memory controller 404 (also referred to as controller circuitry) may be coupled to a memory device 408 and a host 402, and may be configured to control the memory device 408. For example, the memory controller 404 may be configured to operate a multi-channel structure via word lines. The memory controller 404 may manage data stored in or to be stored in the memory device 408 and communicate with the host 402. In some embodiments, the memory controller 404 is designed to operate in low-duty-cycle environments, such as Secure Digital (SD) cards, Compact Flash (CF) cards, Universal Serial Bus (USB) flash drives, or other media used in electronic devices such as personal computers, digital cameras, and mobile phones. In some embodiments, the memory controller 404 is designed to operate in high-duty-cycle environments, such as SSDs or embedded multimedia cards (eMMCs), serving as data storage and enterprise storage arrays for mobile devices such as smartphones, tablets, laptops, etc. The memory controller 404 may be configured to control the operation of the memory device 408, such as read, erase, and program operations. The memory controller 404 can also be configured to manage various functions relating to data stored or to be stored in the memory device 408, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 404 can also be configured to process error correction codes (ECC) for data read from or written to the memory device 408. Any other suitable function, such as formatting the 3D memory device 408, can also be performed by the memory controller 404. At the heart of this disclosure, the memory controller 404 can be configured to receive data, generate parity information corresponding to the data, and control the memory device 408 to store the parity information.

[0134] The memory controller 404 can communicate with the host 402 according to a specific communication protocol. For example, the memory controller 404 can communicate with the host 402 through at least one of various interface protocols, such as USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI-E protocol, Advanced Technology Attachment (ATA) protocol, Serial-ATA protocol, Parallel-ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, FireWire protocol, etc.

[0135] The memory controller 404 and one or more memory devices 408 can be integrated into various types of memory devices, for example, included in the same package, such as a Universal Flash Memory (UFS) package or an eMMC package. That is, the memory system 400 can be implemented and packaged into different types of end electronic products. Figure 4BIn one example shown, the memory controller 404 and a single memory device 408 can be integrated into a memory card 401. The memory card 401 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a Memory Stick, a Multimedia Card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 401 may also include a memory card connector 403 that electrically couples the memory card 401 to the host 402. In such a case... Figure 4C In another example shown, the memory controller 404 and multiple memory devices 408 may be integrated into the SSD 405. The SSD 405 may also include an SSD connector 407 that electrically couples the SSD 405 to the host 402. In some embodiments, the storage capacity and / or operating speed of the SSD 405 is greater than the storage capacity and / or operating speed of the memory card 401.

[0136] Figure 5A A schematic diagram of an example memory controller 500 cooperating with host 501 and memory device 503 in a RAID process, according to some aspects of this disclosure, is shown. The memory controller 500, host 501, and memory device 503 can establish a memory system 5. The memory controller 500 can be... Figure 4A An exemplary embodiment of the memory controller 404 is shown, where the host 501 and the memory device 503 can be respectively... Figure 4A An exemplary implementation of the host 402 and memory device 408 in the example.

[0137] The memory controller 500 can be configured to control the operation of the memory device 503 by generating control signals to control striping, parity information calculation, and data storage in the memory device 503. According to some embodiments of this disclosure, the memory controller 500 can be configured to receive signals (e.g., instruction signals) from the host 501 for performing operations concerning the memory device 503.

[0138] like Figure 5A As shown, in some examples, the memory controller 500 may include a processor 502, a buffer 504, and interface (I / F) circuitry, which includes host I / F circuitry 506-1 and memory I / F circuitry 506-2. In some embodiments, the memory controller 500 may include different modules / circuits, such as integrated circuit (IC) chips (implemented as, for example, application-specific integrated circuits (ASICs) or field-programmable gate arrays (FPGAs)), or may combine several electronic devices, each having one or more dedicated functions. Figure 5AAs an illustrative example, some aspects of this disclosure are shown to aid in understanding by illustrating the integrated processor 502, buffer 504, and I / F circuitry. However, this description should not be construed as limiting the physical layout of these components. In some embodiments, components of the memory controller 500 may be distributed in different physical locations but communicate with each other via a network.

[0139] Processor 502 may include any suitable type of general-purpose or special-purpose microprocessor, digital signal processor, or microcontroller. Processor 502 may be configured as a separate processor module dedicated to analyzing signals (e.g., signals from host 501) and / or controlling the scanning scheme. Alternatively, processor 502 may be configured as a shared processor module for performing functions other than signal analysis / scanning scheme control. In some embodiments, processor 502 may include multiple functional units or modules that can be implemented using software, hardware, middleware, firmware, or any combination thereof. According to some embodiments of this disclosure, processor 502 may also be configured to cooperate with other circuitry to perform striping and to compute, store, and control parity data.

[0140] Buffer 504 may include any suitable type of storage space provided to store information that processor 502 may need to operate. Buffer 504 may be volatile or non-volatile, magnetic, semiconductor-based, magnetic tape-based, optical, removable, non-removable, or other types of storage devices or tangible (i.e., non-transitory) computer-readable media, including but not limited to ROM, flash memory, dynamic RAM, static RAM, hard disk, SSD, optical disk, etc. Buffer 504 may be configured to store one or more computer programs that can be executed by processor 502 to perform functions related to the RAID process disclosed in this disclosure. For example, buffer 504 may be configured to store one or more programs that can be executed by processor 502 in cooperation with other circuitry to generate RAID stripes, calculate parity data, control the storage of parity data, and perform recovery. In some embodiments, buffer 504 may also be configured to store / cache information and data received and / or used by processor 502. For example, buffer 504 may store / cache data received from host 501 and / or parity data generated during the RAID process. In some implementations, each buffer 504 configured to temporarily store parity information (e.g., as a RAID buffer) may be associated with a limit (e.g., 320KB). When the RAID parity data exceeds the limit, the memory controller 500 may perform a swapping operation.

[0141] The memory controller 500 may include I / F circuitry. In some examples, the I / F circuitry may include, for example, a host I / F circuit 506-1 operatively coupled to the host 501 via a processor bus and configured to receive instructions from the host 501. The host I / F circuit 506-1 may include serially attached SCSI (SAS), parallel SCSI, PCIe, NVM Mesh, Advanced Host Controller Interface (AHCI), and any suitable type. In some examples, the I / F circuitry may also include memory I / F circuitry 506-2. Memory I / F circuitry 506-2 may include a single data rate (SDR) NAND flash interface, an open NAND flash interface (ONFI), a switchable double data rate (DDR) interface, and any suitable type. In some implementations, memory I / F circuitry 506-2 may be configured to transmit control signals to the memory device 503 and receive data and status signals from the memory device 503. Status signals can indicate the status of each operation performed by memory device 503 (e.g., failure, success, delay, etc.), and can be fed back to memory controller 500.

[0142] In some implementations, the memory controller 500 may include ECC circuitry 508, garbage collection (GC) circuitry, bad block management circuitry, and RAID circuitry 514 in the backend. In some implementations, the ECC circuitry 508 may be configured to process error correction codes regarding data read from or written to the memory device 503. Error correction codes may include, but are not limited to, Hamming codes, Reed-Solomon codes, and low-density parity-checking (LDPC) codes.

[0143] In some implementations, when a read or program operation on a memory block in memory device 503 fails, the garbage collection (GC) circuitry in memory controller 500 can transfer valid data, including any associated parity data, from the failed memory block to another memory block. In this case, depending on the request, parity data from the corresponding stripe can be used to reconstruct the missing data corresponding to the failed block. In some instances, after the data transfer is complete, bad block management circuitry in memory controller 500 can mark the failed memory block as bad, ensuring it is no longer used for future data storage. Furthermore, the GC circuitry can update the associated parity data in the stripe to reflect the new memory block location.

[0144] In some implementations, processor 502 may instruct and configure RAID circuit 514 to perform striping according to the core of this disclosure, as well as to calculate, store, and control parity data. For example, processor 502 may transfer data to RAID circuit 514 during a write operation, and processor 502 may also instruct RAID circuit 514 to process data based on a striping strategy to generate parity information. In other examples, when a portion of data cannot be read from a corresponding page of memory device 503 (e.g., a failed data portion), processor 502 may instruct RAID circuit 514 to locate the data portion to obtain other data portions and parity data portions in the same stripe as the data portion. Accordingly, a reconstructed data portion can be generated based on other data portions and parity portions in the same stripe to replace the failed data portion. As an example, in Figure 5A In this specification, RAID circuitry 514 is described as a module separate from processor 502. However, in some embodiments, part or all of processor 502 may serve as part or all of the RAID circuitry performing the RAID process. This disclosure is not limited thereto.

[0145] Figure 5B A schematic diagram of an example memory device 503, including a memory cell array 50 and peripheral circuitry, is shown according to some aspects of this disclosure. The peripheral circuitry may include various types of peripheral circuitry formed using complementary metal-oxide-semiconductor (CMOS) technology. For example, the peripheral circuitry may include a page buffer 51, a column decoder / bit line driver 52, a row decoder / word line driver 53, a voltage generator 54, a control logic unit 55, a cache / register 56, an interface (I / F) 57, and a data bus 58. It will be understood that in some examples, additional circuitry, such as a sense amplifier, may also be included.

[0146] In some implementations, page buffer 51 may be configured to buffer data read from or programmed into memory array 50 according to control signals issued by control logic unit 55. Row decoder / word line driver 53 may be configured, controlled by control logic unit 55, to select blocks of memory array 50 and the word line WL of the selected blocks. Column decoder / bit line driver 52 may be controlled by control logic unit 55 to select one or more connection strings by applying bit line voltages generated from voltage generator 54. Control logic unit 55 may be coupled to each peripheral circuit and configured to control the operation of the peripheral circuits. Cache / register 56 may be coupled to control logic unit 55 and may include a status register, a command register, and an address register for storing status information, command opcodes, and command addresses for controlling the operation of each peripheral circuit. Interface 57 may be coupled to control logic unit 55 and configured to interface memory array 50 with a memory controller (e.g., memory controller 500). Voltage generator 54 can be controlled by control logic unit 55 to generate word line voltages (e.g., read voltage, programming voltage, pass voltage, local voltage, and verification voltage) and bit line voltages to be supplied to memory cell array 50.

[0147] Back Figure 5A The host 501 can be configured to send data to or receive data from the memory device 503. To send or receive data from the memory device 503, the host 501 can send instructions to the memory controller 500, and the memory controller 500 can communicate with the host 501 according to a specific communication protocol, such as PCIe or NVMe, that defines the interconnection between the host 501 and the memory system. Specifically, during a write operation, the memory controller 500 can receive data from the host 501, which may include various types of information to be stored in the memory device 503 (e.g., a NAND memory device), such as user data, metadata, or system logs. In some embodiments according to this disclosure, under the control of the processor 502 in the memory controller 500, the data can undergo a RAID process to generate parity information. These processes may involve striping and encoding the data to ensure data redundancy and improve fault tolerance in the event of data corruption or block failure.

[0148] Once the data is ready for storage, host 501 can generate a corresponding write command. This write command, along with the data, can be transmitted to memory controller 500 via host I / F circuitry 506-1. Subsequently, host I / F circuitry 506-1 of memory controller 500 can send the associated write command to processor 502 for further data processing. For example, processor 502 can instruct RAID circuitry 514 to determine striping, generate parity information, and recover data using the parity information. In some embodiments, processor 502 can be configured to process write commands so that memory controller 500 can work with memory device 503 to perform the necessary write cycles to securely store data and parity information in memory device 503.

[0149] In some implementations... Figure 5A The host 501 can be configured to generate write commands and send them along with data to the memory controller 500. Once the memory controller 500 receives the data, it can manage how the data is organized, including determining the striping pattern and distributing the data across different blocks or faces of the memory device 503. In this disclosure, the term "striping" is used to refer to dividing data into segments, distributing these segments (along with parity information) across multiple faces in the memory device 503, and associating these segments to generate parity information.

[0150] Figure 6A A schematic diagram of a first example data structure and non-integer striping configuration for a RAID algorithm implemented in a memory device 600 according to some aspects of this disclosure is shown. Figure 6B Some aspects of this disclosure are shown. Figure 6A A schematic diagram of the first exemplary striped configuration from another viewpoint 601. Figure 7 A flowchart of an exemplary method 700 for operating a memory device according to some aspects of this disclosure is shown. Reference will be made in the following description. Figure 5A , Figure 6A , Figure 6B and Figure 7 Some embodiments of this disclosure are described.

[0151] In this disclosure, the term "non-integer" is used to describe coupling to R strings on each word line to form R pages laterally (including the first page coupled to string SRT0, the second page coupled to string STR1, the third page coupled to string STR2, ..., and the page coupled to string STR... R-1In one face of page R, the number of pages used to store the parity data portion can be arranged between R pages (corresponding to 1-WL protection) and 2R pages (corresponding to 2-WL protection). It is understood that the non-integer striping configuration implemented in memory device 600 and according to method 700 is not exhaustive, and other striping configurations and methods can be performed based on the core of this disclosure to achieve the same / similar purpose. Details will be described later.

[0152] In some implementations, the memory controller 500 may be configured to determine J stripes based on a striping group, where J is an integer. Each of the J stripes may correspond to a parity data portion. The term "striping group" is used to describe all pages to be striped and can be distributed across each face of each die. In some implementations, the value of J may be determined based on various factors, such as the volume and importance of the data to be stored. In some instances, the value of J may be a multiple of the value of R, which is greater than 1 and less than 2. Therefore, the ratio of J to R is a non-integer. R may represent the number of strings coupled to a word line in a face. Accordingly, R is an integer. In some implementations, the ratio of J to R may be determined based on the distribution of programming faults associated with the memory device.

[0153] In some implementations, the ratio of J to R can include a number greater than 1 and less than 2. That is, the ratio is not an integer. For example, the ratio of J to R could be 1.5. In other instances, the ratio could be 1.25, 1.75, 1.3, or another value between 1 and 2. Non-integer striping implies that the storage area determined by the striping group for the J parity data portions may require more than R pages and less than 2R pages. This non-integer striping configuration can handle most two-word-line leakage issues and provides coverage for most DPPM issues with a relatively reasonable RAID buffer size, while reducing buffer occupancy and maintaining performance.

[0154] In some instances, programming fault distributions may include at least one of a defective parts per million units (DPPM) distribution or a pattern-sensitive fault distribution. DPPM is a measure used to quantify the number of defective parts in a group of one million parts, and it is generally used to assess the quality and reliability of products, including memory devices. DPPM values ​​can be affected by pattern-sensitive faults. Pattern-sensitive faults are defects in memory devices triggered by specific data patterns. Unlike random defects, pattern-sensitive faults can depend on the interaction of data in adjacent memory cells. For example, especially in modern, tightly stacked memory cell arrays, writing a certain pattern can cause damage in nearby memory cells.

[0155] Figure 8A bar graph illustrating the distribution of programming faults 800 in different strings in a memory device, according to some aspects of this disclosure, is shown. Figure 8 The programming fault distribution 800 in the code can be pattern-sensitive. For example, Figure 8 Most programming faults, especially those related to word lines and word line short circuits, occur in strings 0 through 3. In some examples, based on the programming fault distribution 800, striping strategies and patterns according to some embodiments of this disclosure can be determined accordingly.

[0156] Research indicates that in 3D NAND memory device applications, programming state failures (PSFs) can occur during programming operations due to, for example, word line leakage. This can happen during multi-faceted programming. If a memory block within a face experiences PSF due to word line leakage, the leakage will affect the voltage along the x-path (the voltage applied to the word line) throughout the multi-faceted programming operation. Affecting the voltage applied to the word line can impact the data in the corresponding memory cell along that word line. Since each word line can correspond to multiple memory cells in a string, significant amounts of data may be lost or corrupted, potentially causing system failures. This type of failure is generally defined as a reliability failure in 3D NAND memory devices, which can further lead to system failures.

[0157] In 3D NAND memory devices, an internal voltage supply is typically shared across different planes during programming operations to save circuit area and reduce power consumption. When one plane has a defect, other planes sharing the internal voltage supply may fail to reach the target level. In other words, the PSF (Power Supply Filter) in one plane will also affect the voltage on the x-path in other adjacent planes, thus affecting the written data in those adjacent planes. Therefore, even when only one plane has a physical defect, failures during read operations can often occur on multiple planes. This suggests that failures in memory devices can be pattern-sensitive. This phenomenon is called adjacent-plane interference (NPD), which can cause data loss.

[0158] refer to Figure 7 Method 700 begins at operation 702. At operation 702, Figure 5A The memory controller 500 can receive a data portion for generating parity information. In some implementations, the data portion may come from the host 501 along with a write instruction. The data portion may correspond to J stripes, and each of the J stripes may correspond to a parity data portion.

[0159] refer to Figure 6A The memory device 600 can be Figure 5BThe implementation of memory device 503 may include a NAND memory device. For ease of illustration, Figure 6A The NAND memory device 600 is represented in tabular format. Furthermore, the NAND memory device 600 can be simplified to show two sides of a die, with four memory strings on each side. In this example, data is to be stored in two dies ("Die0" and "Die1"), each with two sides ("Plane0" and "Plane1"). Each side may include one or more memory blocks configured to store data. Each memory block may correspond to six vertically arranged word lines, such as... Figure 6A As shown (“WL0” to “WL5”), each word line can be coupled to four strings (“SRT0”, “STR1”, “STR2” and “STR3”) in each face to form four pages.

[0160] In various implementations, the memory device may have more than two dies, and each die may have more than two faces. Each memory block may include more than six word lines, and each word line may be coupled to more than four strings to form more than four pages. Therefore, it can be understood that... Figure 6A This can describe part or all of the data to be stored in the memory device 600. In other words, Figure 6A It is possible to describe only one striped group. For example, Figure 6A The dashed lines in the diagram indicate that the memory device 600 may include additional pages for another striping group. That is, the pages shown in the solid lines are in one striping group, and there may be one or more other striping groups. One or more striping groups can be striped in the same or similar manner according to the first striping group.

[0161] Accordingly, Figure 6A An exemplary striping configuration implementing SLC technology can be shown. Clearly, Figure 6A The striping configuration in [the context] can also be applied to MLC, TLC, or QLC. For example, when TLC technology is applied to storage cells, Figure 6A Each physical page in the system can correspond to three logical pages used to store the previous page (UP) data portion, the middle page (MP) data portion, and the next page (LP) data portion.

[0162] In the Figure 6A In the provided example, all subsets of the pages in each face of each die (i.e., the striping group) can participate in generating J stripes. The term "subset of pages" is used to describe all pages to be striped and can include all pages in the striping group. Figure 6AAs shown, in one plane, a word line is coupled to four strings to form four pages, indicating that the value of R is 4. For example, when the ratio of J to R is determined to be 1.5, the memory controller 500 can be responsible for determining 4 × 1.5 = 6 stripes. In other words, the value of J (representing the number of stripes) can be 6. In some embodiments, a parity data portion corresponding to one of the six stripes can be stored at the end of each stripe 604. However, in some embodiments, the parity data portion can be stored in other memory locations such as dedicated memory blocks. For comparison purposes... Figure 2A 1-WL protection or Figure 3A As in 2-WL protection, maintain a data to parity ratio of 15:1, such as Figure 6A As shown, 15 data parts can be encoded (e.g., Figure 6A Data0 to Data14 in the dataset are used to generate a single parity data section (e.g., Parity0).

[0163] Method 700 can proceed to operation 704, where it can be based on... Figure 5A The memory controller 500 receives data and generates J parity data portions. In some embodiments, a stripe may include one parity data portion. Figure 6A In the example, 15 data portions can be used to generate a parity data portion. In some implementations, the processor 502 in the memory controller 500 can, for example, instruct the RAID circuitry 514 to process the 15 data portions and calculate a parity data portion based on the 15 data portions and one or more RAID algorithms. The encoding operation can be derived for... Figure 6A The parity data portion of stripe 604 is shown. In some instances, a series of XOR operations can be performed on the 15 data portions corresponding to stripe 604. For the data portions Data0, Data1, ..., Data14 to be stored in the 15 pages of stripe 604, the parity data can be generated as follows:

[0164] Parity0 = (Data0) XOR (Data1) XOR (Data2)…XOR (Data14) (3).

[0165] The parity check data portion serves as a form of redundancy, used to reconstruct lost or corrupted data in the event of a read failure. Figure 6A In order to keep the illustration clear, the logo is only attached to the part of the strip.

[0166] Method 700 proceeds to operation 706. At operation 706, the J parity data portions and the data portions can be stored in memory device 503. In some embodiments, memory controller 500 can be configured to store the original data portions and parity data portions based on corresponding stripes, thereby distributing these data portions across different memory pages in stripes or other memory locations. This approach ensures that all necessary data, including parity information, is available for subsequent recovery if necessary.

[0167] After the initial programming operation, when changes are made to the stored data, the parity information can also be updated accordingly via the GC circuitry, for example. Whenever data is modified, the memory controller 500 can be configured to recalculate the parity data portion based on the new data, ensuring that the stored parity information remains synchronized with the updated data. Real-time updates of the parity information ensure continuous protection of the data throughout its lifecycle in the memory device 503, maintaining the integrity and reliability of the stored data.

[0168] At operation 708, a read failure associated with a specific data segment may occur. This failure can be caused by various types of problems. For example, when the memory controller 500 encounters a problem during a data programming operation, it may be recognized that the data was not correctly written to the storage block. Subsequently, when the memory controller 500 attempts to read the stored data, a read failure may occur. At operation 710, the processor 502 in the memory controller 500 may instruct the RAID circuitry 514 to locate the data segment that has become corrupted or unreadable based on the read failure. Based on the unreadable data segment, the remaining data segments and parity data segments in the same band can be located. In some embodiments, the processor 502 may, for example, instruct... Figure 5A The RAID circuit 514 in the RAID uses the remaining accessible data portion and parity data portion in the same strip to manage the recovery process in order to rebuild a new data portion corresponding to the unreadable data portion.

[0169] For example, in a data portion of a strip (e.g., Figure 6A In the event of a read failure associated with Data0, recovery can be achieved by performing a decoding operation using the parity data and the remaining data portions (e.g., from Data1 to Data14). For example, a series of XOR operations can be performed on the parity data and the remaining data portions. Figure 6A When data segment Data2 fails, the data segment corresponding to the reconstructed data segment Data2 can be generated as follows:

[0170] (Datat2) = Parity0 XOR (Data0) XOR (Data1) XOR (Data3)…XOR (Data14) (4).

[0171] In some implementations, RAID can be used to handle programming failures through a data recovery mechanism. For example, when a programming failure occurs during the process of writing data to a storage block, resulting in corrupted or incomplete data portions, the RAID circuitry 514 can identify the affected data based on its error detection mechanism. By referencing the remaining data portions and parity data portions in the same band, the RAID circuitry 514 can reconstruct the corrupted or missing data portions. This recovery process ensures data integrity and reliability when programming operations fail.

[0172] In some embodiments, after the memory controller 500 has completed the recovery process using parity information and restored the new data portion, the new data portion can be written to different locations on the memory device 503 via the memory I / F circuit 506-2 to replace the unreadable data portion. In some embodiments, the parity information can be recalculated to ensure that the redundancy mechanism remains effective and is effective for error detection and recovery when necessary in the future. In some embodiments, the memory controller 500 can be configured to recalculate updated parity information for this stripe that now includes the newly generated data.

[0173] At operation 712, when no read fault is detected, processor 502 can send a notification to host 501 via host I / F circuit 506-1. This notification can be configured to inform host 501 that not only has the fault been recovered, but parity information has been successfully updated or no further read faults have been detected, thereby ensuring that the memory system remains fully protected from future faults. According to some embodiments, this arrangement will allow memory device 503 to log events to its internal error tracking system.

[0174] In some embodiments, this disclosure may (for example) be in Figure 5A The memory controller 500 provides a non-transitory computer-readable storage medium. This non-transitory computer-readable storage medium may store one or more programming instructions executable by the processor 502 (e.g., firmware). When the memory controller 500 executes one or more programming instructions, the operation according to method 700 can be performed.

[0175] In some implementations, processor 502 may instruct RAID circuitry 514 to determine multiple data portions from the striped group to generate a parity data portion. Figure 6AIn the provided example, a striped group may include four subsets of pages: a first subset 602 of pages in Plane0 of Die0, a second subset 608 of pages in Plane1 of Die0, a third subset 620 of pages in Plane0 of Die1, and a fourth subset 622 of pages in Plane1 of Die1. The first subset 602, the second subset 608, the third subset 620, and the fourth subset 622 constitute the participating... Figure 6A All pages in the striped group. In other words, these subsets of pages can form the striped group.

[0176] by Figure 6A For example, processor 502 can instruct RAID circuitry 514 to determine 15 data portions from a striped group, including a first subset 602 of pages in Plane 0 of Die 0, a second subset 608 of pages in Plane 1 of Die 0, a third subset 620 of pages in Plane 0 of Die 1, and a fourth subset 622 of pages in Plane 1 of Die 1. Figure 6A As shown, 15 data portions (e.g., Data0 to Data14) to be stored in 15 pages can form stripe 604. In some embodiments, processor 502 may also instruct RAID circuitry 514 to calculate a parity data portion using the 15 data portions. For example, a series of XOR operations can be performed on the 15 data portions to generate a parity data portion (e.g., "Parity0"). Processor 502 may generate write commands to store the 15 data portions and the parity data calculated according to equation (3) in memory device 503. In some examples, the parity data portion may be stored in the last page of stripe 604 (e.g., corresponding to the last page of ... Figure 6A In the “Pairty0” page. In some examples, the parity data portion may be stored in another memory location, such as a dedicated memory block.

[0177] In some memory systems, particularly in NAND memory devices, there is a high risk of short-circuit faults between two adjacent word lines. This type of fault occurs when electrical interference or leakage causes data corruption in a memory cell located between two physically adjacent word lines. This corruption can lead to the loss or alteration of stored data, rendering it inaccessible or incorrect. To mitigate this and other risks and improve the reliability of the memory system, the memory controller 500 (e.g., via firmware) can be configured to enforce specific rules for determining how striped pages can be organized across word lines.

[0178] In some implementations, processor 502 may instruct RAID circuitry 514 to follow some striping method for selecting pages corresponding to non-adjacent word lines to form stripes. In some implementations, processor 502 may be configured to take into account data structures and potential adjacent word line failures. In some implementations, placement rules may be built into, for example, firmware in memory controller 500.

[0179] Figure 9A and Figure 9B A flowchart illustrating an example method for determining stripes according to some aspects of this disclosure is shown. Figure 9A In operation 902 of method 900, when it is determined that the i-th page coupled to the first word line is included in one of the J stripes in a subset of the pages of a face, in operation 904, the processor 502 further determines that another stripe may include the i-th page coupled to the second word line adjacent to the first word line. In other words, in a subset of the pages of a face, two i-th pages coupled to two adjacent word lines may belong to different stripes in the J stripes. Hereinafter, the term "two i-th pages" refers to two pages in the same string / segment (i.e., having the same string index) of the same face. Furthermore, hereinafter, the term "page included in a stripe" describes a data portion to be stored in a page that may participate in the generation of the stripe. In some implementations, J parity data portions may be generated in parallel based on striping groups.

[0180] use Figure 6A As an example, when processor 502 determines that page 606 (i.e., the first page coupled to word line WL0 in a subset 608 of pages) is included in the first stripe, processor 502 may allocate page 610 coupled to word line WL1 adjacent to word line WL0 to a second stripe different from the first stripe. That is, pages 606 and 610 may be allocated to two different stripes.

[0181] In terms of physical location, Figure 6A Page 606 in the text can be equivalent to Figure 2B PAGE1 in the middle, and Figure 6A Page 610 in the text can be equivalent to Figure 2B In some implementations, the data portion corresponding to PAGE1 and another data portion corresponding to PAGE2 can be assigned to different stripes. Because of the high risk of short-circuit faults between two adjacent word lines, this placement of pages coupled to two adjacent word lines on different stripes can mitigate word line and word line short-circuit faults, and thus improve the reliability of the memory system.

[0182] In some implementations, processor 502 can assign two adjacent pages coupled to the same word line to different stripes. This striping approach can address the potential risk that a failure affecting a single word line could corrupt multiple pages stored on that word line. Figure 9B In operation 903 of method 901, when it is determined that the i-th page coupled to the first word line is included in one of the J stripes in a subset of pages of a face, in operation 905, processor 502 can further determine that another stripe includes the (i+1)-th page coupled to the same first word line. In other words, in a subset of pages, two adjacent pages coupled to the same word line can belong to different stripes of the J stripes.

[0183] use Figure 6A As an example, when processor 502 determines that page 606 (i.e., the first page coupled to word line WL0 in subset 608 of pages) is included in the first stripe, processor 502 may allocate page 616, which is adjacent to page 606 and coupled to the same word line WL0, to the second stripe. That is, pages 606 and 616 can belong to two different stripes. In terms of physical location, returning to... Figure 2B , Figure 6A Page 606 in the text can be equivalent to Figure 2B PAGE1 in the middle, and Figure 6A Page 616 in the text can be equivalent to Figure 2B Page 6 of the document.

[0184] In some implementations, within a subset of pages, each of the first, second, and third pages coupled to the same word line may belong to a corresponding strip in J strips. The second and third pages may be adjacent to the first page coupled to the same word line. In some implementations, within a subset of pages, each of the fourth, fifth, and sixth pages coupled to the first, second, and third word lines, respectively, may belong to a corresponding strip in J strips. The first and third word lines are adjacent to the second word line. Furthermore, the fourth, fifth, and sixth pages are included in the same string.

[0185] In some implementations, in Figure 6A In a subset 608 of the pages, processor 502 can assign page 612, coupled to the same word line WL1 and laterally arranged in different strings, and its adjacent pages 610 and 614, to three different stripes out of six stripes. In some embodiments, processor 502 can assign page 612, vertically arranged in the same string and coupled to three different word lines, and its adjacent pages 616 and 618, to three different stripes.

[0186] In some implementations, processor 502 may apply these striping methods as striping patterns to all subsets of a page. For example, a striping pattern may be applied to a first stripe comprising a first set of pages and a second set of pages (corresponding to K pages, where K is an integer). The first set of pages may include the i-th page from each subset of pages coupled to the k-th word line, where 1 ≤ i ≤ R. The second set of pages may include the j-th page from each subset of pages coupled to the (k+1)-th word line, where 1 ≤ j ≤ R and j ≠ i. It can be understood that the (k+1)-th word line is a word line adjacent to the k-th word line. The k-th word line and the (k+1)-th word line are among multiple word lines in a plane.

[0187] For example, in Figure 6A In this context, the first set may include the first page (including Data0, Data1, Data2, and Data3 to be stored in STR0) coupled to word line WL0 from each subset of pages. To reduce word line and word line short-circuit faults, pages corresponding to strings different from STR0 can be selected within the same stripe. For example, the third page (including Data4, Data5, Data6, and Data7 to be stored in STR2) coupled to word line WL1 can be determined as the second set of the first stripe.

[0188] In some implementations, the stripe may include a third set of pages and a fourth set of pages. The third set of pages may include the i-th page from each subset of pages coupled to the k-th word line in a plurality of word lines, 1≤i≤R. The fourth set of pages may include the i-th page from each subset of pages coupled to the (k+n)-th word line in a plurality of word lines, n>1. That is, the (k+n)-th word line is not a word line adjacent to the k-th word line. The k-th word line and the (k+n)-th word line are among the plurality of word lines in a plane.

[0189] For example, in Figure 6A In this stripe, the first set of pages may include the first page coupled to word line WL0 from each subset of pages (including Data0, Data1, Data2, and Data3 to be stored in STR0). Subsequently, pages coupled to non-adjacent word lines from the same segment can be selected for this stripe. For example, the fourth set may include pages coupled to word line WL3 from each subset of pages in the same string (including Data8, Data9, Data10, and Data11). By organizing the pages of the stripe according to the pattern, the memory system can increase its resilience to general physical failures.

[0190] Figure 6B Some aspects of this disclosure are shown. Figure 6A A schematic diagram of an example striped configuration from another perspective, 601. Figure 6B It shows from different perspectives Figure 6A The subset of pages 602 and stripe 604. For example... Figure 6A and Figure 6B As shown, in one plane, word lines are coupled to four strings such that R equals 4. Furthermore, a total of six stripes are generated based on this striping group, and J can be equal to 6, such that the ratio of J to R is 1.5.

[0191] Figure 10 A schematic diagram of a third example data structure and non-integer striping configuration for a RAID algorithm implemented in a memory device 1000 according to some aspects of this disclosure is shown. Nine stripes 1004 are generated based on each subset 1002 of a page. Figure 10 This is another example illustrating a J / R ratio of 1.5, but with different J and R values, and a data structure. For example, as... Figure 10 As shown, J=9, R=6, and each die can include 4 faces.

[0192] However, the non-integer striping configuration provided by this disclosure is not limited to 1.5-WL protection (i.e., not limited to a J to R ratio equal to 1.5). According to the core of this disclosure, the ratio of J (i.e., the number of stripes) to R (i.e., the number of strings coupled to word lines in a plane) can be a value greater than 1 and less than 2.

[0193] For example, Figure 11 A schematic diagram of a third example data structure and non-integer striping configuration for a RAID algorithm implemented in a memory device 1100 according to some aspects of this disclosure is shown. In some embodiments, the ratio of J to R may be 1.25. Figure 11 In the example shown, five stripes can be generated based on each subset 1102 of the pages in each face of each die. That is, J is 5, although in Figure 11 In the text, only one stripe, 1104, is annotated. For example... Figure 11 As shown, the number of strings coupled to the word line in a plane can be 4. That is, R is 4. In each stripe, 15 data portions are used to generate a parity data portion, maintaining a 15:1 data to parity ratio.

[0194] It should be understood that providing a 15:1 data to parity ratio, as described in some embodiments of this disclosure, is for the purpose of fairly comparing different striping configurations on a common baseline. However, this disclosure is not limited to this specific ratio. In some embodiments, the data to parity ratio may differ from 15:1. For example, Figure 12 A schematic diagram of a fourth example data structure and non-integer striping configuration for a RAID algorithm implemented in a memory device 1200 according to some aspects of this disclosure is shown. Figure 12The ratio of J to R is shown to be 1.5, where J (the number of stripes) equals 9, and R (the number of strings coupled to word lines in a plane) equals 6. Figure 12 In the example, the data to parity ratio is 23:1, not 15:1.

[0195] Figure 13 A schematic diagram of a fifth example data structure and non-integer striping configuration for a RAID algorithm implemented in a memory device 1300 according to some aspects of this disclosure is shown. Seven stripes are generated based on a subset 1302 of pages in each face of each die (i.e., striping groups), although in Figure 13 In the text, only one stripe, 1304, is annotated. Therefore, J equals 7. (As shown...) Figure 13 As shown, in a plane, four strings are coupled to a word line such that R equals 4. Accordingly, the ratio of J to R can be 1.75. According to... Figure 13 Fifteen data portions are used to generate a parity data portion, maintaining the data-to-parity ratio at 15:1 for comparison.

[0196] It is understood that, in some embodiments of this disclosure, a subset of pages may not cover all pages coupled to multiple word lines in a single face. Figure 14A A schematic diagram of a sixth example data structure and non-integer striping configuration for a RAID algorithm implemented in a memory device 1400, according to some aspects of this disclosure, is shown. Figure 14A As shown, the subset 1402 of pages is not rectangular, such that pages P1 (string S4 coupled to word line WL4) and P2 are not included in the subset 1402 of pages used for this striped group. It can be understood that since each subset 1402 of pages is not a regular shape, the number of word lines in this striped group (corresponding to parameter Q) is not an integer, such that the value of Q is 4.67. Q may represent the number of word lines coupled to a subset of pages in the striped group. In some embodiments, the memory device 1400 may include one or more other striped groups. Unstriped P1 and P2 may be included in one of these striped groups.

[0197] based on Figure 14A The first banding group in the middle generated seven bands, although in Figure 14A In the text, only one stripe, 1404, is annotated. Therefore, J equals 7. (As shown...) Figure 14A As shown, in a plane, six strings are coupled to word lines such that R equals 6. Correspondingly, the ratio of J to R is approximately 1.167. According to... Figure 14A Fifteen data parts are used to generate a parity data part, keeping the data to parity ratio at 15:1. Figure 14B Some aspects of this disclosure are shown. Figure 14A A schematic diagram of the sixth exemplary striped configuration from another perspective 1401. Figure 14B China shows from different perspectives Figure 14A The subset of pages 1402, stripe 1404, and unstriped pages P1 and P2.

[0198] Figure 15 A schematic diagram of a seventh example data structure and non-integer striping configuration for a RAID algorithm implemented in a memory device 1500 according to some aspects of this disclosure is shown. Figure 15 Another example is shown, in which some pages are not striped and do not participate in striping groups. For example, coverage is coupled to... Figure 15 Some page 1506 regions of the word line WL2 were not striped in the striping group. Based on a subset 1502 of pages in each face of each die, seven stripes 1504 were generated. Therefore, J equals 7. Figure 15 As shown, in a plane, six strings are coupled to word lines such that R equals 6. Accordingly, the ratio of J to R can be 1.167. According to... Figure 15 Fifteen data portions are used to generate a parity data portion, maintaining the data-to-parity ratio at 15:1. This is understandable because some pages coupled to some word lines in this striping group do not participate in the striping group, so the number of word lines in the striping group is not an integer, making the value of Q 2.3.

[0199] Based on the foregoing, it can be understood that this disclosure does not limit the J and R values ​​or the data structure. In some implementations, the J and R values, as well as other parameters (e.g., Q), can be flexibly determined according to actual needs. At the core of this disclosure, the ratio of J to R can include values ​​greater than 1 and less than 2.

[0200] Figure 16A schematic diagram of data recovery protection in an example non-integer striping configuration according to some aspects of this disclosure is shown. In this non-integer striping example, portions of three adjacent word lines WLn-1, WLn, and WLn+1 can be included in three stripes shown at different gray levels. When a PSF occurs at position ① and affects the two portions above it coupled to word line WLn-1, the fault can be corrected based on this non-integer striping. The reason is that the faulty portion at position ① and the two faulty portions above it corresponding to word line WLn-1 belong to three different stripes. Therefore, based on this striping strategy, the data portions in these three positions can all be recovered. Similarly, when a PSF occurs at position ③ and affects positions ① and ② coupled to word line WLn, this fault can also be repaired. When a PSF occurs at position ④ and affects positions ① and ② above it, the fault cannot be corrected because the faulty portions at positions ④ and ① belong to the same stripe. Note that although protection against the PSF at position ④ may be less, as Figure 10 As shown, the occurrence rate of word line and word line short-circuit faults at this location is also relatively low. Therefore, this non-integer striping strategy provides sufficient data protection to improve the reliability of the memory device.

[0201] According to some embodiments of this disclosure, protection strategies with reasonable costs can be adopted based on the distribution of defective parts per million units (DPPM) while minimizing the impact on performance. Accordingly, striping based on integer multiples of word lines may not be necessary. Striping configurations can be customized according to actual needs. According to some embodiments of this disclosure, non-integer striping configurations covering most word line leakage problems are obtained. Non-integer striping configurations can provide coverage of most DPPM problems with relatively reasonable RAID buffer usage while reducing buffer occupancy in terms of performance.

[0202] The foregoing description of the specific embodiments will reveal the general nature of this disclosure, enabling those skilled in the art to readily modify and / or adapt such particular embodiments for various applications without excessive experimentation, using knowledge in the art, without departing from the general conception of this disclosure. Therefore, based on the teachings and guidance presented herein, such modifications and alterations are intended to fall within the meaning and scope of equivalents of the disclosed embodiments. It should be understood that the wording or terminology used herein is for descriptive rather than limiting purposes, and that the terminology or terminology in this specification should be interpreted by those skilled in the art based on the teachings and guidance.

[0203] The embodiments of this disclosure have been described above using functional building blocks that illustrate specific functions and their relationships. For ease of description, the boundaries of these functional building blocks are arbitrarily defined herein. Alternative boundaries may be defined as long as the specific functions and their relationships are properly performed.

[0204] The summary and abstract section may illustrate one or more, but not all, exemplary embodiments of this disclosure conceived by one or more inventors, and therefore is not intended to limit this disclosure and the appended claims in any way.

[0205] The breadth and scope of this disclosure should not be limited by any of the exemplary embodiments described above, but should be defined solely by the appended claims and their equivalents.

Claims

1. A memory system, comprising: Memory device, the memory device comprising one or more dies, each including a plurality of faces, wherein: Each of the plurality of faces includes a subset of pages corresponding to a plurality of word lines to form a striped group in the one or more dies, wherein one word line of the plurality of word lines is coupled to R strings in each face to form R pages; and The striping group forms J strips, where each of R and J is an integer, and the ratio of J to R is a value greater than 1 and less than 2; and A memory controller, coupled to the memory device, and configured to: Receive the data portions corresponding to the J stripes; Based on the aforementioned data portion, J parity check data portions are generated; and The memory device is controlled to store the J parity check data portions.

2. The memory system according to claim 1, wherein: The ratio of J to R is 1.

5.

3. The memory system according to claim 1, wherein: The ratio of J to R is 1.

25.

4. The memory system according to claim 1, wherein: The ratio of J to R is 1.

75.

5. The memory system according to any one of claims 1 to 4, wherein, The memory controller is also configured to: The ratio of J to R is determined based on the distribution of programming faults associated with the memory device.

6. The memory system according to any one of claims 1 to 5, wherein: In the subset of the pages, the two i-th pages of two adjacent word lines coupled to the multiple word lines belong to two stripes of the J stripes, 1≤i≤R.

7. The memory system according to any one of claims 1 to 5, wherein: In the subset of the pages, two adjacent pages coupled to the same word line among the multiple word lines belong to two of the J stripes.

8. The memory system according to any one of claims 1 to 5, wherein: In the subset of the pages, each of the first, second, and third pages coupled to the same word line belongs to the corresponding strip in the J strips, and the second and third pages are adjacent to the first page corresponding to the same word line.

9. The memory system according to any one of claims 1 to 5, wherein: In the subset of the pages, each of the fourth, fifth, and sixth pages, respectively coupled to the first, second, and third word lines, belongs to the corresponding strip among the J strips, wherein: The first character line and the third character line are adjacent to the second character line; and The fourth page, the fifth page, and the sixth page correspond to the same string.

10. The memory system according to any one of claims 1 to 5, wherein: The first strip of the J stripes includes a first set of pages and a second set of pages; The first set of pages includes the i-th page from each subset of pages coupled to the first word line in the plurality of word lines, 1≤i≤R; and The second set of pages includes the j-th page from each subset of pages coupled to the second word line adjacent to the first word line, 1≤j≤R and j≠i.

11. The memory system according to any one of claims 1 to 5, wherein: The first strip of the J strips includes the third set of pages and the fourth set of pages; The third set of pages includes the i-th page from each subset of pages coupled to the first word line in the plurality of word lines, 1≤i≤R; and The fourth set of pages includes the i-th page from each subset of pages coupled to a third word line that is not adjacent to the first word line.

12. The memory system according to any one of claims 1 to 11, wherein, The memory controller is also configured to perform an encoding operation on the data portion to generate the J parity data portions.

13. The memory system according to any one of claims 1 to 12, wherein, The memory controller is also configured to: Receive a first data portion corresponding to a first page in a subset of the pages and a second data portion corresponding to a second page in a subset of the pages; and Perform an XOR operation on the first data portion and the second data portion.

14. The memory system according to any one of claims 1 to 13, wherein: One of the J stripes corresponds to one of the J parity check data portions; and The memory controller is also configured to control the memory device to store the parity data portion of the J parity data portions in the last page of the strip.

15. The memory system according to any one of claims 1 to 14, wherein, The memory controller is also configured to respond to a read failure associated with the third data portion: Locate the third data portion corresponding to the read failure in the memory device; Obtain the remaining data portion and the first parity data portion of the strip containing the third data portion; The reconstructed data portion is generated based on the first parity check data portion and the remaining data portion; and Replace the third data portion with the reconstructed data portion.

16. The memory system of claim 15, wherein, The memory controller is configured to: An XOR operation is performed on the remaining data portion and the first parity data portion to generate the reconstructed data portion.

17. The memory system according to any one of claims 1 to 16, wherein, The memory controller is also configured to: When no read fault is associated with the J stripes, a notification signal is sent to the host coupled to the memory controller.

18. The memory system according to any one of claims 1 to 17, wherein, The memory device includes NAND memory cells, and the memory controller includes a flash memory controller.

19. A memory controller, comprising: An interface (I / F) circuit, said interface (I / F) circuit being coupled to a memory device, said memory device comprising one or more dies, each comprising a plurality of faces, wherein: Each of the plurality of faces includes a subset of pages corresponding to a plurality of word lines to form a striped group in the one or more dies, wherein one word line of the plurality of word lines is coupled to R strings in each face to form R pages; and The striping group forms J strips, where each of R and J is an integer, and the ratio of J to R is a value greater than 1 and less than 2; and A processor, coupled to the I / F circuit and configured to: Receive the data portions corresponding to the J stripes; Based on the aforementioned data portion, J parity check data portions are generated; and The I / F circuit is controlled to send a write command, the data portion, and the J parity data portions to the memory device to store the J parity data portions and the data portion in the memory device.

20. The memory controller of claim 19, wherein: The ratio of J to R is 1.

5.

21. The memory controller according to claim 19, wherein: The ratio of J to R is 1.

25.

22. The memory controller according to claim 19, wherein: The ratio of J to R is 1.

75.

23. The memory controller of any one of claims 19-22, wherein, The processor is also configured to: The ratio of J to R is determined based on the distribution of programming faults associated with the memory device.

24. The memory controller according to any one of claims 19 to 23, wherein: In the subset of the pages, the two i-th pages of two adjacent word lines coupled to the multiple word lines belong to two stripes of the J stripes, 1≤i≤R.

25. The memory controller according to any one of claims 19 to 23, wherein: In the subset of the pages, two adjacent pages coupled to the same word line among the multiple word lines belong to two of the J stripes.

26. The memory controller according to any one of claims 19 to 23, wherein: In the subset of the pages, each of the first, second, and third pages coupled to the same word line belongs to the corresponding strip in the J strips, and the second and third pages are adjacent to the first page corresponding to the same word line.

27. The memory controller according to any one of claims 19 to 23, wherein: In the subset of the pages, each of the fourth, fifth, and sixth pages, respectively coupled to the first, second, and third word lines, belongs to the corresponding strip among the J strips, wherein: The first character line and the third character line are adjacent to the second character line; and The fourth page, the fifth page, and the sixth page are included in the same string.

28. The memory controller according to any one of claims 19 to 23, wherein: The first strip of the J stripes includes a first set of pages and a second set of pages; The first set of pages includes the i-th page from each subset of pages coupled to the first word line in the plurality of word lines, 1≤i≤R; and The second set of pages includes the j-th page from each subset of pages coupled to the second word line adjacent to the first word line, 1≤j≤R and j≠i.

29. The memory controller according to any one of claims 19 to 23, wherein: The first strip of the J strips includes the third set of pages and the fourth set of pages; The third set of pages comprises the i-th page coupled to the first word line from each subset of pages, 1 ≤ i ≤ R; and The fourth set of pages includes the i-th page from each subset of pages coupled to a third word line that is not adjacent to the first word line.

30. The memory controller of any one of claims 19-29, wherein, The processor is also configured to perform encoding operations on the data portions to generate the J parity data portions.

31. The memory controller according to any one of claims 19 to 30, wherein, The processor is also configured to: The I / F circuit is controlled to receive a first data portion of a first page corresponding to a subset of the pages and a second data portion of a second page corresponding to a subset of the pages; and Perform an XOR operation on the first data portion and the second data portion.

32. The memory controller according to any one of claims 19 to 31, wherein: One of the J stripes corresponds to one of the J parity check data portions; and The processor is also configured to: Generate the write command; and The I / F circuit is controlled to send the write command and the parity data portion to the memory device to store the parity data portion in the last page of the stripe.

33. The memory controller according to any one of claims 19 to 32, wherein, The processor is also configured to respond to a read failure associated with the third data portion: Locate the third data portion corresponding to the read failure in the memory device; Obtain the remaining data portion and the first parity data portion of the strip containing the third data portion; The reconstructed data portion is generated based on the first parity check data portion and the remaining data portion; and The I / F circuit is controlled to send the reconstructed data portion to the memory device for storage in the memory device.

34. The memory controller according to any one of claims 19 to 33, wherein, The processor is also configured to generate the J parity data portions in parallel.

35. A method for implementing independent disk redundancy device (RAID) striping in a memory device, said memory device comprising one or more dies, each comprising a plurality of facets, wherein: Each of the plurality of faces includes a subset of pages corresponding to a plurality of word lines to form a striped group in the one or more dies, wherein one word line of the plurality of word lines is coupled to R strings in each face to form R pages; and The striping group forms J strips, where each of R and J is an integer, and the ratio of J to R is a value greater than 1 and less than 2; and The method includes: Receive the data portions corresponding to the J stripes; Based on the aforementioned data portion, generate J parity check data portions; and The memory device is controlled to store the J parity check data portions.

36. The method of claim 35, wherein: The ratio of J to R is 1.

5.

37. The method of claim 35, wherein: The ratio of J to R is 1.

25.

38. The method of claim 35, wherein: The ratio of J to R is 1.

75.

39. The method according to any one of claims 35 to 38, further comprising: The ratio of J to R is determined based on the distribution of programming faults associated with the memory device.

40. The method according to any one of claims 35 to 39, wherein: In the subset of the pages, the two i-th pages of two adjacent word lines coupled to the multiple word lines belong to two stripes of the J stripes, 1≤i≤R.

41. The method according to any one of claims 35 to 39, wherein: In the subset of the pages, two adjacent pages coupled to the same word line among the multiple word lines belong to two of the J stripes.

42. The method according to any one of claims 35 to 39, wherein: In the subset of the pages, each of the first, second, and third pages coupled to the same word line belongs to the corresponding strip in the J strips, and the second and third pages are adjacent to the first page corresponding to the same word line.

43. The method according to any one of claims 35 to 39, wherein: In the subset of the pages, each of the fourth, fifth, and sixth pages, respectively coupled to the first, second, and third word lines, belongs to the corresponding strip among the J strips, wherein: The first character line and the third character line are adjacent to the second character line; and The fourth page, the fifth page, and the sixth page are included in the same string.

44. The method according to any one of claims 35 to 39, wherein: The first strip of the J stripes includes a first set of pages and a second set of pages; The first set of pages includes the i-th page from each subset of pages coupled to the first word line in the plurality of word lines, 1≤i≤R; and The second set of pages includes the j-th page from each subset of pages coupled to the second word line adjacent to the first word line, 1≤j≤R and j≠i.

45. The method according to any one of claims 35 to 39, wherein: The first strip of the J strips includes the third set of pages and the fourth set of pages; The third set of pages includes the i-th page from each subset of pages coupled to the first word line in the plurality of word lines, 1≤i≤R; and The fourth set of pages includes the i-th page from each subset of pages coupled to a third word line that is not adjacent to the first word line.

46. ​​The method according to any one of claims 35 to 45, wherein, Generating the J parity check data portions based on the data portion includes performing an encoding operation on the data portion to generate the J parity check data portions.

47. The method according to any one of claims 35 to 46, wherein, Generating the J parity check data portions based on the aforementioned data portions includes: Receive a first data portion corresponding to a first page in a subset of the pages and a second data portion corresponding to a second page in a subset of the pages; and Perform an XOR operation on the first data portion and the second data portion.

48. The method according to any one of claims 35 to 47, wherein: One of the J stripes corresponds to one of the J parity check data portions; and Controlling the memory device to store the J parity data portions includes controlling the memory device to store the parity data portions in the last page of the stripe.

49. The method of any one of claims 35 to 48, further comprising responding to a read failure associated with the third data portion: Locate the third data portion corresponding to the read failure in the memory device; Obtain the remaining data portion and the first parity data portion of the strip containing the third data portion; The reconstructed data portion is generated based on the first parity check data portion and the remaining data portion; and Replace the third data portion with the reconstructed data portion.

50. The method according to claim 49, wherein, The data portion used to generate the reconstruction includes: An XOR operation is performed on the remaining data portion and the first parity data portion to generate the reconstructed data portion.

51. The method according to claims 35 to 50, further comprising: When no read fault is associated with the J stripes, a notification signal is sent to the host.

52. A non-transitory storage medium coupled to a memory device and a processor, the memory device comprising one or more dies, each including a plurality of faces, wherein: Each of the plurality of faces includes a subset of pages corresponding to a plurality of word lines to form a striped group in the one or more dies, wherein one word line of the plurality of word lines is coupled to R strings in each face to form R pages; and The striping group forms J strips, where each of R and J is an integer, and the ratio of J to R is a value greater than 1 and less than 2; and The non-transitory storage medium is configured to store instructions, which, when executed by the processor, cause the processor to: Receive the data portions corresponding to the J stripes; Based on the aforementioned data portion, J parity check data portions are generated; and The memory device is controlled to store the J parity check data portions.

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