Data transmission methods, data transmission systems, and in-vehicle infotainment systems

Abstract

This disclosure provides a data transmission method, a data transmission system, and an in-vehicle infotainment system, relating to the field of vehicle data transmission technology. The method includes: a first chip, in response to detecting a high level at a first port of a second chip, pulling up the level of a second port; the first chip initiating a processing procedure for a third chip to send a first dataset to the first chip via the second chip; and the third chip, in response to detecting a high level at the second port, initiating a processing procedure for the first chip to send a second dataset to the third chip via the second chip; wherein the second dataset is determined based on the first dataset. This method can effectively control hardware costs and hardware design complexity while reducing system load and improving the efficiency and stability of hardware-based data transmission.

Description

Technical Field

[0001] This disclosure relates to the field of vehicle data transmission technology, and in particular to a data transmission method, a data transmission system, and an in-vehicle infotainment system. Background Technology

[0002] With the development of vehicle electrification and intelligence, in assisted driving systems, the screen content of one electronic device can be simultaneously projected onto the screen of another device. A typical application is the real-time transmission of the screen content of mobile phones, tablets, and other devices to in-vehicle terminals. Currently, data transmission is generally based on single-chip unidirectional data transmission, and most commercially available chips are designed for scenarios such as mobile phone data transmission. In case of data transmission failure, simply reseating the chip resolves the issue, and stability requirements are not high. Therefore, they cannot meet the stability requirements for data transmission between multi-chip (or multi-core) in-vehicle systems. Summary of the Invention

[0003] This disclosure proposes a data transmission method, a data transmission system, and a vehicle-mounted system. By using a single second chip, bidirectional data transmission between multiple chips can be completed without the need for image encoding and decoding. This effectively controls hardware costs and hardware design complexity while reducing system load and improving the efficiency and stability of hardware-based data transmission.

[0004] In a first aspect, embodiments of this disclosure propose a data transmission method, comprising: a first chip pulling up the level of a second port in response to detecting that the level of a first port of a second chip is pulled high; the first chip initiating a processing procedure for a third chip to send a first dataset to the first chip via the second chip; and the third chip initiating a processing procedure for a first chip to send a second dataset to the third chip via the second chip in response to detecting that the level of the second port is pulled high; wherein the second dataset is determined based on the first dataset.

[0005] Secondly, embodiments of this disclosure provide a data transmission system, including: a first chip, a second chip, and a third chip. The first chip is configured to, in response to detecting a high level at a first port of the second chip, pull up the level of a second port and initiate a process for the third chip to send a first dataset to the first chip via the second chip; and the third chip is configured to, in response to detecting a high level at the second port, initiate a process for the first chip to send a second dataset to the third chip via the second chip; wherein the second dataset is determined based on the first dataset.

[0006] Thirdly, embodiments of this disclosure provide a vehicle infotainment system, including a data transmission system as described in any of the implementations of the second aspect above.

[0007] The data transmission method, data transmission system, and vehicle-mounted system provided in this disclosure can include a second chip positioned between a first chip and a third chip. The first chip monitors whether the level of a first port of the second chip is pulled high, and in response to detecting that the level of the first port is pulled high, it controls and triggers bidirectional multi-chip data transmission between itself and the third chip by pulling the level of its second port high. Specifically, the first chip, acting as the receiving end, initiates a processing program for the third chip to transmit its first dataset to the first chip via the second chip, and the third chip, acting as the receiving end, initiates a processing program for the first chip to transmit its second dataset to the third chip via the second chip. Thus, by using a single second chip, bidirectional data transmission between multiple chips can be completed without the need for image encoding and decoding. This effectively controls hardware costs and hardware design complexity while reducing system load and improving the efficiency and stability of hardware-based data transmission.

[0008] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this disclosure, nor is it intended to limit the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0009] Other features, objects, and advantages of this disclosure will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0010] Figure 1 A flowchart illustrating a data transmission method provided in this embodiment of the disclosure;

[0011] Figure 2 A flowchart illustrating another data transmission method provided in this disclosure embodiment;

[0012] Figure 3 This is a schematic diagram illustrating the connection relationships between the components of a data transmission system in an application scenario, provided by an embodiment of the present disclosure.

[0013] Figure 4 This is a structural block diagram of a data transmission system provided in an embodiment of the present disclosure;

[0014] Figure 5 This is a structural block diagram of a vehicle infotainment system provided in an embodiment of the present disclosure. Detailed Implementation

[0016] The exemplary embodiments of this disclosure are described below with reference to the accompanying drawings, including various details of the embodiments to aid understanding; these should be considered merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of this disclosure. Similarly, for clarity and brevity, descriptions of well-known functions and structures are omitted in the following description. It should be noted that, unless otherwise specified, the embodiments and features described in this disclosure can be combined with each other.

[0017] It should be noted that the collection, acquisition, storage, processing, transmission, provision, disclosure, and application of user personal information (such as information required by the corresponding vehicle system when a user logs into the vehicle) in the technical solution disclosed herein are all performed with the user's knowledge and explicit authorization, comply with the provisions of relevant laws and regulations, and do not violate public order and good morals.

[0018] With the development of vehicle electrification and intelligence, in assisted driving, the screen content of one electronic device can be synchronously projected onto the screen of another device to achieve screen display. A typical application is the real-time transmission of the screen content of mobile phones, tablets, and other devices to the in-vehicle terminal device. However, current implementations are generally based on single-chip unidirectional data transmission, and most finished chips are designed for scenarios such as data transmission based on mobile phones. In case of data transmission failure, simply re-plugging and re-plugging can solve the problem, and the stability requirements are not high. Therefore, it cannot meet the stability requirements for data transmission between multi-chip (or multi-core) in-vehicle systems. Moreover, the network transmission scheme used in related technologies for image transmission between chips mounted on different motherboards in the in-vehicle system requires image encoding and decoding, which will put a large load on the system and result in high latency, affecting data transmission efficiency. In addition, there is a need for multimodal data fusion in the existing smart cockpit domain, that is, to collect data from different sensors (such as radar sensors, vision sensors, etc.), and data from different sources may come from different cores, which will further involve data transmission between multiple cores, and there are requirements for data transmission efficiency and stability.

[0019] Please refer to Figure 1 , Figure 1 A flowchart of a data transmission method provided in this disclosure embodiment can be applied to, but is not limited to, vehicle infotainment systems. The process 100 includes the following steps:

[0020] Step 101: In response to detecting that the level of the first port of the second chip has been pulled high, the first chip pulls the level of the second port high.

[0021] In this step, the second chip can indicate that it is working properly by pulling the level of its first port high, and can further trigger the first chip to pull the level of its second port high. The first port and the second port can be a General Purpose Input / Output (GPIO) port, a Serial Peripheral Interface (SPI) port, or an Inter-Integrated Circuit (I2C) port, respectively.

[0022] Step 102: The first chip starts the processing program that sends the first dataset from the third chip to the first chip via the second chip.

[0023] Step 103: In response to detecting that the level of the second port is pulled high, the third chip starts a processing program to send the second dataset from the first chip to the third chip via the second chip; wherein the second dataset is determined based on the first dataset.

[0024] In this step, the first chip can process the first dataset sent by the third chip and arriving via the second chip to obtain the second dataset to be sent to the third chip, thereby reducing the computing power pressure on the third chip side.

[0025] Based on step 101 above, after the first chip pulls the level of its second port high, the corresponding processing programs can be started at the receiving end (the first chip and the third chip respectively). Furthermore, by setting a second chip between the first and third chips, bidirectional transmission of data sets between the first and third chips can be achieved. Further, the first and second ports mentioned above are GPIO ports. Thus, by setting the GPIO ports at the receiving end of each data set, control over frame data transmission can be easily achieved.

[0026] The data transmission method provided in this disclosure embodiment can place a second chip between a first chip and a third chip. The first chip is responsible for monitoring whether the level of the first port of the second chip is pulled high. In response to detecting that the level of the first port is pulled high, the first chip controls and triggers bidirectional multi-chip data transmission between itself and the third chip by pulling the level of its second port high. Specifically, the first chip, as the receiving end, initiates a processing program for the third chip to transmit its first dataset to the first chip via the second chip, and the third chip, as the receiving end, initiates a processing program for the first chip to transmit its second dataset to the third chip via the second chip. That is, there are two data transmission paths between the first chip and the third chip via the second chip. In this way, by using a single second chip, bidirectional data transmission between multiple chips can be completed without the need for image encoding and decoding. This can effectively control hardware costs and hardware design complexity while reducing system load and improving the efficiency and stability of hardware-based data transmission.

[0027] Please refer to Figure 2 , Figure 2 A flowchart of another data transmission method provided in this disclosure embodiment, which can be applied to, but is not limited to, vehicle infotainment systems, includes the following steps in process 200:

[0028] Step 201: In response to detecting that the level of the first port of the second chip has been pulled high, the first chip pulls the level of the second port high.

[0029] Step 202: The first chip starts the processing program that sends the first dataset from the third chip to the first chip via the second chip.

[0030] Step 203: In response to detecting that the level of the second port is pulled high, the third chip starts a processing program to send the second dataset from the first chip to the third chip via the second chip; wherein the second dataset is determined based on the first dataset.

[0031] Steps 201-203 above are the same as those mentioned above. Figure 1 The steps 101-103 shown are the same. For the same parts, please refer to the corresponding parts of the previous embodiment. They will not be repeated here.

[0032] Step 204: In response to the failure to acquire the second dataset, the third chip pulls the level of the third port high. This third port can be a GPIO port, SPI port, or I2C port.

[0033] Based on step 203 above, after the third chip, as the receiving end, starts the processing program for the first chip to send the second dataset via the second chip, it monitors in real time whether the second dataset sent by the first chip has been successfully obtained. If it fails, it needs to pull the level of its third port high in time to notify the sending end, i.e. the first chip, of the failure of the transmission of the second dataset.

[0034] Step 205: In response to detecting that the level of the third port is pulled high and detecting that the processing program corresponding to the second dataset is abnormal, the first chip pulls the level of the second port low.

[0035] Based on step 204 above, when the first chip learns that the third chip has not successfully received the second dataset it sent and confirms that its corresponding processing program is abnormal, it can switch the level of its previously high second port to low so as to respond promptly in the event of a fault.

[0036] The data communication method provided in this disclosure can achieve bidirectional data transmission between multiple chips by using a single second chip without the need for image encoding / decoding. A third chip is responsible for detecting the success or failure of receiving the second dataset. When unsuccessful reception is detected, it notifies the first chip by raising the level of its third port. The first chip is further responsible for specific fault detection. If a data transmission anomaly is confirmed, it responds promptly by lowering the previously raised level of the second port to facilitate further troubleshooting. Thus, while achieving fault detection during bidirectional data transmission, it also simplifies the communication process between the first and third chips. Furthermore, their division of labor avoids potential conflicts that could occur if both the first and third chips operate the same chip (the second chip) simultaneously.

[0037] Furthermore, in some optional implementations of the embodiments of this disclosure, in the above... Figure 2 Based on the corresponding embodiment, the third chip may also include the following: in response to detecting that the level of the second port is pulled low, the third chip stops executing the processing program corresponding to the first dataset.

[0038] In this embodiment, in order to ensure the reliability of bidirectional data transmission between the first chip and the third chip, the third chip can stop transmitting the data set to the first chip via the second chip when it detects a signal indicating that the first chip has determined that the processing program corresponding to the second data set is abnormal.

[0039] Furthermore, in some optional implementations of the embodiments of this disclosure, in the above... Figure 2 Based on the corresponding embodiments, the following may also be included:

[0040] The first chip performs a preset repair operation for the processing program corresponding to the second dataset; and in response to completing the preset repair operation, the first chip pulls the level of the second port high again.

[0041] In this embodiment, when the main control chip, i.e., the first chip, determines that a corresponding processing program is abnormal, it can control the execution of a preset repair operation to ensure smooth bidirectional data transmission with the third chip. This preset repair operation may include, but is not limited to, a restart operation to quickly restore data transmission.

[0042] Furthermore, in some optional implementations of the embodiments of this disclosure, the above... Figure 2 Based on the corresponding embodiments, the following may also be included: In response to the failure to acquire the first dataset and the detection of an anomaly in the processing program corresponding to the first dataset, the first chip, as the main control chip, can directly pull the level of the second port low. Further, the first chip performs a preset repair operation for the processing program corresponding to the first dataset; and in response to completing the preset repair operation, the first chip pulls the level of the second port high again.

[0043] Furthermore, in some optional implementations of the embodiments of this disclosure, the first chip can determine whether the processing program corresponding to the second dataset is abnormal by detecting whether there is an anomaly in the path from the first chip to the second chip for conversion and then to the third chip for reception. That is, it can determine whether the processing program is abnormal by detecting whether there is an abnormal path in the path corresponding to the first chip at the sending end, the path corresponding to the second chip at the intermediate conversion end, and the path corresponding to the third chip at the receiving end. Further, the first chip performs a preset repair operation on the processing program corresponding to the second dataset, which may include: performing a restart operation on the abnormal path, that is, by performing a targeted restart operation on the segmented path where only the anomaly exists, the impact of the fault can be effectively reduced and the recovery efficiency improved; or performing a restart operation on the entire path from the first chip through the second chip to the third chip, achieving more convenient fault recovery.

[0044] Furthermore, the first chip can determine whether the processing program corresponding to the first dataset is abnormal by detecting whether there is an anomaly in the path from the third chip to the second chip and back to the first chip for reception. Specifically, it determines whether the processing program is abnormal by checking whether there are any abnormal paths in the path corresponding to the third chip at the transmitting end, the path corresponding to the intermediate second chip, and the path corresponding to the first chip at the receiving end. Furthermore, the first chip performs a preset repair operation on the processing program corresponding to the first dataset, which may include: performing a restart operation on the abnormal path or performing a restart operation on the entire path from the first chip through the second chip to the third chip.

[0045] Furthermore, in some optional implementations of the embodiments of this disclosure, the following may also be included: the third chip, in response to detecting that the level of the second port has been pulled high again, restarts the processing program corresponding to the first dataset. In this implementation, when the third chip detects a signal indicating that the above-mentioned repair is complete and data transmission can continue, it may restart the processing program that sends the first dataset from the third chip to the first chip via the second chip, thereby achieving stability of bidirectional data transmission with the first chip.

[0046] In some optional implementations of the embodiments of this disclosure, in the above... Figure 1 Corresponding embodiments or Figure 2 Based on the corresponding embodiments, step 101 or step 201 above can be specifically executed as follows:

[0047] In response to detecting that the level of the first port is pulled high, the first chip initializes the first data transmission parameter corresponding to the first dataset and the second data transmission parameter corresponding to the second dataset; and in response to completing the initialization of the first data transmission parameter and the second data transmission parameter, the first chip pulls the level of the second port high.

[0048] In this embodiment, the second chip can indicate that it can work normally by pulling the level of its first port high, triggering the first chip to initialize the relevant parameters for bidirectional data transmission with the third chip, and after the initialization is completed, pulling the level of its second port high, thereby triggering the start of the bidirectional data transmission processing program between the first chip and the third chip, while reducing the computing power pressure on the third chip side.

[0049] Furthermore, in some optional implementations of any of the above embodiments of this disclosure, the first dataset may be data in Display Serial Interface (DSI) format when it is sent by the third chip, and may be data in Camera Serial Interface (CSI) format when it is converted by the second chip and arrives at the first chip.

[0050] Furthermore, in some optional implementations of any of the above embodiments of this disclosure, the second dataset may be in DSI format when it is sent by the first chip, and may be in CSI format when it is converted by the second chip and arrives at the third chip.

[0051] In some optional implementations of the embodiments of this disclosure, in the above... Figure 1 Corresponding embodiments or Figure 2 Based on the corresponding embodiments, the following may also be included:

[0052] The second chip responds to the detection that the first chip writes the first data transmission parameter and the second data transmission parameter into the register of the second chip, reuses the first port as the fourth port, and sets the level of the fourth port to low; and the second chip responds to the detection of a preset event, pulls the level of the fourth port high until the register detects that the level of the second port has been pulled high, and then pulls the level of the fourth port low again.

[0053] In this embodiment, reusing the first port as the fourth port can be understood as switching the function corresponding to the port. Specifically, the function of the port used to indicate that the second chip can work normally (corresponding to the first port) is switched to the function of indicating that the second chip has detected a preset event (corresponding to the fourth port). After the function switch, the first port is used as the fourth port. That is, the first port and the fourth port here refer to the same port performing different functions in different processes or stages. The fourth port can be a GPIO port, SPI, or I2C port.

[0054] Furthermore, in this embodiment, after initializing the first data transmission parameters corresponding to the first dataset and the second data transmission parameters corresponding to the second dataset, the first chip can write these parameters into the second chip for later use. Upon detecting that the first and second data transmission parameters have been written, the second chip reuses the first port used to indicate that it is functioning correctly, switching its function to indicate that the second chip has detected a preset event, thus using it as a fourth port. This port reuse saves port resources. Furthermore, since multiple chips are connected via hardware electronic component connectors with a fixed number of pins, port reuse significantly reduces the pin requirements of the connectors, improving the compatibility between the connectors and the chips. The fourth port is normally low when the preset event is not detected, for example, when the second chip detects the event. When the second chip detects the event, it can pull the fourth port high to indicate this. After determining through a register that the first chip has pulled the second port high again, the fourth port can be pulled low to reset its level.

[0055] In some optional implementations of the embodiments of this disclosure, in the above... Figure 1 Corresponding embodiments or Figure 2 Based on the corresponding embodiments, the first data transmission parameter includes a first preset input parameter and a first preset output parameter, and the second data transmission parameter includes a second preset input parameter and a second preset output parameter; further, the preset events include, but are not limited to, one of the following: the parameter corresponding to the data input from the third chip to the second chip does not match the first preset input parameter; the parameter corresponding to the data output from the second chip to the first chip does not match the first preset output parameter; the parameter corresponding to the data input from the first chip to the second chip does not match the second preset input parameter; the parameter corresponding to the data output from the second chip to the third chip does not match the second preset output parameter.

[0056] In this embodiment, when the first chip initializes its data transmission parameters, it may specifically involve input and output parameters corresponding to data transmission in different directions. This facilitates comprehensive monitoring of the input and output data of the second chip, ensuring the quality of bidirectional data transmission. The aforementioned preset event can be used to indicate that the second chip detects a discrepancy between the parameters corresponding to the input or output data and the corresponding data transmission parameters set during the initialization of the first chip. This can be achieved by promptly notifying the second chip by pulling the fourth port high. The data input from the third chip to the second chip and the data input from the first chip to the second chip can both be in the DSI format; the data output from the second chip to the first chip and the data output from the second chip to the third chip can both be in the CSI format.

[0057] Furthermore, in some optional implementations of any of the above embodiments of this disclosure, the first data transmission parameter and the second data transmission parameter include, but are not limited to, at least one of the following: image width, image height, and frame rate. In this embodiment, by initializing at least one of the image width, image height, and frame rate corresponding to the first dataset, and by initializing at least one of the image width, image height, and frame rate corresponding to the second dataset, the second chip can be used to effectively identify the aforementioned preset events.

[0058] More specifically, the discrepancy between the parameters corresponding to the data input from the third chip to the second chip and the first preset input parameters may include: the image width corresponding to the data input from the third chip to the second chip not matching the image width in the first preset input parameters, and / or the image height corresponding to the data input from the third chip to the second chip not matching the image height in the first preset input parameters.

[0059] The discrepancy between the parameters corresponding to the data output from the second chip to the first chip and the first preset output parameters may include: the image width corresponding to the data output from the second chip to the first chip not matching the image width in the first preset output parameters, and / or the image height corresponding to the data output from the second chip to the first chip not matching the image height in the first preset output parameters.

[0060] The discrepancy between the parameters corresponding to the data input from the first chip to the second chip and the second preset input parameters may include: the image width corresponding to the data input from the first chip to the second chip not matching the image width in the second preset input parameters, and / or the image height corresponding to the data input from the first chip to the second chip not matching the image height in the second preset input parameters.

[0061] The discrepancy between the parameters corresponding to the data output from the second chip to the third chip and the second preset output parameters may include: the image width corresponding to the data output from the second chip to the third chip not matching the image width in the second preset output parameters, and / or the image height corresponding to the data output from the second chip to the third chip not matching the image height in the second preset output parameters.

[0062] Furthermore, the aforementioned first preset input parameter, first preset output parameter, second preset input parameter, and second preset output parameter may include, but are not limited to, at least one of the following: image width, image height, and frame rate.

[0063] Furthermore, in some optional implementations of any of the above embodiments of this disclosure, the first chip, in response to the second chip pulling the level of the fourth port high, knows that the second chip has detected the preset event, and can determine that there is an anomaly in the processing program corresponding to the data. It can further pull the level of the second port low and execute the corresponding preset repair operation.

[0064] Furthermore, in some optional implementations of any of the above embodiments of this disclosure, the number of times the level of the fourth port is pulled high can be counted to realize the statistical recording of data anomalies, so as to provide an information source for subsequent fault diagnosis.

[0065] Furthermore, in some optional implementations of the embodiments of this disclosure, the following may also be included: the second chip, in response to detecting that the data of the first frame is not received from the frame header, performs a discard operation on the data of the first frame; and the second chip performs a discard operation on the data of the second frame corresponding to the preset event. In this embodiment, in order to ensure the quality of the bidirectional data transmission between the first chip and the third chip, if the received data is detected not to start from the frame header, the frame, i.e., the first frame, can be determined as an error frame and discarded. Similarly, the frame corresponding to the aforementioned detected preset event can also be determined as an error frame and discarded.

[0066] Furthermore, in some optional implementations of the embodiments of this disclosure, in order to ensure the quality of bidirectional data transmission between the first chip and the third chip, the second chip can be controlled to output data from the frame header when outputting the corresponding data to the first chip or the third chip.

[0067] Furthermore, in an optional implementation of this disclosure, in the above... Figure 1 Corresponding embodiments and Figure 2Based on the corresponding embodiments, the second chip can be integrated on the first chip. In this case, the first chip is mainly responsible for processing the first dataset, and the third chip is mainly responsible for acquiring the first dataset and processing the data of the in-vehicle infotainment system that supports a large number of upper-layer apps.

[0068] Furthermore, in another optional implementation of the embodiments of this disclosure, in the above... Figure 1 Corresponding embodiments and Figure 2 Based on the corresponding embodiments, the second chip can also be integrated on the third chip.

[0069] Furthermore, in some optional implementations of the embodiments of this disclosure, in the above... Figure 1 Corresponding embodiments and Figure 2 Based on the corresponding embodiments, the first chip and the third chip can be specifically implemented as system-on-chip (SoC) in the vehicle infotainment system to form a dual SoC architecture in the vehicle infotainment system; and the second chip can be specifically implemented as a field programmable gate array (FPGA) or a complex programmable logic device (CPLD).

[0070] To enhance understanding, this disclosure also provides a specific implementation scheme for a data transmission system 300, using a concrete application scenario as an example, such as... Figure 3 As shown, the data transmission system 300 includes an FPGA chip (corresponding to the second chip in the above embodiment) 301, a flash memory FLASH 302, a SOC-B chip (corresponding to the first chip in the above embodiment) 303, and a SOC-A chip (corresponding to the third chip in the above embodiment) 304 as an example. Specifically, it can be applied to advanced driving assistance scenarios. It requires transmitting map images from SOC-A to SOC-B, processing them using algorithms (such as cropping and sensor data aggregation), and then transmitting them back to SOC-A. Through this implementation scheme, DSI data can be converted to CSI data using FPGA, thereby converting display data into camera data and achieving data transmission.

[0071] In this configuration, the GPIO_EVENT pin of FPGA 301 (which can be a 1.8V pin) is low by default and is used as the GPIO_EVNET_READY pin (corresponding to the first port in the above embodiment). FPGA 301 can also load firmware from FLASH 302 via the Serial Peripheral Interface (SPI) pin (which can be a 1.8V pin). Once the firmware loading is complete and FPGA 301 is functioning normally, FPGA 301 will pull the GPIO_EVNET_READY pin high.

[0072] After receiving the signal that the GPIO_EVNET_READY pin is pulled high, the SOC-B 303 can configure the FPGA 301 through a two-wire serial bus (Inter-Integrated Circuit, I2C) pin (which can be a 1.8V pin). This configuration is responsible for initializing the parameters for bidirectional data transmission (which may include the image line length, image line count, and frame rate in both input and output directions). After configuration, the SOC-B 303 can write the bidirectional data transmission parameters into the registers in the FPGA 301 to notify the firmware to switch the function of the GPIO_EVENT pin from the GPIO_EVNET_READY pin to the GPIO_EVNET_INIT pin (corresponding to the fourth port in the above embodiment), thereby reusing the GPIO_EVNET pin and saving GPIO resources.

[0073] The GPIO_EVNET_INIT pin is normally low. When an event occurs in the FPGA 301 that the SOC-B 303 needs to process (such as when the real-time parameters of the input or output image do not match the parameters set during initialization), the GPIO_EVNET_INIT pin will be pulled high and held until the SOC-B 303 reads the pin status through the register and then switches from high to low to achieve a reset.

[0074] After initialization, SOC-B 303 pulls its GPIO_STATE pin (corresponding to the second port in the above embodiment) high and starts the A2B processing program, that is, starts the processing program from SOC-A 304 through FPGA 301 to SOC-B 303.

[0075] After detecting that the GPIO_STATE pin is high, SOC-A 304 starts the B2A processing program, that is, it starts the processing program from SOC-B 303 to SOC-A 304 via FPGA 301. Further, if SOC-A 304 fails to acquire the transmitted image due to an image output failure, it pulls its GPIO_ERR pin (corresponding to the third port in the above embodiment) high to notify SOC-B 303 that SOC-A 304 is currently unable to acquire the transmitted image. After receiving the notification, SOC-B 303 checks the status of the data transmission path (which may include paths corresponding to the sending end, receiving end, and intermediate conversion process) within FPGA 301 via I2C. If the data transmission status is abnormal, it pulls the GPIO_STATE pin low and performs a repair action. After repair, it pulls the GPIO_STATE pin high again. Furthermore, after the SOC-A 304 pulls the GPIO_ERR pin high, it monitors the GPIO_STATE pin status. If it detects that the GPIO_STATE pin is pulled low, it exits the processing program and restarts the processing program after detecting that the GPIO_STATE pin is pulled high.

[0076] Thus, by using a single-chip FPGA 301, bidirectional data transmission between SOC-B 303 and SOC-A 304 is achieved, saving hardware costs and hardware design complexity, and improving the stability of hardware-based data transmission. Furthermore, by using a serial notification design with low interaction costs, the fault path in case of failure is: FPGA 301 <-> board_b (carrying SOC-B 303) <-> board_a (carrying SOC-A 304). Board_b, directly connected to FPGA 301, is responsible for directly interacting with the chip's register information and handling specific fault detection. Board_a only uses the detection results, simplifying the communication process. Further troubleshooting of the problem log only requires checking the core log of board_b, improving maintenance efficiency and avoiding potential conflicts that could occur when two main controllers operate on the same chip simultaneously.

[0077] The SOC-A 304 and SOC-B 303 each have one GPIO pin, which can be connected to the 1.2V input pin of the FPGA301 via voltage divider resistors, serving as output control pins for the Mobile Industry Processor Interface (MIPI) (e.g., ...). Figure 3(See GPIO_MIPI_OUT_A and GPIO_MIPI_OUT_B). Specifically, when the pin is high, the FPGA 301 outputs MIPI-CSI format data; when the pin is low, the FPGA 301 stops outputting MIPI-CSI data. The output of MIPI-CSI data can be controlled by using registers or GPIO switches. After output begins, it needs to be output from the frame header.

[0078] The firmware loaded on FPGA 301 can read the real-time line length (image width), line count (image height), and frame rate in both the input and output directions through the FPGA 301's registers. It can discard the current frame if the line length or line count of the received MIPI-DSI data does not meet the corresponding preset values, or in other situations that may cause image abnormalities. Furthermore, it can notify the SOC via a GPIO interrupt when the line length or line count of the MIPI-DSI data does not meet the corresponding preset values. Further, the firmware supports individual resets or restarts of individual paths, as well as a chip-wide reset, minimizing the coupling between the two paths on a single chip. It also supports separate resets for the transceiver modules, employing a module-level and channel-isolated reset method to minimize the impact of faults and maximize recovery speed. Specifically, the SOC-B 303 can initiate a reset operation via the GPIO_RST pin (which can be a 1.8V pin).

[0079] Furthermore, the firmware can read the line length, line count, and MIPI (Cyclic Redundancy Check) error count from the registers. Since the FPGA301 only starts sending data after receiving the frame header, if the first received data after power-on does not start from the frame header, the erroneous frame is discarded. Furthermore, the firmware can support outputting patterns for convenient eye diagram measurement.

[0080] Further reference Figure 4 As an implementation of the methods shown in the above figures, this disclosure provides an embodiment of a data transmission system, which corresponds to the aforementioned method embodiment. This system can be applied to various electronic devices, such as in-vehicle infotainment systems in vehicles.

[0081] like Figure 4As shown, the screen projection data transmission system 400 of this embodiment may include: a first chip 401, a second chip 402 and a third chip 403.

[0082] The first chip 401 is configured to pull up the level of the second port 4011 in response to detecting that the level of the first port 4021 of the second chip 402 is pulled high, and to initiate a process in which the third chip 403 sends a first dataset to the first chip 401 via the second chip 402; and the third chip 403 is configured to initiate a process in response to detecting that the level of the second port 4011 is pulled high, and to initiate a process in which the first chip 401 sends a second dataset to the third chip 403 via the second chip 402; wherein the second dataset is determined based on the first dataset.

[0083] In this embodiment, the specific processing of the first chip 401, the second chip 402, and the third chip 403 in the data transmission system 400 and the resulting technical effects can be referred to respectively. Figure 1 The relevant descriptions of steps 101-103 in the corresponding embodiments will not be repeated here.

[0084] In some optional implementations of the embodiments of this disclosure, the first chip 401 is further configured to: in response to detecting that the level of the first port 4021 is pulled high, initialize the first data transmission parameter corresponding to the first dataset and the second data transmission parameter corresponding to the second dataset; and in response to completing the initialization of the first data transmission parameter and the second data transmission parameter, pull the level of the second port 4011 high.

[0085] In some optional implementations of the embodiments of this disclosure, the third chip 403 is further configured to pull the level of the third port (not shown in the figure) high in response to the failure to acquire the second dataset; the first chip 401 is further configured to pull the level of the second port 4011 low in response to detecting that the level of the third port is pulled high and detecting that the processing program corresponding to the second dataset is abnormal.

[0086] In this embodiment, the specific processing of the first chip 401 and the third chip 403 in the data transmission system 400 and the resulting technical effects can be referred to respectively. Figure 2 The relevant descriptions of steps 204-205 in the corresponding embodiments will not be repeated here.

[0087] In some optional implementations of the embodiments of this disclosure, the first chip 401 is further configured to: perform a preset repair operation for the processing program corresponding to the second dataset; and, in response to the completion of the preset repair operation, pull the level of the second port 4011 high again.

[0088] In some optional implementations of the embodiments of this disclosure, the third chip 403 is further configured to: stop executing the processing program corresponding to the first dataset in response to detecting that the level of the second port 4011 is pulled low; and restart the processing program corresponding to the first dataset in response to detecting that the level of the second port 4011 is pulled high again.

[0089] In some optional implementations of the embodiments of this disclosure, the second chip 402 is further configured to: in response to detecting that the first chip 401 writes the first data transmission parameter and the second data transmission parameter into the register of the second chip 402, reuse the first port 4021 as the fourth port and set the level of the fourth port to low; and in response to detecting a preset event, pull the level of the fourth port high until the register detects that the level of the second port 4011 has been pulled high, and then pull the level of the fourth port low again.

[0090] In some optional implementations of the embodiments of this disclosure, the first data transmission parameter includes a first preset input parameter and a first preset output parameter; the second data transmission parameter includes a second preset input parameter and a second preset output parameter; and the preset event includes one of the following: the parameter corresponding to the data input from the third chip 403 to the second chip 402 does not match the first preset input parameter; the parameter corresponding to the data output from the second chip 402 to the first chip 401 does not match the first preset output parameter; the parameter corresponding to the data input from the first chip 401 to the second chip 402 does not match the second preset input parameter; and the parameter corresponding to the data output from the second chip 402 to the third chip 403 does not match the second preset output parameter.

[0091] In some optional implementations of the embodiments of this disclosure, the second chip 402 is further configured to: in response to detecting that the data of the first frame has not been received from the frame header, perform a discard operation on the data of the first frame; and perform a discard operation on the data of the second frame corresponding to a preset event.

[0092] In some optional implementations of the embodiments of this disclosure, the first data transmission parameter and the second data transmission parameter mentioned above each include at least one of the following: image width, image height, and frame rate.

[0093] This embodiment exists as a system embodiment corresponding to the above method embodiment. The data transmission system 400 provided in this embodiment can set a second chip 402 between the first chip 401 and the third chip 403. The first chip 401 is responsible for monitoring whether the level of the first port 4021 of the second chip 402 is pulled high. In response to detecting that the level of the first port 4021 is pulled high, it controls and triggers bidirectional multi-chip data transmission between itself and the third chip 403 by pulling the level of its second port 4011 high. Specifically, the first chip 401, acting as the receiving end, initiates a processing program by the third chip 403 to transmit its first dataset to the first chip 401 via the second chip 402, and the third chip 403, acting as the receiving end, initiates a processing program by the first chip 401 to transmit its second dataset to the third chip 403 via the second chip 402. In this way, by using the single chip 402, bidirectional data transmission between multiple chips can be completed without the need for image encoding and decoding. This effectively controls hardware costs and hardware design complexity while reducing system load and improving the efficiency and stability of hardware-based data transmission.

[0094] Further reference Figure 5 Corresponding to the implementation of the system shown in the above embodiments, this disclosure provides an embodiment of an in-vehicle infotainment system, which is similar to the one described above. Figure 4 Corresponding to the system embodiment shown, this vehicle-mounted system can be applied to various vehicles.

[0095] like Figure 5 As shown, the vehicle infotainment system 500 in this embodiment may include: as described above. Figure 4 The technical effects of the data transmission system 400 shown in any of the corresponding embodiments can be referred to Figure 4 The relevant descriptions in the corresponding embodiments will not be repeated here.

[0096] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), system-on-a-chip (SoCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transferring data and instructions to the storage system, the at least one input device, and the at least one output device.

[0097] The program code used to implement the methods of this disclosure may be written in any combination of one or more programming languages. This program code may be provided to a processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus, such that when executed by the processor or controller, the program code causes the functions / operations specified in the flowcharts and / or block diagrams to be implemented. The program code may be executed entirely on a machine, partially on a machine, as a standalone software package partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0098] In the context of this disclosure, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0099] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device for displaying information to the user (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor); and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the computer. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0100] According to the technical solution of this disclosure embodiment, a second chip can be set between the first chip and the third chip. The first chip is responsible for monitoring whether the level of the first port of the second chip is pulled high. In response to detecting that the level of the first port is pulled high, the first chip controls and triggers bidirectional multi-chip data transmission between itself and the third chip by pulling the level of its second port high. Specifically, the first chip, as the receiving end, initiates a processing program for the third chip to transmit its first dataset to the first chip via the second chip, and the third chip, as the receiving end, initiates a processing program for the first chip to transmit its second dataset to the third chip via the second chip. In this way, by using the second chip as a single chip, bidirectional data transmission between multiple chips can be completed without the need for image encoding and decoding. This effectively controls hardware costs and hardware design complexity while reducing system load and improving the efficiency and stability of hardware-based data transmission.

[0101] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this disclosure can be achieved, and this is not a limitation herein; and the terms "first," "second," "third," "fourth," etc. (if present) in this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence, nor do they constitute a specific limitation.

[0102] It should also be understood that expressions such as "comprising," "including," "having," "containing," and / or "comprising" are open-ended rather than closed-ended expressions in this disclosure, indicating the presence of the stated features, elements, and / or components, but not excluding the presence of one or more other features, elements, components, and / or combinations thereof. Furthermore, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features, not just individual elements in the list. Additionally, when describing embodiments of this disclosure, the word "may" is used to mean "one or more embodiments of this disclosure." And the term "exemplary" is intended to refer to an example or illustration.

[0103] Unless otherwise specified, all terms used herein (including engineering and technical terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It should also be understood that, unless expressly stated in this disclosure, terms as defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or overly formalized meaning.

[0104] The specific embodiments described above do not constitute a limitation on the scope of protection of this disclosure. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A data transmission method, comprising: In response to detecting that the level of the first port of the second chip has been pulled high, the first chip pulls the level of the second port high. The first chip initiates a processing program that sends the first dataset to the first chip via the second chip from the third chip; In response to detecting that the level of the second port is pulled high, the third chip initiates a processing procedure to send a second dataset from the first chip to the third chip via the second chip; wherein the second dataset is determined based on the first dataset.

2. The method according to claim 1, wherein the first chip, in response to detecting that the level of the first port of the second chip is pulled high, pulls the level of the second port high, comprising: In response to detecting that the level of the first port is pulled high, the first chip initializes the first data transmission parameters corresponding to the first dataset and the second data transmission parameters corresponding to the second dataset. In response to completing the initialization of the first data transmission parameters and the second data transmission parameters, the first chip pulls the level of the second port high.

3. The method according to claim 2, further comprising: In response to the failure to acquire the second dataset, the third chip pulls the level of the third port high; In response to detecting that the level of the third port is pulled high and detecting an anomaly in the processing program corresponding to the second dataset, the first chip pulls the level of the second port low.

4. The method according to claim 3, further comprising: The first chip performs a preset repair operation for the processing program corresponding to the second dataset; as well as In response to completing the preset repair operation, the first chip pulls the level of the second port high again.

5. The method according to claim 4, further comprising: The third chip stops executing the processing program corresponding to the first dataset in response to detecting that the level of the second port is pulled low; as well as The third chip, in response to detecting that the level of the second port has been pulled high again, restarts the processing program corresponding to the first dataset.

6. The method according to claim 5, further comprising: In response to detecting that the first chip has written the first data transmission parameter and the second data transmission parameter into the register of the second chip, the second chip reuses the first port as the fourth port and sets the level of the fourth port to low. In response to detecting a preset event, the second chip pulls the level of the fourth port high until the register detects that the level of the second port has been pulled high, and then pulls the level of the fourth port low again.

7. The method according to claim 6, wherein, The first data transmission parameters include a first preset input parameter and a first preset output parameter, and the second data transmission parameters include a second preset input parameter and a second preset output parameter; as well as The preset event includes one of the following: The parameters corresponding to the data input from the third chip to the second chip do not match the first preset input parameters; The parameters corresponding to the data output from the second chip to the first chip do not match the first preset output parameters; The parameters corresponding to the data input from the first chip to the second chip do not match the second preset input parameters; The parameters corresponding to the data output from the second chip to the third chip do not match the second preset output parameters.

8. The method of claim 6, further comprising at least one of the following: In response to detecting that the data of the first frame was not received from the frame header, the second chip performs a data discard operation on the first frame; The second chip performs a discard operation on the data of the second frame corresponding to the preset event.

9. The method according to any one of claims 2 to 8, wherein, The first data transmission parameter and the second data transmission parameter each include at least one of the following: image width, image height, and frame rate.

10. A data transmission system, comprising: The first chip, the second chip, and the third chip; among them... The first chip is configured to pull up the level of the second port in response to detecting that the level of the first port of the second chip is pulled high, and to initiate a process for the third chip to send the first dataset to the first chip via the second chip; The third chip is configured to initiate a process for sending a second dataset from the first chip to the third chip via the second chip in response to detecting that the level of the second port is pulled high; wherein the second dataset is determined based on the first dataset.

11. A vehicle infotainment system, comprising: The data transmission system as described in claim 10.

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