Display device

Abstract

An embodiment discloses a display device, which includes: a display panel, the display panel including a display area and a non-display area having a plurality of pixels; a data driver that applies a data signal to the display panel; and a gating driver that applies a gating signal to the display panel, wherein each of the plurality of pixels includes a pixel circuit for driving a light-emitting element, and some of the plurality of switching elements of the pixel circuit are disposed in the non-display area.

Description

Technical Field

[0001] The embodiments relate to an apparatus, and in particular, for example, but not limited to, a display apparatus. Background Technology

[0002] Organic light-emitting display devices include self-emissive organic light-emitting diodes (hereinafter referred to as "OLEDs"), and have the advantages of fast response time, high luminous efficiency, high brightness, and wide viewing angle. In addition to fast response time, excellent luminous efficiency, excellent brightness, and excellent viewing angle, OLEDs also possess excellent contrast and color reproduction because black grayscale can be represented as true black.

[0003] The pixel circuit of an organic light-emitting display device includes an OLED, driving elements for driving the OLED, and multiple switching elements. In the pixel circuit, some switching elements are made of oxide thin-film transistors with excellent insulating properties, while other switching elements can be made using low-temperature polycrystalline silicon (LTPS) transistors to achieve fast response characteristics.

[0004] Polycrystalline silicon thin-film transistors require an excimer laser annealing (ELA) crystallization process to crystallize amorphous silicon. Therefore, when polycrystalline silicon thin-film transistors are present in both pixel circuits in the display area and gating drive circuits in the non-display area, the process size becomes larger due to the need to perform ELA processing on both the display and non-display areas. Summary of the Invention

[0005] The embodiments relate to providing a display device in which an excimer laser annealing (ELA) process is performed only in non-display areas.

[0006] The purpose of this disclosure is not limited to the foregoing, and other purposes not mentioned will be clearly understood by those skilled in the art from the following description.

[0007] A display device according to one embodiment of the present disclosure includes: a display panel including a display area and a non-display area having a plurality of pixels; a data driver that applies a data signal to the display panel; and a gating driver that applies a gating signal to the display panel, wherein each of the plurality of pixels includes a pixel circuit for driving a light-emitting element, and some of the plurality of switching elements in the pixel circuit are disposed in the non-display area.

[0008] The pixel circuit may include: a driving element comprising a first electrode connected to a first node, a gate electrode connected to a second node, and a third electrode connected to a third node; and a 1-1 switching element that connects a first driving voltage line connected to the pixel driving voltage to the first node, and the 1-1 switching element may be disposed in a non-display area.

[0009] The first driving voltage line can extend from the non-display area to the display area and can be connected to the first node.

[0010] The first driving voltage line can extend from the non-display area to the display area and can be commonly connected to the driving elements of multiple pixels.

[0011] The driving element can be an oxide thin-film transistor, and the 1-1 switching element can be a polysilicon thin-film transistor.

[0012] The display device may include 1-2 switching elements that connect a first node to a second driving voltage line connected to a pixel driving voltage, wherein the 1-2 switching elements may be disposed in each pixel circuit.

[0013] The 1-1 switching element can apply a pixel driving voltage to the first node in response to the first EM signal, and the 1-2 switching element can apply a pixel driving voltage to the first node in response to the 1-2 EM signal which is synchronized with the first EM signal and has an opposite phase.

[0014] 1-1 The switching element can be a polysilicon thin-film transistor, and 1-2 The switching element can be an oxide thin-film transistor.

[0015] The pixel circuit may include a second switching element that connects the second node to a reference voltage line; a third switching element that connects the anode of the light-emitting element to an initialization voltage line; and a fourth switching element that connects the second node to a data line, wherein the second and fourth switching elements may be oxide thin-film transistors.

[0016] The pixel circuit may include: a first capacitor, one end of which is connected to a second node and the other end of which is connected to a third node; a second capacitor, one end of which is connected to the third node and the other end of which is connected to a reference voltage line; and a sixth switching element that connects the second capacitor to the reference voltage line.

[0017] The gating driver may include a first light-emitting signal driver that applies a first EM signal to a 1-1 switching element and a third switching element.

[0018] The gating driver may include a second light-emitting signal driver that applies the 1-2 EM signal to the 1-2 switching element, and the 1-2 EM signal may have a phase opposite to that of the first EM signal.

[0019] The gating driver may include a third light-emitting signal driver that applies an EM signal to the 1-1 switching element and the 1-2 switching element. The third light-emitting signal driver may include a first output unit that outputs a first EM signal to the 1-1 switching element and a second output unit that outputs a 1-2 EM signal to the 1-2 switching element, and the 1-2 EM signal may have a phase opposite to that of the first EM signal.

[0020] A display device according to one aspect of the present disclosure includes: a display panel including a display area and a non-display area having a plurality of pixels; a data driver that applies a data signal to the display panel; and a gating driver that applies a gating signal to the display panel, wherein some switching elements of the pixel circuit of each of the plurality of pixels are disposed in the non-display area, all switching elements of the pixel circuit disposed in the display area are oxide thin-film transistors, and the switching elements of the pixel circuit disposed in the non-display area and the switching elements of the gating driver are polysilicon thin-film transistors.

[0021] Other systems, methods, features, and advantages will be apparent to those skilled in the art upon examination of the following figures and detailed description. All such additional systems, methods, features, and advantages are intended to be included within this specification, within the scope of this disclosure, and protected by the appended claims. Nothing in this section should be construed as limiting those claims. Further aspects and advantages are discussed below in conjunction with embodiments of this disclosure.

[0022] It should be understood that both the foregoing general description and the following detailed description are exemplary and illustrative, and are intended to provide further explanation of the claimed inventive concept. Attached Figure Description

[0023] The above and other objects, features, and advantages of this disclosure will become more apparent to those skilled in the art from the detailed description of exemplary embodiments thereof with reference to the accompanying drawings, in which:

[0024] Figure 1 This is a diagram illustrating a display device according to one embodiment of the present disclosure;

[0025] Figure 2 This is a schematic diagram illustrating a display panel according to one embodiment of the present disclosure.

[0026] Figure 3 This is a circuit diagram illustrating a pixel circuit according to one embodiment of the present disclosure;

[0027] Figure 4 This is a circuit diagram illustrating a pixel circuit according to another embodiment of the present disclosure;

[0028] Figure 5 This is a diagram illustrating the brightness deviation of a pixel circuit according to another embodiment of the present disclosure;

[0029] Figure 6 This is a waveform diagram of a pixel circuit according to another embodiment of the present disclosure;

[0030] Figure 7A This is a diagram showing the current flowing in the pixel circuit during the initialization operation;

[0031] Figure 7B This is a diagram showing the current flowing in the pixel circuit during the sampling operation;

[0032] Figure 7C It is a diagram showing the current flowing in the pixel circuit during a data write operation;

[0033] Figure 7D It is a diagram showing the current flowing in the pixel circuit during light emission operation;

[0034] Figure 8 This is a diagram illustrating a gating driver according to one embodiment of the present disclosure;

[0035] Figure 9 This is according to one embodiment of the present disclosure. Figure 8 Example of modification;

[0036] Figure 10 This is a diagram illustrating a gating driver according to another embodiment of the present disclosure;

[0037] Figure 11 This is a diagram illustrating a gating driver according to yet another embodiment of the present disclosure;

[0038] Figure 12 This is a diagram illustrating a light-emitting signal driver according to one embodiment of the present disclosure;

[0039] Figure 13 This is a waveform diagram of a light-emitting signal driver according to one embodiment of the present disclosure;

[0040] Figure 14 This is a diagram illustrating a light-emitting signal driver according to one embodiment of the present disclosure;

[0041] Figure 15 This is a waveform diagram of a light-emitting signal driver according to one embodiment of the present disclosure;

[0042] Figure 16 This is a diagram illustrating a light-emitting signal driver according to one embodiment of the present disclosure; and

[0043] Figure 17This is a waveform diagram of a light-emitting signal driver according to one embodiment of the present disclosure.

[0044] Throughout the accompanying drawings and detailed description, unless otherwise stated, the same reference numerals shall be construed as referring to the same elements, features, and structures. For clarity, illustration, and convenience, the relative sizes and depictions of these elements may be exaggerated. Detailed Implementation

[0045] Reference will now be made in detail to embodiments of this disclosure, examples of which are illustrated in the accompanying drawings. In the following description, detailed descriptions of well-known functions or configurations relevant to this document will be omitted or may be briefly discussed where it is determined that such detailed descriptions would unnecessarily obscure the essential points of the inventive concept. The described process steps and / or order of operations are exemplary; however, the order of steps and / or operations is not limited to the order set forth herein and may be varied as is known in the art, except for steps and / or operations that must occur in a specific order. The same reference numerals always refer to the same elements. The names of the corresponding elements used in the following explanation may be chosen solely for the convenience of writing the specification and may therefore differ from those used in actual products.

[0046] The advantages and features of this specification, as well as methods of implementing them, will become apparent from the following detailed description of embodiments taken in conjunction with the accompanying drawings. However, this specification is not limited to the embodiments described below, and can be implemented in various different forms. The embodiments are provided merely to fully disclose this specification and to fully convey the scope of this disclosure to those skilled in the art.

[0047] Since the shapes, sizes, proportions, angles, numbers, etc., disclosed in the accompanying drawings for describing the embodiments of this specification are merely exemplary, this specification is not limited to the items shown in the drawings. Throughout the specification, the same reference numerals indicate the same components. Furthermore, in describing this specification, detailed descriptions of related known technologies will be omitted where it is determined that such detailed descriptions may unnecessarily obscure the gist of this specification. When using terms such as "set up," "comprise," "have," "compose of," etc., as mentioned in this specification, other components may be added unless only "only" is used. Unless otherwise expressly stated, components indicated in the singular may also include those in the plural.

[0048] Any implementation described in this article as an "example" is not necessarily to be interpreted as preferred or advantageous over other implementations.

[0049] When interpreting a component, even without a separate explicit description of the error tolerance, the component is interpreted as including the error tolerance.

[0050] When describing positional relationships, for example, when the positional relationship between two components is described as "above", "on top of", "below", "adjacent", etc., one or more other components may be located between the two components unless "closely to" or "directly" is used.

[0051] In the description of time relationships, when the time relationship is described as "after", "followed", "then", "before", etc., non-continuous cases may also be included unless "immediately" or "directly" is used.

[0052] Terms such as first, second, A, B, (a), and (b) may be used to describe components of this specification. These terms are used only for the purpose of distinguishing one component from another, and the nature, order, sequence, etc., of the corresponding components are not limited by these terms. When a component is described as “connected,” “linked,” or “coupled” to another component, it should be understood that, unless otherwise expressly stated, the component may be directly connected or linked to other components, but another component may be “inserted” between components that may be indirectly connected or linked to each other.

[0053] "At least one" should be understood as a combination of one or more related components. For example, the term "at least one of the first component, the second component, and the third component" includes not only the first component, the second component, or the third component, but also all combinations of two or more of the first component, the second component, and the third component.

[0054] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which the example embodiments pertain. It should also be understood that terms such as those defined in common dictionaries should be interpreted as having a meaning consistent with, for example, their meaning in the context of the relevant field, and should not be interpreted in an idealized or overly formal sense unless explicitly defined herein. For example, as one of ordinary skill in the art will understand, the terms “component” or “unit” can be applied to, for example, a single circuit or structure, an integrated circuit, a computational block of a circuit device, or any structure configured to perform the described functions.

[0055] Features of the various embodiments described herein can be combined with each other in part or in whole, and technically, various links and operations are possible, and embodiments can be implemented independently of each other or together in a related relationship.

[0056] In the following description, embodiments of this specification will be described with reference to the accompanying drawings and embodiments. For ease of description, the components shown in the drawings are at different scales than actual scales, and are therefore not limited to the scales shown in the drawings.

[0057] In the following, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0058] Figure 1 This is a diagram illustrating a display device according to one embodiment of the present disclosure.

[0059] Reference Figure 1 The display device according to the embodiments of the present disclosure includes a display panel PNL and a display panel driving circuit.

[0060] The display area AA of the display panel PNL includes a pixel array that displays pixel data of the input image. The pixel data of the input image is displayed in the pixels of the pixel array. The pixel array includes multiple data lines DL, multiple gate lines GL intersecting the data lines DL, and pixels arranged in a matrix. In addition to the matrix arrangement, the arrangement of pixels can be formed in various forms such as pixels sharing the same color of light, stripes, diamonds, etc.

[0061] When the resolution of the pixel array is n*m, the pixel array can include n pixel columns and m pixel lines L1 to Lm intersecting the pixel columns. Pixel lines include pixels arranged along a first direction. Pixel columns include pixels arranged along the first direction. A horizontal time period 1H is obtained by dividing a frame time period by the number of m pixel lines L1 to Lm. Pixel data is written to the pixels of a pixel line within a horizontal time period 1H.

[0062] Each pixel comprises two or more subpixels 101 to achieve color. For example, each pixel may be divided into red subpixels, green subpixels, and blue subpixels. Each pixel may also include a white subpixel. Each subpixel 101 may include pixel circuitry. Pixel circuitry may include pixel electrodes, one or more thin-film transistors (TFTs), and capacitors. Pixel circuitry is connected to a data line DL and a gate line GL.

[0063] A touch sensor can be mounted on the display panel 100 to realize a touchscreen. Touch input can be sensed using a separate touch sensor or by pixels. The touch sensor can be implemented as an on-cell type sensor mounted on the screen of the display panel, an added-type sensor, or an in-cell type touch sensor built into a pixel array.

[0064] The display panel driving circuit can write the input image data to the pixels of the display panel PNL under the control of the timing controller 130. The display panel driving circuit may include a data driver 110, a gating driver 120, a timing controller 130 for controlling the operating timing of the drivers 110 and 120, a level shifter 140 connected between the timing controller 130 and the gating driver 120, and a power supply unit 150.

[0065] Data driver 110 converts pixel data of the input image, received from timing controller 130 as a digital signal for each frame, into analog gamma-compensated voltages and outputs data signals Vdata1 to Vdata3. The data signals Vdata1 to Vdata3 output from data driver 110 are provided to data line DL. Data driver 110 may use a digital-to-analog converter (hereinafter referred to as "DAC") to output data signals Vdata1 to Vdata3, which converts the digital signal into analog gamma-compensated voltages.

[0066] The display panel driving circuit may also include a demultiplexer array 112 disposed between the data driver 110 and the data line DL.

[0067] The demultiplexer array 112 can sequentially connect one channel of the data driver 110 to multiple data lines DL to distribute the data signal output from one channel of the data driver 110 to the daily data lines DL in a time-division manner, thereby reducing the number of channels of the data driver 110.

[0068] The gating driver 120 may be formed in a border area BZ on the display panel 100 where no image is displayed, or at least a portion of the gating driver 120 may be disposed in the pixel array. The gating driver 120 receives a clock signal from the level shifter 140 and outputs a gating signal GATE. The gating signal GATE is provided to the gating line GL.

[0069] Gating signals GATE1 to GATE3 applied to the gating line GL turn on the switching elements of sub-pixel 101 to select pixels charged with voltages of data signals Vdata1 to Vdata3. The switching elements of sub-pixel 101 are turned on or off in response to gating signals GATE1 to GATE3. The gating driver 120 uses a shift register to shift the gating signals.

[0070] The timing controller 130 can control the operation timing of the display panel drivers 110 and 120 at a frame frequency of input frame frequency × i (i is a positive integer greater than 0) Hz by multiplying the input frame frequency by i.

[0071] The timing controller 130 receives pixel data of the input image and timing signals synchronized with the pixel data from the host system 200. The pixel data of the input image received in the timing controller 130 is a digital signal. The timing controller 130 sends the pixel data to the data driver 110. The timing signals include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a clock signal CLK, and a data enable signal DE. Since the vertical and horizontal time periods can be determined by counting the data enable signal DE, the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync can be omitted. The data enable signal DE can have a period of one horizontal time period 1H.

[0072] The timing controller 130 can generate data timing control signals for controlling the data driver 110, gating timing control signals for controlling the gating driver 120, and control signals for controlling the switching elements of the demultiplexer array 112, etc., based on timing signals received from the host system 200. The gating timing control signals can be generated as clocks at digital signal voltage levels.

[0073] The host system 200 can be any of a television (TV), set-top box, navigation system, personal computer (PC), home theater, mobile system, and wearable system. In mobile and wearable devices, the data driver 110, timing controller 130, level shifter 140, etc., can be integrated into a single driver integrated circuit (IC). In mobile systems, the host system 200 can be implemented as an application processor (AP).

[0074] The clock output from level shifter 140 oscillates between a gating high voltage VGH and a gating low voltage VGL, and is supplied to gating driver 120 via clock line CL. The clock output from level shifter 140 can be applied to at least one of demultiplexer array 112, gating driver 120, and touch sensor driver.

[0075] The power supply unit 150 generates the voltage required to drive the pixel array and display panel driving circuitry of the display panel 100 using a DC-DC converter. The DC-DC converter may include a charge pump, regulator, buck converter, boost converter, buck-boost converter, etc.

[0076] The power supply unit 150 can adjust the DC input voltage from the host system 200 to generate a DC voltage (e.g., gamma reference voltage VGMA, gating high voltage VGH, gating low voltage VGL, pixel common voltage, etc.). The gamma reference voltage VGMA can be provided to the data driver 110. The gamma reference voltage VGMA can be divided by grayscale by the voltage divider circuit of the data driver 110 and provided to the DAC of the data driver 110. The power supply unit 150 can generate a constant voltage (e.g., common voltage Vcom, pixel drive voltage EVDD, pixel base voltage EVSS, etc.) commonly applied to the pixel.

[0077] Figure 2 A diagram of a display panel according to one embodiment of the present disclosure.

[0078] Reference Figure 2 In the display panel PNL according to the embodiment, some switching elements SW1 constituting the pixel circuit provided in the display area AA can be provided in the non-display area NA together with the gating driver 120. The switching elements SW1 of the pixel circuit provided in the non-display area NA can be low-temperature polycrystalline silicon (LTPS) thin-film transistors (hereinafter referred to as "polycrystalline silicon thin-film transistors").

[0079] Polycrystalline silicon thin-film transistors offer advantages such as fast response time and excellent temperature and light stability. However, excimer laser annealing (ELA) is required to form polycrystalline silicon. ELA is one of the most widely used crystallization methods and can be used to form polycrystalline silicon by irradiating it with pulsed ultraviolet (UV) light.

[0080] According to this embodiment, since the polysilicon thin-film transistors (TFTs) are located in the non-display area NA among the switching elements constituting the pixel circuit, it is advantageous to perform the excimer laser annealing process only in the non-display area NA. When polysilicon TFTs are present in the display area AA, the laser annealing process must be performed on the entire panel, resulting in increased manufacturing costs. Furthermore, since polysilicon TFTs and oxide TFTs are located together in the pixel, the process complexity increases.

[0081] The switching element SW1, located in the non-display area NA, can be a switching element that applies a pixel driving voltage. However, the implementation is not limited to this. Depending on the driving characteristics, the pixel circuit may include multiple polysilicon thin-film transistors, and these polysilicon thin-film transistors may be located in the non-display area NA.

[0082] Figure 3 This is a circuit diagram illustrating a pixel circuit according to one embodiment of the present disclosure.

[0083] Reference Figure 3 The adjacent first pixel circuit PIC1 and second pixel circuit PIC2 may each include a light-emitting element EL, a driving element DR that provides current to the light-emitting element EL, multiple switching elements M1, M2, M3, M4, M5 and M6, a first capacitor Cst and a second capacitor Ca.

[0084] In the pixel circuit, the driving element DR and the second to sixth switching elements M2, M3, M4, M5, and M6 can be implemented as n-type oxide thin-film transistors, and the first switching element M1 can be implemented as a p-type polysilicon thin-film transistor. Therefore, the driving element DR and the second to sixth switching elements M2, M3, M4, M5, and M6 can be turned on in response to the selection of a high voltage VGH, while the first switching element M1 can be turned on in response to the selection of a low voltage VGL.

[0085] The first switching element M1 can be disposed in the non-display area NA (GIP area within the panel), and the first driving voltage line PL1 can be connected to the driving element DR. The driving element DR of the first pixel circuit PIC1 and the driving element DR of the second pixel circuit PIC2 can be commonly connected to the first driving voltage line PL1 through the first switching element M1. Therefore, when the first switching element M1 is turned on, the pixel driving voltage EVDD can be applied to the first pixel circuit PIC1 and the second pixel circuit PIC2. According to this embodiment, since the first switching element M1 is disposed in the non-display area NA and the pixel driving voltage EVDD is provided to multiple pixel circuits, the first switching element M1 can be omitted in each pixel circuit.

[0086] Constant voltages, such as pixel drive voltage EVDD, low-potential power supply voltage ELVSS, reference voltage Vref, and initialization voltage Vinit, are applied to the pixel circuit. The light-emitting element EL can be implemented as an organic light-emitting diode (OLED). The OLED may include an organic compound layer formed between the anode and cathode. The organic compound layer may include a hole injection layer HIL, a hole transport layer HTL, an emissive layer EML, an electron transport layer ETL, an electron injection layer EIL, etc., but this disclosure is not limited thereto. The anode of the light-emitting element EL can be connected to a fourth node n4, and the cathode of the light-emitting element EL can be connected to a VSS node to which the low-potential power supply voltage ELVSS is applied.

[0087] When a voltage is applied to the anode and cathode of an OLED, excitons are formed as holes passing through the hole transport layer (HTL) and electrons passing through the electron transport layer (ETL) move to the emissive layer (EML). In this case, visible light can be emitted from the emissive layer (EML).

[0088] The driving element DR may include a gate electrode connected to the second node DRG, a first electrode connected to the first node DRD, and a third electrode connected to the third node DRS. Therefore, the voltage applied to each electrode of the driving element DR may be the same as the voltages of the first to third nodes DRD, DRG, and DRS.

[0089] The first capacitor Cst may have one end connected to the second node DRG and the other end connected to the third node DRS. The first capacitor Cst may store the gate-source voltage Vgs of the driving element DR. The second capacitor Ca may have one end connected to the third node DRS and the other end connected to the reference voltage line VL1.

[0090] The transmission rate of the data voltage Vdata at the gate-source voltage Vgs of the driving element DR can be determined based on the capacitance ratio of the first capacitor Cst and the second capacitor Ca. The capacitance values ​​of the first capacitor Cst and the second capacitor Ca can be appropriately selected based on the voltage range of the data voltage Vdata and the driving characteristics of the display panel PNL.

[0091] During the initialization operation (INIT) and data write operation (DW), the first switching element M1 can be turned off in response to the high gate voltage VGH of the first EM signal EM1, and can block the current path between the first drive voltage line PL1, to which the pixel drive voltage is applied, and the first node DRD. The first switching element M1 can be turned on in response to the low gate voltage VGL of the first EM signal EM1, and can connect the first drive voltage line PL1 to the first node DRD during the sampling operation (SMPL) and emission operation (EMI). The first switching element M1 may include a gate electrode to which the first EM signal EM1 is applied, a first electrode connected to the first drive voltage line PL1, and a second electrode connected to the first node DRD.

[0092] The second switching element M2 can be turned on in response to the high gate voltage VGH of the second scan signal SC2, and can provide a reference voltage Vref to the second node DRG during the initialization operation INIT and the sampling operation SMPL. The second switching element M2 may include a gate electrode to which the second scan signal SC2 is applied, a first electrode connected to a reference voltage line VL1 to which the reference voltage Vref is applied, and a second electrode connected to the second node DRG.

[0093] The third switching element M3 can be turned on in response to the high gate voltage VGH of the first EM signal EM1, and can apply the initialization voltage Vinit to the fourth node n4 during the initialization operation INIT and the anode reset operation AR. The third switching element M3 may include a gate electrode to which the third scan signal SC3 is applied, a first electrode connected to the fourth node n4, and a second electrode connected to the initialization voltage line VL2 to which the initialization voltage Vinit is applied.

[0094] The fourth switching element M4 can be turned on in response to the high gate voltage VGH of the first scan signal SC1, and can provide a data voltage Vdata to the second node DRG during the data write operation DW. The fourth switching element M4 may include a gate electrode to which the first scan signal SC1 is applied, a first electrode connected to a data line DL to which the data voltage Vdata is applied, and a second electrode connected to the second node DRG.

[0095] The fifth switching element M5 can be turned off in response to the low gate voltage VGL of the second EM signal EM2, and can block the current path between the third node DRS and the fourth node n4 during the sampling operation SMPL and the data write operation DW. The fifth switching element M5 can be turned on in response to the high gate voltage VGH of the second EM signal EM2, and can form a current path between the driving element DR and the light-emitting element EL during the initialization operation INIT and the light-emitting operation EMI. The fifth switching element M5 may include a gate electrode to which the second EM signal EM2 is applied, a first electrode connected to the third node DRS, and a second electrode connected to the fourth node n4.

[0096] The sixth switching element M6 can be turned on in response to the gating high voltage VGH of the third scan signal SC3, and can apply the reference voltage Vref to the second capacitor Ca during the sampling operation SMPL and the data writing operation DW.

[0097] This embodiment illustrates a pixel circuit consisting of seven transistors and two capacitors, but the embodiments of this disclosure are not limited thereto. For example, the pixel circuit may consist of four transistors, five transistors, or eight transistors, and may have one or two capacitors. That is, the pixel circuit of this embodiment can be applied to any pixel circuit including oxide thin-film transistors and polysilicon thin-film transistors, wherein the polysilicon thin-film transistors are disposed in the non-display area NA.

[0098] Figure 4 This is a circuit diagram illustrating a pixel circuit according to another embodiment of the present disclosure. Figure 5 This is a diagram showing the brightness deviation of a pixel circuit according to another embodiment of the present disclosure.

[0099] Reference Figure 4 According to the embodiment, the pixel circuit may include a 1-1 switching element M11 and a 1-2 switching element M12 connected to the pixel driving voltage EVDD. The 1-1 switching element M11 may be disposed in the non-display area NA and connected to the pixel circuit in the display area AA. The 1-2 switching element M12 may be disposed in each pixel circuit in the display area AA and may apply the pixel driving voltage EVDD to the driving element DR.

[0100] According to the implementation, the first driving voltage line PL1 can be commonly connected to the first node DRD of each driving element DR in the first pixel circuit PIC1 and the second pixel circuit PIC2. Furthermore, the second driving voltage line PL2 can be connected to each driving element DR in the first pixel circuit PIC1 and the second pixel circuit PIC2.

[0101] Switching element M11 (1-1) can be a p-type polysilicon thin-film transistor, and switching element M12 (1-2) can be an n-type oxide thin-film transistor. Switching element M11 (1-1) can apply a pixel driving voltage EVDD to driving element DR in response to a first EM signal EM1. Switching element M12 (1-2) can respond to a 1-2 EM signal, which is the inverted signal of the first EM signal EM1. The pixel driving voltage EVDD is applied to the driving element DR.

[0102] According to this embodiment, since the pixel driving voltage EVDD can be applied to the driving element DR of each pixel circuit through the 1-2 switching element M12, the RC delay can be reduced according to the pixel position. Since the 1-2 switching element M12 is an oxide thin-film transistor, stress may occur, and the threshold voltage may change due to the relatively high pixel driving voltage EVDD. However, according to this embodiment, since the pixel driving voltage EVDD is applied in an auxiliary manner through the 1-1 switching element M11, it has the advantage of being able to stably maintain the output characteristics of the pixel driving voltage EVDD.

[0103] Reference Figure 5 When comparing the brightness deviation measurement results SL1 with both 1-1 and 1-2 switching elements and SL2 with only 1-2 switching elements, it can be seen that the brightness deviation is smaller when both 1-1 and 1-2 switching elements are present. The X-axis is the measurement result of the threshold voltage fluctuation when the threshold voltage change is '0', and the Y-axis is the measurement result of the brightness change based on brightness (0.0%) when the threshold voltage change is '0'.

[0104] When the threshold voltage of the 1-2 switching element M12 changes due to stress, the backlash deviation of the pixel driving voltage caused by the threshold voltage fluctuation of the 1-2 switching element M12 can be reduced by the 1-1 switching element M11. Therefore, the brightness deviation can be reduced by reducing the fluctuation of the DRS node.

[0105] Figure 6 This is a waveform diagram illustrating a driving method for a pixel circuit according to another embodiment of the present disclosure. Figures 7A to 7D This is a diagram showing the current flowing in the pixel circuit during a refresh operation.

[0106] Reference Figure 6 and Figure 7A During the initialization operation INIT, the second switch element M2, the third switch element M3, and the fifth switch element M5 can be turned on. During the initialization operation INIT, the 1-1 switch element M11, the 1-2 switch element M12, and the fourth switch element M4 can be turned off.

[0107] Reference Figure 6 and Figure 7B During the sampling operation SMPL, switching elements M11 (1-1), M12 (1-2), M2 (second), and M6 (sixth) can be turned on, while other switching elements M3, M4, and M5 can be turned off. During SMPL, when the voltage at the third node DRS rises and thus the gate-source voltage Vgs of the driving element DR reaches the threshold voltage Vth, the driving element DR can be turned off. When SMPL ends, the voltages at the master node are DRD = EVDD, DRG = Vref, and DRS = Vref - Vth. Therefore, when SMPL ends, the gate-source voltage Vgs of the driving element DR is Vgs = Vth. The sampling threshold voltage Vth of the driving element DR can be charged to the first capacitor Cst.

[0108] Reference Figure 6 and Figure 7C During the data write operation (DW), the pixel data voltage Vdata can be applied to the second node DRG because the fourth switch element M4 and the sixth switch element M6 are turned on. In this case, the other switch elements M11, M12, M2, M3, and M5 can be turned off. When the data write operation (DW) ends, the voltage of the master node can be changed to DRD = EVDD, DRG = Vdata, and DRS = Vref - Vth + C' × (Vdata - Vref). Here, C' = Cst / (Cst + Ca).

[0109] Reference Figure 6 and 7DDuring the EMI period of the light-emitting operation, switching elements M11 (1-1), M12 (1-2), and M5 (5-5) can be turned on, while other switching elements M2, M3, M4, and M6 can be turned off. According to this embodiment, during the EMI period of the light-emitting operation, the pixel driving voltage can be applied simultaneously through switching elements M11 (1-1) and M12 (1-2).

[0110] Figure 8 This is a diagram illustrating a strobe driver according to one embodiment of the present disclosure. Figure 9 yes Figure 8 Example of modification. Figure 10 This is a diagram illustrating a strobe driver according to another embodiment of the present disclosure. Figure 11 This is a diagram illustrating a gating driver according to yet another embodiment of the present disclosure.

[0111] Reference Figure 8 Based on the display area AA, the first strobe driver 121 can be set on the left and the second strobe driver 122 can be set on the right. Figure 8 It is connected to Figure 3 The block diagram of the gating driver for the pixel circuit.

[0112] The first gating driver 121 may include a first EM region EMB1, a first scan region SCB1, and a first switch region ELT. The first switch region ELT may be a region where a first switching element M1 is arranged. The first EM region EMB1 can apply an EM signal to the first switch region ELT. The first scan region SCB1 can apply a first scan signal to the display region AA. The first EM region EMB1, the first scan region SCB1, and the first switch region ELT can be set from outside the display device in one step in the direction in which the display region AA is set.

[0113] The second gating driver 122 may include a third scan area SCB3, a second EM area EMB2, and a second scan area SCB2. The third scan area SCB3, the second EM area EMB2, and the second scan area SCB2 may be sequentially arranged from the outside of the display device in the direction of setting the display area AA.

[0114] In this embodiment, the first scan signal to the third scan signal and the second EM signal can be signals provided to oxide thin-film transistors included in the pixel circuit. The first EM signal can be a signal provided to a first switching element M1 disposed in the non-display area NA. The link area Link can be disposed between the display area AA and the gating driver 120. The reference voltage Vref line, the initialization voltage Vinit line, etc., can be disposed in the link area Link. (See reference...) Figure 9In a dual-feed structure where the first switching element M1 is located on both sides of the display area, the first switching area ELT and the first EM area EMB1 can be located on both sides of the display area AA.

[0115] Figure 10 It is connected to Figure 4 A block diagram of the gating driver for the pixel circuit. (Refer to...) Figure 10 The first gating driver 121 may include a first EM region EMB1, a 1-2 EM region EMB12, a first scan region SCB1, and a first switching region ELT. The first EM region EMB1 can apply EM signals to the first switching region ELT. The 1-2 EM region EMB12 can apply 1-2 EM signals to 1-2 switching elements M12 in the display region AA. The 1-2 EM signals may have an opposite phase to the first EM signal.

[0116] The first scan area SCB1 can apply the first scan signal to the display area AA. The first EM area EMB1, 1-2EM area EMB12, the first scan area SCB1, and the first switch area ELT can be sequentially arranged from the outside of the display device in the direction of setting the display area AA.

[0117] The second gating driver 122 may include a third scan area SCB3, a second EM area EMB2, and a second scan area SCB2. The third scan area SCB3, the second EM area EMB2, and the second scan area SCB2 may be sequentially arranged from the outside of the display device in the direction of setting the display area AA.

[0118] In this embodiment, the first scan signal to the third scan signal and the second EM signal can be signals provided to the driving element DR, the 1-2 switching element M12, and the second to sixth switching elements M2, M3, M4, M5, and M6 included in the pixel circuit. The first EM signal can be a signal provided to the 1-1 switching element M11 disposed in the non-display area NA.

[0119] Figure 11 It is connected to Figure 4 A block diagram of the gating driver for the pixel circuit. (Refer to...) Figure 11 The first gating driver 121 may include a 1-1 EM region EMB11, a first scan region SCB1, and a first switch region ELT. The 1-1 EM region EMB11 can apply a first EM signal to a 1-1 switch element M11 in the first switch region ELT, and apply a 1-2 EM signal to a 1-2 switch element M12 in the display region AA. The 1-2 EM signal may have a phase opposite to the first EM signal.

[0120] The first scan area SCB1 can apply the first scan signal to the display area AA. 1-1 The EM area EMB11, the first scan area SCB1, and the first switch area ELT can be sequentially arranged from the outside of the display device in the direction in which the display area AA is set.

[0121] The second gating driver 122 may include a third scan area SCB3, a second EM area EMB2, and a second scan area SCB2. The third scan area SCB3, the second EM area EMB2, and the second scan area SCB2 may be sequentially arranged from the outside of the display device in the direction of setting the display area AA.

[0122] In this embodiment, the first scan signal to the third scan signal and the second EM signal may be signals provided to the oxide thin-film transistors included in the pixel circuit. The first EM signal may be a signal provided to the 1-1 switching element M11 disposed in the non-display area NA.

[0123] Figure 12 This is a diagram illustrating a light-emitting signal driver according to one embodiment of the present disclosure. Figure 13 This is a waveform diagram of a light-emitting signal driver according to one embodiment of the present disclosure.

[0124] The light-emitting signal driver EMC1 may include first transistors to sixth transistors T1, T2, T3, T4, T5, and T6, a third capacitor CQ, and a fourth capacitor CQB. In the first transistor T1, the first electrode may be connected to the input terminal of the start signal GVST, the gate electrode may be connected to the power supply line of the first clock signal GCLK1, and the second electrode may be connected to the third node Q2.

[0125] In the second transistor T2, the first electrode can be connected to the third node Q2, the gate electrode can be connected to the power supply line that selects the low voltage VGL, and the second electrode can be connected to the first node Q.

[0126] In the third transistor T3, the first electrode can be connected to the power supply line of the gating low voltage VGL, the gate electrode can be connected to the first node Q, and the second electrode can be connected to the second node QB. The third transistor T3 can be turned on by the voltage of the first node Q and can apply the gating low voltage VGL to the second node QB.

[0127] In the fourth transistor T4, the first electrode can be connected to the second node QB, the gate electrode can be connected to the third node Q2, and the second electrode can be connected to the power supply line of the gating high voltage VGH. The fourth transistor T4 can be turned on by the voltage of the third node Q2, and the gating high voltage VGH can be applied to the second node QB.

[0128] In the fifth transistor T5, since the first electrode is connected to the power supply line of the gate low voltage VGL, the gate electrode is connected to the first node Q, and the second electrode is connected to the output terminal OUT, the fifth transistor T5 can be turned on or off according to the voltage of the first node Q, and can output the gate low voltage VGL to the output terminal OUT.

[0129] In the sixth transistor T6, since the first electrode is connected to the power supply line of the gate high voltage VGH, the gate electrode is connected to the second node QB, and the second electrode is connected to the output terminal OUT, the sixth transistor T6 can be turned on or off according to the voltage of the second node QB, and can output the gate high voltage VGH to the output terminal OUT.

[0130] The third capacitor CQ can be connected between the first node Q and the output terminal OUT, and the fourth capacitor CQB can be connected between the second node QB and the gate high voltage VGH.

[0131] The first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 can be p-type polycrystalline silicon thin-film transistors, and the third transistor T3 can be an n-type polycrystalline silicon thin-film transistor.

[0132] In the first output section T11, when the output signal of the start signal GVST is input at a low level and the first clock signal GCLK1 is applied as a gating low voltage VGL, the first node Q and the third node Q2 can be charged with the gating low voltage because the first transistor T1 and the second transistor T2 are turned on.

[0133] When the first node Q and the third node Q2 are charged with the low gate voltage VGL, the second node QB can be charged with the high gate voltage VGH because the third transistor T3 is turned off and the fourth transistor T4 is turned on.

[0134] When the low-voltage VGL is input to the gate electrode, the fifth transistor T5 can be turned on, and the sixth transistor T6 can be turned off. Therefore, the fifth transistor T5 can output the low-voltage VGL to the 1-1 switching element M11 of the pixel circuit PIC. On the other hand, when the fifth transistor T5 is turned off and the sixth transistor T6 is turned on, the high-voltage VGH can be output.

[0135] Since the low voltage VGL is output to the gate electrode of the first switching element M1 of the pixel circuit PIC, the first switching element M1 of the pixel circuit PIC can be turned on and the pixel driving voltage EVDD can be applied to the driving element DR.

[0136] According to the implementation method, since the gating drive circuit of the pixel circuit and the first switching element M1 are both located in the non-display area NA, the excimer laser annealing (ELA) process can be performed only in the non-display area NA.

[0137] Figure 14 This is a diagram illustrating a light-emitting signal driver according to one embodiment of the present disclosure. Figure 15 This is a waveform diagram of a light-emitting signal driver according to one embodiment of the present disclosure.

[0138] Reference Figure 14 and Figure 15 In the pixel circuit PIC, the 1-1 switching element M11 can be located in the non-display area NA, and the 1-2 switching element M12 can be located in the display area AA. The light emission signal driver can include a first light emission signal driver EMC11 that applies an output voltage to the 1-1 switching element M11 and a second light emission signal driver EMC12 that applies an output voltage to the 1-2 switching element M12.

[0139] Switching element M11 (1-1) can be a p-type polysilicon thin-film transistor, and switching element M12 (1-2) can be an n-type oxide thin-film transistor. In the second output section T12, the first light-emitting signal driver EMC11 can output a low-gating voltage, and the second light-emitting signal driver EMC12 can output a high-gating voltage to simultaneously turn on switching elements M11 (1-1) and M12 (1-2). The output voltage of the first light-emitting signal driver can be simultaneously applied to the third switching element M3 of the pixel circuit PIC.

[0140] Figure 16 This is a diagram illustrating a light-emitting signal driver according to one embodiment of the present disclosure. Figure 17 This is a waveform diagram of a light-emitting signal driver according to one embodiment of the present disclosure.

[0141] Reference Figure 16 and Figure 17 The third light-emitting signal driver EMC13 may include a first driving region EMC131 that applies a low-voltage gate to the 1-1 switching element M11 and a second driving region EMC132 that applies a high-voltage gate to the 1-2 switching element M12.

[0142] The first drive region EMC131 can have the same Figure 14 The structure is the same as that of the light-emitting signal driver described in [the document]. The second driving region EMC132 may include a seventh transistor T5A and an eighth transistor T5B.

[0143] The seventh transistor T5A may include a first electrode connected to the low-gating voltage VGL, a gate electrode connected to the sixth transistor T6, and a second electrode connected to the second output terminal OUT2. Therefore, the seventh transistor T5A can output a signal with a phase opposite to that of the output signal of the fifth transistor T5.

[0144] The eighth transistor T5B may include a first electrode connected to the gate high voltage VGH, a gate electrode connected to the fifth transistor T5, and a second electrode connected to the second output terminal OUT2. Therefore, the eighth transistor T5B can output a signal with a phase opposite to that of the output signal of the sixth transistor T6.

[0145] According to the implementation method, during the third output period T13, the first drive region EMC131 and the second drive region EMC132 can share a switching component and separate the output terminals OUT1 and OUT2, thereby enabling the 1-1 switching element M11 and the 1-2 switching element M12 to be turned on simultaneously. Afterwards, the 1-1 switching element M11 and the 1-2 switching element M12 can be turned off simultaneously.

[0146] According to one implementation, since the excimer laser annealing (ELA) process is performed only in the non-display area, the display device can be manufactured at a low cost.

[0147] The effects of this disclosure are not limited to those described above, and those skilled in the art will clearly understand from the description of the claims other effects not mentioned.

[0148] Since the description of the problem to be solved, the means for solving the problem, and the aforementioned effects do not specify the essential features of the claims, the scope of the claims is not limited to the items described in the description.

[0149] Although embodiments of the present disclosure have been described in more detail with reference to the accompanying drawings, the present disclosure is not necessarily limited to these embodiments, and various modifications can be made without departing from the technical concept of the present disclosure. Therefore, the embodiments disclosed herein are not intended to limit the technical concept of the present disclosure, but rather to describe the technical spirit of the present disclosure, and the scope of the technical concept of the present disclosure is not limited by these embodiments. Therefore, it should be understood that the above embodiments are illustrative and not restrictive in all respects.

[0150] Cross-references to related applications

[0151] This application claims priority and benefit to Korean Patent Application No. 10-2024-0200631, filed on December 30, 2024, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A display device, the display device comprising: The display panel includes a display area and a non-display area having multiple pixels. A data driver that applies data signals to the display panel; as well as A gating driver that applies a gating signal to the display panel. Each of the plurality of pixels includes a pixel circuit that drives a light-emitting element, and Some of the multiple switching elements of the pixel circuit are located in the non-display area.

2. The display device according to claim 1, wherein, The pixel circuit includes a driving element and a 1-1 switching element. The driving element includes a first electrode connected to a first node, a gate electrode connected to a second node, and a third electrode connected to a third node. The 1-1 switching element connects a first driving voltage line, which is connected to the pixel driving voltage, to the first node. The 1-1 switch element is located in the non-display area.

3. The display device according to claim 2, wherein, The first driving voltage line extends from the non-display area to the display area, and the first driving voltage line is connected to the first node.

4. The display device according to claim 3, wherein, The first driving voltage line extends from the non-display area to the display area, and the first driving voltage line is commonly connected to the driving elements of the plurality of pixels.

5. The display device according to claim 2, wherein, The driving element is an oxide thin-film transistor, and the 1-1 switching element is a polysilicon thin-film transistor.

6. The display device according to claim 2, wherein the display device includes 1-2 switching elements connecting the first node to a second driving voltage line, the second driving voltage line being connected to the pixel driving voltage. in, The 1-2 switching elements are disposed in each pixel circuit.

7. The display device according to claim 6, wherein, The 1-1 switching element responds to the first emitting EM signal by applying the pixel driving voltage to the first node, and The 1-2 switching elements apply the pixel driving voltage to the first node in response to the 1-2 EM signal, the 1-2 EM signal being synchronized with the first EM signal and having a phase opposite to the first EM signal.

8. The display device according to claim 6, wherein, The 1-1 switching element is a polycrystalline silicon thin-film transistor, and the 1-2 switching element is an oxide thin-film transistor.

9. The display device according to claim 6, wherein, The pixel circuit includes: A second switching element connects the second node to a reference voltage line; A third switching element connects the anode of the light-emitting element to the initialization voltage line; and A fourth switching element connects the second node to the data line, and The second to the fourth switching elements are oxide thin-film transistors.

10. The display device according to claim 9, wherein, The pixel circuit includes: A first capacitor, one end of which is connected to the second node and the other end of which is connected to the third node; A second capacitor, one end of which is connected to the third node and the other end of which is connected to the reference voltage line; and A sixth switching element connects the second capacitor to the reference voltage line.

11. The display device according to claim 9, wherein, The gating driver includes a first light-emitting signal driver, which applies a first EM signal to the 1-1 switching element and the third switching element.

12. The display device according to claim 11, wherein, The gating driver includes a second light-emitting signal driver that applies the 1-2 EM signal to the 1-2 switching element, and The 1-2 EM signal has a phase opposite to that of the first EM signal.

13. The display device according to claim 9, wherein, The gating driver includes a third light-emitting signal driver, which applies an EM signal to the 1-1 switching element and the 1-2 switching element. The third light-emitting signal driver includes a first output unit that outputs a first EM signal to the 1-1 switching element and a second output unit that outputs a 1-2 EM signal to the 1-2 switching element. The 1-2 EM signal has a phase opposite to that of the first EM signal.

14. A display device, the display device comprising: The display panel includes a display area and a non-display area having multiple pixels. A data driver that applies data signals to the display panel; as well as A gating driver that applies a gating signal to the display panel. In this configuration, some switching elements of the pixel circuit of each of the plurality of pixels are disposed in the non-display area. The pixel circuit is configured such that all switching elements in the display area are oxide thin-film transistors, and The pixel circuit is located in the non-display area. The switching element and the gating driver are both located in the non-display area. The switching element is a polysilicon thin-film transistor.

15. The display device according to claim 14, wherein, The pixel circuit includes: A driving element, the driving element comprising a first electrode connected to a first node, a gate electrode connected to a second node, and a third electrode connected to a third node; A 1-1 switching element connects the first node to a first driving voltage line connected to the pixel driving voltage; 1-2 switching elements, wherein the 1-2 switching elements connect the first node to a second driving voltage line connected to the pixel driving voltage; A second switching element connects the second node to a reference voltage line; A third switching element connects the anode of the light-emitting element to the initialization voltage line; and A fourth switching element connects the second node to the data line. The 1-1 switching element is a polycrystalline silicon thin-film transistor. The second to fourth switching elements are oxide thin-film transistors, and The 1-1 switch element is located in the non-display area.

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