Display device

Abstract

In some examples, the display device includes: a display panel including a first region and at least one second region; a plurality of gate lines arranged along a first direction in the first and second regions; a plurality of first data lines arranged along a second direction perpendicular to the first direction in the first region; a plurality of second data lines arranged along the second direction in the second region and having a length shorter than that of the first data lines; a plurality of vertical interconnects arranged along the second direction in the first region; and a plurality of horizontal interconnects arranged along the first direction in the first and second regions. Each vertical interconnect is electrically connected to a corresponding second data line via a corresponding horizontal interconnect, and each vertical interconnect has a length inversely proportional to the length of the second data line to be connected.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0198532, filed in Korea on December 27, 2024, the entire contents of which are expressly incorporated herein by reference. Technical Field

[0003] This disclosure relates to a display device, and more specifically, to a display device having a minimal bezel area and being able to easily compensate for storage capacity. Background Technology

[0004] With the development of information technology, the field of display devices for displaying information is developing rapidly, and various display devices with advantageous properties such as thinning, lightness and low power consumption are being developed.

[0005] In this type of display device, wiring is arranged outside the display area for applying various signals to the display area. This wiring is a primary reason for increasing the bezel area of ​​the display device. Summary of the Invention

[0006] Therefore, one or more embodiments of this disclosure relate to a display device that substantially eliminates one or more problems caused by the limitations and disadvantages of related technologies.

[0007] One aspect of this disclosure is to provide a display device capable of preventing image quality degradation by compensating for changes in storage capacitance caused by free-form or irregular shapes.

[0008] Another aspect of this disclosure is to provide a display device capable of minimizing the bezel area by providing a correction component in the display area for correcting deviations in the storage capacitor.

[0009] Additional features and aspects will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practice of the disclosed concept provided herein. Other features and aspects of the disclosed concept may be realized and obtained by means of the structures specifically pointed out in the written description or derived therefrom, the claims thereof, and the accompanying drawings.

[0010] To achieve these and other aspects of the inventive concept, as specifically implemented and broadly described, in one aspect, this disclosure provides a display device comprising: a display panel including a first region and at least one second region; a plurality of gate lines along a first direction in the first region and the second region; a plurality of first data lines arranged in the first region along a second direction perpendicular to the first direction; a plurality of second data lines arranged in the second region along the second direction and having a length shorter than the length of the first data lines; a plurality of vertical interconnects arranged in the first region along the second direction; and a plurality of horizontal interconnects arranged in the first region and the second region along the first direction, wherein each vertical interconnect is electrically connected to a corresponding second data line via a corresponding horizontal interconnect, and each vertical interconnect has a length inversely proportional to the length of the second data line to be connected.

[0011] In one implementation, the data signal can be directly applied to each first data line, and the data signal can be applied to each second data line via the vertical connection and the horizontal connection.

[0012] The display device may further include: a first contact hole that electrically connects each vertical wire to a corresponding horizontal wire; and a second contact hole that electrically connects each horizontal wire to a corresponding second data line.

[0013] The display device may further include: a thin-film transistor, which is disposed in the first region and the second region respectively; and a light-emitting diode, which is disposed on the thin-film transistor.

[0014] The thin-film transistor may include: a semiconductor layer disposed on a substrate; a gate electrode disposed on the semiconductor layer; and a source electrode and a drain electrode disposed on the gate electrode.

[0015] The display device may further include: a gate insulating layer disposed between the semiconductor layer and the gate electrode; an interlayer insulating layer disposed between the gate electrode and the source electrode and the drain electrode; a planarization layer disposed on the source electrode and the drain electrode; and a connection pattern disposed on the planarization layer and connected to one of the source electrode and the drain electrode.

[0016] The vertical interconnects may be disposed on the planarization layer, and the horizontal interconnects may be disposed on the interlayer insulating layer. The vertical interconnects may include the same material as the connection pattern, and / or the horizontal interconnects may include the same material as the source electrode and the drain electrode. In one embodiment, each vertical interconnect may be electrically connected to a corresponding horizontal interconnect through a first contact hole disposed in the planarization layer.

[0017] The vertical connection can extend a predetermined distance from the first contact hole, and the extension distance of the vertical connection can be inversely proportional to the length of the second data line to be connected.

[0018] The distance between the horizontal lines connected to the second data line can increase as the length of the second data line decreases.

[0019] The display panel can have a free form.

[0020] The first region can be a rectangular region, and the second region can be a non-rectangular region.

[0021] The display panel may have a circular shape.

[0022] The first region may be the central region of the circular shape, and the second region may be the two side regions of the central region.

[0023] The vertical connecting line may not be arranged in the second region.

[0024] The multiple first data lines can be configured to have the same length.

[0025] The length of the second data line can decrease from the central region outwards.

[0026] The second region may include a left second region and a right second region located to the left and right of the central region, respectively, and the leftmost vertical line in the first region may be electrically connected to the rightmost second data line in the left second region via the horizontal line.

[0027] The second vertical line from the leftmost side of the first region can be electrically connected via the horizontal line to the second data line from the rightmost side of the second region on the left.

[0028] The first region and the second region may be display regions, and a curved region and a second non-display region may be formed at the lower end of the first non-display region surrounding the display region.

[0029] Multiple data lines and multiple signal lines can be provided in the second non-display area and the curved area, and the multiple data lines can be electrically connected to the multiple first data lines respectively, and the multiple signal lines can be electrically connected to the multiple vertical lines respectively.

[0030] This disclosure provides a display device, comprising: a display panel including a first region and at least one second region; a plurality of gate lines along a first direction in the first region and the second region; a plurality of first data lines arranged in the first region along a second direction perpendicular to the first direction; a plurality of second data lines arranged in the second region along the second direction and having a length shorter than the length of the first data lines; a plurality of vertical interconnects arranged in the first region along the second direction; a plurality of horizontal interconnects arranged in the first region and the second region along the first direction; and a plurality of compensation interconnects extending from the plurality of vertical interconnects, wherein each vertical interconnect is electrically connected to a corresponding second data line via a corresponding horizontal interconnect, and each compensation interconnect has a length inversely proportional to the length of the second data line to be connected.

[0031] This disclosure provides a display device, comprising: a display panel including a first region and at least one second region; a plurality of gate lines along a first direction in the first region and the second region; a plurality of first data lines arranged in the first region along a second direction perpendicular to the first direction; a plurality of second data lines arranged in the second region along the second direction and having a length shorter than the length of the first data lines; a plurality of vertical connecting lines arranged in the first region along the second direction; and a plurality of horizontal connecting lines arranged in the first region and the second region along the first direction, wherein the distance between the horizontal connecting lines is inversely proportional to the length of the second data lines to which the horizontal connecting lines are to be connected.

[0032] In one or more embodiments, image quality degradation can be prevented by compensating for differences in storage capacitance caused by differences in the length of data lines disposed in freeform or irregular areas of the display device.

[0033] Furthermore, the display device can minimize its bezel area by setting a correction pattern in the display area to correct deviations in the storage capacitor.

[0034] Because the deviation of the storage capacitor is corrected to prevent image quality degradation, low power consumption is achieved due to high efficiency.

[0035] It should be understood that the foregoing general description and the following detailed description are illustrative and intended to provide further explanation of the claimed inventive concept. Attached Figure Description

[0036] The accompanying drawings, which provide a further understanding of this disclosure and are incorporated in and constitute a part of this application, illustrate embodiments of this disclosure and, together with the specification, serve to explain the principles of this disclosure.

[0037] Figure 1 The diagram illustrates a schematic block diagram of a display device according to one or more embodiments of the present disclosure.

[0038] Figure 2 The diagram illustrates a schematic block diagram of a sub-pixel in a display device according to one or more embodiments of the present disclosure.

[0039] Figure 3 The diagram illustrates a schematic circuit diagram of a sub-pixel in a display device according to one or more embodiments of the present disclosure.

[0040] Figure 4 The diagram illustrates a schematic plan view of a display device according to one embodiment of the present disclosure.

[0041] Figure 5 The diagram illustrates the arrangement of lines in the display area of ​​a display device according to one embodiment of the present disclosure.

[0042] Figure 6A Diagram along Figure 4 A schematic cross-sectional view of the display device taken by line I-I'.

[0043] Figure 6B Diagram along Figure 5 A schematic cross-sectional view of the display device taken from line II-II'.

[0044] Figure 7 The diagram illustrates the line arrangement in the display area of ​​a display device according to another embodiment of the present disclosure. Detailed Implementation

[0045] The advantages and features of this disclosure, and the methods for implementing them, will become clear from the embodiments described below with reference to the accompanying drawings. However, this disclosure can be implemented in many different forms and should not be construed as limited to the embodiments set forth herein. The embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of this disclosure to those skilled in the art to which this disclosure pertains.

[0046] The shapes, dimensions, scales, angles, quantities, etc., disclosed in the accompanying drawings used to describe embodiments of this disclosure are merely illustrative examples, and therefore this disclosure is not limited to the illustrated examples. Throughout this disclosure, the same reference numerals refer to the same parts unless otherwise stated. Furthermore, in the following description of this disclosure, detailed descriptions of known related technologies may be omitted or briefly discussed where such detailed descriptions might unnecessarily obscure the main points of this disclosure.

[0047] When the terms “comprising,” “having,” “including,” etc., are used in this disclosure, additional parts may be added unless a more restrictive term such as “only” is used herein. Furthermore, when a component is indicated in the singular, the plural is included, and vice versa, unless otherwise stated.

[0048] When analyzing components, it should be interpreted that the error range is included, even if it is not explicitly described.

[0049] When describing positional relationships, for example, when the positional relationship between two parts / layers is described as "above", "on top", "below", "below", "adjacent", etc., one or more other parts / layers may be placed between the two parts / layers, unless more restrictive terms such as "immediately following" or "directly" are used with them.

[0050] When describing temporal relationships, such as when the temporal sequence is described as “after,” “following,” “next,” “before,” etc., discontinuous or sequential situations may also be included unless more restrictive terms such as “immediately” or “directly” are used.

[0051] Although the terms first, second, etc., may be used to describe various components, these components are not substantially limited by these terms. These terms are used to indicate a component separate from another component and do not limit any particular order or sequence. Therefore, within the technical spirit of this disclosure, the first component described below may substantially be the second component, and vice versa.

[0052] When describing the components of this disclosure, terms such as first, second, A, B, (a), (b), etc., may be used. These terms are intended only to distinguish a component from other components, and the nature, order, sequence, or number of components is not limited by these terms. When describing a component as being “connected,” “joined,” or “attached” to another component, it should be understood that the component may be directly “connected,” “joined,” or “attached” to the other component, but other components may also be “inserted” between components, or components may be “connected,” “coupled,” or “attached” through other components.

[0053] Features of various embodiments of this disclosure may be combined or integrated with each other in part or in whole, may be technically linked and driven in various ways, and each embodiment may be implemented independently of each other or together in a mutually dependent relationship.

[0054] All components of each display device according to all embodiments of this disclosure are operatively combined and configured.

[0055] As used herein, “display device” can include display devices in a narrow sense, such as display modules that include a display panel and a drive unit for driving the display panel. Additionally, display devices can also include unit electronics or unit equipment, such as laptops, televisions, computer monitors, automotive displays, or other forms of vehicles, which are complete products (or end products) including display modules, device displays, mobile electronic devices such as smartphones or electronic boards.

[0056] Therefore, the display device in this disclosure may include the display device itself in a narrow sense, such as a display module, as well as a unit device that is an application product or end consumer device that includes a display module.

[0057] This disclosure is applicable to various display devices. For example, it can be applied to organic light-emitting display devices, liquid crystal display devices, electrophoretic display devices, quantum dot display devices, micro light-emitting diode (LED) display devices, and mini LED display devices. For ease of explanation, an organic light-emitting display device may be described as an example of a display device. However, this disclosure is not limited to organic light-emitting display devices.

[0058] Reference will now be made in detail to aspects of this disclosure, examples of which are shown in the accompanying drawings. Wherever possible, the same reference numerals will be used throughout the drawings to refer to the same or similar parts.

[0059] Figure 1 The diagram illustrates a schematic block diagram of a display device according to the present disclosure. Figure 2 The diagram illustrates a schematic block diagram of a subpixel in a display device according to the present disclosure.

[0060] Reference Figure 1 The display device 100 may include an image processor 102, a timing controller 104, a gate driver 106, a data driver 107, a power supply 108, and a display panel 109.

[0061] The image processor 102 outputs drive signals for driving various components, as well as image data supplied from the outside. For example, the drive signals output from the image processor 102 may include, but are not limited to, data enable signals, vertical synchronization signals, horizontal synchronization signals, clock signals, etc.

[0062] The timing controller 104 receives drive signals and image data from the image processor 102. Based on the drive signals input from the image processor 102, the timing controller 104 generates and outputs a gate timing control signal GDC for controlling the operating timing of the gate driver 106 and a data timing control signal DDC for controlling the operating timing of the data driver 107.

[0063] Gate driver 106 outputs a scan signal to display panel 109 in response to a gate timing control signal GDC supplied from timing controller 104. Gate driver 106 outputs the scan signal through multiple gate lines GL1 to GLm (m is an integer equal to or greater than 2). In one embodiment, gate driver 106 may be formed as an integrated circuit (IC), but is not limited thereto. In another embodiment, gate driver 106 may include various gate driving circuits formed directly on display panel 109. In this case, gate driver 106 may be a GIP (gate in panel).

[0064] Data driver 107 outputs a data voltage to display panel 109 in response to a data timing control signal DDC input from timing controller 104. Data driver 107 samples and latches a digital data signal DATA supplied from timing controller 104, and converts the digital data signal DATA into an analog data voltage based on gamma voltage. Data driver 107 outputs the data voltage through multiple data lines DL1 to DLn (n is an integer equal to or greater than 2). In one embodiment, data driver 107 may be formed as an integrated circuit (IC), but is not limited thereto.

[0065] Power supply 108 outputs a high-level voltage and a low-level voltage, and supplies these voltages to display panel 109. The high-level voltage is supplied to display panel 109 via a first power line EVDD, and the low-level voltage is supplied to display panel 109 via a second power line EVSS. Alternatively or additionally, the voltage output from power supply 108 can be output to gate driver 106 and / or data driver 107 to drive those drivers 106 and 107.

[0066] The display panel 109 displays an image in response to a scan signal supplied from the gate driver 106, a data voltage supplied from the data driver 107, and power supplied from the power supply 108.

[0067] Display panel 109 includes a plurality of subpixels SP for displaying images. In one embodiment, subpixels SP may include red (R) subpixels, green (G) subpixels, and blue (B) subpixels. Alternatively, subpixels SP may include white (W) subpixels, red (R) subpixels, green (G) subpixels, and blue (B) subpixels. In one embodiment, the white (W) subpixels, red (R) subpixels, green (G) subpixels, and blue (B) subpixels may have substantially the same area. Alternatively, the white (W) subpixels, red (R) subpixels, green (G) subpixels, and blue (B) subpixels may have different areas.

[0068] Reference Figure 2 Each sub-pixel SP can be connected to a gate line GL1, a data line DL1, a first power line EVDD, and a second power line EVSS. The number of transistors and capacitors and the driving method can be determined by the configuration of the pixel circuitry in the sub-pixel SP. For example, a sub-pixel SP may include two transistors and one capacitor (2T1C), but is not limited thereto. In another embodiment, the sub-pixel SP may include 3T1C, 4T1C, 5T1C, 6T1C, 7T1C, 3T2C, 4T2C, 5T2C, 6T2C, 8T2C, etc.

[0069] Figure 3 The diagram illustrates a schematic circuit diagram of a sub-pixel in a display device according to the present disclosure.

[0070] Reference Figure 3 The display device 100 includes gate lines GL, data lines DL, and power lines PL that intersect each other to define sub-pixels SP. Switching thin-film transistors Ts, driving thin-film transistors Td, storage capacitors Cst, and light-emitting diodes D can be disposed in the sub-pixels SP.

[0071] The switching thin-film transistor Ts is connected to the gate line GL and the data line DL. The driving thin-film transistor Td and the storage capacitor Cst are connected between the switching thin-film transistor Ts and the power line PL, and the light-emitting diode D is connected to the driving thin-film transistor Td.

[0072] In the display device 100, when the switching thin-film transistor Ts is turned on by the gate signal applied to the gate line GL, the data signal applied to the data line DL is applied to the gate electrode 114 through the switching thin-film transistor Ts. Figure 6A ) and one electrode of the storage capacitor Cst.

[0073] The driving thin-film transistor Td is turned on by a data signal applied to its gate electrode 114, such that a current proportional to the data signal is supplied from the power line PL through the driving thin-film transistor Td to the light-emitting diode D. The light-emitting diode D then emits light with a brightness proportional to the current flowing through the driving thin-film transistor Td. In this case, the storage capacitor Cst is charged to a voltage proportional to the data signal, such that the voltage at the gate electrode 114 in the driving thin-film transistor Td remains constant during one frame. Therefore, the display device 100 can display the desired image.

[0074] exist Figure 3 In the present invention, the display device 100 includes two thin-film transistors Ts and Td, and a storage capacitor Cst in the sub-pixel SD. However, the display device 100 may include three or more thin-film transistors and two or more storage capacitors in the sub-pixel SP.

[0075] Figure 4 The diagram illustrates a schematic plan view of a display device according to one embodiment of the present disclosure. Figure 5 The diagram illustrates the arrangement of lines in the display area of ​​a display device according to one embodiment of the present disclosure.

[0076] In one embodiment, the display device 100 may be applied to a free-form display device, but is not limited thereto. As used herein, a free-form display device may refer to a display device having a non-rectangular shape. For example, a free-form display device may be a non-rectangular display device such as a circle, ellipse, curved shape, or irregular shape, but is not limited thereto.

[0077] In one exemplary embodiment, the display device 100 can be a free-form display device applicable to various electronic devices such as watches and / or dashboards in vehicles. Hereinafter, a display device 100 having a circular shape will be described in more detail. In another embodiment, the display device 100 can be applied to a display device with rounded corners.

[0078] Reference Figure 4 and Figure 5 According to one embodiment, the display device includes a display area AA for displaying a real image and a non-display area NA (i.e., a first non-display area NA2 or a second non-display area NA2) disposed outside the display area AA.

[0079] Multiple gate lines GL1 to GLm and multiple data lines DL1 to DLn are arranged in the display area AA to define multiple sub-pixels SP1, SP2, and SP3. In one embodiment, sub-pixels SP1, SP2, and SP3 may include red (R) sub-pixels, green (G) sub-pixels, and blue (B) sub-pixels. Alternatively or additionally, sub-pixels SP may further include white (W) sub-pixels. In one embodiment, sub-pixels SP1, SP2, and SP3 may form a pixel P.

[0080] Thin-film transistors with switching elements and display elements for realizing a real image are set in each sub-pixel SP1, SP2 or SP3.

[0081] Display elements may include a variety of display elements. For example, display elements may include, but are not limited to, organic light-emitting elements, liquid crystal display elements, quantum dot display elements, micro LED (light-emitting diode) display elements, and mini LED display elements.

[0082] The display area AA can be divided into a first area A1, a second area A2, and a third area A3 along a first direction (horizontal direction, x-axis direction). Furthermore, since the areas on both sides of the first area are referred to as the second area, the second area A2 can be called the left second area and the third area A3 can be called the right second area.

[0083] In the first region A1 of the display area AA, multiple first data lines DL1 and multiple vertical connecting lines VLINK are arranged along a second direction (vertical direction, y-axis direction). In this case, one first data line DL1 and one vertical connecting line VLINK correspond to a sub-pixel column arranged along the second direction. Each of the multiple sub-pixels arranged in a sub-pixel column is electrically connected to the corresponding first data line DL1 to receive a data signal. In this case, the corresponding vertical connecting line VLINK is not electrically connected to the multiple sub-pixels arranged in the sub-pixel column.

[0084] Display areas A2 and A3 are arranged on both sides of the first area A1. Multiple second data lines DL2 and multiple third data lines DL3 extending along a second direction (vertical direction, y-axis direction) are arranged in the second area A2 and the third area A3, respectively. No vertical connecting lines VLINK are arranged in the second area A2 and the third area A3.

[0085] Multiple first data lines DL1 arranged in the first region A1 are formed to have the same length from the bottom to the top of the circular display area AA. The length of the second data line DL2 arranged in the second region A2 decreases from the central region outwards, that is, from the boundary of the first region A1 to the left end. Furthermore, the length of the third data line DL3 arranged in the third region A3 decreases from the central region outwards, that is, from the boundary of the first region A1 to the right end.

[0086] Multiple horizontal connecting lines HLINK are arranged along the first direction (x-axis direction) in the first area A1, the second area A2, and the third area A3 of the display area AA. The multiple horizontal connecting lines HLINK can be spaced apart from each other with the same spacing, but are not limited to this.

[0087] Each horizontal HLINK is electrically connected to a corresponding vertical VLINK in the first region A1 via the first contact hole CNT1. Each horizontal HLINK is provided with an insulating layer between it and the second data line DL2 in the second region A2 and the third data line DL3 in the third region A3, and is electrically connected via the second contact hole CNT2.

[0088] exist Figure 4 In one embodiment, multiple vertical VLINK lines and multiple horizontal HLINK lines are arranged on one side of sub-pixels SP1, SP2, and SP3. In another embodiment, the multiple vertical VLINK lines and multiple horizontal HLINK lines may be arranged across sub-pixels SP1, SP2, and SP3.

[0089] The leftmost vertical connection VLINK in the first region A1 can be electrically connected via the horizontal connection HLINK to the closest second data line DL2 arranged in the second region A2, that is, the rightmost second data line DL2 in the second region A2. Furthermore, the second vertical connection VLINK located from the leftmost side of the first region A1 can be electrically connected via the horizontal connection HLINK to the second second data line DL2 located from the rightmost side of the second region A2, but this is not a limitation.

[0090] The rightmost vertical line VLINK in the first region A1 can be electrically connected via the horizontal line HLINK to the nearest third data line DL3 in the third region A3, that is, the leftmost third data line DL3 in the third region A3. Furthermore, the second vertical line VLINK from the rightmost position in the first region A1 can be electrically connected via the horizontal line HLINK to the second third data line DL3 from the leftmost position in the third region A3, but this is not a limitation.

[0091] A gate driver 106 for applying various signals to sub-pixels SP1, SP2, and SP3 can be disposed in a first non-display area NA1 surrounding the display area AA. Figure 1 Gate driver 106 is connected to gate line GL1 through gate line GLm. Figure 1 The scan signal is applied to sub-pixels SP1, SP2, and SP3. In one embodiment, the gate driver 106 may be a gate driving circuit directly disposed on the substrate 140. Figure 6A and Figure 6B GIP circuitry on ).

[0092] A curved region BA extending from the first non-display region NA1 can be formed on the lower end of the first non-display region NA1. The curved region BA can be bent by bending in a certain direction. The second non-display region NA2 is the region extending from the curved region BA. A flexible circuit film (FPC) is attached to the second non-display region NA2.

[0093] Since the flexible circuit film FPC is disposed on the lower surface of the display device 100 by bending the bending area BA, the bezel of the display device 100 can be reduced.

[0094] A driving element DR is mounted on a flexible circuit film (FPC), and lines are formed in the FPC to supply data signals output from the driving element DR and various signals output from the outside to the display area AA. In one embodiment, the driving element DR may be directly mounted in a second non-display area NA2.

[0095] Multiple data lines (DLINK) and multiple signal lines (SLINK) are set in the second non-display area (NA2) and the curved area (BA).

[0096] Multiple data links (DLINKs) are electrically connected to multiple first data lines (DL1) in the first region A1. Multiple signal links (SLINKs) are electrically connected to multiple vertical links (VLINKs) in the first region A1. The connections between the data links (DLINKs) and the first data lines (DL1), and between the signal links (SLINKs) and the vertical links (VLINKs) can be established via solder pad electrodes. Data signals are applied to the multiple data links (DLINKs) and the multiple signal links (SLINKs).

[0097] The data signal is directly applied to the first data line DL1 in the first area A1 of the display area AA via the data connection DLINK, so as to supply the data signal to multiple sub-pixels SP1, SP2, and SP3 corresponding to the sub-pixel columns in the first area A1. The data signal is applied to the second data line DL2 in the second area A2 of the display area AA via the signal connection SLINK, the vertical connection VLINK, and the horizontal connection HLINK, so as to supply the data signal to multiple sub-pixels SP1, SP2, and SP3 corresponding to the sub-pixel columns in the second area A2. The data signal is applied to the third data line DL3 in the third area A3 of the display area AA via the signal connection SLINK, the vertical connection VLINK, and the horizontal connection HLINK, so as to supply the data signal to multiple sub-pixels SP1, SP2, and SP3 corresponding to the sub-pixel columns in the third area A3.

[0098] In the display device 100 of this disclosure, the connection lines that supply data signals to the sub-pixels SP1, SP2, and SP3 in the second region A2 and the third region A3, which are respectively located outside the curved region BA and the second non-display region NA2 in the first direction (width direction, x-axis direction), are not located in the non-display region NA, but are located in the display region AA. Therefore, the border area can be minimized.

[0099] A compensation line COLINK is formed for each of the multiple vertical interconnects VLINK. In one embodiment, the compensation line COLINK can be formed by extending from each vertical interconnect VLINK. Since the vertical interconnect VLINK extends from the lower end of the display area AA to the first contact hole CNT1, the compensation line COLINK can be formed by extending a predetermined distance l from the first contact hole CNT1 along the second direction (y-axis direction).

[0100] In this way, the compensation connection COLINK is formed by extending from the vertical connection VLINK. This is to compensate for the storage capacitance of the data lines DL, thereby eliminating the deviation in storage capacitance between data lines DL with different lengths.

[0101] In the freeform or non-rectangular display device 100, the length of the data line DL varies depending on the position. In particular, the data signal is applied to the sub-pixels SP1, SP2 and SP3 using the vertical connection VLINK and the horizontal connection HLINK, and the storage capacitance formed in the data line DL varies depending on the position.

[0102] This difference in storage capacitance is a major cause of image distortion and quality degradation. Various methods can be used to eliminate this difference in storage capacitance between the data lines DL. For example, the storage capacitance can be compensated by generating parasitic capacitance through the formation of a separate metal pattern in the first non-display area NA1. However, in this case, because the area of ​​the first non-display area NA1 increases due to the metal pattern, there is a problem of increased bezel area of ​​the display device 100.

[0103] In this disclosure, by arranging compensation lines COLINK in the display area AA, the increase in the border area caused by the individual metal pattern can be prevented.

[0104] The compensation link (COLINK) can be configured to extend from the vertical link (VLINK). In one embodiment, the length l of the compensation link (COLINK) is inversely proportional to the lengths of the second data line DL2 in the second region A2 and the third data line DL2 in the third region A3.

[0105] The reason for the storage capacitance deviation in the second data line DL2 and the third data line DL3 is that the lengths of the second data line DL2 and the third data line DL2 are shorter than the length of the first data line DL1. Since the difference in storage capacitance between the first data line DL1 and the second and third data lines DL2 increases as the relative lengths of the second and third data lines DL2 decrease, the length l of the compensation connection COLINK used to compensate for the storage capacitance difference must be inversely proportional to the lengths of the second data line DL2 in the second region A2 and the third data line DL3 in the third region A3.

[0106] That is to say, the compensation line COLINK, which extends from the vertical connection VLINK connecting the shortest second data line DL2 and the third data line DL2 located on the outermost side of the second region A2 and the third region A3 respectively, is the longest, and the length of the compensation line COLINK gradually decreases from the outermost side of the second region A2 and the third region A3 to the first region A1 (i.e., as the length of the second data line DL2 and the third data line DL3 increases).

[0107] As described above, in the display device 100, the pattern for compensating for changes in storage capacitance caused by the length difference of the data line DL is not provided in the non-display area NA of the display device 100, but is provided in the display area AA, thereby minimizing the bezel area.

[0108] The configuration of the display device 100 will be described in more detail below with reference to the accompanying drawings.

[0109] Figure 6A Diagram along Figure 4A schematic cross-sectional view of the display device taken by line I-I'. Figure 6B Diagram along Figure 5 A schematic cross-sectional view of the display device taken from line II-II'.

[0110] Reference Figure 6A and Figure 6B A buffer layer 142 is disposed on the substrate 140. In one embodiment, the substrate 140 may comprise a rigid material such as glass. In another embodiment, the substrate may include, but is not limited to, plastic materials such as polyimide (PI), polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), polyethersulfone (PES), polycarbonate (PC), and combinations thereof.

[0111] For example, when the substrate 140 includes polyimide, the substrate 140 may include a plurality of polyimide layers, and an inorganic layer may be further disposed between the polyimide layers, but is not limited thereto.

[0112] A buffer layer 142 can be provided on the entire substrate 140 to improve the adhesion between the layer provided on the substrate 140 and the substrate 140, and to prevent alkaline components from leaking from the substrate 140. In addition, the buffer layer 142 can delay the diffusion of moisture or oxygen that has penetrated into the substrate 140.

[0113] In one embodiment, the buffer layer 142 may include, but is not limited to, inorganic insulating materials such as silicon oxide (SiOx, where 0 < x ≤ 2) and silicon nitride (SiNx, where 0 < x ≤ 2). The buffer layer 142 may have a single-layer structure or a multi-layer structure. For example, the buffer layer 142 may have an alternating stacked structure of silicon nitride (SiNx) layers and silicon oxide (SiOx) layers. In some embodiments, the buffer layer 142 may be omitted depending on the type and material of the substrate 140 and the structure and / or type of the thin-film transistor.

[0114] A thin-film transistor T is disposed on the buffer layer 142 in the display area AA. For ease of illustration, in Figure 6A Only the driving thin-film transistor T is shown among the various thin-film transistors that can be arranged in the display area AA, but other thin-film transistors such as switching thin-film transistors can also be provided. Furthermore, in Figure 6A The diagram shows a thin-film transistor T with a top-gate structure. The structure of the thin-film transistor T is not limited to this, and other thin-film transistor T with structures such as a bottom-gate structure can be implemented.

[0115] The thin film transistor T may include a semiconductor layer 112 disposed on a buffer layer 142, a gate insulating layer 144 disposed on the semiconductor layer 112, a gate electrode 114 disposed on the gate insulating layer 144, an interlayer insulating layer 146 disposed on the gate electrode 114, and a source electrode 115 and a drain electrode 116 disposed on the interlayer insulating layer 146.

[0116] In one embodiment, the semiconductor layer 112 may include a polycrystalline semiconductor. For example, the polycrystalline semiconductor may include, but is not limited to, low temperature polycrystalline silicon (LTPS) having a high mobility.

[0117] In another embodiment, the semiconductor layer 112 may include an oxide semiconductor. For example, the oxide semiconductor may include, but is not limited to, indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), indium gallium tin oxide (IGTO), indium gallium oxide (IGO), and combinations thereof. In some embodiments, the semiconductor layer 112 may include a channel region 112a in a central region, and source regions 112b and drain regions 112c that are doped regions on both sides of the channel region 112a.

[0118] In one embodiment, the gate insulating layer 144 may be disposed in a display area AA and a non-display area NA. In another embodiment, the gate insulating layer 144 may be disposed only in the display area AA. For example, the gate insulating layer 144 may include inorganic insulating materials such as silicon oxide (SiOx, where 0 < x ≤ 2) and silicon nitride (SiNx, where 0 < x ≤ 2). The gate insulating layer 144 may have a single-layer structure or a multi-layer structure. However, embodiments of the present disclosure are not limited thereto.

[0119] In one embodiment, the interlayer insulating layer 146 may be dispose in the display area AA and the non-display area NA. In another embodiment, the interlayer insulating layer 146 may be disposed only in the display area AA. For example, the interlayer insulating layer 146 may include, but is not limited to, organic materials such as photoacrylic acid or inorganic insulating materials such as silicon oxide (SiOx, where 0 < x ≤ 2) and silicon nitride (SiNx, where 0 < x ≤ 2). The interlayer insulating layer 146 may have a single-layer structure or a multi-layer structure. In another embodiment, the interlayer insulating layer 146 may have a multi-layer structure including at least one organic layer and at least one inorganic layer. However, embodiments of the present disclosure are not limited thereto.

[0120] In one embodiment, each of the source electrode 115 and drain electrode 116 may include, but is not limited to, molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), combinations thereof, or alloys thereof. Each of the source electrode 115 and drain electrode 116 may have a single-layer structure with a multilayer structure. However, embodiments of the present disclosure are not limited thereto. The source electrode 115 and drain electrode 116 may contact the source region 112b and drain region 112c of the semiconductor layer 112, respectively, through contact holes formed in the gate insulating layer 144 and / or the interlayer insulating layer 146.

[0121] A horizontal interconnect HLINK is provided on the interlayer insulating layer 146. In one embodiment, the horizontal interconnect HLINK may include the same material as the source electrode 115 and the drain electrode 116, but is not limited thereto.

[0122] In some embodiments, a bottom shielding metal layer may be disposed between the substrate 140 and the semiconductor layer 112. The bottom shielding metal layer may be arranged to minimize back channel phenomena caused by charges trapped in the substrate 140 and to prevent persistence or performance degradation of the transistor. For example, the bottom shielding metal layer may include, but is not limited to, titanium (Ti), molybdenum (Mo), and alloys thereof. The bottom shielding metal layer may have a single-layer structure or a multi-layer structure.

[0123] A first planarization layer 148 is disposed on a substrate 140 on which a thin-film transistor T is disposed. In one embodiment, the first planarization layer 148 may be, but is not limited to, an organic material such as photoacrylic acid. In another embodiment, the first planarization layer 148 may have a multilayer structure having at least one inorganic layer and at least one organic layer.

[0124] A connection pattern 154 is formed on the first planarization layer 148. The connection pattern 154 can be electrically connected to one of the source electrode 115 and drain electrode 116 of the thin-film transistor T through contact holes formed in the first planarization layer 148. For example, the connection pattern 154 may include a metallic component.

[0125] A vertical connection VLINK is formed on the first planarization layer 148. In one embodiment, the vertical connection VLINK may include, but is not limited to, the same metal composition as the connection pattern 154. The vertical connection VLINK can be electrically connected to the horizontal connection HLINK through a first contact hole CNT1 formed in the first planarization layer 148.

[0126] exist Figure 6A and Figure 6BIn one embodiment, a horizontal connection HLINK is provided on the interlayer insulating layer 146, and a vertical connection VLINK is provided on the first planarization layer 148. In another embodiment, a vertical connection VLINK may be provided on the interlayer insulating layer 146, and a horizontal connection HLINK may be provided on the first planarization layer 148.

[0127] A second planarization layer 150 is disposed on a first planarization layer 148 having a connecting pattern 154 and a vertical link VLINK. In one embodiment, the second planarization layer 150 may include, but is not limited to, an organic material such as photopolymer acrylic. In another embodiment, the second planarization layer 150 may have a multilayer structure having at least one inorganic layer and at least one organic layer. In one embodiment, the second planarization layer 150 may comprise the same material as the first planarization layer 148. In another embodiment, the second planarization layer 150 may comprise a different material than the first planarization layer 148.

[0128] By providing two or more planarization layers 148 and 150, various electrodes and lines can be arranged between the first planarization layer 148 and the second planarization layer 150. In this case, since the electrodes can be arranged vertically, the area occupied by the electrodes and lines in the sub-pixel can be reduced. Therefore, the area of ​​the sub-pixel can be reduced and a display device 100 with high resolution can be manufactured.

[0129] A light-emitting diode (or light-emitting element) D is disposed on the second planarization layer 150 in the display area AA. The light-emitting diode D may include a first electrode 132, a light-emitting layer 134, and a second electrode 136 respectively disposed sequentially on the second planarization layer 150.

[0130] A first electrode 132 is disposed on the second planarization layer 150. The first electrode 132 can be electrically connected to the connection pattern 154 through a contact hole formed in the second planarization layer 150. In other words, the first electrode 132 can be electrically connected to one of the source electrode 115 or the drain electrode 116 of the thin-film transistor T through the connection pattern 154.

[0131] For example, the first electrode 132 may include, but is not limited to, metallic components such as silver (Ag), aluminum (Al), molybdenum (Mo), tungsten (W), chromium (Cr), combinations thereof, or alloys thereof. In another embodiment, the first electrode 132 may include, but is not limited to, transparent metal oxides such as indium tin oxide (ITO) and / or indium zinc oxide (IZO).

[0132] In one embodiment, when the display device 100 is a top-emitting type, the first electrode 132 may further include an opaque conductive material serving as a reflective electrode. In another embodiment, when the display device 100 is a bottom-emitting type, the first electrode 132 may be disposed using a transparent conductive material such as ITO and / or IZO.

[0133] A dam layer (BNK) is provided on the second planarization layer 150 at the boundary of each sub-pixel. The dam layer (BNK) can be a partition wall that defines each sub-pixel. The dam layer (BNK) separates each sub-pixel and prevents the mixing and output of light of a specific color from adjacent sub-pixels.

[0134] For example, the dam layer BNK may include, but is not limited to, inorganic materials such as silicon oxide (SiOx, where 0 < x ≤ 2) and silicon nitride (SiNx, where 0 < x ≤ 2), organic materials such as benzocyclobutene (BCB), acrylic resins, epoxy resins, phenolic resins, polyamide resins and / or polyimide resins, photosensitizers containing black pigments and / or dyes, and combinations thereof.

[0135] The light-emitting layer 134 may be disposed on the inclined surface of the first electrode 132 and the embankment layer BNK and disposed on a portion of the embankment layer BNK in the display area AA, and extend to the non-display area NA.

[0136] In one embodiment, the light-emitting layer 134 may include, but is not limited to, a red light-emitting layer that emits red light and is disposed in a red sub-pixel, a green light-emitting layer that emits green light and is disposed in a green sub-pixel, and a blue light-emitting layer that emits blue light and is disposed in a blue sub-pixel. For example, the light-emitting layer 134 may include, but is not limited to, an organic light-emitting layer, or an inorganic light-emitting layer such as a nanoscale material layer, quantum dots, a micro LED light-emitting layer, or a mini LED light-emitting layer.

[0137] In one embodiment, the light-emitting layer 134 may include a light-emitting material layer. In another embodiment, the light-emitting layer 134 may further include a hole injection layer, a hole transport layer, and / or an electron blocking layer disposed between the first electrode 132 and the light-emitting material layer, and an electron injection layer, an electron transport layer, and / or a hole blocking layer disposed between the light-emitting material layer and the second electrode 136.

[0138] A second electrode 136 is disposed on the light-emitting layer 134. In one embodiment, the second electrode 136 may have a single-layer or multi-layer structure of a metallic component or its alloy. In another embodiment, the second electrode 136 may comprise a transparent metal oxide such as ITO and / or IZO. However, embodiments of this disclosure are not limited thereto.

[0139] In one embodiment, when the display device 100 is a top-emitting type, the second electrode 136 may be arranged using a transparent or semi-transparent conductive material. For example, the second electrode 136 may include, but is not limited to, alloys such as LiF / Al, CsF / Al, Mg:Ag, Ca / Ag, Ca:Ag, LiF / Mg:Ag, LiF / Ca / Ag, LiF / Ca:Ag, and combinations thereof.

[0140] In another embodiment, when the display device 100 is a bottom-emitting type, the second electrode 136 may be arranged using an opaque conductive material. For example, the second electrode 136 may include, but is not limited to, silver (Ag), aluminum (Al), gold (Au), molybdenum (Mo), tungsten (W), chromium (Cr), and / or alloys thereof.

[0141] In another embodiment, the light-emitting diode D may have a tandem structure. The tandem structure includes a plurality of light-emitting portions and at least one charge-generating layer disposed between the light-emitting portions. The charge-generating layer is used to connect the plurality of light-emitting portions. In one embodiment, a plurality of charge-generating layers, including a first charge-generating layer and a second charge-generating layer, may be provided. In one embodiment, the charge-generating layer may include an N-type charge-generating layer and a P-type charge-generating layer. For example, the charge-generating layer may include, but is not limited to, an organic layer doped with alkali metals such as Li, Na, K, and / or Cs and / or alkaline earth metals such as Mg, Sr, Ba, and / or Ra.

[0142] An encapsulation layer 180 is provided in the display area AA and the non-display area NA to encapsulate the light-emitting diode D. When the light-emitting diode D is exposed to moisture or oxygen, pixel shrinkage (shrinkage of the light-emitting area) or defects such as dark spots forming in the light-emitting area may occur. Furthermore, moisture or oxygen can oxidize electrodes made of metallic components. The encapsulation layer 180 prevents moisture and oxygen from penetrating from the outside to prevent defects in the light-emitting diode D and its various electrodes.

[0143] In one embodiment, the encapsulation layer 180 may include, but is not limited to, a first encapsulation layer 182, a second encapsulation layer 184, and a third encapsulation layer 186. In another embodiment, the encapsulation layer 180 may include two, four, or more layers.

[0144] In one embodiment, each of the first encapsulation layer 182 and the third encapsulation layer 186 may include inorganic materials such as silicon oxide (SiOx, where 0 < x ≤ 2) and silicon nitride (SiNx, where 0 < x ≤ 2). Each of the first encapsulation layer 182 and the third encapsulation layer 186 may have a single-layer structure or a multi-layer structure. In another embodiment, each of the first encapsulation layer 182 and the third encapsulation layer 186 may further include at least one organic layer disposed between the inorganic layers. The second encapsulation layer 184 may include an epoxy resin. However, embodiments of this disclosure are not limited thereto.

[0145] Although Figure 6A and Figure 6B Although not shown, a touch component may be disposed on the encapsulation layer 180. The touch component may be disposed in the display area AA and sense touch input. The touch component may use a user's finger or stylus to sense external touch information.

[0146] Figure 7 The diagram illustrates the line arrangement in the display area AA of a display device 200 according to another embodiment of this disclosure. In this embodiment of the display device 200, only the arrangement of the horizontal connecting lines HLINK and the vertical connecting lines VLINK differs from those of the display device 100 in the first embodiment; the other configurations are the same as those of the display device 100. Therefore... Figure 7 Only the arrangement of the horizontal HLINK and vertical VLINK is shown. Specifically, the second and third regions, located on either side of the first region A1 of the display area AA, are symmetrical with respect to the first region A1, such that the arrangement of the horizontal HLINK and vertical VLINK in the second and third regions is identical to each other. Therefore, for ease of description, in... Figure 7 Only the first region A1 and the second region A2 of the display area AA are shown.

[0147] Reference Figure 7 In the first region A1 of the display area AA of the display device 200, multiple first data lines DL1 and multiple vertical connecting lines VLINK are arranged along the second direction (vertical direction, y-axis direction). In the second region A2 of the display area AA, multiple second data lines DL2 extending in the second direction are arranged. In this embodiment, the vertical connecting lines VLINK are not arranged in the second region A2.

[0148] The multiple first data lines DL1 arranged in the first region A1 are all formed to have the same length from the bottom to the top of the display area AA. Conversely, the multiple second data lines DL2 arranged in the second region A2 have a length that decreases from the central region to the outside, that is, from the boundary of the first region A1 to the left end.

[0149] Multiple horizontal lines HLINK are set along the first direction (horizontal direction, x-axis direction) in the first area A1 and the second area A2 of the display area AA.

[0150] The horizontal connection HLINK is electrically connected to the vertical connection VLINK in the first region A1 via the first contact hole CNT1. An insulating layer is formed between the horizontal connection HLINK and the second data line DL2 to electrically connect them to each other via the second contact hole CNT2.

[0151] The leftmost vertical connection VLINK in the first region A1 can be electrically connected via the horizontal connection HLINK to the closest second data line DL2 arranged in the second region A2, that is, the rightmost second data line DL2 in the second region A2. Furthermore, the second vertical connection VLINK from the leftmost position in the first region A1 can be electrically connected via the horizontal connection HLINK to the second second data line DL2 from the rightmost position in the second region A2, but this is not a limitation.

[0152] The data signal is directly applied to each first data line DL1 in the first region A1 of the display area AA to supply the data signal to multiple sub-pixels SP1, SP2, and SP3 corresponding to the sub-pixel columns in the first region A1. The data signal is applied to each second data line DL2 in the second region A2 of the display area AA through the vertical connection VLINK and the horizontal connection HLINK to provide the data signal to multiple sub-pixels SP1, SP2, and SP3 corresponding to the sub-pixel columns in the second region A2.

[0153] In the display device 200 of this disclosure, a data signal is provided to a region that is a curved area BA and a second non-display area NA2. Figure 4 The lines connecting sub-pixels SP1, SP2, and SP3 in the outer display area AA, in the first direction of the width direction, are arranged in the display area AA, not in the non-display area NA. Figure 4 In ), the border area can be minimized.

[0154] In one embodiment, according to the display device 200, the multiple horizontal interconnects HLINK provided in the display area DA are not arranged with equal spacing. In the freeform or non-rectangular display device 200, since differences in storage capacitance occur between data lines DL with different lengths, the differences in storage capacitance are compensated by changing the length of the vertical interconnects VLINK connected to the data lines DL according to the length of the data lines DL.

[0155] In other words, the difference in storage capacitance can be compensated by setting the length of the vertical connection line to be inversely proportional to the length of the second data line DL2. For example, the vertical connection line VLINK connected to the outermost second data line DL2 located in the second region A2 is the longest, and the length of the vertical connection line VLINK gradually decreases from the outermost part of the second region A2 to the first region A1.

[0156] In other words, depending on the length of the second data line DL2, the difference in storage capacitance can be compensated by increasing the distance "d" between the horizontal connection HLIN that connects to the vertical connection VLINKK and the second data line DL2. For example, as the lengths of multiple second data lines DL2 decrease, the difference in storage capacitance can be compensated by adjusting the distance "d" between the horizontal connections HLINK that each electrically connects to the corresponding second data line DL2.

[0157] While the circular display device described above applies to freeform or non-rectangular display devices such as watches, this disclosure is not limited to display devices having this specific shape. In one embodiment, the first region A1 may be a rectangular region, and the second region A2 may be a non-rectangular (circular) region, but is not limited thereto.

[0158] This disclosure can be applied to display devices with various shapes other than square or rectangular shapes, or display devices with freeform or non-rectangular partial areas. For example, when some areas have freeform or non-rectangular shapes, the length of the data lines in the freeform areas is reduced, and the storage capacitance of the data lines in the freeform or non-rectangular areas can be compensated for by horizontal and vertical connections provided in the freeform areas. In one embodiment, the first area A1 can be a rectangular area, and the second area A2 can be a non-rectangular area, but is not limited thereto.

[0159] It will be apparent to those skilled in the art that various modifications and variations may be made to this disclosure without departing from its scope. Therefore, this disclosure is intended to cover modifications and variations thereof, provided they fall within the scope of the appended claims and their equivalents.

Claims

1. A display device, comprising: The display panel includes a first region and at least one second region; Multiple gate lines, the multiple gate lines being along a first direction in the first region and the second region; Multiple first data lines are arranged in the first region along a second direction perpendicular to the first direction; Multiple second data lines are arranged in the second region along the second direction and have a length shorter than that of the first data line; Multiple vertical connecting lines are arranged along the second direction in the first region; as well as Multiple horizontal lines are connected, and these horizontal lines are arranged along the first direction in the first region and the second region. Each vertical connection is electrically connected to a corresponding second data line via a horizontal connection, and Each vertical line has a length inversely proportional to the length of the second data line to be connected.

2. The display device according to claim 1, wherein the data signal is applied directly to each first data line, and the data signal is applied to each second data line through the vertical connection and the horizontal connection.

3. The display device according to claim 1, further comprising: The first contact hole electrically connects each vertical wire to the corresponding horizontal wire. and The second contact hole electrically connects each horizontal wire to the corresponding second data line.

4. The display device according to claim 3, further comprising: Thin-film transistors, wherein the thin-film transistors are respectively disposed in the first region and the second region; and A light-emitting diode, wherein the light-emitting diode is disposed on the thin-film transistor.

5. The display device according to claim 4, wherein the thin-film transistor comprises: A semiconductor layer disposed on a substrate; A gate electrode, wherein the gate electrode is disposed on the semiconductor layer; and A source electrode and a drain electrode are disposed on the gate electrode.

6. The display device according to claim 5, further comprising: A gate insulating layer is disposed between the semiconductor layer and the gate electrode; An interlayer insulating layer is disposed between the gate electrode and the source electrode and the drain electrode; A planarization layer is disposed on the source electrode and the drain electrode; and A connection pattern is disposed on the planarization layer and connected to one of the source electrode and the drain electrode.

7. The display device according to claim 6, wherein the vertical connecting lines are arranged on the planarization layer and the horizontal connecting lines are arranged on the interlayer insulating layer.

8. The display device according to claim 7, wherein the vertical connecting line comprises the same material as the connecting pattern.

9. The display device of claim 7, wherein the horizontal interconnect comprises the same material as the source electrode and the drain electrode.

10. The display device of claim 7, wherein each vertical line is electrically connected to the corresponding horizontal line through the first contact hole disposed in the planarization layer.

11. The display device of claim 3, wherein the vertical connection extends a predetermined distance from the first contact hole, and the extension distance of the vertical connection is inversely proportional to the length of the second data line to be connected.

12. The display device according to claim 1, wherein the distance between the horizontal lines connected to the second data line increases as the length of the second data line decreases.

13. The display device according to claim 1, wherein the display panel has a free form.

14. The display device according to claim 13, wherein the first region is a rectangular region and the second region is a non-rectangular region.

15. The display device according to claim 1, wherein the display panel has a circular shape.

16. The display device according to claim 15, wherein the first region is the central region of the circular shape, and the second region is the two side regions of the central region.

17. The display device according to claim 1, wherein the vertical connecting line is not arranged in the second region.

18. The display device according to claim 1, wherein the plurality of first data lines are formed to have the same length.

19. The display device of claim 16, wherein the length of the second data line decreases from the central region toward the outside.

20. The display device of claim 16, wherein the second region comprises a left second region and a right second region located to the left and right of the central region, respectively, and The leftmost vertical line in the first region is electrically connected to the rightmost second data line in the leftmost second region via the horizontal line.

21. The display device according to claim 20, wherein a second vertical line disposed from the leftmost side of the first region is electrically connected via the horizontal line to a second data line disposed from the rightmost side of the second left region.

22. The display device according to claim 1, wherein the first region and the second region are display regions, and A curved region and a second non-display region are formed at the lower end of the first non-display region surrounding the display area.

23. The display device according to claim 22, wherein a plurality of data connections and a plurality of signal connections are provided in the second non-display area and the curved area, and The plurality of data lines are electrically connected to the plurality of first data lines, and the plurality of signal lines are electrically connected to the plurality of vertical lines.

24. A display device, comprising: The display panel includes a first region and at least one second region; Multiple gate lines, the multiple gate lines being along a first direction in the first region and the second region; Multiple first data lines are arranged in the first region along a second direction perpendicular to the first direction; Multiple second data lines are arranged in the second region along the second direction and have a length shorter than that of the first data line; Multiple vertical connecting lines are arranged along the second direction in the first region; Multiple horizontal lines are arranged along the first direction in the first region and the second region; as well as Multiple compensation lines extend from the multiple perpendicular lines. Each vertical connection is electrically connected to a corresponding second data line via a horizontal connection, and Each compensation line has a length inversely proportional to the length of the second data line to be connected.

25. A display device, comprising: The display panel includes a first region and at least one second region; Multiple gate lines, the multiple gate lines being along a first direction in the first region and the second region; Multiple first data lines are arranged in the first region along a second direction perpendicular to the first direction; Multiple second data lines are arranged in the second region along the second direction and have a length shorter than that of the first data line; Multiple vertical connecting lines are arranged along the second direction in the first region; as well as Multiple horizontal lines are connected, and these horizontal lines are arranged along the first direction in the first region and the second region. The distance between the horizontal lines is inversely proportional to the length of the second data line to which the horizontal lines are to be connected.

Images