Display device

Abstract

According to one aspect of the present invention, a display device includes: a substrate including an active region, a first non-active region surrounding the active region, a curved region extending from and bending from the first non-active region, and a second non-active region extending from the curved region; a plurality of light-emitting diodes disposed in the active region on the substrate; a touch sensing unit disposed above the plurality of light-emitting diodes; a first planarization layer disposed on the touch sensing unit; a first weir disposed in the first non-active region and surrounding the active region; a second planarization layer disposed on the first weir and the first planarization layer; and a second weir disposed along the boundary between the first non-active region and the curved region in the first non-active region, wherein the second weir and the first planarization layer are formed of the same material on the same layer.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0195981, filed on December 24, 2024, the disclosure of which is incorporated herein by reference. Technical Field

[0003] The present invention relates to a display device, and more specifically, to a display device that minimizes the amount of organic material used to flatten the upper part of the display device so as to avoid excessive coating on the curved areas. Background Technology

[0004] With the advent of the information age, the field of display devices that visually express electrical information signals has developed rapidly, and research continues to improve the performance of various display devices, such as thinness, light weight and low power consumption.

[0005] Representative display devices may include liquid crystal displays (LCDs), field-emitting diode (FED) displays, electrowetting displays (EWDs), and organic light-emitting diode (OLEDs).

[0006] Electroluminescent displays, represented by organic light-emitting diodes (OLEDs), are self-emissive, eliminating the need for a separate light source, unlike liquid crystal displays (LCDs). Therefore, OLEDs can be manufactured with light weight and thin profiles. Furthermore, OLEDs are expected to be used in various fields because they are advantageous not only in terms of power consumption due to low-voltage driving, but also in terms of color reproduction, response speed, viewing angle, and contrast ratio (CR). Summary of the Invention

[0007] One objective of this invention is to provide a display device that minimizes the amount of organic material used to planarize the upper part of the display device to avoid excessive coating on the curved areas.

[0008] Another objective of this invention is to provide a display device that expands the space for accommodating over-coated organic materials.

[0009] Another objective of this invention is to provide a low-power display device in which the over-coating of organic materials in the bending region is minimized to improve lifespan, thereby improving the reliability of the display device and reducing power consumption.

[0010] The purpose of this invention is not limited to the purposes mentioned above, and those skilled in the art will clearly understand from the following description other purposes not mentioned above.

[0011] According to one aspect of the present invention, a display device includes: a substrate, the substrate including an active region, a first non-active region surrounding the active region, a curved region extending from and bending from the first non-active region, and a second non-active region extending from the curved region; a plurality of light-emitting diodes disposed in the active region on the substrate; a touch sensing unit disposed above the plurality of light-emitting diodes; a first planarization layer disposed on the touch sensing unit; a first weir disposed in the first non-active region and surrounding the active region; a second planarization layer disposed on the first weir and the first planarization layer; and a second weir disposed along the boundary between the first non-active region and the curved region in the first non-active region, wherein the second weir and the first planarization layer are formed of the same material on the same layer.

[0012] According to another aspect of the present invention, a display device includes: a substrate, the substrate including an active region having a plurality of sub-pixels, a first non-active region surrounding the active region, and a curved region extending from and curved from the first non-active region; a plurality of light-emitting diodes, the light-emitting diodes being disposed on the substrate in each of the plurality of sub-pixels; a touch sensing unit disposed above the plurality of light-emitting diodes; a first planarization layer disposed on the touch sensing unit; a first weir, the first weir being disposed in the first non-active region and surrounding the active region; a second planarization layer, the second planarization layer being disposed on the first weir and the first planarization layer; and a second weir, the second weir being disposed along the boundary of the first non-active region and the curved region in the first non-active region, wherein the second weir and the first planarization layer are formed of the same material on the same layer.

[0013] Further details of exemplary embodiments are included in the detailed description and accompanying drawings.

[0014] In the display device of the present invention, the over-coating of organic materials in the bending area is minimized, thereby improving the reliability of the display device.

[0015] In the display device of the present invention, the space for accommodating over-coated organic material is expanded, thereby further minimizing the over-coating of organic material.

[0016] In the display device according to the invention, the over-coating of organic materials in the bending area is minimized, thereby improving the reliability and lifespan of the display device, and thus achieving a low-power display device with reduced power consumption.

[0017] The effects of the present invention are not limited to those illustrated above; many more effects are included in the present invention. Attached Figure Description

[0018] The above and other aspects, features and advantages of the present invention will become more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, wherein:

[0019] Figure 1A This is a plan view of a mother substrate used in a manufacturing method for a display device according to an exemplary embodiment of the present invention;

[0020] Figure 1B yes Figure 1A An enlarged plan view of region B;

[0021] Figure 1C This is a plan view of a display device according to an exemplary embodiment of the present invention;

[0022] Figure 1D yes Figure 1C A magnified plan view of region E;

[0023] Figure 2 It is along Figure 1A A cross-sectional view taken by line A-A';

[0024] Figure 3A It is along Figure 1B A cross-sectional view taken from line C-C';

[0025] Figure 3B It is along Figure 1D A cross-sectional view taken by line F-F';

[0026] Figure 4A It is along Figure 1B A cross-sectional view taken from line D-D';

[0027] Figure 4B It is along Figure 1D A cross-sectional view taken from line G-G';

[0028] Figure 5 It is along Figure 1D A cross-sectional view taken by line H-H';

[0029] Figure 6 yes Figure 1A An enlarged plan view of region I;

[0030] Figure 7 It is along Figure 6 The cross-sectional view taken from line J-J'. Detailed Implementation

[0031] The advantages and features of the present invention, as well as the methods for achieving these advantages and features, will become apparent from the exemplary embodiments described in detail below together with the accompanying drawings. However, the invention is not limited to the exemplary embodiments disclosed herein, but will be implemented in various forms. The exemplary embodiments are provided by way of example only, so that those skilled in the art can fully understand the disclosure and scope of the invention.

[0032] The shapes, dimensions, ratios, angles, quantities, etc., shown in the accompanying drawings used to describe exemplary embodiments of the present invention are merely examples, and the invention is not limited thereto. Throughout the specification, similar reference numerals generally denote similar elements. Furthermore, in the following description of the invention, detailed explanations of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of the invention. Terms such as “comprising,” “having,” and “including” as used herein are generally intended to allow for the addition of additional components, unless these terms are used in conjunction with the term “only.” Unless explicitly stated otherwise, any reference to the singular may include the plural.

[0033] Even if not explicitly stated, the components are interpreted as including the normal error range.

[0034] When using terms such as “on top of,” “above,” “below,” and “next” to describe the positional relationship between two parts, one or more parts may be located between the two parts, unless these terms are used with the terms “immediately” or “directly.”

[0035] When one element or layer is disposed "on" another element or layer, other layers or other elements may be inserted between them, or the element or layer may be disposed directly on another element or layer.

[0036] Although the terms "first," "second," etc., are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from other components. Therefore, within the scope of the inventive concept, the first component mentioned below can be the second component.

[0037] Throughout the specification, the same reference numerals generally denote the same elements.

[0038] For ease of description, the dimensions and thickness of each component shown in the accompanying drawings are illustrated. However, the invention is not limited to the dimensions and thickness of the illustrated components.

[0039] The features of the various embodiments of the present invention may be partially or entirely attached or combined with each other, and may be technically interlocked and operated in various ways. The embodiments may be implemented independently or in conjunction with each other.

[0040] In the following, various embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0041] Figure 1A This is a plan view of a mother substrate used in a method for manufacturing a display device according to an exemplary embodiment of the present invention. Figure 1B yes Figure 1A A magnified plan view of region B. Figure 1C This is a plan view of a display device according to an exemplary embodiment of the present invention. Figure 1D yes Figure 1C A magnified plan view of region E. Figure 1A This is a plan view of the mother substrate SUB before the trimming process in the manufacturing method of the display device. Figure 1C This is a plan view of the substrate 110 after the finishing process.

[0042] Display device 100 is a device for displaying images to a user. Display device 100 includes display elements for displaying images, driving elements for driving the display elements, and wiring for transmitting various signals to the display elements and driving elements.

[0043] Depending on the type of display device 100, the display element can be defined in different ways. For example, when the display device 100 is an organic light-emitting display device, the display element can be an organic light-emitting diode (OLED) comprising an anode, an organic light-emitting layer, and a cathode. For example, when the display device 100 is a liquid crystal display device, the display element can be a liquid crystal display element. In the following, it is assumed that the display device 100 is an organic light-emitting display device, but the display device 100 is not limited to organic light-emitting display devices.

[0044] Reference Figures 1A to 1D During the manufacturing process of the display device 100, a step of forming the substrate 110 by performing a trimming process on the mother substrate SUB can be performed. For example, the trimming process can be a laser cutting process or a scribing process that applies physical force directly to the mother substrate SUB using a tool such as a cutter. The trimming process can be performed along a predetermined trimming line a.

[0045] The substrate 110 is a component for supporting various components included in the display device 100 and may be formed of an insulating material. Meanwhile, the substrate 110 is configured to support the lowermost part of the display device 100, so the substrate may also be referred to as the lower substrate, but is not limited thereto.

[0046] The substrate 110 includes an active region AA and an inactive region.

[0047] The active area AA is the area on the substrate 110 where an image is displayed. In the active area AA, multiple sub-pixels SP constituting multiple pixels and driving circuits for driving the multiple sub-pixels SP can be provided.

[0048] Multiple sub-pixels SP are the smallest units constituting the active region AA, and display elements can be disposed in each of the multiple sub-pixels SP. For example, an organic light-emitting diode (OLED) including an anode, an organic light-emitting layer, and a cathode can be disposed in each of the multiple sub-pixels SP, but is not limited thereto. The organic light-emitting diode can be disposed in the active region AA on the substrate 110. Furthermore, the driving circuit for driving the multiple sub-pixels SP can include driving elements and wiring. For example, the driving circuit can be composed of thin-film transistors, storage capacitors, gate lines, and data lines, but is not limited thereto.

[0049] The passive region is the area in which no image is displayed. The passive region may refer to the outer portion of the substrate 110 surrounding the active region AA. The passive region may overlap with the black matrix. Various wiring and circuits for driving the organic light-emitting diodes in the active region AA are provided in the passive region. For example, connection lines for transmitting signals to multiple sub-pixels SP and driving circuits of the active region AA, or driving ICs D-ICs such as gate driver ICs or data driver ICs, may be provided in the passive region, but it is not limited to these.

[0050] The non-active region includes the first non-active region NA1, the curved region BA, and the second non-active region NA2.

[0051] The first non-active region NA1 is the region surrounding and extending from the active region AA. The curved region BA can extend from one side of the first non-active region NA1 and is curved. The second non-active region NA2 extends from the curved region BA and is located below the active region.

[0052] At the same time, refer to Figure 1A and Figure 1C The first non-active region NA1 and the second non-active region NA2 may be disposed on the same plane as the active region AA, or may be disposed parallel to the active region AA and kept flat. For example, the first non-active region NA1 may be disposed on the same plane as the active region AA and be flat, and the second non-active region NA2 may be disposed below the active region AA, parallel to the active region AA, and be flat. Therefore, the active region AA, the first non-active region NA1, and the second non-active region NA2 may be referred to as, for example, non-curved regions, but are not limited thereto.

[0053] Reference Figure 1A and Figure 1CThe driver IC D-IC is located in the second non-active area NA2. The driver IC D-IC can provide data signals to multiple sub-pixels SP. For example, the driver IC D-IC samples and latches the data signal provided by the timing controller in response to a data timing control signal provided by the timing controller, converting the data signal into a gamma reference voltage and outputting the converted gamma reference voltage. The driver IC D-IC can output data signals through multiple data lines. For example, in the second non-active area NA2 where the driver IC D-IC is located, pad units are provided, and a printed circuit board electrically connected to the pad units is also provided to provide signals to the driver IC D-IC, but this is not limited to this.

[0054] Meanwhile, the driver IC D-IC is disposed on one side of the display panel in a chip-on-panel (COP) manner to connect to the display panel, or disposed in a separate flexible film in a chip-on-film (COF) manner to connect to the substrate 110. In the display device 100 according to an exemplary embodiment of the present invention, it is assumed that the driver IC D-IC is disposed in a COP manner, but it is not limited thereto.

[0055] At this time, when the substrate 110 is bent, the driver IC D-IC disposed in the second non-active region NA2 can be positioned below the active region AA. For example, the printed circuit board of the pad unit connected to the substrate 110 and the driver IC D-IC can be moved to the rear surface of the substrate 110 and overlap with the active region AA. Therefore, circuit elements such as the driver IC D-IC and the printed circuit board may not be visible from the top of the substrate 110. Thus, the size of the non-active region visible from the top of the substrate 110 is reduced, thereby achieving a narrow bezel.

[0056] Even if not shown in the accompanying drawings, a through-hole may be provided in the active area AA. For example, in the area of ​​the active area AA where a through-hole is provided, no image may be displayed. The through-hole may be a hole passing through the substrate 110. A through-hole may be formed to cover a camera or light sensor. Therefore, in the display device 100, a through-hole is provided in the active area AA to reduce the bezel area that is a non-active area and to maximize the active area AA. As described above, a product with a design that maximizes the active area AA is preferred both aesthetically and practically by maximizing the user's screen immersion.

[0057] Reference Figures 1A to 1D In the first non-active region NA1, a second weir DAM2 is disposed in the region adjacent to the curved region BA. The second weir DAM2 is disposed in the first non-active region NA1 along the boundary between the first non-active region NA1 and the curved region BA. The second weir DAM2 can restrict the position of the planarization layer so as not to allow the planarization layer used to planarize the upper part of the components of the display device 100 to overflow into the curved region BA in the active region AA and the first non-active region NA1.

[0058] At the same time, refer to Figure 1A Before the finishing process, a second weir, DAM2, can be set to extend straight across one side of the mother substrate SUB along the boundary of the first non-active region NA1 and the bent region BA. (Refer to...) Figure 1C After the finishing process, the second weir DAM2 can be partially removed so that it is only located in the area adjacent to the bending zone BA. The following will refer to Figures 3 to... Figure 7 The second weir, DAM2, after the repair process is described in detail.

[0059] In the following text, we will refer to... Figure 2 Describe the cross-sectional structure of the active region AA.

[0060] Figure 2 It is along Figure 1A A cross-sectional view taken from line A-A'. Figure 2 This is a cross-sectional view showing the cross-sectional structure of a sub-pixel SP disposed in the active region AA according to an exemplary embodiment of the present invention.

[0061] Reference Figure 2 In a display device 100 according to an exemplary embodiment of the present invention, in the active region AA, a substrate 110, a light-shielding layer LS, a first buffer layer 111, a first thin-film transistor TR1, a second thin-film transistor TR2, a first gate insulating layer 112a, a first interlayer insulating layer 113a, a second buffer layer 114, a second gate insulating layer 112b, a second interlayer insulating layer 113b, a connecting electrode CE, a first planarization layer 115a, a second planarization layer 115b, an auxiliary electrode AE, a dam 116a, a spacer 116b, a light-emitting diode 120, a packaging unit 117, a touch buffer layer 118a, a touch sensing unit, a touch interlayer insulating layer 118b, a third planarization layer 118c, and a fourth planarization layer 119 are disposed.

[0062] The substrate 110 is used to support and protect the components of the display device 100 disposed thereon.

[0063] The substrate 110 is a component for supporting various components included in the display device 100 and may be formed of an insulating material. Meanwhile, the substrate 110 is configured to support the lowermost part of the display device 100, so the substrate may also be referred to as the lower substrate, but is not limited thereto.

[0064] The substrate 110 may include a first substrate 110a, a second substrate 110b, and an interlayer insulating film 110c. The interlayer insulating film 110c may be disposed between the first substrate 110a and the second substrate 110b. As described above, the substrate 110 is composed of the first substrate 110a, the second substrate 110b, and the interlayer insulating film 110c to suppress moisture penetration. However, the substrate 110 may be configured as a single layer, but is not limited thereto.

[0065] For example, the first substrate 110a and the second substrate 110b may be polyimide (PI) substrates, and the interlayer insulating film 110c may be formed from a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or multiple layers thereof.

[0066] Interlayer insulating film 110c may not be provided in at least some regions. For example, interlayer insulating film 110c may not be formed in stress concentration regions such as bending region BA or the outermost region.

[0067] A light-shielding layer LS may be disposed on the substrate 110. The light-shielding layer LS is a protective layer formed of metal disposed beneath semiconductor layers A1 and A2 of multiple transistors TR1 and TR2 to shield external light in the display device 100. The light-shielding layer LS can minimize damage to semiconductor layers A1 and A2 caused by external light.

[0068] The first buffer layer 111 can be disposed on the substrate 110 while covering the light-shielding layer LS. Specifically, the multi-buffer layer 111a can be disposed on the substrate 110 while covering the light-shielding layer LS, and the active buffer layer 111b can be disposed on the multi-buffer layer 111a.

[0069] The multiple buffer layer 111a can delay the diffusion of moisture or oxygen into the substrate 110, and includes at least one of silicon nitride SiNx and silicon oxide SiOx.

[0070] The active buffer layer 111b can protect the first semiconductor layer A1 and block various types of defects introduced from the substrate 110. For example, the active buffer layer 111b may include at least one of amorphous silicon (a-Si), silicon nitride SiNx, and silicon oxide SiOx.

[0071] The first thin-film transistor TR1 may be disposed on the first buffer layer 111. The first thin-film transistor TR1 may include a first semiconductor layer A1, a first gate G1, a first source S1, and a first drain D1. Here, depending on the design of the pixel circuit, the first source S1 may be used as the first drain, and the first drain D1 may be used as the first source.

[0072] A first semiconductor layer A1 may be disposed on the first buffer layer 111 to overlap with the light-shielding layer LS. The first semiconductor layer A1 may include amorphous silicon or polycrystalline silicon. For example, the first semiconductor layer A1 may include low-temperature polycrystalline silicon (LTPS). For example, polycrystalline silicon materials have high mobility (100 cm⁻¹). 2 ( / Vs or higher), resulting in low power consumption and excellent reliability. Therefore, according to an exemplary embodiment, polycrystalline silicon material can be applied to the gate driver used in driving elements to drive thin-film transistors and / or multiplexers (MUX) used in display elements, and also serves as the first semiconductor layer A1 for driving thin-film transistors in display device 100, but is not limited thereto. For example, depending on the characteristics of display device 100, polycrystalline silicon material can also be used as the second semiconductor layer A2 for switching thin-film transistors. Amorphous silicon (a-Si) material is deposited on the first buffer layer 111, and a dehydrogenation process and a crystallization process are performed to form polycrystalline silicon, and the polycrystalline silicon is patterned to form the first semiconductor layer A1.

[0073] Here, the first semiconductor layer A1 may include a first channel region forming a channel therein when the first thin-film transistor TR1 is driven, and a first source region and a first drain region on both sides of the first channel region. The first source region refers to the portion of the first semiconductor layer A1 connected to the first source S1, and the first drain region refers to the portion of the first semiconductor layer A1 connected to the first drain D1. For example, the first source region and the first drain region may be configured by ion doping (impurity doping) of the first semiconductor layer A1. The first source region and the first drain region may be generated by implanting ions into polycrystalline silicon material, and the first channel region may refer to the portion that is not doped with ions but is retained as polycrystalline silicon material.

[0074] A first gate insulating layer 112a may be disposed on the first semiconductor layer A1. The first gate insulating layer 112a may be composed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or multiple layers thereof. Contact holes may be formed in the first gate insulating layer 112a for connecting the first source S1 and the first drain D1 of the first thin-film transistor TR1 to the first source region and the first drain region of the first semiconductor layer A1 of the first thin-film transistor TR1, respectively.

[0075] The first gate G1 of the first thin-film transistor TR1 and the first capacitor electrode C1 of the storage capacitor Cst can be disposed on the first gate insulating layer 112a.

[0076] At this time, the first gate G1 and the first capacitor electrode C1 can be formed by a single layer or multiple layers of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd) and their alloys. The first gate G1 can be formed on the first gate insulating layer 112a and overlap with the first channel region of the first semiconductor layer A1 of the first thin film transistor TR1.

[0077] The first capacitor electrode C1 may be omitted based on the driving characteristics of the display device 100 and the structure and type of the thin-film transistor. The first gate G1 and the first capacitor electrode C1 can be formed using the same process. Furthermore, the first gate G1 and the first capacitor electrode C1 can be formed on the same layer using the same material.

[0078] A first interlayer insulating layer 113a may be disposed above the first gate insulating layer 112a, the first gate G1, and the first capacitor electrode C1. The first interlayer insulating layer 113a may be a single layer of silicon nitride (SiNx) or silicon oxide (SiOx), or a multilayer thereof. Contact holes for exposing the first source region and the first drain region of the first semiconductor layer A1 of the first thin-film transistor TR1 may be formed in the first interlayer insulating layer 113a.

[0079] The second capacitor electrode C2 of the storage capacitor Cst may be disposed on the first interlayer insulating layer 113a. The second capacitor electrode C2 may be formed from a single layer or multiple layers of any one or more of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd) and their alloys. The second capacitor electrode C2 may be formed on the first interlayer insulating layer 113a to overlap with the first capacitor electrode C1. Furthermore, the second capacitor electrode C2 may be formed from the same material as the first capacitor electrode C1. The second capacitor electrode C2 may be omitted based on the driving characteristics of the display device 100 and the structure and type of the thin-film transistor.

[0080] A second buffer layer 114 may be disposed on the first interlayer insulating layer 113a and the second capacitor electrode C2. The second buffer layer 114 may be composed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or multiple layers thereof. Contact holes for exposing the first source region and the first drain region of the first semiconductor layer A1 of the first thin-film transistor TR1 may be formed in the second buffer layer 114. In addition, contact holes for exposing the second capacitor electrode C2 of the storage capacitor Cst may be formed in the second buffer layer 114.

[0081] The second buffer layer 114 may be formed by multiple layers, but is not limited to this.

[0082] The second semiconductor layer A2 of the second thin-film transistor TR2 may be disposed on the second buffer layer 114. Here, the second thin-film transistor TR2 may include the second semiconductor layer A2, the second gate insulating layer 112b, the second gate G2, the second source S2, and the second drain D2. Here, depending on the pixel circuit design, the second source S2 may be used as the drain, and the second drain D2 may be used as the source.

[0083] Furthermore, the second semiconductor layer A2 may include a second channel region forming a channel when the second thin-film transistor TR2 is driven, and a second source region and a second drain region on both sides of the second channel region. The second source region may refer to the portion of the second semiconductor layer A2 connected to the second source S2, and the second drain region may refer to the portion of the second semiconductor layer A2 connected to the second drain D2.

[0084] The second semiconductor layer A2 can be formed of oxide semiconductor. Oxide semiconductor materials have a larger band gap than silicon materials, preventing electrons from jumping across the band gap in the off state. Therefore, oxide semiconductor materials have low cutoff current. Thus, thin-film transistors including semiconductor layers formed of oxide semiconductors are suitable for, but not limited to, switching thin-film transistors that maintain a short on-time and a long off-time.

[0085] According to the characteristics of the display device 100, a thin-film transistor including a semiconductor layer formed of oxide semiconductor can be used as a driving thin-film transistor. Furthermore, due to the smaller cutoff current, the size of the auxiliary capacitor can be reduced, making oxide semiconductor suitable for high-resolution display elements. For example, the second semiconductor layer A2 can be formed of a metal oxide, and can be formed of various metal oxides such as indium gallium zinc oxide (IGZO). Here, among various metal oxides, it is assumed that the second semiconductor layer A2 of the second thin-film transistor TR2 is composed of IGZO, but it is not limited thereto. Therefore, the second semiconductor layer A2 can be formed of other metal oxides such as indium zinc oxide (IZO), indium gallium tin oxide (IGTO), or indium gallium oxide (IGO) instead of IGZO.

[0086] The second semiconductor layer A2 can be formed by depositing a metal oxide on the second buffer layer 114, performing a heat treatment for stabilization, and then patterning the metal oxide.

[0087] The second gate insulating layer 112b may be disposed on the entire substrate 110 including the second semiconductor layer A2. For example, the second gate insulating layer 112b may be composed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or multiple layers thereof.

[0088] The second gate G2 may be disposed on the second gate insulating layer 112b.

[0089] The second gate G2 may be formed from a single layer or multiple layers of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni) and neodymium (Nd) and their alloys.

[0090] For example, a metal material is formed on the second gate insulating layer 112b, a photoresist pattern is formed on the metal material, and then the metal material is wet-etched using the photoresist pattern as a mask to form the second gate G2. As a wet etchant for etching the metal material, a material that selectively etches molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd) or alloys thereof constituting the metal material can be used, but not the insulating material.

[0091] The second interlayer insulating layer 113b may be disposed on the second gate insulating layer 112b and the second gate G2. Contact holes for exposing the first semiconductor layer A1 of the first thin-film transistor TR1 and the second semiconductor layer A2 of the second thin-film transistor TR2 may be formed in the second interlayer insulating layer 113b. For example, contact holes for exposing the first source region and the first drain region of the first semiconductor layer A1 of the first thin-film transistor TR1 may be formed in the second interlayer insulating layer 113b. Contact holes for exposing the second source region and the second drain region of the second semiconductor layer A2 of the second thin-film transistor TR2 may be formed in the second interlayer insulating layer 113b.

[0092] The second interlayer insulating layer 113b can be configured as a single layer of silicon nitride SiNx or silicon oxide SiOx or multiple layers thereof.

[0093] The connecting electrode CE, the first source S1 and the first drain D1 of the first thin film transistor TR1, and the second source S2 and the second drain D2 of the second thin film transistor TR2 can be disposed on the second interlayer insulating layer 113b.

[0094] The connection electrode CE can be electrically connected to the second drain D2 of the second thin-film transistor TR2. Furthermore, the connection electrode CE can be electrically connected to the second capacitor electrode C2 of the storage capacitor Cst through contact holes formed in the second buffer layer 114 and the second interlayer insulating layer 113b. In other words, the connection electrode CE can be used to electrically connect the second capacitor electrode C2 of the storage capacitor Cst and the second drain D2 of the second thin-film transistor TR2 to each other.

[0095] Here, the first source S1 and the first drain D1 of the first thin film transistor TR1 can be connected to the first semiconductor layer A1 of the first thin film transistor TR1 through contact holes formed in the first gate insulating layer 112a, the first interlayer insulating layer 113a, the second buffer layer 114 and the second interlayer insulating layer 113b.

[0096] The second source S2 and the second drain D2 of the second thin-film transistor TR2 can be connected to the second semiconductor layer A2 through a contact hole formed in the second gate insulating layer 112b.

[0097] The connecting electrode CE, the first source S1 and the first drain D1 of the first thin film transistor TR1, and the second source S2 and the second drain D2 of the second thin film transistor TR2 can be formed from the same material using the same process.

[0098] For example, the connecting electrode CE, the first source S1 and the first drain D1 of the first thin-film transistor TR1, and the second source S2 and the second drain D2 of the second thin-film transistor TR2 can be formed from a single layer or multiple layers of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd) and their alloys. For example, the connecting electrode CE, the first source S1 and the first drain D1 of the first thin-film transistor TR1, and the second source S2 and the second drain D2 of the second thin-film transistor TR2 can be formed from a titanium (Ti) / aluminum (Al) / titanium (Ti) three-layer structure, but are not limited thereto.

[0099] The connecting electrode CE can be connected to the second drain D2 of the second thin-film transistor TR2 so as to be integrally formed with the second drain D2, but is not limited thereto.

[0100] The first planarization layer 115a may be disposed on the connecting electrode CE, the first source S1 and the first drain D1 of the first thin film transistor TR1, the second source S2 and the second drain D2 of the second thin film transistor TR2, and the second interlayer insulating layer 113b.

[0101] The first planarization layer 115a may be an organic layer used to planarize and protect the upper parts of the first thin-film transistor TR1 and the second thin-film transistor TR2. For example, the first planarization layer 115a may be formed of an organic material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin or polyimide resin.

[0102] An auxiliary electrode AE ​​may be disposed on the first planarization layer 115a. The auxiliary electrode AE ​​may be connected to the second drain D2 of the second thin-film transistor TR2 through contact holes in the first planarization layer 115a. The auxiliary electrode AE ​​may be used to electrically connect the second thin-film transistor TR2 and the anode 121 to each other. The auxiliary electrode AE ​​may be formed of a single layer or multiple layers of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd) and their alloys. The auxiliary electrode AE ​​may be formed of the same material as the second source S2 and the second drain D2 of the second thin-film transistor TR2.

[0103] The second planarization layer 115b may be disposed above the auxiliary electrode AE ​​and the first planarization layer 115a. For example, the second planarization layer 115b may be formed of an organic material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin. The first planarization layer 115a and the second planarization layer 115b may constitute the planarization layer 115.

[0104] The light-emitting diode 120 may be disposed on the second planarization layer 115b. The light-emitting diode 120 includes an anode 121, a light-emitting layer 122, and a cathode 123.

[0105] The anode 121 may be disposed on the second planarization layer 115b. In this case, the anode 121 can be electrically connected to the auxiliary electrode AE ​​through a contact hole disposed in the second planarization layer 115b. The anode 121 may be formed of a metallic material.

[0106] When the display device 100 is a top-emitting type (where light emitted from the light-emitting diode 120 is emitted onto the substrate 110 on which the light-emitting diode 120 is disposed), the anode 121 may include a reflective layer and a transparent conductive layer disposed on the reflective layer. The transparent conductive layer may be formed of a transparent conductive oxide such as indium tin oxide (ITO) or indium zinc oxide (IZO), and the reflective layer may be formed of silver (Ag), aluminum (Al), gold (Au), molybdenum (Mo), tungsten (W), chromium (Cr), or alloys thereof, but is not limited thereto.

[0107] A dam unit 116 is disposed on the anode 121. The dam unit 116 includes a dam section 116a and a spacer 116b.

[0108] The dam 116a may be provided while covering the end of the anode 121. The portion of the dam 116a corresponding to the light-emitting area of ​​the sub-pixel may be open. A portion of the anode 121 may be exposed through the open portion of the dam 116a (hereinafter referred to as the open area). In this case, the dam 116a may be formed of an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx) or an organic insulating material such as benzocyclobutene resin, acrylic resin or imide resin, but is not limited thereto.

[0109] Spacer 116b may be further disposed on embankment 116a. Spacer 116b may be used to maintain a predetermined gap so that the mask is not allowed to contact the substrate during the manufacturing process of the light-emitting layer 122 of the light-emitting diode 120 formed of organic material.

[0110] For example, spacer 116b may be formed of inorganic insulating materials such as silicon nitride (SiNx) or silicon oxide (SiOx) or organic insulating materials such as benzocyclobutene resin, acrylic resin or imide resin, but is not limited thereto.

[0111] A light-emitting layer 122 is disposed on the anode 121, the embankment 116a, and the spacer 116b. The light-emitting layer 122 may be disposed in the opening area of ​​the embankment 116a and near the opening area of ​​the embankment 116a. Therefore, the light-emitting layer 122 may be disposed on the anode 121 exposed through the opening area of ​​the embankment 116a.

[0112] The light-emitting layer 122 may include multiple organic material layers. For example, the light-emitting layer 122 may include organic material layers such as a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer. Furthermore, when the light-emitting layer 122 emits white light, the light emitted from the light-emitting layer 122 can be converted into light of various colors through multiple color filters, but is not limited to these.

[0113] A cathode 123 is disposed on the light-emitting layer 122. The cathode 123 supplies electrons to the light-emitting layer 122, allowing the cathode to be formed of a conductive material with a low work function. The cathode 123 can be formed as a single layer on multiple sub-pixels SP. That is, the cathodes 123 of multiple sub-pixels SP can be connected to form a single unit.

[0114] For example, the cathode 123 may be formed of a transparent conductive material such as indium tin oxide (ITO) and indium zinc oxide (IZO) or ytterbium (Yb) alloy, and may also include, but is not limited to, a metal doped layer.

[0115] The packaging unit 117 is disposed on the light-emitting diode 120.

[0116] The packaging unit 117 may have a single-layer structure or a multi-layer structure. For example, the packaging unit 117 may have a multi-layer structure including a first packaging layer 117a, a second packaging layer 117b, and a third packaging layer 117c. However, the packaging unit may also be formed with a single-layer structure, but is not limited thereto.

[0117] The first encapsulation layer 117a and the third encapsulation layer 117c may be formed of inorganic materials, and the second encapsulation layer 117b may be formed of organic materials. The second encapsulation layer 117b may be the thickest among the first encapsulation layer 117a, the second encapsulation layer 117b, and the third encapsulation layer 117c. The second encapsulation layer 117b may planarize the upper part of the light-emitting diode 120.

[0118] In the packaging unit 117, the first packaging layer 117a may be disposed on the cathode 123 and positioned as the closest to the light-emitting diode 120. For example, the first packaging layer 117a may be composed of silicon nitride (SiNx), silicon oxide (SiOx), silicon oxide nitride (SiON), or aluminum oxide (Al2O3), but is not limited thereto.

[0119] The second encapsulation layer 117b can be formed to have a smaller area than the first encapsulation layer 117a. In this case, the second encapsulation layer 117b can be formed to expose both ends of the first encapsulation layer 117a. The second encapsulation layer 117b can be used to enhance the buffering function to reduce stress between layers caused by the bending of the flexible display device and to enhance the planarization function.

[0120] For example, the second encapsulation layer 117b may be formed of an organic insulating material such as acrylic resin, epoxy resin, polyimide, polyethylene, or silicon carbide (SiOC). For example, the second encapsulation layer 117b may be formed by an inkjet printing method, but is not limited thereto.

[0121] The third encapsulation layer 117c may be formed above the substrate 110 on which the second encapsulation layer 117b is formed, so as to cover the upper and side surfaces of the second encapsulation layer 117b and the first encapsulation layer 117a. In this case, the third encapsulation layer 117c can minimize or block the penetration of external moisture or oxygen into the first encapsulation layer 117a and the second encapsulation layer 117b. For example, the third encapsulation layer 117c may be made of an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), silicon nitride oxide (SiON), or aluminum oxide (Al2O3), but is not limited to these.

[0122] The touch sensing unit can be disposed on the package unit 117. The touch sensing unit can be disposed above the light-emitting diode 120.

[0123] The touch sensing unit may include a touch buffer layer 118a, a touch interlayer insulating layer 118b, a touch electrode TE, a third planarization layer 118c, and a touch routing line TL (see Figure 6 The touch buffer layer 118a may not be included in the touch sensing unit and may be disposed between the third encapsulation layer 117c and the touch sensing unit. The touch electrode TE may include the touch sensor electrode TS and the touch bridging electrode TB located on different layers. The touch electrode TE may be disposed in the active area AA.

[0124] For example, the touch buffer layer 118a may be disposed above the third encapsulation layer 117c, and the touch bridging electrode TB may be disposed on the touch buffer layer 118a.

[0125] The touch interlayer insulating layer 118b can be disposed on the touch bridging electrode TB, and the touch sensor electrode TS can be disposed on the touch interlayer insulating layer 118b.

[0126] A third planarization layer 118c is disposed on the touch sensor electrode TS. The third planarization layer 118c can be an organic layer used to planarize and protect the upper part of the touch sensor electrode TS. Therefore, the third planarization layer 118c can be configured to contact the touch sensor electrode TS. For example, the third planarization layer can be formed of organic materials such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin, but is not limited thereto. For example, the touch buffer layer 118a, the touch interlayer insulating layer 118b, and the third planarization layer 118c can be formed of inorganic or organic insulating materials. Therefore, the touch buffer layer 118a, the touch interlayer insulating layer 118b, and the third planarization layer 118c can minimize the step at the location where the touch electrode TE is disposed and electrically insulate the touch sensor electrode TS from the touch bridging electrode TB.

[0127] A fourth planarization layer 119 is disposed on the third planarization layer 118c and the first weir DAM1. The fourth planarization layer 119 can planarize the upper portions of the plurality of touch electrodes TE. Specifically, the fourth planarization layer 119 can be configured to planarize the entire upper portion of the active region AA, the first non-active region NA1, and the second non-active region NA2 on the substrate 110. Therefore, the fourth planarization layer 119 can be disposed on the uppermost layer of the substrate 110, but is not limited thereto. The fourth planarization layer 119 can be formed of an organic material such as an epoxy resin, but is not limited thereto.

[0128] In the following text, reference will be made to Figures 3A to 7 Together, we describe the cross-sectional structure of the first non-active region NA1 adjacent to the bending region BA.

[0129] Figure 3A It is along Figure 1B The cross-sectional view taken from line C-C'. Figure 3B It is along Figure 1D The cross-sectional view taken by line F-F'. Figure 4A It is along Figure 1B The cross-sectional view taken by line D-D'. Figure 4B It is along Figure 1D A cross-sectional view taken from line G-G'. Figure 5 It is along Figure 1D A cross-sectional view taken from line H-H'. Figure 6 yes Figure 1A A magnified plan view of region I. Figure 7 It is along Figure 6 The cross-sectional view taken from line J-J'. Figures 3A to 7 These are cross-sectional and plan views of each region of the first non-active region NA1 according to an exemplary embodiment of the present invention. Figure 3A and 3B It shows a cross-sectional view of the same area, and Figure 4A and 4BIt is a cross-sectional view showing the same area. Figure 3A and 4A This is a cross-sectional view before the finishing process. Figure 3B and 4B This is a cross-sectional view after the finishing process.

[0130] Reference Figures 3A to 7 In a display device 100 according to an exemplary embodiment of the present invention, a power line PL, a first weir DAM1, a second weir DAM2, a third planarization layer 118c and a fourth planarization layer 119 are provided in the first non-active region NA1 of the substrate 110.

[0131] In the first non-active region NA1, a power line PL can be disposed on the second interlayer insulating layer 113b. For example, a low-potential voltage or a high-potential voltage can be provided to the sub-pixels SP of the display device 100 through the power line PL. In this case, the power line PL can be formed on the same layer using the same material as the first gate G1 disposed in the active region AA, but is not limited thereto.

[0132] At the same time, refer to Figure 3A and 3B The power line PL may include multiple holes. Therefore, gases generated during the manufacturing process from the first gate insulating layer 112a or the first interlayer insulating layer 113a can be easily discharged to the outside through the multiple holes of the power line PL.

[0133] Reference Figure 3A and 3B In the first non-active region NA1, a plurality of weirs are disposed in the region adjacent to the end of the substrate 110. Each of the plurality of weirs is disposed around the active region AA in the first non-active region NA1.

[0134] Multiple weirs may include the first weir DAM1 and the second weir DAM2.

[0135] Multiple first weirs DAM1 are configured to be adjacent to the active region AA to suppress over-coating of the second encapsulation layer 117b.

[0136] Figure 3A and 3B The first weir DAM1 shown may be the outermost weir among the plurality of first weirs DAM1 located at the outermost periphery of the substrate 110. In the following text, the first weir DAM1 may cover the ends of the plurality of inorganic insulating layers disposed in the first non-active region NA1, but is not limited thereto.

[0137] The plurality of first weirs DAM1 may have a structure in which a plurality of organic layers formed of the same material as the components disposed in the active region AA are laminated. For example, each of the plurality of first weirs DAM1 may be formed with the second planarization layer 115b and the embankment 116a using the same process and the same material, and may be formed with the spacer 116b using the same process, but is not limited thereto.

[0138] Furthermore, even in Figure 3A and 3B The diagram shows multiple first weirs DAM1 configured as one, but it is not limited to this; the number of multiple weirs can be changed as needed.

[0139] Reference Figure 3A , Figure 4A , Figure 4B and Figure 5 The second weir DAM2 is positioned adjacent to the curved region BA in the first non-active region NA1. For example, the second weir DAM2 may be formed on the same layer as the third planarization layer 118c using the same material. The end of the fourth planarization layer 119 may be disposed inside the second weir DAM2. The fourth planarization layer 119 may fill the space between the first weir DAM1 and the second weir DAM2. The second weir DAM2 may be configured to be adjacent to the curved region BA in the first non-active region NA1 to minimize over-coating of the fourth planarization layer 119. Therefore, the second weir DAM2 can minimize malfunctions of components disposed in the curved region BA and the second non-active region NA2 due to the fourth planarization layer 119.

[0140] In addition, refer to Figure 3A and 3B The end of the third planarization layer 118c can be further disposed on the inner side compared to the first weir DAM1. The fourth planarization layer 119 can also fill the space between the end of the third planarization layer 118c and the first weir DAM1.

[0141] At this time, refer to Figure 3A , Figure 4A , Figure 4B and Figure 5 The second weir DAM2 can be configured to be spaced apart from the plurality of inorganic insulating layers whose ends are covered by the first weir DAM1 in the first non-active region NA1. In the first non-active region NA1, the plurality of inorganic insulating layers disposed between the substrate 110 and the plurality of light-emitting diodes 120 can be further disposed inside the second weir DAM2 and spaced apart from the second weir DAM2. That is, the plurality of inorganic insulating layers may not be disposed below the second weir DAM2. At this time, the fourth planarization layer 119 can further fill the space between the first weir DAM1 and the second weir DAM2, and this space is the same size as the space in which the inorganic insulating layers are removed.

[0142] At the same time, refer to Figure 3A , Figure 4A , Figure 4B , Figure 5 and Figure 7 An additional inorganic layer 118a-1 is disposed below the second dam DAM2. The additional inorganic layer 118a-1 may be formed on the same layer using the same material as the touch buffer layer 118a. For example, the additional inorganic layer 118a-1 and the touch buffer layer 118a may be deposited on the same layer using the same process, and then etched in the process of forming the second dam DAM2 to form together with the second dam DAM2, but is not limited thereto.

[0143] An additional inorganic layer 118a-1 may be provided to improve the adhesion strength with the second dam DAM2. For example, the additional inorganic layer 118a-1 improves the adhesion strength between the substrate 110 or dam unit 116 and the second dam DAM2 to minimize the deviation of the second dam DAM2, but is not limited thereto.

[0144] At the same time, refer to Figures 3A to 5 In the first non-active region NA1 adjacent to the curved region BA, the fourth planarization layer 119 may have different cross-sections in the region where the second weir DAM2 is provided and in the region where the second weir DAM2 is not provided. For example, as Figure 3A and 3B As shown, in the first non-active region NA1 adjacent to the bending region BA, in the region where the second weir DAM2 has been removed by a trimming process, the end of the fourth planarization layer 119 can be disposed on the same plane as the end of the substrate 110. Furthermore, the thickness of the fourth planarization layer 119 can decrease from the inside of the first non-active region NA1 toward the end of the fourth planarization layer 119. For example... Figure 4A , Figure 4B and Figure 5 As shown, in the first non-active region NA1 adjacent to the bending region BA, in the region where the second weir DAM2 has not been removed by the trimming process, the end of the fourth planarization layer 119 may be further disposed inside the substrate 110.

[0145] Reference Figure 6 and Figure 7 The touch sensing unit also includes multiple touch sensing lines TD and multiple touch routing lines TL disposed in the first non-active area NA1.

[0146] Multiple touch sensing lines TD are connected to multiple touch electrodes TE disposed in the active region AA, and extend from the multiple touch electrodes TE to a first non-active region NA1 adjacent to the curved region BA. For example, the multiple touch sensing lines TD may be formed on the same layer using the same material as the touch sensor electrodes TS disposed in the active region AA, but are not limited thereto.

[0147] Multiple touch routing lines TL can be electrically connected to multiple touch electrodes TE and extend to the first non-active area NA1, the curved area BA, and the second non-active area NA2. The multiple touch routing lines TL can be respectively connected to multiple touch sensing lines TD in the first non-active area NA1. For example, the multiple touch routing lines TL can be formed on the same layer using the same material as the auxiliary electrode AE ​​disposed in the active area AA, but are not limited thereto.

[0148] For example, multiple touch sensing lines TD and multiple touch routing lines TL can be configured to send / receive touch sensing signals to / from the touch driving circuit that controls the touch sensing unit.

[0149] At the same time, refer to Figure 6 and Figure 7 Multiple touch routing lines TL can be configured to overlap with the second dam DAM2. That is, the second dam DAM2 can be configured to overlap with multiple touch routing lines TL in the first non-active area NA1 of the adjacent curved area BA. At this time, the fourth planarization layer 119 can fill the space between the end of the third planarization layer 118c and the second dam DAM2.

[0150] At this time, refer to Figure 7 The third planarization layer 118c is disposed in the region adjacent to the multiple touch routing lines TL to expose the ends of the touch buffer layer 118a and cover the ends of the touch sensing lines TD. That is, in the region adjacent to the multiple touch routing lines TL, the third planarization layer 118c can be partially removed until the region exposing the ends of the touch buffer layer 118a. Therefore, the space between the ends of the third planarization layer 118c and the second weir DAM2 can be further expanded, and the fourth planarization layer 119 can fill more of the space between the ends of the third planarization layer 118c and the second weir DAM2.

[0151] At the same time, refer to Figure 7 Various wirings VL can be further disposed in the first non-active region NA1 adjacent to the multiple touch routing lines TL. The wiring VL can be disposed further inside the ends of the multiple touch sensing lines TD. For example, the wiring VL can be a power line that provides a low-potential voltage or a high-potential voltage to the sub-pixel SP. The wiring VL can be formed on the same layer using the same material as the source electrodes S1 and S2 and the drain electrodes D1 and D2 disposed in the active region AA, but is not limited thereto.

[0152] In display devices, vias formed to correspond to cameras or light sensors can be provided in the active area. Since the camera or light sensor is located within the via, an additional planarization layer can be provided, in addition to components such as encapsulation layers, to planarize its top surface. However, when an additional planarization layer is provided, in non-active areas, the added planarization layer can be over-applied to areas where multiple pads or driver ICs are located, leading to malfunctions of multiple pads or driver ICs.

[0153] In a display device 100 according to an exemplary embodiment of the present invention, a second weir DAM2 is disposed in the region adjacent to the curved region BA of the first non-active region NA1 to minimize over-coating of the fourth planarization layer 119.

[0154] In a display device 100 according to an exemplary embodiment of the present invention, a second weir DAM2 is disposed in a region adjacent to a curved region BA in a first non-active region NA1. The second weir DAM2 may be formed on the same layer as the third planarization layer 118c used for planarizing the upper portions of the plurality of touch electrodes TE. Therefore, the second weir DAM2 may be formed above the touch routing line TL disposed in the first non-active region NA1 adjacent to the curved region BA. Thus, the second weir DAM2 may be configured to minimize over-coating of the fourth planarization layer disposed on the uppermost layer of the substrate 110. In a display device 100 according to an exemplary embodiment of the present invention, the second weir DAM2 is disposed in a region adjacent to the curved region BA in the first non-active region NA1 to minimize over-coating of the fourth planarization layer 119. Furthermore, the reliability of the display device can be improved.

[0155] Exemplary embodiments of the present invention can also be described as follows:

[0156] According to one aspect of the present invention, a display device includes: a substrate, the substrate including an active region, a first non-active region surrounding the active region, a curved region extending from and bending from the first non-active region, and a second non-active region extending from the curved region; a plurality of light-emitting diodes disposed in the active region on the substrate; a touch sensing unit disposed above the plurality of light-emitting diodes; a first planarization layer disposed on the touch sensing unit; a first weir disposed in the first non-active region and surrounding the active region; a second planarization layer disposed on the first weir and the first planarization layer; and a second weir disposed along the boundary between the first non-active region and the curved region in the first non-active region, wherein the second weir and the first planarization layer are formed of the same material on the same layer.

[0157] The end of the second planarization layer may be located inside the second weir.

[0158] In the first non-active region where the second weir is not provided and which is adjacent to the bending region, the end of the second planarization layer may be disposed on the same plane as the end of the substrate.

[0159] In the first non-active zone where the second weir is not installed, the thickness of the second planarization layer can decrease from the inside of the first non-active zone toward the end of the second planarization layer.

[0160] The display device may further include: an encapsulation layer disposed between the plurality of light-emitting diodes and the touch sensing unit; a touch buffer layer disposed between the encapsulation layer and the touch sensing unit; and an additional inorganic layer disposed below the second dam and formed on the same layer as the touch buffer layer using the same material.

[0161] The touch sensing unit may include: a plurality of touch electrodes disposed in the active area; a plurality of touch sensing lines extending from the plurality of touch electrodes to a first non-active area adjacent to the curved area; and a plurality of touch routing lines connected to the plurality of touch sensing lines in the first non-active area and extending to the curved area and the second non-active area.

[0162] The multiple touch routing lines can be configured to overlap with the second weir.

[0163] In the region adjacent to the plurality of touch routing lines, the first planarization layer may be configured to cover the ends of the touch sensing lines and expose the ends of the touch buffer layer.

[0164] The second planarization layer can fill the space between the end of the first planarization layer and the second weir.

[0165] The display device may further include a plurality of inorganic insulating layers disposed between the substrate and the plurality of light-emitting diodes.

[0166] In the first non-active region, the plurality of inorganic insulating layers may be further disposed on the inner side compared to the second weir, and may be spaced apart from the second weir.

[0167] In the first non-active region, the ends of the plurality of inorganic insulating layers may be covered by the first weir, and the second planarization layer may be disposed in the space between the first weir and the second weir.

[0168] The end of the first planarization layer may be further disposed on the inner side relative to the first weir, and the second planarization layer may also fill the space between the end of the first planarization layer and the first weir.

[0169] According to another aspect of the present invention, a display device includes: a substrate, the substrate including an active region having a plurality of sub-pixels, a first non-active region surrounding the active region, and a curved region extending from and curved from the first non-active region; a plurality of light-emitting diodes, the light-emitting diodes being disposed on the substrate in each of the plurality of sub-pixels; a touch sensing unit disposed above the plurality of light-emitting diodes; a first planarization layer disposed on the touch sensing unit; a first weir, the first weir being disposed in the first non-active region and surrounding the active region; a second planarization layer, the second planarization layer being disposed on the first weir and the first planarization layer; and a second weir, the second weir being disposed along the boundary of the first non-active region and the curved region in the first non-active region, wherein the second weir and the first planarization layer are formed of the same material on the same layer.

[0170] The end of the second planarization layer may be located inside the second weir.

[0171] In the first non-active region where the second weir is not provided and which is adjacent to the curved region, the thickness of the second planarization layer may decrease from the inside of the first non-active region toward the end of the second planarization layer.

[0172] In the first non-active region where the second weir is not provided, the end of the second planarization layer may be disposed on the same plane as the end of the substrate.

[0173] The display device may further include: an encapsulation layer disposed between the plurality of light-emitting diodes and the touch sensing unit; a touch buffer layer disposed between the encapsulation layer and the touch sensing unit; and an additional inorganic layer disposed below the second dam and formed on the same layer as the touch buffer layer using the same material.

[0174] The substrate may further include a second non-active region extending from the bending region.

[0175] The touch sensing unit may include: a plurality of touch electrodes disposed in the active area; and a plurality of touch routing lines electrically connected to the plurality of touch electrodes and extending in the first non-display area to the curved area and the second non-active area.

[0176] The multiple touch routing lines may be configured to overlap with the second weir, and in the area adjacent to the multiple touch routing lines, the first planarization layer may be configured to expose the ends of the touch buffer layer.

[0177] Although exemplary embodiments of the present invention have been described in detail with reference to the accompanying drawings, the present invention is not limited thereto and may be embodied in many different forms without departing from the technical concept of the invention. Therefore, the exemplary embodiments of the present invention are provided for illustrative purposes only and are not intended to limit the technical concept of the invention. The scope of the technical concept of the present invention is not limited thereto. Therefore, it should be understood that the above exemplary embodiments are exemplary in all respects and do not limit the present invention. The scope of protection of the present invention should be interpreted based on the appended claims, and all technical concepts within their equivalent scope should be interpreted as falling within the scope of the present invention.

Claims

1. A display device, comprising: A substrate, the substrate including an active region, a first non-active region surrounding the active region, a curved region extending from and bending from the first non-active region, and a second non-active region extending from the curved region; Multiple light-emitting diodes are disposed in the active region on the substrate; A touch sensing unit is disposed above the plurality of light-emitting diodes; A first planarization layer is disposed on the touch sensing unit; A first weir is disposed in the first non-active region and surrounds the active region; A second planarization layer is disposed on the first weir and the first planarization layer; as well as A second weir is disposed in the first non-active region along the boundary between the first non-active region and the curved region. The second weir and the first planarization layer are formed on the same layer using the same material.

2. The display device according to claim 1, wherein the end of the second planarization layer is disposed inside the second weir.

3. The display device according to claim 1, wherein in the first non-active region where the second weir is not provided and adjacent to the curved region, the end of the second planarization layer is disposed on the same plane as the end of the substrate.

4. The display device according to claim 3, wherein in the first non-active region where the second weir is not provided, the thickness of the second planarization layer decreases from the inside of the first non-active region toward the end of the second planarization layer.

5. The display device according to claim 1, further comprising: An encapsulation layer is disposed between the plurality of light-emitting diodes and the touch sensing unit; A touch buffer layer is disposed between the encapsulation layer and the touch sensing unit; as well as An additional inorganic layer is disposed below the second weir and is formed on the same layer of the same material as the touch buffer layer.

6. The display device according to claim 5, wherein the touch sensing unit comprises: Multiple touch electrodes are disposed in the active area; Multiple touch sensing lines extend from the multiple touch electrodes to a first non-active region adjacent to the curved region; as well as Multiple touch routing lines connect to multiple touch sensing lines in the first non-active area and extend to the curved area and the second non-active area. The multiple touch routing lines are configured to overlap with the second weir.

7. The display device of claim 6, wherein in the region adjacent to the plurality of touch routing lines, the first planarization layer is configured to cover the ends of the touch sensing lines and expose the ends of the touch buffer layer.

8. The display device according to claim 7, wherein the second planarization layer fills the space between the end of the first planarization layer and the second weir.

9. The display device according to claim 1, further comprising: Multiple inorganic insulating layers are disposed between the substrate and the plurality of light-emitting diodes. In the first non-active region, the plurality of inorganic insulating layers are further disposed on the inner side compared to the second weir, and are spaced apart from the second weir.

10. The display device of claim 9, wherein in the first non-active region, the ends of the plurality of inorganic insulating layers are covered by the first weir, and the second planarization layer is disposed in the space between the first weir and the second weir.

11. The display device of claim 10, wherein the end of the first planarization layer is further disposed inside the first weir, and the second planarization layer also fills the space between the end of the first planarization layer and the first weir.

12. The display device according to claim 1, further comprising: A third planarization layer is disposed on the substrate, and the light-emitting diode is disposed on the third planarization layer; as well as A dam portion is disposed on the third planarization layer and covers the end of the anode of the light-emitting diode.

13. The display device of claim 12, wherein the first weir, the third flattening layer, and the embankment are formed using the same process and the same materials.

14. The display device according to claim 6, further comprising: The wiring is arranged in the first non-active area adjacent to the multiple touch routing lines. The wiring is further disposed on the inside compared to the ends of the multiple touch sensing lines.

15. The display device of claim 6, wherein each of the plurality of touch electrodes comprises a touch sensor electrode and a touch bridging electrode located on different layers. The touch sensing unit further includes a touch interlayer insulating layer disposed on the touch bridging electrode. The touch sensor electrodes are disposed on the interlayer insulating layer of the touch sensor. The multiple touch sensing lines and the touch sensor electrodes disposed in the active area are formed on the same layer of the same material.

16. The display device of claim 1, wherein in a first non-active region adjacent to the curved region, the second planarization layer has different cross sections in the region where the second weir is provided and in the region where the second weir is not provided.

17. A display device, comprising: The substrate includes an active region having a plurality of sub-pixels, a first non-active region surrounding the active region, and a curved region extending from and bending from the first non-active region. A plurality of light-emitting diodes, wherein each of the plurality of sub-pixels is disposed on the substrate; A touch sensing unit is disposed above the plurality of light-emitting diodes; A first planarization layer is disposed on the touch sensing unit; A first weir is disposed in the first non-active region and surrounds the active region; A second planarization layer is disposed on the first weir and the first planarization layer; as well as A second weir is disposed in the first non-active region along the boundary between the first non-active region and the curved region. The second weir and the first planarization layer are formed on the same layer using the same material.

18. The display device according to claim 17, wherein the end of the second planarization layer is disposed inside the second weir.

19. The display device of claim 17, wherein in a first non-active region where the second weir is not provided and adjacent to the curved region, the thickness of the second planarization layer decreases from the inside of the first non-active region toward the end of the second planarization layer.

20. The display device of claim 19, wherein in the first non-active region where the second weir is not provided, the end of the second planarization layer is disposed on the same plane as the end of the substrate.

21. The display device according to claim 17, further comprising: An encapsulation layer is disposed between the plurality of light-emitting diodes and the touch sensing unit; A touch buffer layer is disposed between the encapsulation layer and the touch sensing unit; as well as An additional inorganic layer is disposed below the second weir and is formed on the same layer of the same material as the touch buffer layer.

22. The display device of claim 21, wherein the substrate further comprises a second non-active region extending from the curved region. The touch sensing unit includes: Multiple touch electrodes are disposed in the active area; as well as Multiple touch routing lines, electrically connected to the multiple touch electrodes, extend from the first non-display area to the curved area and the second non-active area. The plurality of touch routing lines are configured to overlap with the second weir, and in the region adjacent to the plurality of touch routing lines, the first planarization layer is configured to expose the ends of the touch buffer layer.

23. The display device according to claim 17, further comprising: A third planarization layer is disposed on the substrate, and the light-emitting diode is disposed on the third planarization layer; as well as A dam portion is disposed on the third planarization layer and covers the end of the anode of the light-emitting diode.

24. The display device of claim 17, wherein the first weir, the third flattening layer, and the embankment are formed using the same process and the same materials.

25. The display device according to claim 22, further comprising: The wiring is arranged in the first non-active area adjacent to the multiple touch routing lines. The touch sensing unit further includes multiple touch sensing lines extending from the multiple touch electrodes to a first non-active region adjacent to the curved region. The wiring is further disposed on the inside compared to the ends of the multiple touch sensing lines.

26. The display device of claim 25, wherein each of the plurality of touch electrodes comprises a touch sensor electrode and a touch bridging electrode located on different layers. The touch sensing unit further includes a touch interlayer insulating layer disposed on the touch bridging electrode. The touch sensor electrodes are disposed on the interlayer insulating layer of the touch sensor. The multiple touch sensing lines and the touch sensor electrodes disposed in the active area are formed on the same layer of the same material.

27. The display device of claim 17, wherein in a first non-active region adjacent to the curved region, the second planarization layer has different cross sections in the region where the second weir is provided and in the region where the second weir is not provided.

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