Display device

Abstract

This disclosure provides a display device comprising: a substrate including a display area comprising subpixels and a non-display area surrounding the display area; a first line disposed on the substrate and extending in a first direction; a planarization layer disposed on the first line; a light-emitting element including a first electrode disposed on the planarization layer, an intermediate layer disposed on the first electrode, and a second electrode disposed on the intermediate layer; a dam including an opening area for exposing at least a portion of the first electrode; and a first line break region located in the non-display area, wherein a corresponding portion of the first line is removed in the first line break region, the substrate and the dam are configured to contact each other in the first line break region, and the display device is capable of improving visibility.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0201204, filed on December 30, 2024, the contents of which are hereby expressly incorporated by reference. Technical Field

[0003] This disclosure relates to electronic devices, and more specifically, to display devices. Background Technology

[0004] In today's information society, display devices used to present images or visual information to users are becoming increasingly important. The demand for such devices has spurred rapid development in display technology, resulting in the development of various types and applications of display devices. Furthermore, as display devices become thinner and lighter, their applications are expanding, and displays are widely used in various fields of devices, equipment, and systems.

[0005] Display devices are widely used not only as televisions or monitors, but also as displays for laptops, tablets, smartphones, portable display devices, portable information devices, and more.

[0006] Display devices can be classified into reflective display devices and emissive display devices. Reflective display devices display images or information by reflecting natural light or light from an external lighting device. Emissive display devices display images or information using light generated by embedded light-emitting elements or light sources disposed within the display device. Summary of the Invention

[0007] One or more aspects of this disclosure may provide a display device including a structure in which a black dam is configured to contact a substrate and to improve light-shielding efficiency.

[0008] One or more aspects of this disclosure may provide a display device including a structure in which internal light and external light are blocked in a non-display area, and which is capable of improving visibility.

[0009] One or more aspects of this disclosure may provide a display device including a structure that can prevent excessive etching of the metal layer and minimize the distance between lines, and is capable of displaying high resolution.

[0010] One or more aspects of this disclosure may provide a display device including a structure in which metal layers located in different layers are simultaneously removed, and capable of achieving processing optimization.

[0011] One or more aspects of this disclosure may provide a display device including a structure in which the distance between lines can be minimized, and which is capable of displaying high resolution and being driven with low power.

[0012] One or more aspects of this disclosure may provide a display device including a structure in which the vertical thickness of a dam in a region where a first line is broken is greater than the vertical thickness of a dam above another first line.

[0013] The aspects, examples, and implementations provided in this disclosure are not limited to the foregoing description, and additional aspects, examples, and implementations provided in this disclosure will become apparent to those skilled in the art from the following description.

[0014] According to one or more exemplary embodiments of this disclosure, a display device may be provided, comprising: a substrate including a display area comprising subpixels and a non-display area surrounding the display area; a first line disposed on the substrate and extending in a first direction; a planarization layer disposed on the first line; a light-emitting element including a first electrode disposed on the planarization layer, an intermediate layer disposed on the first electrode, and a second electrode disposed on the intermediate layer; a dam including an opening region for exposing at least a portion of the first electrode; and a first line break region located in the non-display area, wherein a corresponding portion of the first line is removed in the first line break region. In one or more aspects, the substrate and the dam may be configured to contact each other in the first line break region.

[0015] According to one or more aspects of this disclosure, a display device may be provided that can improve light-shielding efficiency by including a structure in which a black dam is configured as a contact substrate.

[0016] According to one or more aspects of this disclosure, a display device may be provided that can improve visibility by including a structure in which internal light and external light are blocked in a non-display area.

[0017] According to one or more aspects of this disclosure, a display device may be provided that is capable of presenting high resolution by including a structure in which excessive etching of the metal layer can be prevented and the distance between lines can be minimized.

[0018] According to one or more aspects of this disclosure, a display device may be provided that enables processing optimization by including a structure in which metal layers located in different layers are simultaneously removed.

[0019] According to one or more aspects of this disclosure, a display device may be provided that is capable of presenting high resolution and being driven with low power by including a structure in which the distance between lines can be minimized.

[0020] According to one or more aspects described herein, a display device may be provided, comprising: a substrate including a display area comprising subpixels and a non-display area; a first line disposed on the substrate and extending in a first direction; an insulating layer disposed on the first line; a light-emitting element including a first electrode disposed on the insulating layer, an intermediate layer disposed on the first electrode, and a second electrode disposed on the intermediate layer; a dam including an opening region for exposing at least a portion of the first electrode; and a first line break region located in the non-display area. In one or more aspects, in the display device, a first portion of the first line is broken from a second portion of the first line in the first line break region. In one or more aspects, in the display device, the vertical thickness of the dam in the first line break region is greater than the vertical thickness of the dam above another first line.

[0021] The effects or advantages of the aspects, examples, and implementations described herein are not limited thereto, and additional effects or advantages will become apparent to those skilled in the art from the following description. Attached Figure Description

[0022] The accompanying drawings are included to provide a further understanding of this disclosure and are incorporated in and constitute a part of this disclosure. The drawings illustrate aspects of this disclosure and, together with the description, serve to explain the principles of this disclosure. Therefore, it should be understood that the aspects, examples, and embodiments described herein are not limited to the illustrations in the drawings. In the drawings:

[0023] Figure 1 An example system configuration of a display device according to various aspects of this disclosure is shown.

[0024] Figure 2 It is a cross-sectional view of an example subpixel region defined in a display panel according to various aspects of this disclosure.

[0025] Figure 3 yes Figure 1 An example of a magnified view of region A.

[0026] Figure 4 This is an example of a cross-sectional view of a display panel according to various aspects of this disclosure.

[0027] Figure 5 This illustrates the structure of a typical gate electrode and Figure 4 An example of a cross-sectional view of the structure of the gate electrode.

[0028] Figure 6 yes Figure 4 An example of a cross-sectional view of the data lines in the diagram.

[0029] Figure 7 An example of a process for manufacturing a display panel according to various aspects of this disclosure is shown.

[0030] Figure 8 An example of a process for manufacturing a display panel according to various aspects of this disclosure is shown.

[0031] Figure 9 An example of a process for manufacturing a display panel according to various aspects of this disclosure is shown.

[0032] Figure 10 An example of a process for manufacturing a display panel according to various aspects of this disclosure is shown.

[0033] Figure 11 An example of a process for manufacturing a display panel according to various aspects of this disclosure is shown.

[0034] Figure 12 An example of a process for manufacturing a display panel according to various aspects of this disclosure is shown.

[0035] Figure 13 An example of a process for manufacturing a display panel according to various aspects of this disclosure is shown.

[0036] Figure 14 An example of a process for manufacturing a display panel according to various aspects of this disclosure is shown. Detailed Implementation

[0037] Reference will now be made in detail to exemplary embodiments of this disclosure, examples or aspects of which may be illustrated in the accompanying drawings. In the following description, unless otherwise stated, the structures, implementations, methods, and operations described herein are not limited to the specific examples, aspects, and embodiments set forth herein, and may be modified as is known in the art. Unless otherwise stated, similar reference numerals always refer to similar elements. The names of the various elements used in the following description are chosen solely for ease of writing and may therefore differ from those used in actual products. The advantages and features of this disclosure and its implementation methods will be illustrated by the following exemplary embodiments described with reference to the accompanying drawings. However, this disclosure may be implemented in different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure may be sufficiently thorough and complete to assist those skilled in the art in fully understanding the scope of this disclosure. Furthermore, the scope of protection of this disclosure is defined by the claims and their equivalents. In the following description, detailed descriptions of relevant known functions or configurations may be omitted where such detailed descriptions may unnecessarily obscure aspects of this disclosure. The shapes, dimensions, ratios, angles, numbers, etc., shown in the accompanying drawings to describe various exemplary embodiments of this disclosure are merely given by way of example. Therefore, this disclosure is not limited to the illustrations in the drawings. Terms such as “comprising,” “having,” “including,” “constituting,” “made of,” and “formed from” as used herein are generally intended to allow for the addition of other components unless used in conjunction with the term “only.” As used herein, the singular form is intended to include the plural form unless the context clearly indicates otherwise.

[0038] Although the terms “first,” “second,” A, B, (a), or (b), etc., may be used herein to describe various elements, these elements should not be construed as being limited by these terms, as they are not used to define a particular order or priority. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0039] When the first element is referred to as "connected or coupled to," "in contact with," or "overlapping with" the second element, it should be interpreted as meaning that not only can the first element be "directly connected or coupled to," "directly in contact with," or "directly overlap with" the second element, but a third element can also be "inserted" between the first and second elements, or the first and second elements can be "connected or coupled," "in contact with," or "overlapping" with each other via a fourth element. Here, the second element can be included in at least one of two or more elements that are "connected or coupled," "in contact with," or "overlapping" with each other.

[0040] When describing positional relationships, such as when using terms like "above," "over," "below," "on top," "below," "beside," or "near" to describe the positional relationship between two parts, one or more other parts may be located between these two parts, unless more restrictive terms such as "immediately," "directly," or "closely" are used. For example, when an element or layer is placed "on" another element or layer, a third element or layer may be inserted therebetween. Furthermore, the terms "left," "right," "top," "bottom," "downward," "upward," "upper," and "lower" refer to any frame of reference.

[0041] Furthermore, when referring to any size, relative size, etc., it should be assumed that the numerical or corresponding information of the component or feature (e.g., level, range, etc.) includes the tolerance or error range that may be caused by various factors (e.g., process factors, internal or external influences, noise, etc.), even if no relevant description is specified. In addition, the term "may" fully encompasses all the meanings of the term "can".

[0042] In the following description, various exemplary aspects of this disclosure are described in detail with reference to the accompanying drawings. Reference numerals for each element in the drawings may indicate the same element in other drawings, and similar reference numerals may refer to similar elements unless otherwise stated. Identical or similar elements may be indicated by the same reference numerals, even if they are depicted in different drawings. Furthermore, for ease of description, the scale, dimensions, size, and thickness of each element shown in the drawings may differ from the actual scale, dimensions, size, and thickness, and therefore, aspects of this disclosure are not limited to the scale, dimensions, size, and thickness shown in the drawings.

[0043] Figure 1 An example of the system configuration of the display device 100 according to various aspects of this disclosure is shown.

[0044] Reference Figure 1In one or more example embodiments, the display device 100 may include a display panel 110 and at least one display driving circuit as elements for displaying images. The at least one display driving circuit may be a circuit for driving the display panel 110 and includes a data driving circuit 120, a gate driving circuit 130, a controller 140, and other circuit components.

[0045] The display panel 110 may include a substrate 111 and a plurality of sub-pixels SP disposed on the substrate 111.

[0046] The substrate 111 may include a display area DA that allows an image to be displayed and a non-display area NDA surrounding the outer edge of the display area DA.

[0047] The display area DA can also be called the active area, and multiple sub-pixels SP used to display the image can be set in the display area DA. The non-display area NDA can also be called the non-active area, and includes the pad area PA.

[0048] In one or more aspects, the display panel 110 may be configured to have a very small non-display area NDA. The non-display area NDA may also be referred to as a "bezel" or "bezel area". For example, the non-display area NDA may include a first non-display area located outside the display area DA in a first direction, a second non-display area located outside the display area DA in a second direction, a third non-display area located outside the display area DA in a direction opposite to the first direction, and a fourth non-display area located outside the display area DA in a direction opposite to the second direction. For example, the second direction may be perpendicular to the first direction.

[0049] The first non-display area, one of the first to fourth non-display areas, may include a pad area to which one or more drive circuits are connected or bonded. Compared to the first non-display area, the second to fourth non-display areas may have a very small size.

[0050] In one or more aspects, a boundary region may be defined between the display area DA and the non-display area NDA. For example, the boundary region may be curved at an angle relative to the display area DA, and thus at least a portion of the non-display area NDA may be located below the display area DA. In this implementation, when a user views the display device 100 in front of it, all or most of the non-display area NDA may be invisible to the user. For example, the first non-display area may include a curved area. When the curved area is curved, the first non-display area may be invisible in front of the display device 100.

[0051] Several types of signal lines for driving multiple sub-pixels SP can be provided on the substrate 111 of the display panel 110.

[0052] In one or more aspects, the display device 100 herein may be a liquid crystal display device or the like, or a self-emissive display device in which light is emitted from the display panel 110 itself. In the example where the display device 100 is a self-emissive display device, each of the plurality of sub-pixels SP may include a light-emitting element.

[0053] For example, the display device 100 according to an aspect of this disclosure may be an organic light-emitting display device in which an organic light-emitting diode (OLED) is used to realize the light-emitting element. In another example, the display device 100 according to an aspect of this disclosure may be an inorganic light-emitting display device in which an inorganic light-emitting diode based on an inorganic material is used to realize the light-emitting element. In another example, the display device 100 according to an aspect of this disclosure may be a quantum dot display device in which a quantum dot, which is a self-emissive semiconductor crystal, is used to realize the light-emitting element. However, the aspects of this disclosure are not limited thereto.

[0054] The structure of each or at least one of the plurality of sub-pixels SP included in the display device 100 may depend on the type of the display device 100. For example, when the display device 100 is a self-emissive display device that includes self-emissive sub-pixels SP, each sub-pixel SP may include a self-emissive light-emitting element, one or more transistors, and one or more capacitors.

[0055] Reference Figure 1 Each or at least one of the plurality of sub-pixels SP disposed in the display panel 110 may include a light-emitting element ED and a sub-pixel circuit SPC configured to drive the light-emitting element ED.

[0056] Reference Figure 1 The subpixel circuit (SPC) may include a plurality of transistors for driving the light-emitting element (ED) and at least one capacitor. The SPC drives the ED by supplying a driving current to it at a predetermined timing. The ED emits light by being driven by the driving current.

[0057] The multiple transistors may include a driving transistor DT configured to drive a light-emitting element ED and a scanning transistor ST configured to be turned on or off by a scanning signal SC.

[0058] The driving transistor DT can supply driving current to the light-emitting element ED.

[0059] The scanning transistor ST can be configured to control the electrical state of the corresponding node in the sub-pixel circuit SPC, or to control the state or operation of the driving transistor DT.

[0060] At least one capacitor may include a storage capacitor Cst configured to maintain a constant voltage level during a display frame or a period of time of a display frame.

[0061] To drive at least one sub-pixel SP, at least one data signal VDATA as an image signal and at least one scan signal SC as a gate signal can be applied to at least one sub-pixel SP. Furthermore, to drive one or more sub-pixels SP, at least one common driving voltage, including a first common driving voltage VDD and a second common driving voltage VSS, can be applied to one or more sub-pixels SP.

[0062] The light-emitting element (ED) may include a first electrode (PE), an intermediate layer (EL), and a second electrode (CE). The intermediate layer (EL) may be disposed between the first electrode (PE) and the second electrode (CE). The first electrode (PE) may be a pixel electrode (PE), and the second electrode (CE) may be a common electrode (CE).

[0063] For example, a pixel electrode PE can be an electrode disposed in each sub-pixel SP, and a common electrode CE can be an electrode commonly disposed in all or some of the multiple sub-pixels SP. For example, the pixel electrode PE can be an anode electrode, and the common electrode CE can be a cathode electrode. In another example, the pixel electrode PE can be a cathode electrode, and the common electrode CE can be an anode electrode. In the following discussion, for ease of explanation, examples of pixel electrodes PE being anode electrodes and common electrodes CE being cathode electrodes will be provided.

[0064] In an example where the light-emitting element ED is an organic light-emitting diode, the intermediate layer EL may include a light-emitting layer EML, a first common intermediate layer COM1 between the pixel electrode PE and the light-emitting layer EML, and a second common intermediate layer COM2 between the light-emitting layer EML and the common electrode CE. The layer including the first common intermediate layer COM1 and the second common intermediate layer COM2 may be referred to as the common intermediate layer EL_COM.

[0065] For example, an emissive layer EML can be set for each sub-pixel SP, and a common intermediate layer EL_COM can be set publicly across all or some of the multiple sub-pixels SP.

[0066] For example, an EML layer can be set for each luminescent region, and a common intermediate layer EL_COM can be set across multiple luminescent and non-luminescent regions.

[0067] For example, the emissive layer EML and the common intermediate layer EL_COM can be set publicly across all or some of the multiple sub-pixels SP.

[0068] For example, the emissive layer EML and the common intermediate layer EL_COM can be set publicly across multiple emissive and non-emissive regions.

[0069] For example, the first common intermediate layer COM1 may include a hole injection layer (HIL), a hole transport layer (HTL), etc. The second common intermediate layer COM2 may include an electron transport layer (ETL), an electron injection layer (EIL), etc.

[0070] The hole injection layer injects holes from the pixel electrode (PE) into the hole transport layer, which then transports the holes to the light-emitting layer (EML). The electron injection layer injects electrons from the common electrode (CE) into the electron transport layer, which then transports the electrons to the light-emitting layer (EML).

[0071] For example, the common electrode CE can be electrically connected to the second common driving voltage line VSSL. The second common driving voltage VSS can be applied to the common electrode CE through the second common driving voltage line VSSL. The pixel electrode PE can be electrically connected directly or indirectly (via another transistor) to the first node N1 of the corresponding driving transistor DT of each sub-pixel SP. In this document, the second common driving voltage VSS can also be referred to as the "base voltage", and the second common driving voltage line VSSL can also be referred to as the "low power supply voltage line", "low voltage line", or "base voltage line".

[0072] Each light-emitting element (ED) can be configured by overlapping the pixel electrode (PE), the light-emitting layer (EML) in the intermediate layer (EL), and the common electrode (CE). Each ED can form a corresponding light-emitting region. For example, the corresponding light-emitting region of each ED may include the area where the pixel electrode (PE), the light-emitting layer (EML) in the intermediate layer (EL), and the common electrode (CE) overlap.

[0073] In one or more aspects, each or at least one of the plurality of light-emitting elements ED included in the display panel 110 of the display device 100 may be an organic light-emitting diode (OLED), an inorganic light-emitting diode (LED), a quantum dot (QD) light-emitting element, a micro light-emitting diode, a mini light-emitting diode, etc., but the aspects of this disclosure are not limited thereto. In the example where each light-emitting element ED is an organic light-emitting diode (OLED), the intermediate layer EL corresponding to the light-emitting element ED may be a layer comprising organic material.

[0074] The driving transistor DT can be a transistor configured to supply driving current to the light-emitting element ED. The driving transistor DT can be connected between the first common driving voltage line VDDL and the light-emitting element ED.

[0075] The driving transistor DT may include a first node N1, a second node N2, and a third node N3. The first node N1 may be electrically connected to the light-emitting element ED. A data signal VDATA may be applied to the second node N2. A first common driving voltage VDD, transmitted through a first common driving voltage line VDDL, may be applied to the third node N3.

[0076] In the driving transistor DT, the second node N2 can be the gate node, the first node N1 can be the source node or the drain node, and the third node N3 can be the drain node or the source node. In the following discussion, for ease of illustration only, examples are provided where the first, second, and third nodes (N1, N2, and N3) of the driving transistor DT are the source node, the gate node, and the drain node, respectively. However, aspects of this disclosure are not limited thereto.

[0077] Included Figure 1 The scanning transistor ST in the sub-pixel circuit SPC shown can be a switching transistor used to transmit the data signal VDATA, which is an image signal, to the second node N2, which is the gate node of the driving transistor DT.

[0078] The scan transistor ST can be turned on or off by a scan signal SC, which is a gate signal applied via a scan line SCL (which serves as a gate line GL), and controls the electrical connection between the second node N2 of the drive transistor DT and the data line DL. The drain or source electrode of the scan transistor ST can be electrically connected to the data line DL. The source or drain electrode of the scan transistor ST can be electrically connected to the second node N2 of the drive transistor DT. The gate electrode of the scan transistor ST can be electrically connected to the scan line SCL.

[0079] The storage capacitor Cst can be electrically connected between the first node N1 and the second node N2 of the driving transistor DT. The storage capacitor Cst can include a first capacitor electrode electrically connected to the first node N1 of the driving transistor DT or corresponding to the first node N1 of the driving transistor DT, and a second capacitor electrode electrically connected to the second node N2 of the driving transistor DT or corresponding to the second node N2 of the driving transistor DT.

[0080] The storage capacitor Cst can be an external capacitor intentionally designed to be located outside the driving transistor DT, and therefore different from the internal capacitor, such as a parasitic capacitor (e.g., Cgs, Cgd) that can be formed between the first node N1 and the second node N2 of the driving transistor DT.

[0081] Each of the driving transistor DT and the scanning transistor ST can be an n-type transistor or a p-type transistor.

[0082] The display panel 110 may have a top-emitting structure or a bottom-emitting structure.

[0083] In the example where the display panel 110 has a top-emitting structure, at least a portion of the sub-pixel circuit SPC can overlap with at least a portion of the light-emitting element ED in the vertical direction. In this configuration, the area or size of the corresponding light-emitting region can be increased, and the corresponding aperture ratio can be increased.

[0084] In the example of the display panel 110 having a bottom light-emitting structure, the sub-pixel circuit SPC may not overlap with the light-emitting element ED in the vertical direction.

[0085] like Figure 1 As shown, the subpixel circuit SPC can have a 2T (transistor) 1C (capacitor) structure, comprising two transistors (DT and ST) and one capacitor (Cst). In one or more aspects, the subpixel circuit SPC may also include one or more transistors or one or more capacitors in the 2T 1C structure.

[0086] For example, a subpixel circuit SPC can have an 8T1C structure comprising 8 transistors and 1 capacitor. In another example, a subpixel circuit SPC can have a 6T2C structure comprising 6 transistors and 2 capacitors. In yet another example, a subpixel circuit SPC can have a 7T1C structure comprising 7 transistors and 1 capacitor. However, aspects of this disclosure are not limited to such specific structures.

[0087] The type and number of signals supplied to the sub-pixel SP, and / or the type and number of lines connected to the sub-pixel SP, can vary depending on the structure of the corresponding sub-pixel circuit SPC. Furthermore, the type and number of common driving voltages supplied to the sub-pixel SP can vary depending on the structure of the corresponding sub-pixel circuit SPC.

[0088] Several types of signal lines may include, for example, multiple data lines DL for carrying data signals (which may be referred to as data voltages or image signals), multiple gate lines GL for carrying gate signals (which may be referred to as scan signals), etc.

[0089] For example, multiple data lines DL and multiple gate lines GL may intersect each other. Each of the multiple data lines DL may be configured to extend in a first direction, and each of the multiple gate lines GL may be configured to extend in a second direction. For example, the first direction may be a column direction, and the second direction may be a row direction. In another example, the first direction may be a row direction, and the second direction may be a column direction. Hereinafter, for ease of illustration only, the discussion is provided based on an example where the first direction is a column direction and the second direction is a row direction. Hereinafter, for ease of illustration, the discussion may be provided based on an example where each of the multiple data lines DL is configured in a column direction and each of the multiple gate lines GL is configured in a row direction, but aspects of this disclosure are not limited thereto.

[0090] The data driving circuit 120 can be a circuit for driving multiple data lines DL and can output data signals to multiple data lines DL.

[0091] The data drive circuit 120 can receive digital image data DATA from the controller 140, convert the received image data DATA into analog data signals, and output the obtained data signals to multiple data lines DL.

[0092] In one or more aspects, the data driving circuit 120 may be connected to the display panel 110 via tape-on-absence (TAB) technology, or to conductive pads such as bonding pads of the display panel 110 via chip-on-glass (COG) technology or chip-on-panel (COP) technology, or to the display panel 110 via chip-on-film (COF) technology. However, the aspects of this disclosure are not limited thereto.

[0093] In one or more aspects, the data driving circuit 120 may be disposed in and / or electrically connected to only one side or edge (e.g., upper or lower) of the display panel 110, but is not limited thereto. In one or more aspects, depending on the driving scheme, panel design, etc., the data driving circuit 120 may be disposed in at least two sides or two edges of the display panel 110 (e.g., upper and lower) or four sides or four edges of the display panel 110 (e.g., upper, lower, left and right), and / or electrically connected to at least two sides or two edges of the display panel 110 (e.g., upper and lower) or four sides or four edges of the display panel 110 (e.g., upper, lower, left and right), but is not limited thereto.

[0094] The data driving circuit 120 can be connected to an area extending outward from the display area DA of the display panel 110, or it can be located within the display area DA of the display panel 110.

[0095] The gate drive circuit 130 can be a circuit configured to drive multiple gate lines GL and can output gate signals to multiple gate lines GL.

[0096] The gate drive circuit 130 can receive several types of gate drive control signals GCS, and further, it receives a first gate voltage corresponding to the on-level voltage and a second gate voltage corresponding to the off-level voltage. Thus, the gate drive circuit 130 can generate a gate signal and supply the generated gate signal to multiple gate lines GL.

[0097] In one or more aspects, the gate driving circuit 130 included in the display device 100 may be embedded in the display panel 110 using gate in-panel (GIP) technology. In an example of implementing the gate driving circuit 130 using GIP technology, the gate driving circuit 130 may be disposed on the substrate 111 of the display panel 110 during the manufacturing process of the display panel 110 or the display device 100.

[0098] In one or more aspects, the gate drive circuit 130 may be disposed in the non-display area NDA of the display panel 110.

[0099] In one or more aspects, the gate driving circuit 130 may be disposed in the display area DA of the display panel 110. In this implementation, for example, the gate driving circuit 130 may be disposed in a first region (e.g., a left or right region) of the display area DA of the display panel 110 and / or electrically connected to the first region (e.g., a left or right region) of the display area DA of the display panel 110, but is not limited thereto. In one or more aspects, the gate driving circuit 130 may be disposed in a first portion region (e.g., a left or right portion) and a second portion region (e.g., a right or left portion) of the display area DA and / or electrically connected to the first portion region (e.g., a left or right portion) and the second portion region (e.g., a right or left portion) of the display area DA, but is not limited thereto.

[0100] In this document, the gate drive circuit 130 embedded in the display panel 110 using gate in-panel (GIP) technology can also be referred to as "gate in-panel circuit".

[0101] The controller 140 may be a device configured to control the data drive circuit 120 and the gate drive circuit 130, and may control the driving timing of multiple data lines DL and multiple gate lines GL.

[0102] The controller 140 can supply a data control signal DCS to the data drive circuit 120 to control the data drive circuit 120, and supply a gate control signal GCS to the gate drive circuit 130 to control the gate drive circuit 130.

[0103] The controller 140 can receive image data input from the host system 150 and supply image data DATA that can be read by the data driving circuit 120 based on the input image data.

[0104] The controller 140 can be implemented in a component separate from the data drive circuit 120, or integrated with the data drive circuit 120, such that the controller 140 and the data drive circuit 120 can be implemented in a single integrated circuit.

[0105] Controller 140 may be a timing controller used in typical display technologies, or a control device / apparatus capable of performing additional control functions beyond the typical functions of a timing controller. In one or more embodiments, controller 140 may be one or more other control circuits, different from the timing controller, or circuits or components within a control device / apparatus. Controller 140 may be implemented using various circuits or electronic components such as integrated circuits (ICs), field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), processors, etc. However, aspects of this disclosure are not limited thereto.

[0106] The controller 140 can be mounted on a printed circuit board, flexible printed circuit, etc., and can be electrically connected to the data drive circuit 120 and the gate drive circuit 130 through the printed circuit board, flexible printed circuit, etc.

[0107] The controller 140 can send signals to and receive signals from the data drive circuit 120 via one or more predetermined interfaces. For example, such interfaces may include a Low Voltage Differential Signaling (LVDS) interface, an Embedded Point-to-Point Clock Interface (EPI), a Serial Peripheral Interface (SPI), etc. However, aspects of this disclosure are not limited thereto.

[0108] In one or more aspects, in order to provide touch sensing and image display functions, the display device 100 may include a touch sensor and a touch sensing circuit configured to sense the touch sensor and detect whether the touch is applied by an object such as a finger, pen, etc., or to detect the location (or touch coordinates) of the touch.

[0109] The touch sensing circuit may include: a touch driving circuit configured to drive and sense a touch sensor and generate and output touch sensing data; and a touch controller configured to detect whether a touch has been applied or to detect the location (or touch coordinates) of a touch based on the touch sensing data.

[0110] A touch sensor may include multiple touch electrodes. A touch sensor may also include multiple touch lines for electrically connecting the multiple touch electrodes to touch driving circuitry.

[0111] The touch sensor can be disposed on the exterior of the display panel 110 in the form of a touch panel, or it can be disposed inside the display panel 110. A touch sensor disposed on the exterior of the display panel 110 can be referred to as an add-on touch sensor. In an example where an add-on touch sensor is disposed in the display device 100, the touch panel and the display panel 110 can be manufactured separately and combined during the assembly process. The add-on touch panel may include a touch panel substrate and a plurality of touch electrodes disposed on the touch panel substrate.

[0112] In an example where the touch sensor is located inside the display panel 110, the touch sensor can be formed on the substrate together with signal lines and electrodes related to display driving during the manufacturing process of the display panel 110.

[0113] The touch driving circuit can supply touch driving signals to at least one of a plurality of touch electrodes and generate touch sensing data by sensing at least one of the plurality of touch electrodes.

[0114] Touch sensing circuits can perform touch sensing using self-capacitance sensing technology or mutual capacitance sensing technology.

[0115] In an example where the touch sensing circuit performs touch sensing using self-capacitance sensing technology, the touch sensing circuit can perform touch sensing based on the capacitance between each touch electrode and the touch object (e.g., a finger, a pen, etc.). According to self-capacitance sensing technology, each of the multiple touch electrodes can be used as both a driving touch electrode and a sensing touch electrode. The touch driving circuit can drive all or one or more of the multiple touch electrodes and sense all or one or more of the multiple touch electrodes.

[0116] In an example where the touch sensing circuit performs touch sensing using mutual capacitance sensing technology, the touch sensing circuit can perform touch sensing based on the capacitance between the touch electrodes. According to mutual capacitance sensing technology, multiple touch electrodes can be divided into driving touch electrodes and sensing touch electrodes. The touch driving circuit can drive the driving touch electrodes and sense the sensing touch electrodes.

[0117] In one or more aspects, the touch driving circuit and the touch controller included in the touch sensing circuit can be implemented in separate devices or in a single device. In one or more aspects, the touch driving circuit and the data driving circuit can be implemented in separate devices or in a single device.

[0118] The display device 100 may also include a power supply circuit for supplying several types of power to the display driving circuit and / or touch sensing circuit.

[0119] In one or more aspects, the display device 100 can be a mobile terminal, such as a smartphone, tablet, etc., or a monitor, television (TV), etc. Furthermore, the display device 100 can be configured with a wide variety of types, sizes, and shapes to display information or images. For example, the display device 100 can be applied to mobile devices, video phones, smartwatches, watch phones, wearable devices, foldable devices, rollable devices, bendable devices, flexible devices, stretchable devices, curved devices, sliding devices, variable devices, electronic notebooks, e-books, portable multimedia players (PMPs), personal digital assistants (PDAs), MP3 players, mobile medical devices, desktop PCs, laptop PCs, notebook computers, workstations, navigation devices, car navigation devices, vehicle display devices, vehicle equipment, theater equipment, theater display devices, televisions, wallpaper devices, signage devices, gaming devices, laptops, monitors, cameras, camcorders, and home appliances, etc.

[0120] In one or more aspects, the display device 100 may also include electronic devices, such as a camera device (e.g., an image sensor), or a sensor capable of detecting objects, ambient light, etc. For example, the sensor may be a sensor capable of detecting objects or the human body by receiving light such as infrared light, ultrasonic light, ultraviolet light, etc.

[0121] Figure 2 This is a cross-sectional view of an example sub-pixel region defined in the display panel 110 according to various aspects of this disclosure. In the following... Figure 2 In the discussion of the configuration, for the sake of brevity, descriptions of the references are omitted or briefly described. Figure 1 Discussion of features and configurations that are the same, substantially the same, or similar.

[0122] Reference Figure 2 In one or more example embodiments, the display panel 110 may include at least one transistor 230 disposed on a substrate 111 and a light-emitting element ED electrically connected to the at least one transistor 230.

[0123] The transistor 230 may include an active layer 231, a gate electrode 232, a first electrode pattern 233, and a second electrode pattern 234. The light-emitting element ED may include a first electrode PE, an intermediate layer EL, and a second electrode CE.

[0124] Substrate 111 may comprise a single layer or multiple layers. Substrate 111 may comprise glass or plastic material. When substrate 111 comprises multiple layers, substrate 111 may comprise a first substrate, a substrate intermediate layer, and a second substrate. The substrate intermediate layer may be located between the first substrate and the second substrate. For example, each of the first substrate and the second substrate may be a polyimide (PI) layer. The substrate intermediate layer may be an inorganic insulating layer. When charge is stored on the first substrate, which is a polyimide (PI) layer, the substrate intermediate layer may prevent the charge from affecting the transistors on the second substrate through the second substrate, which is also a polyimide (PI) layer.

[0125] The intermediate layer of the substrate can prevent moisture from penetrating upwards through the first substrate. For example, the intermediate layer of the substrate can be silicon nitride (SiN). x ) or silicon oxide (SiO) x Monolayer of silicon nitride (SiN) x ), silicon oxide (SiO) x Multilayers such as silicon oxide (SiO2) x ) and silicon nitride (SiN) x (The two layers of the disclosure are not limited thereto.)

[0126] A light-shielding layer 211 can be provided on the substrate 111.

[0127] The light-shielding layer 211 can be configured to overlap at least a portion of the active layer 231 of the transistor 230. For example, the light-shielding layer 211 can be configured to overlap the channel region of the active layer 231. When the channel region of the active layer 231 is exposed to light, the channel characteristics of the active layer 231 can change, and consequently, the operating characteristics of the transistor 230 can also change. To solve this problem, since the light-shielding layer 211 is configured to overlap the channel region of the transistor 230, the channel region can be prevented from being exposed to light. Therefore, the operating characteristics of the transistor 230 can be stably executed.

[0128] In one or more aspects, the light-shielding layer 211 may be used as a data line DL or a first common drive voltage line VDDL. In this configuration, the light-shielding layer 211 may be connected to the first electrode pattern 233 of the transistor 230.

[0129] The light-shielding layer 211 may have a single-layer structure, but this disclosure is not limited thereto. For example, the light-shielding layer 211 may include copper (Cu), aluminum (Al), molybdenum (Mo), titanium (Ti), or alloys thereof (e.g., MoTi). For example, the light-shielding layer 211 may include a low-reflection material, such as molybdenum titanium oxide (MoTiO2). x ), molybdenum tantalum oxide (MoTaO) x ), tungsten oxide (WO x ), molybdenum copper oxide (MoCuO) x ) and molybdenum chromium oxide (MoCrO) x ).

[0130] Figure 2 A light-shielding layer 211 with a single-layer structure is shown, but aspects of this disclosure are not limited thereto. For example, the light-shielding layer 211 may have a multilayer structure comprising two or more layers. For example, the light-shielding layer 211 may comprise a first layer and a second layer stacked sequentially. The first layer located on the substrate 111 may be an oxide metal layer, and the second layer located on the first layer may comprise a metallic material having low surface resistance. For example, the first layer may comprise a molybdenum titanium oxide (MoTiO2). x ), molybdenum tantalum oxide (MoTaO) x ), tungsten oxide (WO x ), molybdenum copper oxide (MoCuO) x ) and molybdenum chromium oxide (MoCrO) x The second layer may include copper (Cu), aluminum (Al), molybdenum (Mo), titanium (Ti), or alloys thereof (e.g., MoTi).

[0131] A first insulating layer 222 can be disposed on the light-shielding layer 211. The first insulating layer 222 can be a buffer layer. The first insulating layer 222 can include an inorganic insulating material, such as silicon oxide (SiO2). x ), silicon nitride (SiN) x ) or silicon nitride oxide (SiO) x N y However, this disclosure is not limited to these aspects.

[0132] Figure 2 A first insulating layer 222 having a single-layer structure is shown, but aspects of this disclosure are not limited thereto. For example, the first insulating layer 222 may have a multilayer structure. When the first insulating layer 222 has a multilayer structure, the first insulating layer 222 may have a structure in which at least two inorganic insulating materials are alternately stacked, each inorganic insulating material including, for example, silicon oxide (SiO2). x ), silicon nitride (SiN) x ) or silicon nitride oxide (SiO) x Ny Inorganic materials, but this disclosure is not limited to these aspects.

[0133] In one or more aspects, a fourth insulating layer 221 may be disposed between the light-shielding layer 211 and the first insulating layer 222. The fourth insulating layer 221 may be an interlayer insulating layer. The fourth insulating layer 221 may include an inorganic insulating material, such as silicon oxide (SiO2). x ), silicon nitride (SiN) x ) or silicon nitride oxide (SiO) x N y However, this disclosure is not limited to these aspects.

[0134] Figure 2 A fourth insulating layer 221 having a single-layer structure is shown, but aspects of this disclosure are not limited thereto. For example, the fourth insulating layer 221 may have a multilayer structure. When the fourth insulating layer 221 has a multilayer structure, the fourth insulating layer 221 may have a structure in which at least two inorganic insulating materials are alternately stacked, each inorganic insulating material including, for example, silicon oxide (SiO2). x ), silicon nitride (SiN) x ) or silicon nitride oxide (SiO) x N y Inorganic materials, but this disclosure is not limited to these aspects.

[0135] Transistor 230 may be disposed on the first insulating layer 222. Transistor 230 may include an active layer 231, a gate electrode 232, a first electrode pattern 233, and a second electrode pattern 234.

[0136] The active layer 231 of transistor 230 can be disposed on the first insulating layer 222.

[0137] The active layer 231 can be various types of semiconductor layers. For example, the active layer 231 may include oxide semiconductor, amorphous silicon, polycrystalline silicon or low-temperature polycrystalline silicon (LTPS), but this disclosure is not limited thereto.

[0138] Figure 2 An active layer 231 with a single-layer structure is shown, but aspects of this disclosure are not limited thereto. For example, the active layer 231 may have a multi-layer structure.

[0139] When the active layer 231 includes an oxide semiconductor material, an auxiliary electrode including a metal or transparent electrode material can be disposed in the remaining region of the active layer 231 other than the channel region.

[0140] A second insulating layer 223 may be disposed on the active layer 231. The second insulating layer 223 may be a gate insulating layer.

[0141] The second insulating layer 223 may include an inorganic insulating material, such as silicon oxide (SiO2). x ), silicon nitride (SiN) x ) or silicon nitride oxide (SiO) x N y However, this disclosure is not limited to these aspects.

[0142] Figure 2 The diagram shows a structure in which a second insulating layer 223 is disposed on a portion of the upper surface of the active layer 231, but aspects of this disclosure are not limited thereto. For example, the second insulating layer 223 may be disposed to cover the upper surface of the active layer 231.

[0143] The gate electrode 232, the first electrode pattern 233, and the second electrode pattern 234 of the transistor 230 can be disposed on the second insulating layer 223.

[0144] The gate electrode 232 may include a conductive material. For example, the gate electrode 232 may include one or more alloys of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), platinum (Pt), titanium (Ti), nickel (Ni), neodymium (Nd), palladium (Pd), silver (Ag), tungsten (W), or copper (Cu), or two or more of these materials, or may include a transparent conductive material. However, aspects of this disclosure are not limited thereto.

[0145] Reference Figure 2 The second insulating layer 223 can be disposed in the region overlapping with the gate electrode 232. The region where the active layer 231 overlaps with the gate electrode 232 can be used as the channel region of the transistor 230. The region where the active layer 231 does not overlap with the gate electrode 232 can be a conductive region.

[0146] For example, the first electrode pattern 233 can be a source electrode, and the second electrode pattern 234 can be a drain electrode. In another example, the first electrode pattern 233 can be a drain electrode, and the second electrode pattern 234 can be a source electrode.

[0147] Each of the first electrode pattern 233 and the second electrode pattern 234 may include a conductive material. For example, each of the first electrode pattern 233 and the second electrode pattern 234 may include one or more alloys of two or more of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), platinum (Pt), titanium (Ti), nickel (Ni), neodymium (Nd), palladium (Pd), silver (Ag), tungsten (W), or copper (Cu), or may include a transparent conductive material. However, aspects of this disclosure are not limited thereto.

[0148] The first electrode pattern 233 and the second electrode pattern 234 can be electrically connected and physically connected to the conductive portion of the active layer 231 through the contact holes of the second insulating layer 223, respectively.

[0149] The gate electrode 232, the first electrode pattern 233, and the second electrode pattern 234 can be disposed in the same layer and comprise the same material.

[0150] The second electrode pattern 234 can be electrically connected to a portion of the upper surface of the light-shielding layer 211 through a contact hole (e.g., a first contact hole) in the first insulating layer 222. For example, the second electrode pattern 234 can be electrically connected to the light-shielding layer 211 through a contact hole. The first contact hole can be formed by penetrating the fourth insulating layer 221, the first insulating layer 222, and the second insulating layer 223.

[0151] Reference Figure 2 and combined Figure 4 In one or more aspects, the display device may include capacitor 212.

[0152] The capacitor 212 may include a first capacitor electrode 212a and a second capacitor electrode 212b on the first capacitor electrode 212a.

[0153] The first capacitor electrode 212a can be a metal plate. For example, the first capacitor electrode 212a can be located in the same layer as the light-shielding layer 211 and include the same material as the light-shielding layer 211. The second capacitor electrode 212b can be located in the same layer as the active layer 231 and is another active layer in a conductive state.

[0154] A third insulating layer 224 for insulating the transistor 230 can be formed on the gate electrode 232, the first electrode pattern 233, and the second electrode pattern 234. The third insulating layer 224 may comprise an inorganic insulating material, such as silicon oxide (SiO2). x ), silicon nitride (SiN)x ) or silicon nitride oxide (SiO) x N y However, this disclosure is not limited thereto. The third insulating layer 224 may have a single-layer or multi-layer structure.

[0155] A planarization layer 241 may be disposed on the third insulating layer 224. The planarization layer 241 may be used to planarize the steps caused by the transistor 230 and various signal lines. The planarization layer 241 may be in the form of an organic layer such as acrylic resin, epoxy resin, phenolic resin, polyamide resin or polyimide resin.

[0156] A light-emitting element ED can be disposed on the planarization layer 241. The light-emitting element ED may include a first electrode PE, an intermediate layer EL, and a second electrode CE. For example, the first electrode PE may be an anode electrode or a pixel electrode, and the second electrode CE may be a cathode electrode or a common electrode. In another example, the first electrode PE may be a cathode electrode or a common electrode, and the second electrode CE may be an anode electrode or a pixel electrode. The area where the first electrode PE, the intermediate layer EL, and the second electrode CE are stacked can be defined as a light-emitting area.

[0157] The first electrode PE can be formed on the planarization layer 241. The first electrode PE can be electrically connected to the first electrode pattern 233 of the transistor 230 through the contact holes of the planarization layer 241 and the third insulating layer 224.

[0158] A dam 242 may be provided on the planarization layer 241. The dam 242 may be formed to cover at least one edge of the first electrode PE on the planarization layer 241 to define a light-emitting region. The dam 242 may include an opening region OA corresponding to the light-emitting region. The dam 242 may be in the form of an organic layer such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0159] The dam 242 may include an opaque material. The dam 242 may be a black dam with high light absorption. In this implementation, the dam 332 can absorb light traveling in the direction of adjacent sub-pixels, thereby preventing color mixing between sub-pixels SP. Furthermore, the dam 332 can absorb external light incident on the display panel 110, thereby reducing reflectivity and improving reflective visibility.

[0160] For example, a black embankment can be formed by dispersing a colorant in a transparent insulating resin. The colorant can be selected from carbon-based pigments, metal oxide-based pigments, or organic pigments. For example, carbon pigments can be selected from carbon black, carbon nanotubes, vantablack, etc., but this disclosure is not limited thereto. For example, metal oxide pigments can be titanium black (TiNxOy) or Cu-Mn-Fe based black pigments, but this disclosure is not limited thereto. For example, organic pigments can be selected from lactam black, perylene black, or aniline black, but this disclosure is not limited thereto. In another example, the colorant can be a mixture of two or more pigments or dyes with different colors.

[0161] although Figure 2 Although not shown, spacers may be provided on the embankment 242. The spacers may be in the form of organic layers such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0162] The intermediate layer EL can be disposed on the first electrode PE. The intermediate layer EL can cover the portion of the dike 242 and the first electrode PE that is not covered by the dike 242. For example, the intermediate layer EL can be an organic light-emitting layer.

[0163] The intermediate EL can emit any of red, green, blue, and white light. The intermediate EL can be, for example, a white light-emitting layer. The intermediate EL can have a series structure in which two or more stacks are arranged. Each of the stacks can include a hole transport layer (HTL), at least one light-emitting layer (EML), and an electron transport layer (ETL). Additionally, a charge generation layer (CGL) can be arranged between the stacks.

[0164] In one or more aspects, the light-emitting element ED can be disposed in the display panel 110 in a bottom-emitting (BE) or top-emitting (TE) structure. For example, in an example where the light-emitting element ED is disposed in a bottom-emitting (BE) structure, the light-emitting element ED can be configured to emit light in the direction toward the substrate 111, i.e., in the downward direction. In another example where the light-emitting element ED is disposed in a top-emitting (TE) structure, the light-emitting element ED can be configured to emit light in the direction away from the substrate 111, i.e., in the upward direction.

[0165] In an example where the light-emitting element ED is configured with a bottom-emitting (BE) structure, the first electrode PE may include a transparent or semi-transparent conductive material capable of allowing light transmission. For example, the first electrode PE may include a transparent conductive oxide (TCO) selected from the group consisting of indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), zinc oxide, and tin oxide. For example, the first electrode PE may include a semi-transparent conductive material, such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag).

[0166] In an example where the light-emitting element (ED) is configured with a top-emitting (TE) structure, the first electrode (PE) may include a metallic material with high reflectivity. For example, the first electrode (PE) may include a high-reflectivity metallic material such as a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and ITO (ITO / Al / ITO), a stacked structure of silver (Ag) and ITO (ITO / Ag / ITO), a stacked structure of molybdenum titanium (MoTi) and ITO (ITO / MoTi / ITO), indium zinc oxide (IZO), a stacked structure of MoTi and ITO (IZO / MoTi / ITO), an APC alloy, and a stacked structure of an APC alloy and ITO (ITO / APC / ITO). The APC alloy is an alloy of silver (Ag), palladium (Pd), and copper (Cu).

[0167] The second electrode CE can be formed on the intermediate layer EL.

[0168] In an example where the light-emitting element ED is configured with a bottom-emitting (BE) structure, the second electrode CE may include a metallic material with high reflectivity. For example, the second electrode CE may include a high-reflectivity metallic material such as a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and ITO (ITO / Al / ITO), a stacked structure of silver (Ag) and ITO (ITO / Ag / ITO), a stacked structure of molybdenum titanium (MoTi) and ITO (ITO / MoTi / ITO), indium zinc oxide (IZO), a stacked structure of MoTi and ITO (IZO / MoTi / ITO), an APC alloy, and a stacked structure of APC alloy and ITO (ITO / APC / ITO).

[0169] In an example where the light-emitting element ED is configured in a top-emitting (TE) structure, the second electrode CE may include a transparent or semi-transparent conductive material capable of allowing light transmission. For example, the second electrode CE may include a transparent conductive oxide (TCO) selected from the group consisting of indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), zinc oxide, and tin oxide. Alternatively, the second electrode CE may include a semi-transparent conductive material such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag).

[0170] In the following discussion, for ease of description, an example in which the light-emitting element ED is set in a bottom-emitting (BE) structure is provided.

[0171] An encapsulation layer 250 can be provided on the second electrode CE.

[0172] The encapsulation layer 250 can be configured to surround the light-emitting element ED. For example, the encapsulation layer 250 can have a multilayer structure in which organic material layers and inorganic material layers are stacked alternately. The inorganic material layers can be used to block oxygen or moisture from penetrating into the light-emitting element ED. The organic material layers can be configured to have a thickness relatively larger than that of the inorganic material layers to adequately cover undesirable substances (particles) that may be generated during the manufacturing process.

[0173] For example, encapsulation layer 250 may include a first encapsulation layer 251 surrounding the light-emitting element ED, a second encapsulation layer 252 surrounding the first encapsulation layer 251, and a third encapsulation layer 253 surrounding the second encapsulation layer 252. Each of the first encapsulation layer 251 and the third encapsulation layer 253 may include an inorganic insulating material, such as silicon oxide (SiO2). x ), silicon nitride (SiN) x ), silicon nitride oxide (SiON) or aluminum oxide (Al) x O y The second encapsulation layer 252 may include at least one organic insulating material selected from the group consisting of acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, benzocyclobutene resin, and fluoropolymer resin, but this disclosure is not limited thereto.

[0174] Figure 3 yes Figure 1 An example of a magnified view of region A. In the following... Figure 3 In the discussion of the configuration, for simplicity, descriptions of the references are omitted or briefly described. Figure 1 and Figure 2 Discussion of features and configurations that are the same, substantially the same, or similar.

[0175] Figure 3This shows the condition after various power lines and signal lines have been inspected during the manufacturing process.

[0176] During the manufacturing process, it is desirable to inspect the appearance of several power lines and signal lines to improve the reliability of the display panel 110 or display device 100. This appearance inspection can be performed visually. However, since it is not easy to accurately assess whether a metal pattern is open or short-circuited visually, an automated visual inspection (AOI) device can be used, which can optically identify the metal pattern and perform the inspection by comparing the identification result with a standard pattern used as an inspection reference. However, since an automated visual inspection (AOI) device may not be able to fully inspect complex structures, a line open / short circuit (LOS) inspection can be performed to more accurately determine whether a metal pattern is open or short-circuited.

[0177] Reference Figure 3 One or more first lines, such as data lines DL, can be disposed on substrate 111 in a first direction, and one or more second lines, such as gate lines GL, can be disposed in a second direction. The first lines and the second lines can be disposed on different layers.

[0178] Reference Figure 3 One or more first-line break regions (DCAs) where corresponding portions of one or more first lines are removed, and one or more second-line break regions (GCAs) where corresponding portions of one or more second lines are removed, can be located in the non-display area (NDA). For example, the non-display area (NDA) may include a first non-display area located at the lower edge of the display panel 110 and a second non-display area located at the left edge of the display panel 110. Pad areas (PA) may be provided in the first non-display area. Dam structures (DM) may be provided in the second non-display area. Figure 3 The diagram shows a dam structure DM positioned in a second non-display area, but the scope of this disclosure is not limited thereto. The dam structure DM may be positioned outside the display panel 110 along a non-display area NDA. For example, at least one dam structure DM may be positioned in at least one of the first to fourth non-display areas.

[0179] One or more first line break regions DCA can be located in the first non-display area. For example, one or more first line break regions DCA can be set between the outermost sub-pixel SP and the pad area PA on the outer edge of the display area DA.

[0180] One or more second-line break regions (GCAs) can be located in non-display areas other than the first non-display area. For example, one or more second-line break regions (GCAs) can be located in at least one of the second, third, and fourth non-display areas. One or more second-line break regions (GCAs) can be located between the outermost sub-pixel SP and the dam structure DM.

[0181] A block can be formed, with the corresponding edges of the first lines, such as data lines DL, extending to the non-display area NDA, connected to the block. In this configuration, a LOS check can be performed to check whether one or more of the first lines are open or short-circuited. For example, an LOS check can be performed to check for open-circuit defects in each of the lines provided on the substrate 111 or short-circuit defects between the lines.

[0182] In addition, in the case of a second line such as a gate line GL, after the second line is formed to have the same potential to prevent damage caused by static electricity generated during the manufacturing process, subsequent processing can be performed.

[0183] According to this configuration, after performing LOS checks and / or subsequent processing on the first and second lines, the first line disconnection process and the second line disconnection process can be performed. This allows the corresponding portions of the first and second lines to be removed from the non-display area NDA.

[0184] The first and second line disconnection processes are separate processes. For example, the second line disconnection process can be performed after the first line disconnection process and subsequent processing have been performed. However, the first line disconnection process, which removes portions of the first line, can be performed simultaneously with the wet etching process, which patterns the second line. In this case, the etching time for the first line set in the first line disconnection region DCA may increase, and therefore, the second line may be over-etched due to the increased etching time.

[0185] Figure 4 This is an example of a cross-sectional view of the display panel 110 according to various aspects of this disclosure. In the following... Figure 4 In the discussion of the configuration, for the sake of brevity, descriptions of the references are omitted or briefly described. Figures 1 to 3 Discussion of features and configurations that are the same, substantially the same, or similar.

[0186] Reference Figure 4In one or more example embodiments, the display panel 110 may include a substrate 111, a light-shielding layer 211 disposed on the substrate 111, a first line such as a data line DL, a first insulating layer 222 disposed on the first line, a thin film transistor 230 disposed on the first insulating layer 222 and including an active layer 231, a gate electrode 232, a first electrode pattern 233 and a second electrode pattern 234, a third insulating layer 224 disposed on the thin film transistor 230, a planarization layer 241 disposed on the third insulating layer 224, and a light-emitting element ED disposed on the planarization layer 241.

[0187] Reference Figure 4 In one or more aspects, the display panel 110 may include a first line break area DCA and a second line break area GCA.

[0188] In one or more aspects, one or more first lines, such as data lines DL, may not be provided in one or more first line break areas DCA. In one embodiment, the first line may be broken into a first portion and a second portion, wherein, after the first line break area DCA has been formed, the second portion is electrically isolated and configured as an island structure. For example, the first line break area DCA may include a substrate 111 and a dam 242 on the substrate 111. For example, in the first line break area DCA, the substrate 111 may be configured to directly contact the dam 242. In one embodiment, the vertical thickness of the dam 242 in the first line break area DCA is greater than the vertical thickness of the dam 242 above another first line.

[0189] In one or more aspects, one or more second lines, such as gate lines GL, may not be disposed in one or more second line break regions GCA. For example, the second line break region GCA may include a substrate 111, a first insulating layer 222 on the substrate 111, a portion of a second insulating layer 223 on the first insulating layer 222, and a dam 242 on the first insulating layer 222 and the second insulating layer 223. For example, in the second line break region GCA, the substrate 111 may be configured not to directly contact the dam 242.

[0190] Reference Figure 4 The dam 242 in the display panel 110 can be a black dam with high light absorption rate.

[0191] Reference Figure 4Internal light emitted from the light-emitting element (ED) can be reflected at the interfaces of the multiple layers disposed in the display panel 110. However, the internal light can be absorbed by the dam 242 disposed in the first line break region DCA, and therefore cannot leave the display panel 110. Similarly, external light can be absorbed by the dam 242 disposed in the first line break region DCA, and therefore is prevented from entering the interior of the display panel 110. According to these configurations, both internal and external light can be absorbed by the dam 242 in the first line break region DCA, and therefore, the display panel 110 can provide the advantages of increased light-blocking efficiency and improved visibility.

[0192] In this structure, the first line break region DCA disposed in the display panel 110 can increase the light-blocking efficiency based on the increased thickness and light density of the embankment 242. Therefore, the display panel 110 can provide improved visibility.

[0193] Figure 5 The conventional gate electrode structure PG and Figure 4 The corresponding cross-section of the gate electrode structure EG in the following. Figure 5 In the discussion of the configuration, for the sake of brevity, descriptions of the references are omitted or briefly described. Figures 1 to 4 Discussion of features and configurations that are the same, substantially the same, or similar.

[0194] Figure 5 A schematic cross-sectional view is shown of a conventional gate electrode structure PG and a gate electrode structure EG in a display panel 110 according to an exemplary embodiment of the present disclosure.

[0195] When a metal pattern is formed by wet etching of a metal layer, the metal layer located beneath the photoresist can be etched by the etchant and thus has an etch bias.

[0196] For example, when the line is etched, the gate electrode 232 may be over-etched. Therefore, in a typical gate electrode structure PG, when the gate electrode 232 is over-etched, the etch bias PB of the gate electrode 232 located below the photoresist PR may increase. When the etch bias PB increases, the resolution of the pattern based on the width PP of the photoresist PR may decrease.

[0197] In the display panel 110 of the exemplary embodiment of this disclosure, lines other than those provided in the first line break region DCA and the second line break region GCA (e.g., the remaining lines) can be protected by an insulating layer. Therefore, these lines can be etched without additional etching. Thus, in the gate electrode structure EG of the exemplary embodiment of this disclosure, since the gate electrode 232 is not additionally etched, the etching bias EB of the gate electrode 232 located below the photoresist PR can also be reduced. When the etching bias EB is reduced, the resolution of the pattern based on the width EP of the photoresist PR can also be increased. Since over-etching of the second lines can be prevented, the distance between the second lines can be reduced, and therefore, the display device 100 can provide the advantage of displaying a high resolution.

[0198] Figure 6 yes Figure 4 An example cross-sectional view of the data lines in the diagram. In the following... Figure 6 In the discussion of the configuration, for the sake of brevity, descriptions of the references are omitted or briefly described. Figures 1 to 5 Discussion of features and configurations that are the same, substantially the same, or similar.

[0199] In one or more example embodiments, the first line included in the display panel 110 may include any one of a data line DL, a low voltage line VSSL, and a high voltage line VDDL.

[0200] Reference Figure 6 The first line, such as a data line DL, can have a multilayer structure comprising two layers. For example, the first line may include a first layer DL1 and a second layer DL2 disposed on the first layer DL1. The first line may include a first layer DL1 comprising a low-reflectivity oxide and a second layer DL2 disposed on the first layer DL1 and comprising a low-resistivity metal.

[0201] The first layer DL1 may include a low-reflectivity material. The first layer DL1 may include a low-reflectivity oxide. For example, the first layer DL1 may include materials derived from molybdenum titanium oxide (MoTiO2). x ), molybdenum tantalum oxide (MoTaO) x ), tungsten oxide (WO x ), molybdenum copper oxide (MoCuO) x ) and molybdenum chromium oxide (MoCrO) x The materials selected from ).

[0202] The second layer DL2 may include a low-resistivity metal. The second layer DL2 may include a metal with low surface resistance. For example, the second layer DL2 may include a material selected from copper (Cu), aluminum (Al), molybdenum (Mo), titanium (Ti) and their alloys (e.g., MoTi).

[0203] Figures 7 to 14 An example process for manufacturing a display panel 110 according to various aspects of this disclosure is shown. In the following... Figures 7 to 14 In the discussion of the configuration, for the sake of brevity, descriptions of the references are omitted or briefly described. Figures 1 to 6 Discussion of features and configurations that are the same, substantially the same, or similar.

[0204] Reference Figure 7 In one or more example embodiments, a light-shielding layer 211, a first insulating layer 222, an active layer 231, a second insulating layer 223, and a gate material layer GM may be sequentially deposited on a substrate 111.

[0205] For example, a light-shielding material layer can be patterned on the substrate 111 to form a first line such as a data line DL, a light-shielding layer 211, and a first capacitor electrode 212a.

[0206] The first insulating layer 222 can be formed to cover a first line such as a data line DL, a light-shielding layer 211, and a first capacitor electrode 212a. In this case, the first insulating layer 222 may not be formed on a portion of the first line such as the data line DL that is disposed in the non-display area, and therefore, a first line break region DCA can be formed.

[0207] For example, a fourth insulating layer 221 may be formed before the first insulating layer 222 is formed. In an example in which the fourth insulating layer 221 is formed, the fourth insulating layer 221 may not be formed in the first wire break region DCA.

[0208] An active material layer can be patterned on the first insulating layer 222, and thus, an active layer 231, a second capacitor electrode 212b, etc., can be formed.

[0209] The second insulating layer 223 can be patterned and formed on the first insulating layer 222. In this case, the second insulating layer 223 can be configured to cover the active layer 231 and the second capacitor electrode 212b. For example, the second insulating layer 223 may not be formed in the first line break region DCA.

[0210] A gate material layer GM can be formed on the second insulating layer 223. The gate material layer GM can also be formed on the first line, such that the gate material layer GM contacts a portion of the first line disconnection region DCA, such as a data line DL. For example, the gate material layer GM can be connected to both ends of the active layer 231 via contact holes formed in the second insulating layer 223, and can be connected to the light-shielding layer 211 via contact holes CH formed in the first insulating layer 222 and the second insulating layer 223.

[0211] A photoresist PR can be formed in the region corresponding to the pad electrode, gate electrode, first electrode pattern, second electrode pattern, and first line break region DCA. In this case, the photoresist PR can be formed in a portion of the gate material layer GM in the non-display area, and thus, a second line break region GCA can be formed.

[0212] Next, refer to Figure 8 The gate material layer GM can be etched to form pad electrodes 213, gate electrodes 232, first electrode patterns 233 and second electrode patterns 234, and second lines such as gate lines GL. For example, a cover material layer CM covering the first line such as data lines DL can be formed in the first line disconnection region DCA. The gate material layer GM can be patterned by a wet etching process.

[0213] Next, refer to Figure 9 After the second insulating layer 223 is etched and patterned, the photoresist PR can be removed.

[0214] Next, refer to Figure 10 A third insulating layer 224 can be patterned and formed on the transistor 230. The third insulating layer 224 can be configured such that the pad portion in which the pad electrode 213 is disposed, the contact hole CH in which the first electrode pattern 233 of the transistor 230 and the light-shielding layer 211 are connected, the first line break region DCA and the second line break region GCA are open.

[0215] Patterning can be performed on the third insulating layer 224 to form a planarization layer 241.

[0216] Next, refer to Figure 11 The first electrode material can be patterned on the planarization layer 241 to form the first electrode PE. The first electrode PE can be electrically connected to the first electrode pattern 233 of the transistor 230 through the contact hole CH formed on the third insulating layer 224 and the planarization layer 241. A pad electrode capping layer 214 can be formed on the pad electrode 213 of the pad portion.

[0217] Next, refer to Figure 12 Wet etching can be used to simultaneously etch and remove lines formed in the first line break region DCA and the second line break region GCA. For example, an etchant can be used to simultaneously remove a first line such as a data line DL, a cover material layer CM formed on the first line, and a second line such as a gate line GL, which are disposed in the first line break region DCA and the second line break region GCA.

[0218] In this case, the lines other than those set in the first line break region DCA and the second line break region GCA can be protected by the first insulating layer 222 or the third insulating layer 224 and therefore will not be additionally etched.

[0219] In particular, when the first line comprises a low-reflectivity oxide, a residual film may appear during the wet etching process, which could increase the etching time. However, as mentioned above, the lines other than those located in the first line break region DCA and the second line break region GCA are protected by an insulating layer and therefore cannot be additionally etched.

[0220] Next, refer to Figure 13 A dam 242 can be formed to expose at least a portion of the first electrode PE. The portion of the first electrode PE exposed by the dam 242 may correspond to the opening region OA of the dam 242. In this case, the dam 242 may be a black dam. The dam 242 may be formed to directly contact the substrate 111 in the first line break region DCA. The dam 242 may be formed to directly contact the first insulating layer 222 in the second line break region GCA.

[0221] Next, refer to Figure 14 The intermediate layer EL can be formed by depositing an intermediate layer EL organic material on the first electrode PE and the dam 242. The second electrode CE can be formed by depositing a second electrode CE metal layer on the intermediate layer EL.

[0222] use Figures 7 to 14 In this example process, the lines located in the first line break region DCA and the second line break region GCA can be etched simultaneously. In this case, the lines other than those located in the first line break region DCA and the second line break region GCA can be protected by the insulating layer and therefore will not be additionally etched.

[0223] Examples, aspects, and embodiments of the display device 100 and display panel 110 described herein can be described as follows.

[0224] According to one or more exemplary embodiments described herein, a display device can be provided, comprising: a substrate including a display area comprising subpixels and a non-display area surrounding the display area; a first line disposed on the substrate and extending in a first direction; a planarization layer disposed on the first line; a light-emitting element including a first electrode disposed on the planarization layer, an intermediate layer disposed on the first electrode, and a second electrode disposed on the intermediate layer; a dam including an opening region for exposing at least a portion of the first electrode; and a first line break region located in the non-display area, wherein a corresponding portion of the first line is removed in the first line break region. In one or more aspects, the substrate and the dam may be configured to contact each other in the first line break region.

[0225] In one or more aspects, in a display device, the dam may include an opaque material.

[0226] In one or more aspects, in a display device, the embankment can be a black embankment.

[0227] In one or more aspects, in a display device, the black rim may comprise at least one of carbon-based pigments, metal oxide-based pigments, and organic pigments.

[0228] In one or more aspects, in a display device, the first line can be any of a data line, a low-voltage line, and a high-voltage line.

[0229] In one or more aspects, in a display device, the first line may include: a first layer comprising a low-reflectivity oxide; and a second layer disposed on the first layer and comprising a low-resistance metal.

[0230] In one or more aspects, in a display device, the first layer may include molybdenum titanium oxide (MoTiO2). x ), molybdenum tantalum oxide (MoTaO) x ), tungsten oxide (WO x ), molybdenum copper oxide (MoCuO) x ) and molybdenum chromium oxide (MoCrO) x The second layer may include materials selected from copper (Cu), aluminum (Al), molybdenum (Mo), titanium (Ti), and their alloys. In one or more aspects, the second layer may include materials selected from copper (Cu), aluminum (Al), molybdenum (Mo), titanium (Ti), and their alloys.

[0231] In one or more aspects, the display device may further include: a first insulating layer configured to cover a first line; a transistor disposed on the first insulating layer and including an active layer, a gate electrode, a first electrode pattern, and a second electrode pattern; a second line disposed on the same layer as the gate electrode; and a second line break region located in a non-display area, wherein a corresponding portion of the second line is removed in the second line break region. In one or more aspects, the first insulating layer and the barrier may be in contact with each other in the second line break region.

[0232] In one or more aspects, the display device may further include a light-shielding layer configured to overlap at least a portion of the active layer. In one or more aspects, the light-shielding layer may be located between the substrate and the first insulating layer.

[0233] In one or more aspects, the display device may further include a capacitor comprising: a first capacitor electrode located in the same layer as the light-shielding layer; and a second capacitor electrode on the first capacitor electrode located in the same layer as the active layer.

[0234] In one or more aspects, in a display device, the first electrode pattern of a transistor can be electrically connected to a light-shielding layer through contact holes in a first insulating layer.

[0235] In one or more aspects, in a display device, the light-shielding layer and the first line can be disposed in the same layer.

[0236] In one or more aspects, the display device may further include a third insulating layer disposed on the transistor. In one or more aspects, the first electrode of the light-emitting element may be electrically connected to the first electrode pattern of the transistor through contact holes in the third insulating layer and the planarization layer.

[0237] In one or more aspects, in a display device, a non-display area may include: a first non-display area located outside the display area in a first direction; a second non-display area located outside the display area in a second direction perpendicular to the first direction; a third non-display area located outside the display area in a direction opposite to the first direction; and a fourth non-display area located outside the display area in a direction opposite to the second direction. In one or more aspects, a first line break area may be located within the first non-display area. In one or more aspects, a second line break area may be located within at least one of the second to fourth non-display areas.

[0238] In one or more aspects, in a display device, a first non-display area may include a pad area, and a first line break area may be disposed between the outermost subpixel disposed at the outer edge of the display area and the pad area.

[0239] In one or more aspects, in a display device, at least one of the second to fourth non-display areas may include a dam structure, and the second line break region may be disposed between the outermost sub-pixel disposed at the outer edge of the display area and the dam structure.

[0240] According to one or more aspects described herein, a display device may be provided that can improve light-shielding efficiency by including a structure in which a black dam is configured as a contact substrate.

[0241] According to one or more aspects described herein, a display device may be provided that can improve visibility by including a structure in which internal light and external light are blocked in a non-display area.

[0242] According to one or more aspects described herein, a display device may be provided that is capable of presenting high resolution by including a structure in which excessive etching of the metal layer is prevented and the distance between lines is minimized.

[0243] According to one or more aspects described herein, a display device may be provided that enables processing optimization by including a structure in which metal layers located in different layers are simultaneously removed.

[0244] According to one or more aspects described herein, a display device may be provided that is capable of presenting high resolution and being driven with low power by including a structure in which the distance between lines can be minimized.

[0245] According to one or more aspects described herein, a display device may be provided, comprising: a substrate including a display area comprising subpixels and a non-display area; a first line disposed on the substrate and extending in a first direction; an insulating layer disposed on the first line; a light-emitting element including a first electrode disposed on the insulating layer, an intermediate layer disposed on the first electrode, and a second electrode disposed on the intermediate layer; a dam including an opening region for exposing at least a portion of the first electrode; and a first line break region located in the non-display area. In one or more aspects, in the display device, a first portion of the first line is broken from a second portion of the first line in the first line break region. In one or more aspects, in the display device, the vertical thickness of the dam in the first line break region is greater than the vertical thickness of the dam above another first line.

[0246] In one or more aspects, in a display device, the substrate and the embankment may be in contact with each other in the first line disconnected area.

[0247] In one or more aspects, a dike can be a black dike.

[0248] In one or more aspects, in a display device, each of the first line and the other first line can be selected from a data line, a low-voltage line, and a high-voltage line.

[0249] In one or more aspects, in a display device, the second portion of the first line may be electrically isolated.

[0250] In one or more aspects, the display device may further include a second line break region located in a non-display area, wherein a corresponding portion of the second line is removed in the second line break region. In one or more aspects, the first and second line break regions may be configured such that light is blocked in the non-display area.

[0251] In one or more aspects, the substrate and the embankment may not contact each other in the second line disconnected area.

[0252] The foregoing description has been presented to enable any person skilled in the art to make and use the technical concepts of this disclosure, and has been provided in the context of a particular application and its requirements. Various modifications, additions, and substitutions to the described embodiments will be readily apparent to those skilled in the art, and the principles described herein can be applied to other embodiments and applications without departing from the scope of this disclosure. The foregoing description and figures provide examples of the technical concepts of this disclosure for illustrative purposes only. That is, the disclosed embodiments are intended to illustrate the scope of the technical concepts of this disclosure.

Claims

1. A display device, comprising: A substrate, the substrate including a display area containing sub-pixels and a non-display area surrounding the display area; A first line is disposed on the substrate and extends in a first direction; A planarization layer is disposed on the first line; A light-emitting element, the light-emitting element comprising a first electrode disposed on the planarization layer, an intermediate layer disposed on the first electrode, and a second electrode disposed on the intermediate layer; A dam, the dam including an opening region for exposing at least a portion of the first electrode; as well as A first line break area is located in the non-display area, and the corresponding portion of the first line is removed in the first line break area. The substrate and the embankment are in contact with each other in the first line break area.

2. The display device according to claim 1, wherein, The embankment comprises opaque material.

3. The display device according to claim 1, wherein, The dike in question is a black dike.

4. The display device according to claim 3, wherein, The black embankment contains at least one of carbon-based pigments, metal oxide-based pigments, and organic pigments.

5. The display device according to claim 1, wherein, The first line is selected from data lines, low voltage lines, and high voltage lines.

6. The display device according to claim 1, wherein, The first line includes: A first layer, the first layer comprising a low-reflectivity oxide; and The second layer is disposed on the first layer and includes a low-resistance metal.

7. The display device according to claim 6, wherein, The first layer comprises molybdenum titanium oxide (MoTiO) x ), molybdenum tantalum oxide (MoTaO) x ), tungsten oxide (WO x ), molybdenum copper oxide (MoCuO) x ) and molybdenum chromium oxide (MoCrO) x The second layer comprises materials selected from copper (Cu), aluminum (Al), molybdenum (Mo), titanium (Ti), and their alloys.

8. The display device according to claim 1, further comprising: A first insulating layer, the first insulating layer being configured to cover the first wire; A transistor disposed on the first insulating layer and including an active layer, a gate electrode, a first electrode pattern, and a second electrode pattern; The second line is disposed on the same layer as the gate electrode; as well as The second line break area is located in the non-display area, and the corresponding portion of the second line is removed in the second line break area. The first insulating layer and the dike are in contact with each other in the second line disconnection area.

9. The display device according to claim 8, further comprising a light-shielding layer, the light-shielding layer being configured to overlap at least a portion of the active layer. in, The light-shielding layer is located between the substrate and the first insulating layer.

10. The display device according to claim 9, further comprising a capacitor, the capacitor comprising: The first capacitor electrode is located in the same layer as the light-shielding layer; as well as A second capacitor electrode on the first capacitor electrode, the second capacitor electrode being located in the same layer as the active layer.

11. The display device according to claim 9, wherein, The first electrode pattern of the transistor is electrically connected to the light-shielding layer through the contact hole of the first insulating layer.

12. The display device according to claim 11, wherein, The light-shielding layer and the first line are disposed in the same layer.

13. The display device according to claim 8, further comprising a third insulating layer disposed on the transistor. in, The first electrode of the light-emitting element is electrically connected to the first electrode pattern of the transistor through the contact holes of the third insulating layer and the planarization layer.

14. The display device according to claim 8, wherein, The non-display area includes: A first non-display area, which is located outside the display area in the first direction; The second non-display area is located outside the display area in a second direction perpendicular to the first direction; A third non-display area, the third non-display area being located outside the display area in a direction opposite to the first direction; and A fourth non-display area, which is located outside the display area in a direction opposite to the second direction. The first line break area is located in the first non-display area, and the second line break area is located in at least one of the second to the fourth non-display areas.

15. The display device according to claim 14, wherein, The first non-display area includes a pad area, and wherein the first line break area is disposed between the outermost sub-pixel located at the outer edge of the display area and the pad area; and / or Wherein, at least one of the second to the fourth non-display areas includes a dam structure, and the second line break area is disposed between the outermost sub-pixel disposed at the outer edge of the display area and the dam structure.

16. A display device, comprising: A substrate, the substrate including a display area containing sub-pixels and a non-display area; A first line is disposed on the substrate and extends in a first direction; An insulating layer is disposed on the first line; A light-emitting element, the light-emitting element comprising a first electrode disposed on the insulating layer, an intermediate layer disposed on the first electrode, and a second electrode disposed on the intermediate layer; A dam, the dam including an opening region for exposing at least a portion of the first electrode; as well as A first line break area is located in the non-display area, wherein a first portion of the first line is broken from a second portion of the first line in the first line break area; Wherein, the vertical thickness of the embankment in the region where the first line is broken is greater than the vertical thickness of the embankment above the other first line.

17. The display device according to claim 16, wherein, The substrate and the embankment are in contact with each other in the region where the first line is broken.

18. The display device according to claim 16, wherein, The dike in question is a black dike.

19. The display device according to claim 16, wherein, Each of the first line and the other first line is selected from data lines, low voltage lines, and high voltage lines.

20. The display device according to claim 16, wherein, The second part of the first line is electrically isolated.

21. The display device according to claim 16, further comprising a second line break region located in the non-display region, wherein a corresponding portion of the second line is removed in the second line break region, wherein... The first and second line break regions are configured such that light is blocked in the non-display area.

22. The display device according to claim 21, wherein, The substrate and the embankment do not contact each other in the area where the second line is disconnected.

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