A multi-core hardware queue synchronization method and device

Abstract

This specification relates to the field of computer technology, and more particularly to a method and apparatus for synchronizing hardware queues across multiple cores. The method configures a first hardware queue on a slave core to a non-arbitrable state; when a master core connects to a second hardware queue, the first hardware queue on the slave core is configured to an arbitrable state; wherein the second hardware queue corresponds to the first hardware queue; during the process of the master core completing the connection or disconnection of the second hardware queue, the connection or disconnection of the first hardware queue on the slave core is synchronized. Using the embodiments of this specification, the error in the completion time of task calculations on each core is reduced, software performance sampling is facilitated, task performance is improved, and thus processor energy efficiency is enhanced.

Description

Technical Field

[0001] This specification relates to the field of computer technology, and in particular to a hardware queue synchronization method and apparatus for multi-core chips. Background Technology

[0002] The Command Processor (CP) is a core component of the General Purpose Graphics Processing Unit (GPGPU), primarily responsible for parsing and executing parallel computing tasks. Typically, the CP receives command streams (such as several encapsulated kernel dispatch tasks) from the CPU-side driver. Different command streams are pre-filled or continuously populated into different software queues by the driver. First, the CP maps these software queues one by one to the hardware queues of the CP's computing engine. Then, these hardware queues are sequentially connected and processed by the CP's queue manager using a round-robin arbitration method. When processing and parsing a kernel dispatch task within the command stream, the CP, in conjunction with its downstream hardware modules, performs work-group segmentation, distribution, wave unpacking, and resource allocation for the kernel dispatch task. Finally, the resource-allocated waves are emitted to the computing units for computation.

[0003] However, in multi-core scenarios, the hardware queues of each core cannot work synchronously, resulting in low task dispatch efficiency on the core.

[0004] Improving the efficiency of task dispatch in multi-core scenarios is an urgent problem to be solved. Summary of the Invention

[0005] To address the problems in the prior art, this specification provides a method and apparatus for synchronizing hardware queues of multiple cores, which can solve the problem of asynchronous hardware queues of multiple cores.

[0006] This specification provides a hardware queue synchronization method for multiple cores, the method running on the master core, including: Configure the first hardware queue from the chip to a non-arbitrable state; When the master chip is connected to the second hardware queue, the first hardware queue of the slave chip is configured to an arbitrable state; wherein, the second hardware queue has a corresponding relationship with the first hardware queue; During the process of the master chip completing the connection or disconnection of the second hardware queue, the connection or disconnection of the slave chip's first hardware queue is completed synchronously.

[0007] As a further aspect of this specification, configuring the first hardware queue from the chip to a non-arbitrable state further includes: When the master chip disconnects the second hardware queue, the corresponding first hardware queue in the slave chip is configured to disconnect, and the first hardware queue of the slave chip is configured to be in a non-arbitrable state.

[0008] As a further aspect of this specification, after configuring the first hardware queue from the chip to a non-arbitrable state, it also includes: It is confirmed that the slave chip has been disconnected from the connected hardware queue.

[0009] As a further aspect of this specification, determining that the slave chip has been disconnected from the connected hardware queue further includes: When the master core is disconnecting from the connected hardware queue, and the slave core is about to complete the disconnection from the connected hardware queue, a first flag is configured. The first flag determines that the slave chip has been disconnected from the connected hardware queue.

[0010] As a further aspect of this specification, determining that the slave chip has been disconnected from the connected hardware queue further includes: When the master chip is disconnected from the connected hardware queue, during the process of the slave chip entering the disconnection process from the connected hardware queue, a second flag is configured. The second flag determines that the chip has begun to disconnect from the connected hardware queue.

[0011] As a further aspect of this specification, the process of the main chip completing the connection of the second hardware queue further includes: Configure the third flag of the first hardware queue connected from the core; When the first hardware queue is disconnected from the master chip, the disconnection process of the first hardware queue is executed after the third flag of the first hardware queue is changed due to the disconnection of the corresponding second hardware queue by the master chip.

[0012] As a further aspect of this specification, the simultaneous connection or disconnection of the first hardware queue of the slave chip during the process of the master chip completing the connection or disconnection of the second hardware queue further includes: During the process of the master chip connecting to the second hardware queue, it is determined that the master chip and the slave chip have disconnected from their respective connected hardware queues. The master chip establishes a connection with the second hardware queue, and the slave chip establishes a connection with the first hardware queue.

[0013] As a further aspect of this specification, during the connection process between the master chip and the slave chip and the second hardware queue, determining that the master chip and the slave chip have disconnected from their respective connected hardware queues further includes: The first and second flags of the hardware queue that is disconnected from the slave core are synchronized twice. The master core configures a third flag for the hardware queue that is disconnected from the slave core.

[0014] As a further aspect of this specification, the arbitration status, the first mark, the second mark, and the third mark are implemented by one or a combination of the following methods: Registers or software variables.

[0015] As a further aspect of this specification, the first flag, the second flag, and the third flag are implemented through one or more registers.

[0016] This specification also provides a hardware queue synchronization device for multiple cores, comprising: The configuration unit configures the first hardware queue of the slave chip to a non-arbitrable state; when the master chip connects to the second hardware queue, it configures the first hardware queue of the slave chip to an arbitrable state; wherein the second hardware queue has a corresponding relationship with the first hardware queue. The processing unit is configured to simultaneously complete the connection or disconnection of the first hardware queue of the slave core during the process of the master core completing the connection or disconnection of the second hardware queue.

[0017] This specification also provides a general-purpose graphics processor that performs the hardware queue synchronization method described above.

[0018] This specification also provides a computer device, including a memory, a computer program stored on the memory and executable on a general-purpose graphics processor, and the general-purpose graphics processor described above.

[0019] This specification also provides a computer-readable storage medium storing computer instructions that, when executed by a processor, implement the above-described method.

[0020] This specification also provides a computer program product, which includes a computer program that, when executed by a processor, implements the above-described method.

[0021] By utilizing the embodiments in this specification, the error in calculating the end time of a task on each chip is reduced, software performance sampling is facilitated, task performance is improved, and thus the processor's energy efficiency is enhanced. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments or prior art of this specification, the drawings used in the description of the embodiments or prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this specification. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 The diagram shown is a schematic of the command processor structure of the multi-chip architecture GPGPU in the embodiments of this specification. Figure 2 The diagram shown is a schematic of the hardware queue for the computational engine running on the CP on different chips in the embodiments of this specification. Figure 3 The diagram shown is a flowchart of a hardware queue synchronization method for multiple cores according to an embodiment of this specification. Figure 4 The diagram shown is a register diagram of the arbitration state in an embodiment of this specification; Figure 5 The diagram shown is a schematic of selecting a valid hardware queue for arbitration in an embodiment of this specification; Figure 6 The diagram shown is a schematic representation of the structure of a flag implemented using a register in an embodiment of this specification. Figure 7a and Figure 7b The diagram shown is a flowchart illustrating how a master chip controls the hardware queues of each slave chip in an embodiment of this specification. Figure 8a and Figure 8b The diagram shown is a flowchart illustrating how the master chip controls each slave chip to disconnect from the connected hardware queue, as described in this specification embodiment. Figure 9a and Figure 9b The diagram shown is a flowchart illustrating how the master chip controls the reconnection of each slave chip to the hardware queue, as described in an embodiment of this specification. Figure 10 The diagram shown is a structural schematic of the hardware queue synchronization device for multiple cores according to an embodiment of this specification. Figure 11 The diagram shown is a schematic representation of a computer device provided in an embodiment of this specification. Detailed Implementation

[0024] The technical solutions in the embodiments of this specification will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this specification, and not all embodiments. Based on the embodiments in this specification, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this specification.

[0025] like Figure 1 The diagram illustrates the command processor structure of a multi-core architecture GPGPU according to an embodiment of this specification. In this diagram, the CP (Client / Processor) scheduling engine is located on the main core, while the CP computing engines and queue managers are distributed across each core. Each core's CP computing engine has the same number of hardware queues (Q0-QN). These hardware queues are controlled by their respective CP queue managers and are independently connected and disconnected using a round-robin arbitration method. Once the hardware queues of a CP computing engine on a core are connected, the CP computing engine processes the command stream in the corresponding software queue, partially splitting a kernel dispatch task within the command stream, allocating resources, and dispatching it to the computing unit of the current core.

[0026] like Figure 2 The diagram illustrates the hardware queues of the compute engines within the CP on different cores in embodiments of this specification. The diagram shows the connections between the hardware queues on each core. The hardware queues of the compute engines within the CP on each core are obtained by mapping the same software queue to the CP scheduling engine on the main core. At any given time, each compute engine within the CP on each core may have completely different hardware queues executing the command streams in its corresponding software queue. This is because the hardware queues of each compute engine within the CP on each core complete kernel dispatch tasks at different times, and new tasks arrive at different times in different sequences. Furthermore, all hardware queues (Q0-QN) are connected using a round-robin arbitration method. Therefore, a scenario may occur where completely different hardware queues on different cores are working simultaneously. Figure 2 One possible scenario is as follows: On chip 0 (the master chip), the hardware queue currently running in the CP's internal computing engine is Q1, and the next hardware queue to be connected is Q2; on chip 1 (hereinafter referred to as the slave chip or remote chip), the hardware queue currently running in the CP's internal computing engine is Q3, and the next hardware queue to be connected is Qn; on chip 2 (hereinafter referred to as the slave chip or remote chip), the hardware queue currently running in the CP's internal computing engine is Qm, and the next hardware queue to be connected is QN; on chip 3 (hereinafter referred to as the slave chip or remote chip), the hardware queue currently running in the CP is QN, and the next hardware queue to be connected is Q1. Hardware queues are only allowed to be connected to the CP's internal queue manager in the arbitration list. A connected hardware queue is called a connected queue, and it can process the command stream in its corresponding software queue. A connected queue can be disconnected after a period of time. A disconnected hardware queue is called a disconnected queue, and it cannot process the command stream in its corresponding software queue. The connection-disconnection process of a hardware queue is actually a context switching process.

[0027] Because the compute engines within the CP on each chip may be running completely different connection queues at any given time, and because the queue managers within the CP on each chip (responsible for scheduling the polling arbitration, connection, and disconnection of hardware queues) connect subsequent hardware queues in a polling scheduling manner, this results in a long time interval between the hardware queues of the compute engines within the CP on different chips completing a certain kernel dispatch task of the command stream in their corresponding software queue. This makes it difficult for the driver software to perform performance profiling on a certain kernel dispatch task of the command stream in the same software queue on each chip. Furthermore, when there are a large number of mapped hardware queues, after the kernel dispatch task is split and distributed to work-groups, the resource allocation module in the computing unit will expand the work-groups into waves and allocate resources to these waves. Once the computing unit on the chip is running at near full load, there will not be enough resources to allocate to these waves. As a result, each time the hardware queue is connected, a kernel dispatch in the command stream of the corresponding software queue will complete a very small part of the task distribution on the chip. At this time, the following situation will occur: when the computing unit on a chip is close to 100% load, the new connection queue will go through many context switches (disconnect-connect-disconnect-connect…) before a kernel dispatch task in the command stream of the software queue corresponding to the hardware queue can be distributed. This will waste a lot of resources on inefficient hardware queue connections, resulting in a decrease in processor performance.

[0028] like Figure 3 The diagram shows a flowchart of a hardware queue synchronization method for multiple cores according to an embodiment of this specification. The diagram illustrates how the master core configures whether slave cores can be arbitrated, and confirms the synchronization status of the slave core hardware queue with the master core hardware queue before hardware queue connection. This completes the synchronization connection of hardware queues for all cores (including the master and slave cores), reducing the problem of multiple context switches required to complete the distribution of a kernel dispatch task on a particular core due to a surge in load on that core, thus improving processor energy efficiency. The method runs on the master core and specifically includes: Step 301: Configure the first hardware queue from the chip to a non-arbitrable state; Step 302: When the master chip is connected to the second hardware queue, the first hardware queue of the slave chip is configured to an arbitrable state; wherein the second hardware queue has a corresponding relationship with the first hardware queue. Step 303: During the process of the main chip completing the connection or disconnection of the second hardware queue, the connection or disconnection of the slave chip's first hardware queue is completed simultaneously.

[0029] The method described in this specification greatly reduces the error in calculating the end time of a kernel dispatch task on each chip, facilitates software performance sampling of the performance of the kernel dispatch task on a chip, shortens the time spent dispatching kernel dispatch tasks to each chip, improves the performance of a single kernel dispatch task, and thus improves the energy efficiency of the processor.

[0030] As an embodiment of this specification, configuring the first hardware queue from the chip to a non-arbitrable state further includes: When the master chip disconnects the second hardware queue, the corresponding first hardware queue in the slave chip is configured to disconnect, and the first hardware queue of the slave chip is configured to be in a non-arbitrable state.

[0031] In this embodiment, when the master chip disconnects a hardware queue, the slave chip also disconnects the corresponding hardware queue. Furthermore, after disconnecting a hardware queue, the slave chip can configure the hardware queue to a non-arbitrable state. The first hardware queue refers to one or more of the multiple hardware queues in the slave chip, and the second hardware queue refers to one or more of the multiple hardware queues in the master chip.

[0032] In other embodiments, the hardware queues of the slave chip can be configured to be non-arbitrable in advance, or the hardware queues of the slave chip can be configured to be non-arbitrable by default, thereby preventing the slave chip from spontaneously connecting to the hardware queues according to the scheduling policy of the local scheduler.

[0033] In other embodiments, the master chip can configure the first hardware queue of the slave chip to a non-arbitrable state. When the master chip disconnects a hardware queue, the corresponding first hardware queue of the slave chip is also disconnected synchronously, and the arbitration state of the first hardware queue of the slave chip is also configured to a non-arbitrable state. For example, if the hardware queue disconnected by the master chip is Qn, then the hardware queue disconnected by the slave chip can also be Qn, and the arbitration state of the hardware queue Qn in the slave chip will be configured to a non-arbitrable state.

[0034] In other embodiments, the hardware queue disconnected from the main chip and the hardware queue disconnected from the slave chip may have other correspondences. For example, if the hardware queue disconnected from the main chip is Qn, then the hardware queue disconnected from the slave chip may be Qn+1, Qn-1, Qn+m, or Qn-m, etc., where n and m are natural numbers and n + m <= N and nm >= 0.

[0035] The non-arbitrable state may include a slave chip being unable to connect to the hardware queue based on its corresponding arbitration state. The arbitrable state may include a slave chip being able to connect to the hardware queue based on its corresponding arbitration state to form a connected queue. For example, an arbitration state of 0 indicates an arbitrable state, and an arbitration state of 1 indicates a non-arbitrable state. When the first hardware queue is in an arbitrable state, the slave chip can select it as the next hardware queue to connect to; when the first hardware queue is in a non-arbitrable state, the slave chip cannot select it as the next hardware queue to connect to.

[0036] As one embodiment of this specification, after configuring the first hardware queue from the chip to a non-arbitrable state, the following is also included: It is confirmed that the slave chip has been disconnected from the connected hardware queue.

[0037] In this embodiment, determining whether the slave chip has completed the preparation for connecting to the first hardware queue may further include confirming whether the first hardware queue of the slave chip is in a non-arbitrable state. For example, the arbitration state of the first hardware queue can be used to determine whether the hardware queue is in a non-arbitrable state. If it is in a non-arbitrable state and has been disconnected from the connected hardware queue, it indicates that the first hardware queue of the slave chip has completed the preparation for connecting to the first hardware queue.

[0038] As one embodiment of this specification, determining that the slave chip has been disconnected from the connected hardware queue further includes: When the master core is disconnecting from the connected hardware queue, and the slave core is about to complete the disconnection from the connected hardware queue, a first flag is configured. The first flag determines that the slave chip has been disconnected from the connected hardware queue.

[0039] In this embodiment, when the hardware queue of the master chip enters the disconnect function, or after the main process of the disconnect function is completed in the master chip's hardware queue, the slave chip configures a first flag indicating that the hardware queue has completed disconnection. After the slave chip's hardware queue enters the disconnect function and completes the main process of the disconnect function, it sends a first flag indicating that the disconnection is complete to the master chip's hardware queue; or it marks the first flag indicating that the slave chip's hardware queue has completed disconnection through a register; or it can be done through a software variable, whereby when the slave chip's hardware queue executes the disconnection function, a value is assigned to the corresponding variable (first flag) to report to the master chip's hardware queue that the slave chip has completed disconnection from the previous hardware queue.

[0040] As one embodiment of this specification, determining that the slave chip has been disconnected from the connected hardware queue further includes: When the master chip is disconnected from the connected hardware queue, during the process of the slave chip entering the disconnection process from the connected hardware queue, a second flag is configured. The second flag determines that the chip has begun to disconnect from the connected hardware queue.

[0041] In this embodiment, when the main chip's hardware queue enters the disconnect function, or after the main chip's hardware queue completes the main process of the disconnect function, the slave chip configures a second flag indicating the start of the hardware queue disconnection. After the slave chip's hardware queue enters the disconnect function, before executing the main process of the disconnect function, it sends the second flag indicating the start of the disconnection to the main chip's hardware queue; or it marks the slave chip's hardware queue disconnection start flag using a register; or it can use a software variable, assigning a value to the corresponding variable (second flag) when the slave chip's hardware queue executes the disconnect function, to feedback to the main chip's hardware queue that the slave chip has begun disconnecting from the previous hardware queue. This second flag can be used as the state where the slave chip's hardware queue has started disconnecting, or it can be combined with the first flag as the state where the slave chip's hardware queue has completed disconnecting.

[0042] The second flag is combined with the first flag to indicate that the slave chip's hardware queue has completed disconnection. Based on the slave chip's second flag, the master chip can determine that the slave chip's hardware queue has begun executing the disconnection function. After the disconnection function completes, based on the slave chip's first flag, it can determine that the slave chip's hardware queue has completed the disconnection operation from the previous hardware queue. By using the two hardware queue disconnection status flags of the slave chip, it can be ensured that the slave chip has completed the disconnection operation from the previous hardware queue, thus ensuring that the slave chip's hardware queue disconnection operation is synchronized with the master chip's hardware queue disconnection operation. As an embodiment of this specification, the process of the master chip completing the connection of the second hardware queue further includes: Configure the third flag of the first hardware queue connected from the core; When the first hardware queue is disconnected from the master chip, the disconnection process of the first hardware queue is executed after the third flag of the first hardware queue is changed due to the disconnection of the corresponding second hardware queue by the master chip.

[0043] In this embodiment, during the process of the master chip connecting to the second hardware queue, a third flag is configured for the corresponding hardware queue (i.e., the first hardware queue) of the slave chip. For example, the third flag is configured as 1, indicating that the hardware queue of the slave chip has been connected. When the master chip needs to disconnect from the second hardware queue after a period of time, the third flag of the corresponding hardware queue of the slave chip is configured, for example, the third flag is configured as 0. When the slave chip disconnects the corresponding hardware queue at the same time as the master chip disconnects the hardware queue, it repeatedly checks whether the third flag is 0. If it is not 0, the query is repeated. If it is 0, the subsequent steps of disconnecting the hardware queue are entered. That is to say, the third flag can ensure that the hardware queue that the slave chip has connected to maintains the connection relationship of the hardware queue when the master chip has not disconnected it. Only when the hardware queue of the master chip is disconnected will the slave chip execute the hardware queue disconnection process, thereby ensuring the synchronization of the hardware queues of the slave chip and the master chip.

[0044] As one embodiment of this specification, the synchronous connection or disconnection of the first hardware queue of the slave chip during the process of the master chip completing the connection or disconnection of the second hardware queue further includes: During the process of the master chip connecting to the second hardware queue, it is determined that the master chip and the slave chip have disconnected from their respective connected hardware queues. The master chip establishes a connection with the second hardware queue, and the slave chip establishes a connection with the first hardware queue.

[0045] In this embodiment, besides synchronizing with the master chip when the slave chip disconnects from the hardware queue, the master chip can also configure a flag indicating that the last connected hardware queue of the master and slave chips has been disconnected when the master chip connects to the hardware queue. This ensures synchronization between the master and slave chips when connecting to the hardware queue. Determining whether the master and slave chips have disconnected from the connected hardware queue can be achieved using the method described in the previous embodiment. This is done by determining whether the disconnection is complete based on a first flag and a second flag. Specifically, the master and slave chips can synchronize the first and second flags of the recently disconnected hardware queue twice. Simultaneously with configuring the first and second flags of the slave chip's disconnecting hardware queue, the master chip can also configure the first and second flags of the corresponding hardware queue to indicate whether the disconnection of the hardware queue is complete. When configuring the flags of the corresponding hardware queues of the master and slave chips, the flags can be configured by modifying the values ​​of the registers corresponding to the hardware queues of the master and slave chips, or by modifying the software variables corresponding to these hardware queues.

[0046] The connection between the master core and slave core and the hardware queue can be implemented using existing connection functions, which will not be elaborated here.

[0047] As an embodiment of this specification, the arbitration status, the first mark, the second mark, and the third mark are implemented through one or a combination of the following methods: Registers or software variables.

[0048] In this embodiment, the first flag, the second flag, and the third flag can be represented by the same register or software variable, with different bits representing the meaning of each value; or the arbitration status, the first flag, the second flag, and the third flag can also be represented by different registers or software variables, with different bits representing the meaning of each value.

[0049] For example, such as Figure 4 The diagram illustrates the register representation of the arbitration status in an embodiment of this specification. Each hardware queue (Q0-QN) of the CP (Concurrent Processing Engine) on each chip is equipped with an arbitration signal register to indicate its arbitration status. This register can have two possible values: 0 and 1. A value of 1 indicates that the hardware queue will not be arbitrated by the CP queue manager (i.e., non-arbitrable state), while a value of 0 indicates that the hardware queue can be arbitrated by the CP queue manager (i.e., arbitrable state). When a new kernel dispatch task arrives in the software queue corresponding to the hardware queue, the CP queue manager on each chip determines whether the hardware queue will be arbitrated by checking if its arbitration signal register is 0. Once the hardware queue is allowed to be arbitrated, when the CP queue manager on each chip polls and schedules it, the hardware queue will be connected as a connected queue, and then processing will begin for a specific kernel dispatch task in the command stream of the software queue corresponding to that hardware queue. Figure 4 As shown, each hardware queue has one arbitration signal register. When bit 0 is 1, it indicates that the hardware queue cannot enter the arbitration connection; when bit 0 is 0, it indicates that the hardware queue will enter the arbitration connection. The arbitration signal registers of each slave hardware queue are set by the master chip. The master chip clears bit 0 of the arbitration signal register of the same hardware queue in the slave chip, indicating that the hardware queue can enter arbitration in the slave chip. When a slave chip disconnects a hardware queue, it sets bit 0 of the arbitration signal register of that hardware queue to 1, indicating that the hardware queue in the slave chip cannot be arbitrated. Alternatively, when a software queue is mapped to a hardware queue, the master chip sets bit 0 of the arbitration signal register of the corresponding hardware queue in the slave chip to 1, indicating that the corresponding hardware queue in the slave chip cannot be arbitrated.

[0050] like Figure 5 The diagram illustrates the selection of a valid hardware queue for arbitration in an embodiment of this specification. Within each chip's CP (Constant Controller), the queue manager determines whether to poll and connect to a hardware queue based on its availability. The availability of each hardware queue is determined by several hardware queue signals. The value of the arbitration signal register [Hardware Queue] represents the hardware signal after the value of the corresponding arbitration signal register has been converted (inverted). The remaining valid signals [Hardware Queue] represent the results of combinations of other status signals of the hardware queue, such as AND, OR, and NOT operations. These other status signals may include whether the hardware queue has encountered an error, whether it has a task, and whether it has been successfully mapped. When the value of the arbitration signal register [Hardware Queue] (inverted) ANDed with the remaining valid signals [Hardware Queue] equals true (e.g., 1), the hardware queue is valid and will be arbitrated and connected by the queue manager within the CP of that chip. If the logical calculation result is not true (e.g., 0), the hardware queue is invalid and cannot be arbitrated and connected by the queue manager within the CP of that chip.

[0051] For example, such as Figure 6The diagram illustrates the structure of a flag implemented using registers in an embodiment of this specification. The diagram shows the implementation of the first, second, and third flags using three registers, with all three flags having the same structure. This embodiment uses four chips as an example (other embodiments may use eight, sixteen, etc.), including one master chip and three slave chips. Each hardware queue of each chip may include these three synchronization registers, or may only include a portion of them. As shown, bits 0-15 of synchronization registers 0 (second flag), 1 (first flag), and 2 (third flag) are value bits, representing the state of each chip's hardware queue. Bits 16-31 are write enable bits corresponding to bits 0-15. In other embodiments, if there are more chips, synchronization registers 0-2 can use more value bits to identify the state of each chip's hardware queue. For example, to set the least significant bit (bit 0) of synchronization register 0 to 1, synchronization register 0 needs to be configured with a value of 0x10001; to set the least significant bit (bit 0) of synchronization register 0 to 0, synchronization register 0 needs to be configured with a value of 0x10000. On slave chips, synchronization registers 0, 1, and 2 all use the least significant bit (bit 0), and its value is configured by the corresponding hardware queue on the master chip. On the master chip, synchronization registers 0 and 1 for each hardware queue use bits 1-3 to mark the synchronization status of the corresponding hardware queue for each slave chip; synchronization register 2 does not need to be set on the master chip.

[0052] The method described in the embodiments of this specification can achieve synchronization between the master and slave kernels by configuring the corresponding flag bits of the master and slave kernel hardware queues during the process of disconnecting and connecting the hardware queues of the master kernel. This greatly reduces the error in the calculation of the end time of a certain kernel dispatch task on each kernel, facilitates software performance sampling of the performance of the kernel dispatch task on a certain kernel, shortens the time spent dispatching kernel dispatch tasks to each kernel, improves the performance of a single kernel dispatch task, and thus improves the energy efficiency of the processor.

[0053] like Figure 7a and Figure 7bThe diagram shows a flowchart illustrating how a master chip controls the connection of each slave chip to a hardware queue in an embodiment of this specification. The diagram describes how the master chip configures the registers of each chip to achieve synchronization of the connection to the hardware queue. In this embodiment, the arbitration signal register of the hardware queue of each slave chip is set to 1 beforehand, thereby preventing each slave chip from connecting to the hardware queue independently. Each chip can have multiple flag registers. For example, in this embodiment, the master chip includes synchronization register 0 and synchronization register 1, and the slave chips include synchronization register 0, synchronization register 1, and synchronization register 2. The synchronization registers in the following embodiments will only be described using the values ​​of the lowest 4 bits as an example.

[0054] Step 701: The queue manager of core 0 initiates a connection request for the hardware queue Qm and enters the connection function entry point.

[0055] In this step, the arbitration signal register of hardware queues Qm (core 1-core 3) is still 1. This is because the arbitration signal register of hardware queues Qm (core 1-core 3) is configured to 1 by default during initialization to prevent the queue managers of core 1-core 3 from spontaneously arbitrating connection hardware queues Qm. At this time, the synchronization registers 0 and 1 of the local hardware queue Qm (core 0) are 0000, indicating no synchronization flag; the synchronization registers 0 and 1 of hardware queues Qm (core 1-core 3) are 0000, indicating no synchronization flag; and the synchronization register 2 of hardware queues Qm (core 1-core 3) is 0000, indicating no spin-wait (busy wait) flag.

[0056] Step 702: Hardware queue Qm of core 0 clears the arbitration signal register of hardware queues Qm of cores 1-3 to allow the local queue managers of cores 1-3 to arbitrate connections to hardware queue Qm (hardware queues with the same number on all cores are called mirror queues).

[0057] In this step, hardware queue Qm of core 0 sets the arbitration signal register of hardware queues Qm of cores 1-3 to 0, indicating that remote cores are allowed to arbitrate connections to hardware queues Qm. The queue managers of cores 1-3 can now begin connecting to their local hardware queues Qm.

[0058] Step 703: Core 0 hardware queue Qm sequentially queries the synchronization register 0 corresponding to all local hardware queues (Q0-QN) to confirm whether there are any hardware queues that need to be synchronized.

[0059] In this step, the synchronization register 0 of all hardware queues (Q0-QN) in chip 0 is 0000, which means that no queues were previously connected to chips 1-3 and there is no synchronization requirement.

[0060] Step 704: The hardware queue Qm of core 0 configures the synchronization register 2 of hardware queues Qm of core 1-core 3 to 0001, ensuring that when hardware queues Qm of core 1-core 3 enter the disconnect function later, they will enter the busy-wait logic (waiting until core 0 completes the disconnect process of hardware queue Qm before unlocking).

[0061] In this step, the synchronization register 2 of hardware queues Qm from core 1 to core 3 is set from 0000 to 0001, with bit 0 set to 1, which corresponds to the busy-wait enable of hardware queue Qm. This prevents the hardware queue Qm of the slave core from disconnecting prematurely, ensuring that the slave hardware queue Qm can only continue to disconnect after the master core hardware queue Qm has completed its disconnection.

[0062] Step 705: Core 0 hardware queue Qm sets the synchronization register 0 of core 1-core 3 hardware queues Qm to 0001, indicating that subsequent synchronization starts from core hardware queue Qm. At the same time, it sets the flag bit of the synchronization register 0 of the local hardware queue Qm to 1110, which represents the status of the first synchronization process.

[0063] In this step, the synchronization register 0 of the chip 1-chip 3 hardware queue Qm is set from 0000 to 0001, indicating the start of subsequent synchronization from chip hardware queue Qm. The synchronization register 0 of the local hardware queue Qm of chip 0 changes from 0000 to 1110, indicating the status of the first subsequent synchronization process.

[0064] Step 706: The core 0 hardware queue Qm executes the main flow of the connection function, including triggering packet prefetching, preloading configuration of relevant registers, and restoring previously saved tasks.

[0065] In this step, the current register values ​​are maintained (the states of synchronization register 0 and synchronization register 2 remain unchanged) to prepare for and initialize the subsequent kernel dispatch tasks of the hardware queue Qm.

[0066] In step 707, the hardware queue Qm of core 0 completes the connection process and exits the connection function. Next, the hardware queue Qm can start processing kernel dispatch tasks (including work-groups splitting, waves unpacking, waves resource allocation, and dispatching to computing units).

[0067] In this step, the final configuration values ​​are maintained (arbitration signal register is 0, synchronization register 0 and synchronization register 2 remain unchanged), the hardware queue Qm of core 0 is successfully connected, and it waits to process the kernel dispatch task.

[0068] When configuring the registers corresponding to each hardware queue Qm in the aforementioned core 0 hardware queue to complete the local hardware queue Qm connection operation, cores 1-3 will also synchronously complete the connection operation of their respective hardware queue Qm. The following steps can be executed starting from each core after step 702 mentioned above. The following only uses core 1 as an example for illustration: Step 711: After the arbitration signal register of hardware queue Qm is cleared to 0, the queue manager of core 1 initiates a connection request for hardware queue Qm and enters the connection function entry point.

[0069] In this step, the arbitration signal register of hardware queue Qm of chip 1 has been set to 0, that is, arbitration has been enabled; the synchronization register 0 of hardware queue Qm of chip 1 has been set to 0001, indicating that chip 1 will start synchronization when performing hardware queue Qm disconnection operation; the synchronization register 2 of hardware queue Qm of chip 1 has been configured to 0001, indicating that chip 1 will first enter busy waiting logic when performing hardware queue Qm disconnection operation.

[0070] Step 712: The main flow of the connection function is executed in the hardware queue Qm of core 1, which prepares and initializes for the subsequent kernel dispatch tasks of the hardware queue Qm.

[0071] In this step, the registers of hardware queue Qm in kernel 1 maintain their current values, that is, the states of synchronization register 0 and synchronization register 2 remain unchanged. Hardware queue Qm will complete tasks such as prefetching data packets, preloading and configuring relevant registers, and restoring previously saved tasks, in preparation for executing kernel dispatch tasks simultaneously with hardware queue Qm in the main kernel.

[0072] In step 713, the hardware queue Qm of chip 1 completes the connection process and exits the connection function. Next, the hardware queue Qm can start processing kernel dispatch tasks (including work-group splitting, wave expansion, wave resource allocation, and dispatch to computing units).

[0073] In this step, the arbitration signal register is kept at 0, the states of synchronization register 0 and synchronization register 2 remain unchanged, the hardware queue Qm of core 1 is successfully connected, and it waits to process the kernel dispatch task.

[0074] like Figure 8a and Figure 8b The diagram shows a flowchart illustrating how the master chip controls each slave chip to disconnect from the connected hardware queue in an embodiment of this specification. The diagram describes the synchronization process when the slave chip hardware queue Qm and the master chip hardware queue Qm disconnect from the connected hardware queue Qm by configuring synchronization register 0, synchronization register 1, and synchronization register 2.

[0075] Step 801: The queue manager of core 0 initiates a disconnect request for hardware queue Qm and enters the disconnect function entry point.

[0076] In this step, since the kernel dispatch task for hardware queue Qm of core 0 has been completed, but it is unnecessary to continuously occupy this hardware queue while waiting for the kernel dispatch task to complete its calculation, it should switch to the next hardware queue for urgent processing, or the polling arbitration strategy requires switching to the next hardware queue, or the hardware queue needs to be unmapped from the software queue to be remapped to a new software queue. Therefore, core 0 needs to disconnect from hardware queue Qm. The synchronization register 2 of hardware queues Qm of cores 1-3 has a value of 0001, which is the busy-wait flag set when core 0 connected to hardware queue Qm. When hardware queues Qm of cores 1-3 subsequently enter the disconnection function, they will busy-wait on this flag until it reaches 0. If it is 0, the subsequent steps to disconnect hardware queue Qm will continue. If it is not 0, the synchronization register 2 of hardware queue Qm will be queried repeatedly until it reaches 0. The synchronization register 0 of the local hardware queue Qm of core 0 has a value of 1110.

[0077] Step 802, the hardware queue Qm of core 0 executes the disconnect main process.

[0078] In this step, disconnecting the hardware queue Qm of core 0 from the main process may include: stopping the continued issuance of work-groups from the hardware queue Qm, terminating the resource allocation of expanded waves, saving and reclaiming the hardware resources (such as the ring buffer, status register, etc.) occupied by the local hardware queue Qm, clearing the unprocessed data stream in the hardware queue Qm, and finally ensuring that the hardware queue Qm enters an idle state.

[0079] Step 803: The synchronization register 2 of hardware queues Qm for core 0 is set from 0001 to 0000.

[0080] In this step, under the control of hardware queue Qm of core 0, the busy-wait logic of hardware queues Qm of core 1 to core 3 is released, so that hardware queues Qm of core 1 to core 3 do not need to wait continuously when they enter the disconnect function, or although they have already entered the disconnect function, the busy-wait logic has been released, so that hardware queues Qm of core 1 to core 3 can continue to execute the disconnect process.

[0081] In step 804, the hardware queue Qm of core 0 completes all disconnection logic, exits the disconnection function, and the queue manager marks the hardware queue Qm as disconnected, so that it can be rescheduled for reconnection later.

[0082] In this step, the synchronization register 0 of the hardware queue Qm of chip 0 remains at 1110, the hardware queue Qm of chip 0 has been safely disconnected, and the associated hardware resources can continue to be used when the hardware queue Qm is reconnected.

[0083] Before the hardware queue Qm of core 0 completes the disconnection operation, after configuring the synchronization register 2 corresponding to the hardware queues Qm of cores 1-3, the hardware queues Qm of cores 1-3 can continue to perform the disconnection operation. The following steps can be executed by each slave core after the aforementioned step 803. The following only uses core 1 as an example for illustration: Step 811: The queue manager of core 1 initiates a disconnect request for hardware queue Qm and enters the disconnect function entry point.

[0084] In this step, the synchronization register 2 of hardware queue Qm of chip 1 has either been set to 0000 by hardware queue Qm of chip 0, or has not yet been set to 0000 by hardware queue Qm of chip 0 (in which case, hardware queue Qm of chip 1 will keep busy waiting until it is set to 0000 by hardware queue Qm of chip 0); the synchronization register 0 of hardware queue Qm of chip 1 was set to 0001 when chip 0 was connected to hardware queue Qm earlier; the synchronization register 1 of hardware queue Qm of chip 1 is still 0000; the arbitration signal register of hardware queue Qm of chip 1 was set to 0 by hardware queue Qm of chip 0 before connecting to hardware queue Qm (arbitration connection only begins after being set to 0).

[0085] In step 812, the hardware queue Qm of core 1 continuously checks the value of the local synchronization register 2. If it is not 0, it enters the busy-wait logic until it becomes 0000 before continuing execution.

[0086] In this step, hardware queue Qm of chip 1 checks the value of synchronization register 2. If it is 0000, it means that hardware queue Qm of chip 0 has completed the disconnection, and hardware queue Qm of chip 1 can continue to execute the disconnection process (proceeding to the subsequent step 813); if it is 0001, hardware queue Qm of chip 1 is busy waiting for the value of synchronization register 2 to be 0000 in order to ensure that hardware queue Qm of chip 0 can continue to execute the disconnection process after hardware queue Qm of chip 0 has completed the disconnection, so as to avoid hardware queue Qm of chip 1 performing the disconnection operation in advance, which would cause subsequent synchronization state disorder.

[0087] Step 813: Core 1 hardware queue Qm clears its synchronization register 0 from 0001 to 0000, and at the same time clears the corresponding flag bit of the synchronization register 0 of core 0 hardware queue Qm to 0.

[0088] In this step, the hardware queues Qm of cores 1-3 that are disconnecting and Qn of core 0 that are connecting are synchronized for the first time. After the synchronization register 0 of hardware queue Qm of core 0 is set to 0000, it indicates that the hardware queue Qn of core 0 that is connecting and the hardware queues Qm of cores 1-3 that are disconnecting have completed the first synchronization. The synchronization register 0 of the local hardware queues Qm of cores 1-3 changes from 0001 to 0000, and the synchronization register 0 of the local hardware queue Qm of core 0 changes from 1110 to 0000 by hardware queues Qm of cores 1-3 (the corresponding flag is cleared to 0).

[0089] Step 814: The hardware queue Qm of core 1 executes the disconnect main process.

[0090] In this step, disconnecting the hardware queue Qm of core 1 may include: stopping the distribution of work-groups from the hardware queue Qm to the computing engine, terminating the resource allocation of expanded waves; saving and reclaiming the hardware resources (such as the ring buffer, status register, etc.) occupied by the local hardware queue Qm; clearing up the unprocessed data stream of the hardware queue Qm, and finally ensuring that the hardware queue Qm enters an idle state.

[0091] Step 815: Core 1 hardware queue Qm clears its synchronization register 1 from 0001 to 0000, and at the same time clears the corresponding flag bit of the synchronization register 1 of core 0 hardware queue Qm to 0.

[0092] In this step, the hardware queues Qm of cores 1-3 that are disconnecting synchronize with the hardware queue Qn of core 0 that is connecting for the second time. After the synchronization register 1 of the hardware queue Qm of core 0 is set to 0000, it indicates that the hardware queue Qn of core 0 that is connecting has completed the second synchronization with the hardware queue Qm of cores 1-3 that are disconnecting. The synchronization register 1 of the local hardware queues Qm of cores 1-3 changes from 0001 to 0000, and the synchronization register 1 of the local hardware queue Qm of core 0 changes from 1110 to 0000 by the hardware queues Qm of cores 1-3 (the corresponding flag is cleared to 0).

[0093] Step 816: Core 1's local hardware queue Qm sets its arbitration signal register from 0 to 1.

[0094] In this step, in order to prevent the local queue manager of core 1 from arbitrarily arbitrating connections to the hardware queue Qm in the future, and to ensure that the hardware queue Qm of core 1 is only allowed to be re-enabled when the hardware queue Qm of core 0 is initiated to connect, so as to avoid the hardware queue Qm of core 1 being incorrectly scheduled by its local queue manager, the arbitration signal register of the hardware queue Qm of core 1 is set to 1.

[0095] Step 817: Hardware queue Qm of core 1 completes all disconnection operations and exits the disconnection function. The local queue manager marks hardware queue Qm as disconnected and waits for subsequent core 0 hardware queue Qm to be reconnected to regain control of the connection of hardware queue Qm of core 1.

[0096] In this step, the values ​​of synchronization register 0 / synchronization register 1 / synchronization register 2 of hardware queue Qm of chip 1 are 0000 / 0000 / 0000 (all synchronization flags have been cleared). Hardware queue Qm of chip 1 can be configured to set its arbitration signal register to 1 (disabling subsequent arbitration connections), or the arbitration signal register of hardware queue Qm of chip 1 can be configured to 1 by hardware queue Qn that chip 0 is currently connecting to. Thus, hardware queue Qm of chip 1 has been safely disconnected, and the hardware resources to which it belongs can continue to be used when hardware queue Qm of chip 1 is reconnected.

[0097] like Figure 9a and Figure 9b The diagram shows a flowchart illustrating how a master chip controls each slave chip to connect to a new hardware queue Qn, as described in this embodiment of the specification. The diagram depicts the synchronization process between the master chip and the slave chip's disconnected hardware queue Qm when connecting to the new hardware queue Qn, as well as the process by which the master chip controls the slave chips to connect to the hardware queue Qn. The master and slave chips are synchronously connected to the same new hardware queue Qn by configuring the synchronization register 0 and synchronization register 1 of the master chip's hardware queue Qm through the slave chip's hardware queue Qm.

[0098] Step 901: The queue manager of core 0 initiates a connection request for the hardware queue Qn and enters the connection function entry point.

[0099] In this step, the hardware queue Qm previously connected to cores 1-3 is currently in the disconnection process. The synchronization register 0 of the local hardware queue Qm of cores 1-3 is 0001 (indicating that the first synchronization has not been completed when the hardware queue Qm of cores 1-3 is disconnected). The status of the synchronization registers of each core in the current step is as follows: the arbitration signal register of hardware queue Qn of cores 1-3 is 1 (by default, arbitration connection of hardware queue Qn to cores 1-3 is disabled), the synchronization register 0 of the local hardware queue Qm of core 0 is 1110 (the first synchronization has not been completed when the hardware queue Qm of cores 1-3 is disconnected), the synchronization register 1 of the local hardware queue Qm of core 0 is 0000 (the second synchronization has not started when the hardware queue Qm of cores 1-3 is disconnected), and the synchronization register 0 / synchronization register 1 / synchronization register 2 of hardware queue Qn of cores 1-3 are 0000 / 0000 / 0000 respectively (at this time, hardware queue Qn of cores 1-3 has no synchronization mark).

[0100] Step 902: The hardware queue Qn that core 0 is connecting to sets the arbitration signal register of hardware queues Qn from core 1 to core 3 from 1 to 0, allowing the local queue managers of core 1 to core 3 to arbitrate the connection to the hardware queue Qn.

[0101] In this step, the hardware queue Qn that core 0 is connecting to enables the local queue managers of cores 1-3 to begin connecting to their local hardware queues Qn, and the arbitration signal register of hardware queues Qn of cores 1-3 is 0.

[0102] Step 903: The hardware queue Qn that core 0 is currently connecting to sequentially queries the synchronization register 0 of all local hardware queues (Q0-QN). It is found that the synchronization register 0 of the local hardware queue Qm is 1110 (not 0), indicating that when the hardware queues Qm of core 1-core 3 disconnected, the first synchronization with the hardware queue Qn that core 0 is currently connecting to was not yet completed. Therefore, hardware queue Qm needs to be synchronized (that is, the hardware queue Qn that core 0 is currently connecting to needs to wait for the hardware queues Qm of core 1-core 3 to disconnect before continuing to connect).

[0103] In step 904, the hardware queue Qn that core 0 is connecting to configures the synchronization register 1 of the hardware queues Qm of cores 1-3 to 0001, and at the same time configures the flag of the synchronization register 1 of the local hardware queue Qm to 1110, so as to indicate whether the second synchronization between the hardware queue Qn that core 0 is connecting to and the hardware queues Qm that cores 1-3 are disconnecting is complete.

[0104] In this step, the synchronization register 1 of the hardware queues Qm of core 1-core 3 is configured from 0000 to 0001 by the hardware queue Qn to which core 0 is connected, and the synchronization register 1 of the local hardware queue Qm of core 0 is configured from 0000 to 1110.

[0105] Step 905: The hardware queue Qn that core 0 is connecting to continuously queries the synchronization register 0 of the local hardware queue Qm until its value becomes 0000. At this time, it means that the hardware queues Qm of core 1 to core 3 have completed the first synchronization with the hardware queue Qn that core 0 is connecting to during the disconnection process, that is, the synchronization register 0 of the local hardware queue Qm of core 0 has been cleared to 0 (step 813 above).

[0106] In this step, by querying the synchronization register 0 of hardware queue Qm for chip 0, the first synchronization during the disconnection process with hardware queues Qm from chip 1 to chip 3 can be ensured. After the first synchronization is completed with all hardware queues Qn that chip 0 is connecting to and hardware queues Qm that chip 1 to chip 3 are disconnecting from, the synchronization register 0 of the local hardware queue Qm of chip 0 changes from 1110 to 0000.

[0107] In step 906, the hardware queue Qn that core 0 is connecting to continuously queries the synchronization register 1 of the local hardware queue Qm until its value becomes 0000. At this time, it means that the hardware queues Qm of cores 1 to 3 have completed the second synchronization with the hardware queue Qn that core 0 is connecting to during the disconnection process, that is, the synchronization register 1 of the local hardware queue Qm of core 0 has been cleared to 0 (step 815 above).

[0108] In this step, by querying the synchronization register 1 of hardware queue Qm for chip 0, it can be ensured that the second synchronization during the disconnection process of hardware queues Qm from chip 1 to chip 3 is completed. At this point, hardware queues Qm from chip 1 to chip 3 have been safely disconnected, and hardware queues Qn from chip 1 to chip 3 will be arbitrated for connection. After the second synchronization is completed between hardware queue Qn that chip 0 is connecting to and hardware queues Qm from chip 1 to chip 3 that are disconnecting, the synchronization register 1 of the local hardware queue Qm of chip 0 changes from 1110 to 0000.

[0109] Step 907: Core 0 is configuring the synchronization register 2 of the hardware queue Qn that core 1-core 3 hardware queues Qn are connecting to.

[0110] In this step, the hardware queue Qn of core 0 causes the hardware queues Qn of cores 1-3 to enter a busy-wait logic when they subsequently enter the disconnect function (waiting for the hardware queue Qn of core 0 to complete the disconnect process before releasing this busy-wait logic, step 812), to prevent the hardware queues Qn of cores 1-3 from having their synchronization state disordered due to premature disconnection. The synchronization register 2 of the hardware queues Qn of cores 1-3 is configured from 0000 to 0001.

[0111] The execution order of steps 905-907 above does not need to be specified.

[0112] Step 908: The hardware queue Qn that core 0 is connecting to configures the synchronization register 0 of hardware queues Qn (core 1-core 3) to 0001, and at the same time configures the synchronization register 0 of the local hardware queue Qn to 1110, in order to indicate whether the first synchronization process with the hardware queues Qn (core 1-core 3) that are being disconnected is completed when core 0 connects to a new hardware queue Qp.

[0113] Step 909: Core 0 is executing the main flow of the connection function in the hardware queue Qn it is connecting to.

[0114] In this step, the main connection process of the connection function for the kernel 0 hardware queue Qn can include: prefetching data packets for the hardware queue Qn, preloading and configuring relevant registers, and restoring previously saved tasks. This prepares the hardware queue Qn for subsequent kernel dispatch task execution (such as work-group distribution, wave expansion and resource allocation, and sending the allocated waves to the computing unit).

[0115] In step 910, the hardware queue Qn of core 0 completes all connection logic, exits the connection function, and the queue manager marks the hardware queue Qn as connected, after which kernel dispatch tasks can begin to be processed.

[0116] At this step, the synchronization register 0 of hardware queue Qn for kernel 0 is 1110, indicating the synchronization status between kernel 0 and the hardware queues Qn that kernels 1-3 are disconnecting when kernel 0 connects to a new hardware queue Qp. The synchronization register 0 / synchronization register 1 for hardware queue Qm of kernel 0 are 0000 / 0000 respectively, indicating that the disconnection synchronization of hardware queues Qm from kernels 1-3 has been completed. At this point, hardware queue Qn of kernel 0 is successfully connected and awaits processing of the kernel dispatch task for hardware queue Qn.

[0117] After configuring the arbitration signal registers corresponding to hardware queues Qn of core 1-3 to be 0 in the hardware queue Qn of core 0, the local hardware queues Qn of core 1-3 can synchronously start the connection operation. The following steps can be executed by each slave core after the aforementioned step 902. The following is only an example using core 1: Step 911: The chip 1 hardware queue manager initiates a connection request for the hardware queue Qn and enters the connection function entry point.

[0118] In this step, the queue manager of core 1 detects that the arbitration signal register of the local hardware queue Qn has been cleared to 0 (step 902), and the local hardware queue Qm has completed the disconnection process (step 817, the arbitration signal register of the hardware queue Qm of core 1 is set to 1). Therefore, it starts arbitrating the connection to the local hardware queue Qn and enters the connection function entry point. At this time, the state of each register of the hardware queue Qn of core 1 is as follows: the arbitration signal register of the local hardware queue Qn of core 1 is 0, indicating that the hardware queue Qn of core 1 is in a state that can be arbitrated; the synchronization register 0 / synchronization register 2 of the local hardware queue Qn of core 1 is configured to 0001 / 0001 by the hardware queue Qn of core 0, indicating that the hardware queue Qn of core 1 needs to synchronize with the newly connected hardware queue Qp of core 0 when performing the disconnection process; the arbitration signal register of the local hardware queue Qm of core 1 is 1, indicating that the hardware queue Qm has been prohibited from being arbitrated by the queue manager of core 1, and the hardware queue Qm has previously completed the disconnection.

[0119] Step 912: Core 1 hardware queue Qn executes the main flow of the connection function.

[0120] In this step, the kernel 1 hardware queue Qn will complete tasks such as prefetching data packets, preloading and configuring relevant registers, and restoring previously saved tasks, in preparation for executing the kerneldispatch task together with the main kernel's hardware queue Qn.

[0121] In step 913, the hardware queue Qn of core 1 completes all connection logic and exits the connection function. The local queue manager marks the hardware queue Qn as connected, and it will then prepare to process the kerneldispatch task together with the hardware queue Qn of core 0.

[0122] In this step, the register statuses of the relevant hardware queues for chip 1 are as follows: the arbitration signal register for hardware queue Qn of chip 1 is 0, indicating that hardware queue Qn of chip 1 has been allowed to arbitrate; the synchronization register 0 / synchronization register 2 of hardware queue Qn of chip 1 are 0001 / 0001 respectively, indicating that the synchronization flag of hardware queue Qn of chip 1 has been configured; the arbitration signal register for hardware queue Qm of chip 1 is 1, indicating that hardware queue Qm of chip 1 has been disabled to arbitrate and has been disconnected. Hardware queue Qn of chip 1 is successfully connected and will perform kernel dispatch tasks (including work-group splitting, wave expansion, wave resource allocation, and deployment to compute units) together with hardware queue Qn of chip 0.

[0123] like Figure 10The diagram shown is a structural schematic of a hardware queue synchronization device for multiple cores according to an embodiment of this specification. This diagram illustrates a device for operating the methods described in the above embodiments. Each functional module can be implemented through circuits, or the functions of each module can be accomplished through a combination of instruction sets and circuits. Specifically, the device includes: Configuration unit 1001 configures the first hardware queue of the slave chip to a non-arbitrable state; when the master chip connects to the second hardware queue, it configures the first hardware queue of the slave chip to an arbitrable state; wherein, the second hardware queue has a corresponding relationship with the first hardware queue. The processing unit 1002 is configured to simultaneously complete the connection or disconnection of the first hardware queue of the slave chip during the process of the master chip completing the connection or disconnection of the second hardware queue.

[0124] The methods and apparatus in the embodiments of this specification greatly reduce the error in calculating the end time of a kernel dispatch task on each kernel chip, facilitate software performance sampling of the performance of the kernel dispatch task on a kernel chip, shorten the time spent dispatching the kernel dispatch task to each kernel chip, improve the performance of a single kernel dispatch task, and thus improve the energy efficiency of the processor.

[0125] This specification also provides a general-purpose graphics processing unit (GPGPU) that performs the above-described multi-core hardware queue synchronization method.

[0126] like Figure 11The diagram illustrates a computer device according to an embodiment of this specification. The computer device in this embodiment may include a general-purpose graphics processor (GPU) as described in this embodiment, referred to as a processor, and uses the aforementioned multi-core hardware queue synchronization method. This method can be run on the computer device in this embodiment to execute the methods described in this specification. The computer device 1102 may include one or more processors 1104, such as one or more central processing units (CPUs), each of which can implement one or more hardware threads. The computer device 1102 may also include any memory 1106 for storing any kind of information, such as code, settings, data, etc. Non-limitingly, for example, memory 1106 may include any type of RAM, any type of ROM, flash memory, hard disk, optical disk, etc. More generally, any memory can use any technology to store information. Furthermore, any memory can provide volatile or non-volatile retention of information. Furthermore, any memory can represent a fixed or removable component of the computer device 1102. In one scenario, when processor 1104 executes associated instructions stored in any memory or combination of memories, computer device 1102 can perform any operation of the associated instructions. Computer device 1102 also includes one or more drive mechanisms 1108 for interacting with any memory, such as hard disk drive mechanisms, optical disk drive mechanisms, etc.

[0127] Computer device 1102 may also include an input / output module 1110 (I / O) for receiving various inputs (via input device 1112) and providing various outputs (via output device 1114). A specific output mechanism may include a presentation device 1116 and an associated graphical user interface (GUI) 1118. In other embodiments, the input / output module 1110 (I / O), input device 1112, and output device 1114 may be omitted, and the device may function solely as a computer device within a network. Computer device 1102 may also include one or more network interfaces 1120 for exchanging data with other devices via one or more communication links 1122. One or more communication buses 1124 couple the components described above together.

[0128] Communication link 1122 can be implemented in any way, such as via a local area network, a wide area network (e.g., the Internet), a point-to-point connection, or any combination thereof. Communication link 1122 may include any combination of hardwired links, wireless links, routers, gateway functions, name servers, etc., governed by any protocol or combination of protocols.

[0129] This specification also provides computer-readable instructions, wherein when a processor executes the instructions, the program therein causes the processor to perform the methods described above.

[0130] This specification also provides a computer-readable storage medium storing a computer program that, when executed by a processor, performs the methods described above.

[0131] This specification also provides a computer program product, which includes a computer program that, when executed by a processor, implements the above-described method.

[0132] It should be understood that in the various embodiments of this specification, the sequence number of each process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this specification.

[0133] It should also be understood that, in the embodiments of this specification, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this specification generally indicates that the preceding and following related objects have an "or" relationship.

[0134] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed in this specification can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of each example have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this specification.

[0135] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0136] In the several embodiments provided in this specification, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the couplings or direct couplings or communication connections shown or discussed may be indirect couplings or communication connections through some interfaces, devices, or units, or they may be electrical, mechanical, or other forms of connection.

[0137] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of the embodiments described in this specification, depending on actual needs.

[0138] Furthermore, the functional units in the various embodiments of this specification can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0139] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this specification, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this specification. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0140] This specification uses specific embodiments to illustrate the principles and implementation methods of this specification. The descriptions of the above embodiments are only for the purpose of helping to understand the methods and core ideas of this specification. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this specification. Therefore, the content of this specification should not be construed as a limitation of this specification.

Claims

1. A hardware queue synchronization method for multi-core components, characterized in that, The method operates on the main core and includes: Configure the first hardware queue from the chip to a non-arbitrable state; When the master chip is connected to the second hardware queue, the first hardware queue of the slave chip is configured to an arbitrable state; wherein, the second hardware queue has a corresponding relationship with the first hardware queue; During the process of the master chip completing the connection or disconnection of the second hardware queue, the connection or disconnection of the slave chip's first hardware queue is completed synchronously.

2. The method according to claim 1, characterized in that, Configuring the first hardware queue from the chip to a non-arbitrable state further includes: When the master chip disconnects the second hardware queue, the corresponding first hardware queue in the slave chip is configured to disconnect, and the first hardware queue of the slave chip is configured to be in a non-arbitrable state.

3. The method according to claim 1, characterized in that, After configuring the first hardware queue from the chip to a non-arbitrable state, the following is also included: It is confirmed that the slave chip has been disconnected from the connected hardware queue.

4. The method according to claim 3, characterized in that, Determining that the slave chip has been disconnected from the connected hardware queue further includes: When the master core is disconnecting from the connected hardware queue, and the slave core is about to complete the disconnection from the connected hardware queue, a first flag is configured. The first flag determines that the slave chip has been disconnected from the connected hardware queue.

5. The method according to claim 4, characterized in that, Determining that the slave chip has been disconnected from the connected hardware queue further includes: When the master chip is disconnected from the connected hardware queue, during the process of the slave chip entering the disconnection process from the connected hardware queue, a second flag is configured. The second flag determines that the chip has begun to disconnect from the connected hardware queue.

6. The method according to claim 5, characterized in that, The process of the main chip completing the connection of the second hardware queue further includes: Configure the third flag of the first hardware queue connected from the core; When the first hardware queue is disconnected from the master chip, the disconnection process of the first hardware queue is executed after the third flag of the first hardware queue is changed due to the disconnection of the corresponding second hardware queue by the master chip.

7. The method according to claim 6, characterized in that, During the process of the master chip completing the connection or disconnection of the second hardware queue, the synchronous completion of the connection or disconnection of the slave chip's first hardware queue further includes: During the process of the master chip connecting to the second hardware queue, it is determined that the master chip and the slave chip have disconnected from their respective connected hardware queues. The master chip establishes a connection with the second hardware queue, and the slave chip establishes a connection with the first hardware queue.

8. The method according to claim 7, characterized in that, During the process of the master chip connecting to the second hardware queue, determining that the master chip and the slave chip have disconnected from their respective connected hardware queues further includes: The master and slave cores synchronize twice for the first and second flags of the disconnected hardware queue; The master core configures a third flag for the hardware queue that is disconnected from the slave core.

9. The method according to claim 1, characterized in that, The arbitration status, the first indicator, the second indicator, and the third indicator are achieved through one or a combination of the following methods: Registers or software variables.

10. The method according to claim 9, characterized in that, The first flag, the second flag, and the third flag are implemented through one or more registers.

11. A hardware queue synchronization device with multiple cores, characterized in that... include: The configuration unit configures the first hardware queue of the slave chip to a non-arbitrable state; when the master chip connects to the second hardware queue, it configures the first hardware queue of the slave chip to an arbitrable state; wherein the second hardware queue has a corresponding relationship with the first hardware queue. The processing unit is configured to simultaneously complete the connection or disconnection of the first hardware queue of the slave core during the process of the master core completing the connection or disconnection of the second hardware queue.

12. A general-purpose graphics processor, characterized in that, The general-purpose graphics processor executes the hardware queue synchronization method described in any one of claims 1-10.

13. A computer device comprising a memory and a computer program stored in the memory and executable on a general-purpose graphics processor, characterized in that: It also includes a general-purpose graphics processor as described in claim 12 above.

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