An Automated Data Analysis Method for Integrated Circuit Chip Performance Testing

Abstract

This invention discloses an automated data analysis method, system, and storage medium for integrated circuit chip performance testing, belonging to the field of integrated circuit testing technology. The method includes: S1: acquiring raw test data streams in real-time or near real-time from an automated test equipment (ATE), the raw test data streams including multi-batch, multi-site, and multi-pin multi-dimensional test parameters; S2: performing multi-dimensional spatiotemporal alignment and standardization cleaning on the raw test data streams to construct a test dataset with a unified format; S3: performing primary anomaly detection on the test dataset based on an adaptive dynamic threshold algorithm, marking potential failure data points. This invention achieves full automation and intelligence of the test data process from acquisition and analysis to decision feedback, significantly improving the accuracy of defect detection, analysis efficiency, and adaptive optimization capability of the testing process.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit testing and data analysis technology, specifically to an automated data analysis method for integrated circuit chip performance testing. Background Technology

[0002] As integrated circuit manufacturing processes advance to the nanoscale, the complexity and integration of chips are increasing exponentially. Before leaving the factory, chips must undergo rigorous automated testing (ATE) to screen out those that meet functional and performance standards. The ATE testing process generates massive amounts of test data, including but not limited to DC parameters (such as power supply current IDD and leakage current IOFF), AC parameters (such as propagation delay Tpd and setup / hold time), and pass / fail results of functional test vectors. This data is the core basis for evaluating chip quality, monitoring manufacturing process stability, conducting failure analysis, and improving yield.

[0003] Traditional data analysis methods have several limitations: Analysis is delayed and reliant on manual intervention: Test data is typically stored in a database and then analyzed offline by test engineers or data analysts using scripts or commercial software. This approach has a long analysis cycle and cannot provide real-time alerts for anomalies during testing, potentially leading to defective chips continuing to be tested or flowing into subsequent stages, resulting in wasted time and resources. Analysis quality heavily depends on the engineer's personal experience; Threshold settings are rigid: Anomaly detection largely relies on fixed upper / lower limits preset in the test program. However, due to factors such as process fluctuations, aging test hardware (e.g., probe cards), and environmental changes, test parameters themselves have a reasonable statistical distribution. Fixed thresholds are either too lenient, leading to missed detections of chips with marginal performance, or too stringent, causing over-detection and reducing overall yield; Analysis dimensions are limited: Traditional methods often analyze single test items or single chips in isolation, lacking correlation analysis across multiple parameters, sites, batches, and time and space dimensions. It is difficult to detect complex defects caused by minor drifts in multiple parameters, or to identify systematic errors introduced by the test hardware itself (such as poor probe contact at a certain station); it lacks intelligent diagnosis and prediction: for complex failure modes, traditional methods struggle to automatically classify and trace their root causes. Furthermore, it lacks predictive capabilities based on historical data, making it impossible to foresee declining yield trends or potential equipment failures; and it fails to establish a closed-loop optimization mechanism: there is a lack of automated and standardized feedback links between data analysis results and test procedure optimization, production equipment maintenance, and upstream process adjustments, preventing the full realization of the value of data analysis in the continuous improvement of the production process.

[0004] Therefore, the industry needs a method for analyzing integrated circuit test data in real time, automatically, multidimensionally, and intelligently to overcome the above-mentioned shortcomings and improve testing efficiency, accuracy, and the overall quality control level of chip manufacturing. Summary of the Invention

[0005] The purpose of this invention is to overcome the shortcomings of existing technologies and provide an automated data analysis method, system, and storage medium for integrated circuit chip performance testing. This method aims to achieve full automation and intelligence throughout the entire process, from data acquisition, preprocessing, anomaly detection, in-depth analysis to visualization report generation and feedback optimization.

[0006] To achieve the above objectives, the present invention adopts the following technical solution: In a first aspect, the present invention provides an automated data analysis method for integrated circuit chip performance testing, comprising the following steps: S1: Data acquisition step: Acquire raw test data streams from automated test equipment (ATE) in real time or near real time, the raw test data streams including multi-batch, multi-site, and multi-pin multi-dimensional test parameters; S2: Data preprocessing step: Perform multidimensional spatiotemporal alignment and standardization cleaning on the original test data stream to construct a test dataset in a unified format; S3: Primary anomaly detection step: Based on the adaptive dynamic threshold algorithm, perform primary anomaly detection on the test dataset and mark potential failure data points; S4: Deep data analysis steps: Build and apply a composite data analysis engine to perform deep analysis on the data that has passed the initial detection. The data analysis engine includes at least a statistical process control module, a machine learning classification module, and a correlation analysis module. S5: Results Generation and Visualization Steps: Based on the in-depth analysis results, combined with chip design specifications and historical yield baselines, generate multi-dimensional, interactive test analysis reports and visualization dashboards; S6: Feedback optimization step: Based on the analysis results of the test analysis report, feedback optimization parameters are sent to the automated test equipment (ATE) or production execution system (MES) to achieve closed-loop control of the test process.

[0007] Preferably, the multidimensional spatiotemporal alignment and normalization cleaning in step S2 specifically includes: timestamp alignment, site and pin mapping, data normalization, and missing value and noise processing. Among them, data normalization uses Z-score normalization or max-min normalization for continuous parameters and one-hot encoding for discrete parameters; missing value and noise processing uses K-nearest neighbor (KNN) based interpolation to fill missing values ​​and applies wavelet transform filters to eliminate high-frequency noise.

[0008] Preferably, the adaptive dynamic threshold algorithm in step S3 includes: a baseline establishment phase, window sliding and dynamic updating, and anomaly scoring. The threshold is dynamically updated using an exponentially weighted moving average (EWMA) model, and the Mahalanobis distance or Z-value of new data points is calculated as the anomaly score, achieving more sensitive and accurate anomaly detection.

[0009] Preferably, the workflow of the composite data analysis engine in step S4 includes: statistical process control module analysis, machine learning classification module analysis, and correlation analysis module analysis. The machine learning classification module uses ensemble learning models such as gradient boosting decision trees (GBDT) or random forests to intelligently classify the chips; the correlation analysis module is used to uncover the implicit relationships between parameters.

[0010] Preferably, the machine learning classification module has online learning capabilities, which can add newly identified defect samples to the training set and periodically trigger incremental learning, thereby continuously adapting to process changes and new defects.

[0011] Preferably, the report generated in step S5 is dynamic and interactive, allowing users to perform multi-dimensional drill-down analysis and quickly locate the root cause of the problem.

[0012] As a preferred option, the feedback optimization in step S6 is not limited to the test program itself, but also includes early warning of the health status of the test hardware and linkage with the upstream production process, realizing a cross-domain quality closed loop from testing to manufacturing.

[0013] Secondly, the present invention provides an automated data analysis system for implementing the above method, comprising: a data acquisition interface module, a data preprocessing engine, an intelligent analysis core module, a report generation and visualization module, and a closed-loop feedback control module.

[0014] Thirdly, the present invention provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the above-described automated data analysis method.

[0015] The beneficial effects of this invention are: 1. Achieved full-process automation and real-time operation: From data collection to report generation, it greatly reduced manual intervention, transformed data analysis from "after the fact" to "during the process" or even "before the fact", and significantly improved the speed of problem response.

[0016] 2. Improved accuracy and sensitivity of anomaly detection: By using an adaptive dynamic threshold algorithm, the drawbacks of fixed thresholds are overcome, enabling more accurate identification of statistically significant anomalies and reducing missed detections and over-detection.

[0017] 3. Enables deep, multi-dimensional correlation analysis: Through a composite analysis engine that integrates SPC, machine learning, and correlation analysis, it can uncover complex patterns, systematic biases, and potential failure mechanisms from massive amounts of data that cannot be found in a single dimension.

[0018] 4. It has intelligent diagnostic and predictive capabilities: The machine learning-based classification model can not only identify known defects, but also discover unknown abnormal patterns; combined with trend analysis, it can perform predictive maintenance on yield fluctuations and equipment failures.

[0019] 5. A data-driven closed-loop optimization has been formed: the analysis results are directly fed back to the testing program and production system, making the testing and production processes an intelligent system that can learn and optimize itself, continuously improving product quality and manufacturing efficiency.

[0020] 6. Provides an excellent visualization and interactive experience: The generated dynamic dashboards and reports enable engineers to intuitively and quickly grasp the overall testing status and conduct in-depth data exploration, greatly improving decision-making efficiency. Attached Figure Description

[0021] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 The flowchart illustrates the overall process of an automated data analysis method for integrated circuit chip performance testing provided in this embodiment of the invention.

[0023] Figure 2 This is a detailed flowchart of the data preprocessing step (S2) in an embodiment of the present invention; Figure 3 This is a schematic diagram illustrating the principle of the adaptive dynamic threshold algorithm (S3) in this embodiment of the invention; Figure 4 This is a diagram illustrating the structure and workflow of the composite data analysis engine (S4) in this embodiment of the invention. Detailed Implementation

[0024] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0025] Example 1: This example describes an automated data analysis method for integrated circuit chip performance testing.

[0026] like Figure 1 As shown, this method mainly includes the following six core steps: S1: Data acquisition steps.

[0027] The goal of this step is to establish stable and efficient data interfaces with various mainstream ATEs (such as Teradyne, Advantest, Cohu, etc.) to achieve real-time or near real-time (e.g., after each wafer or batch is completed) retrieval of test data. The acquired data stream is highly multi-dimensional: Dimension 1: Batch / Wafer / Chip: Identifies the production batch number, wafer number, and chip coordinates (X, Y) on the wafer to which the data belongs.

[0028] Dimension 2: Test Site: For multi-site ATEs in parallel testing, it is necessary to record which physical test site the data comes from.

[0029] Dimension 3: Test Items and Pins: Record the specific test item name (e.g., "VDDQ_IDD_Standby") and the specific pin or port to be measured.

[0030] Dimension 4: Test parameter values: continuous values ​​(e.g., current 2.1mA), discrete values ​​(e.g., functional test pass = 1 / failure = 0), or strings (e.g., "Pass" / "Fail").

[0031] Dimension 5: Timestamp: Test execution time accurate to the millisecond level.

[0032] Metadata: Test program version, hardware configuration version, ambient temperature, etc.

[0033] In implementation, data can be obtained using standard APIs provided by ATE vendors (such as real-time parsing interfaces for STDF files) or by monitoring network data packets. Data is fed into the data processing pipeline of this invention in the form of streaming or small batches of files.

[0034] S2: Data preprocessing steps.

[0035] like Figure 2 As shown, the original data format is mixed, contains noise, and has inconsistent spatiotemporal information. It must be strictly cleaned and standardized, which is the basis for subsequent accurate analysis.

[0036] S21: Timestamp Alignment. Due to slight clock deviations between modules and channels within the ATE, it is necessary to calibrate and synchronize the timestamps of all test items based on the test start trigger signal to ensure that the data of different test items on the same chip are aligned on the timeline.

[0037] S22: Site and Pin Mapping. Based on the hardware description file in the test program, establish a precise mapping table of "physical site - logic channel - chip pin". For example, map channel 15 of physical site 2 to the "A15 address pin" of the chip. This is crucial for subsequent hardware-related fault location.

[0038] S23: Data normalization.

[0039] For continuous parameters (current, voltage, frequency, etc.): Z-score standardization is used. The overall mean μ and standard deviation σ of the parameter in historical batches are calculated, and the new value x is transformed as follows: x'=(x-μ) / σ. The data processed in this way conforms to a standard normal distribution, which facilitates the comparison of parameters with different dimensions and model processing.

[0040] For categorical / discrete parameters (such as BinCode): One-hot encoding is used to convert them into multidimensional binary vectors.

[0041] S24: Missing values ​​and noise handling.

[0042] Missing value handling: For individual data gaps caused by test interruptions or communication packet loss, the K-nearest neighbor (KNN) interpolation method is used. The K most similar samples are found from data within the same batch, adjacent chips, and the same site, and the missing values ​​are filled using a weighted average of the corresponding parameter values ​​of these samples. This method preserves the local structure of the data better than simple mean imputation.

[0043] Noise Removal: Test data may contain high-frequency random noise (such as fluctuations introduced by power supply ripple). Soft thresholding noise reduction is performed using wavelet transform. Wavelet transform can analyze signals simultaneously in the time and frequency domains, effectively separating the true signal components from the noise components, smoothing data curves without losing key features.

[0044] S3: Primary anomaly detection steps.

[0045] like Figure 3 As shown, this step aims to quickly filter out obvious outliers, reducing the burden on subsequent in-depth analysis. The core of this step is an adaptive dynamic thresholding algorithm.

[0046] S31: Baseline Establishment Phase. In the early stages of New Product Introduction (NPI) or during process stabilization, collect a sufficient number of "golden sample" data (e.g., the first 10 batches). For each key test parameter, calculate its initial mean μ0 and standard deviation σ0. The initial upper control limit (UCL0) and lower control limit (LCL0) can be set to μ0 ± 3σ0.

[0047] S32: Sliding Window and Dynamic Updates. Once mass production begins, fixed thresholds are no longer used. We define a sliding window (e.g., data from the most recent 100 chips, or data from the last 2 hours). Within the window, the moving average and moving standard deviation of the parameters are calculated.

[0048] A better approach is to use the Exponentially Weighted Moving Average (EWMA) model. EWMA assigns higher weights to recent data and is more sensitive to small shifts in the process. The formula for calculating the EWMA statistic Z_t is: Where X_t is the observed value at time t, Z_{t-1} is the EWMA value at the previous time, and λ is the smoothing factor (0 < λ ≤ 1). The dynamic threshold is set based on the prediction variance of Z_t.

[0049] S33: Anomaly Scoring. For a newly arrived data point x_new, we calculate its Mahalanobis distance (or standardized Z-value). Mahalanobis distance takes into account the correlation between parameters and is superior to Euclidean distance.

[0050] Here, μ_window and Σ_window are the mean vector and covariance matrix of the data within the current sliding window. The larger D_M is, the more the point deviates from the overall distribution of the current data. We set an alarm threshold (e.g., D_M > 3.5), and if it is exceeded, it is marked as a primary anomaly. At the same time, the D_M value itself can be output as a continuous "anomaly score" for reference by subsequent modules.

[0051] S4: Deep data analysis steps.

[0052] like Figure 4 As shown, the data that passes the initial detection will be fed into a composite data analysis engine for deeper and more multi-dimensional analysis. This engine consists of three core modules working together.

[0053] S41: Statistical Process Control (SPC) module. This is a classic tool for quality control.

[0054] Control charts: Plot X-bar (mean) and R-range (range) control charts for key parameters to monitor in real time whether the production process is under statistical control. Points exceeding the control limits, continuous upward / downward trends, and cyclical patterns on the charts are all special cause variation signals that require attention.

[0055] Process capability index: Calculates Cpk and Ppk indices to quantitatively assess the production process's ability to meet specification limits. A decrease in Cpk / Ppk is an important indicator of increased process drift or variability.

[0056] S42: Machine Learning Classification Module. This is the core of intelligent diagnostics.

[0057] Model selection: Gradient boosting decision tree (GBDT), such as XGBoost or LightGBM, is adopted. GBDT models have advantages such as high prediction accuracy, ability to handle nonlinear relationships, and insensitivity to missing features, making them very suitable for tabular test data.

[0058] Feature engineering: Extracting rich features from preprocessed data to construct feature vectors. For example: Time-domain characteristics: parameter value itself, difference from the previous chip, moving average / standard deviation.

[0059] Frequency domain characteristics: The amplitude of the main frequency components obtained after performing a Fourier transform on the parameter sequence.

[0060] Statistical characteristics: skewness, kurtosis, quantiles, etc.

[0061] Cross-site characteristics: the maximum difference, variance, etc. of the same parameter of the same chip at different sites.

[0062] Model training: The model is trained using a historically accumulated dataset labeled by engineers. Labels include: "Normal", "Defect_A" (e.g., short circuit), "Defect_B" (e.g., open circuit), and "Defect_C" (e.g., performance degradation). K-fold cross-validation is used to optimize the model's hyperparameters.

[0063] Online inference and updates: The trained model is deployed on the analysis pipeline to perform real-time inference on the feature vectors of each chip, outputting the probability of its belonging to each category. More importantly, the system supports online learning. When engineers identify a new batch of defective chips and their categories, these samples are automatically added to the training pool. The system periodically (e.g., weekly) or after a certain number of samples have accumulated, it triggers incremental learning or full retraining of the model, enabling it to continuously adapt to process changes and identify newly emerging defect patterns.

[0064] S43: Correlation Analysis Module. This module aims to discover hidden correlations between test parameters and between test items and final yield.

[0065] Calculate the correlation coefficient matrix: Calculate the Pearson correlation coefficient (measures linear correlation) and Spearman rank correlation coefficient (measures monotonic correlation) between all continuous parameters.

[0066] Visualization and Clustering: The correlation coefficient matrix is ​​presented as a heatmap. Highly correlated parameters are grouped into "parameter clusters" using clustering algorithms (such as hierarchical clustering). For example, it may be found that a set of core power supply current parameters always drift synchronously, which may point to the same power domain or a common process module.

[0067] Identify key driving factors: By ranking the features by regression analysis or decision tree models, identify the few "driving parameters" that have the greatest impact on the final chip performance (such as the highest operating frequency) or yield. This provides a clear direction for targeted process optimization.

[0068] S5: Results generation and visualization steps.

[0069] This step transforms the results of in-depth analysis into intuitive, easy-to-understand, and interactive information products, which are then delivered to test engineers, product engineers, and quality engineers.

[0070] S51: Batch-level yield summary report. Displays the overall yield of the current batch and recent batches, the yield of each sub-bin, and the gap with the target yield in tabular and trend chart formats. Supports detailed comparisons by wafer and by site.

[0071] S52: Defect Spectrum Analysis and Pareto Chart. Statistical analysis is performed on the defective chips classified by the machine learning module in S4, sorting them by defect type and frequency of occurrence to create a Pareto chart. This allows for easy identification of the most prevalent failure modes (e.g., "Defect_A" accounting for 40% of total failures), enabling focused resource allocation for root cause analysis (RCA).

[0072] S53: Parameter Distribution and Trend Charts. For key parameters, a distribution histogram (overlaid with the specification line) and a trend chart showing changes over chip serial number / time are provided. Engineers can visually determine whether the parameter distribution is normal, whether it is close to the specification boundary, and whether there is any drift over time.

[0073] S54: Interactive Visual Dashboard. This is an integrated portal for all information. A typical dashboard might include: Top: Key Performance Indicators (KPIs) cards, such as total yield for the day, real-time test throughput, and number of abnormal alarms.

[0074] Middle section: Configurable chart area where users can freely drag and drop dimensions (batch, site) and metrics (mean, yield, defect count) to generate custom charts.

[0075] Bottom section: Real-time alert list and detailed data table.

[0076] The core interactive feature is "Drill-down." For example, if a user sees a batch with low yield, they can simply click on a data point for that batch to expand and see the yield of each wafer within that batch; clicking on a low-yield wafer will show a distribution map of defective chips on that wafer; and clicking on a specific defective chip will bring up detailed data for all test items for that chip, along with SPC charts and ML classification results. This interaction greatly accelerates the tracing of root causes of problems.

[0077] S6: Feedback optimization steps.

[0078] This step translates the insights gained from data analysis into practical actions, achieving closed-loop control.

[0079] S61: Test Program Optimization Suggestions. When analysis reveals a systemic failure (such as an abnormally high failure rate for a certain test item at a certain site), and hardware issues have been ruled out, the system can automatically generate test program optimization suggestions. For example: "It is recommended to adjust the measurement delay of test item T23 from 10ms to 15ms to avoid misjudgments caused by insufficient signal stabilization time," and push this to the test program development engineer in the form of a work order.

[0080] S62: Test Hardware Health Warning. By monitoring the consistency of data from multiple sites and the slow degradation trend of specific pin parameters over a long period, the system can predict potential failures of the test hardware. For example: "Warning: The internal resistance of the PowerSupply channel at Site4 has increased by 15% in the past week and is expected to exceed the tolerance range in 3 days. Preventive maintenance is recommended." This warning is sent directly to the equipment maintenance team.

[0081] S63: Production process parameter linkage. This is a higher-level closed loop. Through the correlation analysis module, a strong statistical correlation is found between a certain cluster of abnormal test parameters and a certain exposure focal length parameter of the lithography machine. The system can encapsulate this information into a "process anomaly early warning report" and send it to the Manufacturing Execution System (MES) through a standard interface (such as SECS / GEM). Based on this, the MES can automatically trigger inspections or parameter adjustments of the corresponding process equipment, curbing the generation of defects at the source.

[0082] Example 2: This example describes an automated data analysis system for implementing the method in Example 1.

[0083] This system 800 adopts a modular, loosely coupled microservice architecture design, facilitating deployment and expansion. It mainly includes the following modules: 801: Data Acquisition Interface Module. Responsible for interfacing with various ATE systems and databases, supporting multiple protocols and file formats (such as STDF, CSV, XML). Includes a built-in data buffer queue to handle peak data inflows.

[0084] 802: Data Preprocessing Engine. Includes sub-components such as a time aligner, mapping resolver, normalization processor, and noise filter, efficiently executing all cleaning steps in S2 in a pipeline manner.

[0085] 803: Intelligent Analysis Core Module. This is the brain of the system. It includes: 8031: Adaptive threshold detection unit: realizes dynamic threshold calculation and primary alarm of S3.

[0086] 8032: Composite data analysis engine: It encapsulates the SPC computing engine (8032a), machine learning model service (8032b, which includes a model repository and online inference API), and correlation analysis calculator (8032c).

[0087] 804: Report Generation and Visualization Module. This module utilizes web technologies (such as React / Vue + ECharts / D3.js) to build front-end dashboards and back-end reporting services. It provides a RESTful API for third-party systems to access and analyze the results.

[0088] 805: Closed-loop feedback control module. Responsible for distributing structured optimization suggestions and early warning information to different downstream systems (ATE, MES, maintenance work order system, email / instant messaging tools) through a configured workflow engine.

[0089] 806: Unified Data Warehouse and Management Platform. Stores cleaned, standardized data, analysis results, models, and configuration information. Provides user access control, task scheduling, and system monitoring interfaces.

[0090] The modules communicate with each other through message queues (such as Kafka) or service calls to ensure high throughput and low latency data processing capabilities.

[0091] Example 3: This example provides a computer-readable storage medium.

[0092] A computer-readable storage medium, such as a solid-state drive, USB flash drive, optical disc, server cloud storage, etc., stores a computer program (instructions). When the program is loaded and executed by one or more processors (such as the CPU of a server cluster), it enables a computer system to perform all or part of the steps described in Embodiment 1. The program may be provided in the form of a software development kit (SDK), library functions, or a complete application.

[0093] In summary, this invention provides a complete and advanced integrated circuit chip test data analysis solution. It deeply integrates traditional SPC quality control, modern machine learning algorithms, and big data visualization technology, constructing a complete intelligent closed loop from perception, analysis, decision-making to execution. This invention can significantly improve testing efficiency, reduce testing costs, and accelerate the product quality problem investigation and process improvement cycle, and is of great value in promoting the intelligent and digital transformation of the integrated circuit manufacturing industry.

[0094] The preferred embodiments of the present invention disclosed above are merely illustrative of the invention. These preferred embodiments do not exhaustively describe all details, nor do they limit the invention to the specific implementations described. Clearly, many modifications and variations can be made based on the content of this specification. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to better understand and utilize the invention. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. An automated data analysis method for integrated circuit chip performance testing, characterized in that, Includes the following steps: S1: Data acquisition step: Acquire raw test data streams from automated test equipment (ATE) in real time or near real time, the raw test data streams including multi-batch, multi-site, and multi-pin multi-dimensional test parameters; S2: Data preprocessing step: Perform multidimensional spatiotemporal alignment and standardization cleaning on the original test data stream to construct a test dataset in a unified format; S3: Primary anomaly detection step: Based on the adaptive dynamic threshold algorithm, perform primary anomaly detection on the test dataset and mark potential failure data points; S4: Deep data analysis steps: Build and apply a composite data analysis engine to perform deep analysis on the data that has passed the initial detection. The data analysis engine includes at least a statistical process control module, a machine learning classification module, and a correlation analysis module. S5: Results Generation and Visualization Steps: Based on the in-depth analysis results, combined with chip design specifications and historical yield baselines, generate multi-dimensional, interactive test analysis reports and visualization dashboards; S6: Feedback optimization step: Based on the analysis results of the test analysis report, feedback optimization parameters are sent to the automated test equipment (ATE) or production execution system (MES) to achieve closed-loop control of the test process.

2. The automated data analysis method for integrated circuit chip performance testing according to claim 1, characterized in that, The multidimensional spatiotemporal alignment and standardization cleaning in step S2 specifically includes: S21: Timestamp Alignment: Based on the test start trigger signal and the ATE internal clock, unify the time base of all test items and parameters; S22: Site and Pin Mapping: Based on the load board and probe card configuration information of the TestProgram, map the physical test location to the logic test unit; S23: Data normalization: Perform Z-score normalization or maximum-minimum normalization on continuous parameters, and perform one-hot encoding on discrete parameters; S24: Missing values ​​and noise handling: Missing values ​​are filled using K-nearest neighbor (KNN) based interpolation, and wavelet transform filters are applied to eliminate high-frequency noise.

3. The automated data analysis method for integrated circuit chip performance testing according to claim 1, characterized in that, The adaptive dynamic threshold algorithm in step S3 includes: S31: Baseline Establishment Phase: For each test parameter, during the initial stable production phase, historical data is collected, its statistical distribution is calculated, and initial threshold upper and lower limits (UCL / LCL) are established. S32: Window sliding and dynamic update: Set a time sliding window or batch sliding window, calculate the moving mean and moving standard deviation of the parameters in real time within the window, and dynamically update the threshold based on the exponentially weighted moving average (EWMA) model. S33: Anomaly Scoring: For each new data point, calculate its Mahalanobis distance or Z value from the current dynamic threshold and assign it a continuous anomaly score. When the anomaly score exceeds a preset alarm threshold, it is marked as a potential failure point.

4. The automated data analysis method for integrated circuit chip performance testing according to claim 1, characterized in that, The workflow of the composite data analysis engine in step S4 includes: S41: Statistical Process Control Module Analysis: Plot X-bar-R control charts and Cpk / Ppk process capability index charts for key parameters to identify process drift, abrupt changes, and trends; S42: Machine Learning Classification Module Analysis: The test data is classified using a trained ensemble learning model, which includes: normal chips, chips with known defect types, and chips with unknown abnormal patterns; wherein, the ensemble learning model is either Gradient Boosting Decision Tree (GBDT) or Random Forest. S43: Correlation Analysis Module Analysis: Calculate the Pearson correlation coefficient and Spearman rank correlation coefficient between test parameters, and construct a parameter correlation matrix heatmap; identify parameter clusters and key driving parameters.

5. The automated data analysis method for integrated circuit chip performance testing according to claim 4, characterized in that, The training process of the machine learning classification module is as follows: S421: Feature engineering: Extracting time-domain features, frequency-domain features, and statistical features from preprocessed data to form a high-dimensional feature vector; S422: Model Training: Using historical labeled data, including normal samples and various defective samples, the ensemble learning model is trained and cross-validated. S423: Online learning and updates: Newly identified defect samples are added to the training set, and incremental learning of the model is triggered periodically to adapt to process drift and new defect patterns.

6. The automated data analysis method for integrated circuit chip performance testing according to claim 1, characterized in that, The multi-dimensional test analysis report generated in step S5 includes at least the following: S51: Batch-level yield summary report: Displays the pass rate, yield trend and box plot comparison of different batches, wafers and sites; S52: Defect spectrum analysis and Pareto chart: Statistical analysis of failure test items and failure modes of failed chips, generating Pareto charts to identify the main causes of failure; S53: Parameter Distribution and Trend Chart: Displays the distribution histogram of key parameters and the trend line of changes over time / batch; S54: Interactive Visual Dashboard: Provides dashboards that support users to perform drill-down and roll-up analysis by batch, site, and time range.

7. The automated data analysis method for integrated circuit chip performance testing according to claim 1, characterized in that, The feedback optimization in step S6 includes: S61: Test procedure optimization recommendations: For systematic failure modes, it is recommended to adjust the test conditions, limit values ​​or test order of specific test items; S62: Test Hardware Health Warning: Based on multi-site data consistency analysis and pin performance degradation trends, it warns of probe card contamination and load board channel attenuation issues; S63: Production process parameter linkage: Associate the abnormal parameter clusters analyzed from the test data with the parameters of the front-end manufacturing equipment (such as photolithography and etching) to provide the MES system with process optimization directions.

8. An automated data analysis system for integrated circuit chip performance testing, characterized in that, An automated data analysis method for implementing the integrated circuit chip performance testing method according to any one of claims 1-7, the system comprising: The data acquisition interface module is configured to acquire raw test data streams from automated test equipment (ATE) in real time or near real time. The data preprocessing engine is configured to perform multidimensional spatiotemporal alignment and standardization cleaning on the raw test data stream, and build a test dataset in a unified format. The intelligent analysis core module includes an adaptive threshold detection unit and a composite data analysis engine, configured to perform primary anomaly detection and deep data analysis; The report generation and visualization module is configured to generate multi-dimensional, interactive test analysis reports and visualization dashboards. The closed-loop feedback control module is configured to feed back optimization parameters to the ATE or MES system based on the analysis results.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the program is executed by the processor, it implements an automated data analysis method for integrated circuit chip performance testing as described in any one of claims 1-7.

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