Wiring congestion prediction method, device, equipment and storage medium
By acquiring the chip's layout data, the rectangular uniform line density of the grid cells and the total pin wiring length are calculated, solving the problem of low prediction accuracy in traditional methods and achieving fast and accurate wiring congestion prediction and optimization.
Patent Information
- Application Number
- CN202610241700.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-02-28
- Publication Date
- 2026-07-03
Smart Images
Figure CN122334140A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of chip design technology, and in particular to a wiring congestion prediction method, apparatus, device and storage medium. Background Technology
[0002] Chip congestion prediction is a critical task in the chip design process, used to estimate potential congestion problems during the physical design phase and then take optimization measures. Congestion refers to the excessive crowding of certain areas or signal paths during chip placement and routing due to resource constraints or unreasonable layout. This phenomenon negatively impacts chip performance, power consumption, or area. In FPGA or ASIC design, congestion is mainly manifested as a shortage of routing resources. Although logic resources may still be sufficient, the depletion of routing resources will limit chip performance or hinder the successful implementation of the design.
[0003] Traditional FPGA congestion prediction primarily relies on congestion analysis functions within placement and routing tools. After placement and routing, designers estimate potential congestion issues by analyzing resource utilization, signal path length, and timing constraints, and then propose optimization suggestions. However, traditional methods typically depend on rule-based or experience-based analysis, resulting in long processing times and difficulty in guaranteeing prediction accuracy. This is especially true as design scale increases and congestion issues become more complex, making it challenging for traditional methods to predict congestion quickly and accurately.
[0004] Therefore, how to accurately predict chip wiring congestion is an urgent problem to be solved. Summary of the Invention
[0005] The main objective of this application is to provide a wiring congestion prediction method, apparatus, device, and storage medium, which aims to improve the accuracy of chip wiring congestion prediction.
[0006] In a first aspect, this application provides a cabling congestion prediction method, which includes the following steps: Obtain the basic layout data of the chip, which includes pin information, pin network information and routing resource information; Based on the pin information and the pin network information, determine the rectangular uniform line density of each grid cell wiring of the chip and the total pin wiring length; Based on the rectangular uniform line density of each grid cell, the total pin wiring length, and the wiring resource information, the wiring congestion information of the chip is determined, including the congestion level of each grid cell.
[0007] Secondly, this application also provides a cabling congestion prediction device, which includes an acquisition module and a determination module, wherein: The acquisition module is used to acquire the basic layout data of the chip, which includes pin information, pin network information and routing resource information. The determining module is used to determine the rectangular uniform line density of each grid cell wiring and the total wiring length of the pins of the chip based on the pin information and the pin network information. The determining module is further configured to determine the wiring congestion information of the chip based on the rectangular uniform line density of the wiring of each of the grid cells, the total wiring length of the pins, and the wiring resource information. The wiring congestion information includes the congestion level of each grid cell.
[0008] Thirdly, this application also provides a computer device, the computer device including a processor, a memory, and a computer program stored in the memory and executable by the processor, wherein when the computer program is executed by the processor, it implements the steps of the wiring congestion prediction method as described above.
[0009] Fourthly, this application also provides a computer-readable storage medium storing a computer program, wherein when the computer program is executed by a processor, it implements the steps of the wiring congestion prediction method described above.
[0010] This application provides a wiring congestion prediction method, apparatus, device, and storage medium. This application acquires basic layout data of a chip, including pin information, pin network information, and wiring resource information. Based on the pin information and pin network information, it determines the rectangular uniform line density and total pin wiring length for each grid cell of the chip. Based on the rectangular uniform line density, total pin wiring length, and wiring resource information of each grid cell, it determines the wiring congestion information of the chip, which includes the congestion level of each grid cell. This application calculates the rectangular uniform line density and total pin wiring length of each grid cell using pin information and pin network information, and then accurately determines the wiring congestion information of the chip using the rectangular uniform line density, total pin wiring length, and wiring resource information, greatly improving the accuracy of wiring congestion prediction. Attached Figure Description
[0011] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0012] Figure 1A flowchart illustrating a cabling congestion prediction method provided in an embodiment of this application; Figure 2 A flowchart illustrating a sub-step of the cabling congestion prediction method provided in this application embodiment; Figure 3 This application provides a flowchart illustrating another sub-step of the cabling congestion prediction method in an embodiment of the present application. Figure 4 This application provides a flowchart illustrating another sub-step of the cabling congestion prediction method in an embodiment of the present application. Figure 5 This application provides a flowchart illustrating another sub-step of the cabling congestion prediction method in an embodiment of the present application. Figure 6 A schematic block diagram of a cabling congestion prediction device provided in an embodiment of this application; Figure 7 This is a schematic block diagram of the structure of a computer device provided in an embodiment of this application.
[0013] The realization of the purpose, functional features and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation
[0014] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0015] The flowchart shown in the attached diagram is for illustrative purposes only and does not necessarily include all content and operations / steps, nor does it necessarily have to be performed in the order described. For example, some operations / steps can be broken down, combined, or partially merged, so the actual execution order may change depending on the actual situation.
[0016] Chip congestion prediction is a critical task in the chip design process, used to estimate potential congestion problems during the physical design phase and then take optimization measures. Congestion refers to the excessive crowding of certain areas or signal paths during chip placement and routing due to resource constraints or unreasonable layout. This phenomenon negatively impacts chip performance, power consumption, or area. In FPGA or ASIC design, congestion is mainly manifested as a shortage of routing resources. Although logic resources may still be sufficient, the depletion of routing resources will limit chip performance or hinder the successful implementation of the design.
[0017] Traditional FPGA congestion prediction primarily relies on congestion analysis functions within placement and routing tools. After placement and routing, designers estimate potential congestion issues by analyzing resource utilization, signal path length, and timing constraints, and then propose optimization suggestions. However, traditional methods typically depend on rule-based or experience-based analysis, resulting in long processing times and difficulty in guaranteeing prediction accuracy. This is especially true as design scale increases and congestion issues become more complex, making it challenging for traditional methods to predict congestion quickly and accurately.
[0018] To address the aforementioned problems, embodiments of this application provide a wiring congestion prediction method, apparatus, device, and storage medium. The wiring congestion prediction method includes acquiring basic layout data of a chip, including pin information, pin network information, and wiring resource information; determining the rectangular uniform line density and total pin wiring length for each grid cell of the chip based on the pin information and pin network information; and determining wiring congestion information of the chip based on the rectangular uniform line density, total pin wiring length, and wiring resource information, wherein the wiring congestion information includes the congestion level of each grid cell.
[0019] The cabling congestion prediction method can be applied to computer devices, such as mobile phones, tablets, laptops, desktop computers, and personal digital assistants.
[0020] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.
[0021] Please refer to Figure 1 , Figure 1 This is a flowchart illustrating a cabling congestion prediction method provided in an embodiment of this application.
[0022] like Figure 1 As shown, the cabling congestion prediction method includes steps S101 to S103.
[0023] Step S101: Obtain the basic layout data of the chip, which includes pin information, pin network information and routing resource information.
[0024] The layout foundation data consists of chip design data generated from the chip design. This foundation data includes pin information, pin network information, and routing resource information. The pin information includes the pin coordinates of each pin. The pin network information includes the name of each pin network and an index table of each pin network and each pin. The pin network is a pin network composed of pins based on the chip's functional settings, and includes multiple pins, with each pin mapped one-to-one to a pin network. The routing resource information refers to the available resources for chip routing, including but not limited to global routing resources, long line resources, short line resources, and distributed routing resources.
[0025] In some embodiments, the basic layout data after the chip design layout is obtained can be the basic layout data generated when the chip layout is just completed, or the basic layout data after the chip layout pins are adjusted.
[0026] Step S102: Based on the pin information and the pin network information, determine the rectangular uniform line density of each grid cell wiring of the chip and the total pin wiring length.
[0027] In some embodiments, such as Figure 2 As shown, step S102 includes sub-steps S1021 to S1023.
[0028] Sub-step S1021: Divide the chip into multiple grid units with a preset granularity.
[0029] The preset granularity is the size of the chip area to be divided. The preset granularity can be set according to the actual situation. This application embodiment does not make a specific limitation on this. For example, the preset granularity can be set to an 8*8 granularity, that is, the chip is divided into 64 grid units.
[0030] In some embodiments, a preset granularity is obtained, and the chip is divided into multiple grid cells using the preset granularity. By dividing the chip into multiple grid cells, the accuracy of wiring congestion prediction can be effectively improved.
[0031] Sub-step S1022: Calculate the wiring density of each grid cell based on the pin information and the pin network information to obtain the rectangular uniform line density of the wiring in each grid cell.
[0032] The pin information includes the pin coordinates of each pin, and the pin network information includes the name of each pin network and an index table between each pin network and each pin.
[0033] In some embodiments, such as Figure 3 As shown, sub-step S1022 includes steps S1022a to S1022c.
[0034] Step S1022a: Obtain the pin offset coefficient and the standard deviation of the pin offset.
[0035] The pin offset coefficient is a parameter used to calculate the pin offset. The pin offset coefficient can be set according to the actual situation. This application embodiment does not make specific limitations on this. For example, the pin offset coefficient can be set to 1.6. The pin offset standard deviation is the standard deviation of the pin position offset. The pin offset standard deviation is generated based on the offset of each pin.
[0036] In some embodiments, the standard deviation of the first pin offset of a chip of the same type is obtained, and the standard deviation of the first pin offset of the chip is used as the standard deviation of the pin offset of the chip. By obtaining the standard deviation of the first pin offset of a chip of the same type, the standard deviation of the pin offset of the chip can be obtained efficiently, which greatly improves the efficiency of chip wiring congestion prediction.
[0037] Step S1022b: Determine the boundary coordinates of each pin network based on the pin offset coefficient, the pin offset standard deviation, the index table, and the pin coordinates of each pin.
[0038] The boundary coordinates include the boundary coordinates of the lowest point and the highest point of the pin network.
[0039] Based on the index table and the pin coordinates of each pin, determine the candidate boundary coordinates of each pin network; adjust the candidate boundary coordinates of the pin network according to the pin offset coefficient and the standard deviation of the pin offset to obtain the boundary coordinates of the pin network.
[0040] In some embodiments, the method for determining the candidate boundary coordinates of each pin network based on the index table and the pin coordinates of each pin can be as follows: select each target pin belonging to the pin network from multiple pins according to the index table, obtain the pin coordinates of each target pin, and form the candidate boundary coordinates of the pin network based on the pin coordinates of each target pin.
[0041] In some embodiments, the boundary coordinates of the pin network are obtained by adjusting the candidate boundary coordinates of the pin network according to the pin offset coefficient and the pin offset standard deviation. The method is as follows: select the lowest point boundary coordinates and the highest point boundary coordinates of the pin network from the candidate boundary coordinates to obtain the first candidate boundary coordinates and the second candidate boundary coordinates; multiply the pin offset coefficient and the pin offset standard deviation to obtain the pin target offset; subtract the pin target offset from the first candidate boundary coordinates to obtain the first boundary coordinates; and add the pin target offset to the second candidate boundary coordinates to obtain the second boundary coordinates.
[0042] For example, the lowest and highest point boundary coordinates of the pin network are selected from the candidate boundary coordinates to obtain the first candidate boundary coordinates. The coordinates of the second candidate boundary are The pin offset coefficient is The standard deviation of the pin offset is Offset coefficient of this pin and pin offset standard deviation Perform a multiplication operation to obtain the pin target offset. The first candidate boundary coordinates Subtract the target offset of the pin Obtain the coordinates of the first boundary. The second candidate boundary coordinates Add the target offset of this pin The coordinates of the second boundary are obtained. .
[0043] Step S1022c: Determine the rectangular uniform line density of the wiring for each of the pin networks based on the boundary coordinates of each pin network.
[0044] In some embodiments, the wiring density of each pin network is calculated based on the boundary coordinates to obtain the sub-rectangular uniform line density of each pin network; the sub-rectangular uniform line densities of each pin network contained in each grid cell are weighted and summed to obtain the rectangular uniform line density of wiring in each grid cell.
[0045] In some embodiments, the width and height of the boundary of each pin network are calculated based on the boundary coordinates of each pin network; a preset uniform line density formula is obtained, and the width and height of the boundary of each pin network are calculated to obtain the sub-rectangular uniform line density of the wiring of each pin network; the sub-rectangular uniform line densities of the wiring of each pin network in each grid cell are weighted and summed to obtain the rectangular uniform line density of the wiring of each grid cell.
[0046] In some embodiments, the width and height of the boundary of each pin network can be calculated based on the boundary coordinates of each pin network by subtracting the ordinate of the first boundary coordinate from the ordinate of the second boundary coordinate to obtain the height of the boundary; and by subtracting the abscissa of the first boundary coordinate from the abscissa of the second boundary coordinate to obtain the width of the boundary.
[0047] In some embodiments, obtaining a preset uniform line density formula and calculating the width and height of the boundary of each pin network to obtain the sub-rectangular uniform line density of each pin network wiring can be achieved by: obtaining a preset uniform line density formula, wherein the preset uniform line density formula is as follows: ,Should For the uniform line density of the subrectangle of the pin network routing, For the width of the pin network boundary, this The height of the pin network boundary is given; based on the preset uniform line density formula, the width and height of the boundary of each pin network are calculated to obtain the uniform line density of the sub-rectangle of each pin network wiring.
[0048] In some embodiments, the method of merging the sub-rectangular uniform line densities of the pin network wiring in each grid cell to obtain the rectangular uniform line density of the wiring in each grid cell can be as follows: determine the proportion of each pin network in its respective grid cell, and use the proportion of each pin network in its respective grid cell as a weighting coefficient; multiply the sub-rectangular uniform line density of the pin network wiring in each grid cell by various corresponding weighting coefficients and sum them to obtain the rectangular uniform line density of the wiring in each grid cell.
[0049] Sub-step S1023: Calculate the wiring length of all pins in each grid cell based on the pin information and the pin network information to obtain the total wiring length of the pins in each grid cell.
[0050] In some embodiments, such as Figure 4 As shown, sub-step S1023 includes steps S1023a to S1023b.
[0051] Step S1023a: Determine the wiring length of all pins in each pin network according to the pin coordinates of each pin and the index table.
[0052] The number of pins in each pin network is determined. If the number of pins in a pin network is less than or equal to a preset number of pins, the routing length is predicted by the pin coordinates of each pin in the pin network using a preset minimum right-angle Steiner tree algorithm, resulting in the routing length of all pins in the pin network. If the number of pins in a pin network is greater than the preset number of pins, the pins in the pin network are clustered to obtain multiple pin clusters. The routing length is then predicted by the preset minimum right-angle Steiner tree algorithm for these multiple pin clusters, resulting in the routing length of all pins in the pin network. The preset number of pins can be set according to actual conditions, and this embodiment does not impose a specific limitation on it. For example, the preset number of pins can be set to 20.
[0053] In some embodiments, if the number of pins in the pin network is less than or equal to a preset number of pins, the routing length is predicted by using a preset Rectilinear Steiner Minimum Tree (RSMT) algorithm on the pin coordinates of each pin in the pin network. The method for obtaining the routing length of all pins in the pin network can be as follows: If the number of pins in the pin network is less than or equal to the preset number of pins, obtain the preset RSMT algorithm. ,Should For the wiring length of all pins of the pin network, this The pin coordinates of all pins in the pin network are included. Based on the preset minimum right-angle Steiner tree algorithm, the wiring length of all pins in the pin network is obtained.
[0054] In some embodiments, if the number of pins in the pin network is greater than the preset number of pins, the way to cluster each pin in the pin network to obtain multiple pin clusters is as follows: if the number of pins in the pin network is greater than the preset number of pins, the pins in the pin network are clustered into similar pins, so that the number of pins in each cluster is less than the preset number of pins, thus obtaining multiple pin clusters.
[0055] In some embodiments, the wiring length prediction of the multiple pin clusters of the pin network using a preset minimum Cartesian Steiner tree algorithm to obtain the wiring length of all pins in the pin network can be achieved as follows: determine the cluster center coordinates of each pin cluster, and predict the wiring length of each pin cluster using the preset minimum Cartesian Steiner tree algorithm to obtain a first wiring length; predict the wiring length of each pin in each pin cluster using the preset minimum Cartesian Steiner tree algorithm to obtain a second wiring length of each pin cluster; sum the first wiring length and the second wiring length of each pin cluster to obtain the wiring length of all pins in the pin network. By predicting the wiring length of multiple pin clusters separately, the problem of low accuracy in wiring length prediction caused by a large number of pins in the pin network can be effectively solved.
[0056] Step S1023b: The wiring lengths of each pin network contained in each grid cell are weighted and summed to obtain the total wiring length of each grid cell.
[0057] In some embodiments, it is determined whether a clock pin network exists in a grid cell, and a preset line length adjustment parameter is obtained for each grid cell. If no clock pin network exists in the grid cell, the wiring lengths of each pin network in the grid cell are weighted and summed using the preset line length adjustment parameter to obtain the total pin wiring length of the grid cell. If a clock pin network exists in the grid cell, the wiring length of the clock pin network is multiplied by a preset coefficient to obtain the target wiring length. The wiring lengths of non-clock pin networks and the target wiring length of the clock pin network in the grid cell are weighted and summed using the preset line length adjustment parameter to obtain the total pin wiring length of the grid cell. By weighted summing the wiring lengths of each pin network contained in each grid cell, the total pin wiring length of each grid cell can be accurately obtained.
[0058] In some embodiments, the method for determining whether a clock pin network exists in a grid cell can be: determining whether each pin network in the grid cell carries a clock pin label; if the pin network carries a clock pin label, determining that the pin network is a clock pin network; if the pin network does not carry a clock pin label, determining that the pin network is not a clock pin network.
[0059] In some embodiments, the preset line length adjustment parameter for each grid cell can be obtained by: obtaining the average pin spacing of the grid cell to obtain the average pin spacing; obtaining the standard deviation of the pin offset of each pin in the grid cell; and obtaining the preset line length adjustment parameter calculation formula, which is as follows: ,Should This is a parameter for adjusting the line length. For the preset sensitivity coefficient, this The standard deviation of pin offset in the grid cell. The average pin spacing is used as the reference value. Based on the preset line length adjustment parameter calculation formula, the average pin spacing, the standard deviation of pin offset, and the preset sensitivity coefficient are calculated to obtain the preset line length adjustment parameter of the grid cell. The preset sensitivity coefficient can be set according to actual conditions, and this embodiment does not impose specific limitations on it. For example, the preset sensitivity coefficient can be set to a coefficient between 0.3 and 0.5.
[0060] In some embodiments, if there is no clock pin network in the grid cell, the total pin wiring length of the grid cell can be obtained by weighted summing of the wiring lengths of each pin network in the grid cell using a preset line length adjustment parameter. If there is no clock pin network in the grid cell, the preset line length adjustment parameter is multiplied by the wiring length of each pin network in the grid cell to obtain the target wiring length of each pin network. The target wiring lengths of each pin network are then added together to obtain the total pin wiring length of the grid cell.
[0061] In some embodiments, if a clock pin network exists in the grid cell, the target wiring length can be obtained by multiplying the wiring length of the clock pin network by a preset coefficient.
[0062] In some embodiments, the total pin wiring length of the grid cell can be obtained by weighted summing the wiring lengths of the non-clock pin networks and the target wiring lengths of the clock pin networks using preset line length adjustment parameters. This can be achieved by multiplying the preset line length adjustment parameters by the wiring lengths of the non-clock pin networks in the grid cell and by multiplying the preset line length adjustment parameters by the target wiring lengths of the clock pin networks in the grid cell to obtain the target wiring lengths of each pin network, and then adding the target wiring lengths of each pin network to obtain the total pin wiring length of the grid cell.
[0063] Step S103: Determine the wiring congestion information of the chip based on the rectangular uniform line density of each grid cell wiring, the total pin wiring length, and the wiring resource information. The wiring congestion information includes the congestion level of each grid cell.
[0064] The cabling congestion information includes the congestion level of each grid cell, which includes no congestion, low congestion, medium congestion, and severe congestion.
[0065] In some embodiments, such as Figure 5 As shown, step S103 includes sub-steps S1031 to S1033.
[0066] Sub-step S1031: Determine the wiring resource utilization rate index of each grid cell based on the total pin wiring length of each grid cell and the wiring resource information.
[0067] The cabling resource information includes the sub-caching resource information for each grid cell.
[0068] Obtain the grid percentage of each grid cell relative to all grid cells in the chip. Multiply the total pin wiring length of each grid cell with its corresponding grid percentage to obtain the total pin wiring length percentage of each grid cell. Divide the total pin wiring length percentage of each grid cell by the corresponding sub-wiring resource information to obtain the wiring resource utilization index of each grid cell.
[0069] Sub-step S1032: Normalize the rectangular uniform line density of the wiring of each grid cell to obtain the target spatial distribution density of the wiring of each grid cell.
[0070] Multiply the rectangular uniform line density of each grid cell wiring by a preset static threshold to obtain the rectangular uniform line density threshold of each grid cell wiring. Then, calculate the average of the rectangular uniform line density thresholds of each grid cell wiring to obtain the target rectangular uniform line density threshold. Divide the rectangular uniform line density of each grid cell wiring by the target rectangular uniform line density threshold to obtain the target spatial distribution density of each grid cell wiring.
[0071] Sub-step S1033: Determine the congestion level of each grid cell based on the target spatial distribution density and cabling resource utilization index of each grid cell.
[0072] In some embodiments, the congestion index coefficient of each grid cell is obtained, which is determined based on the standard deviation of pin offset in the grid cell; the target spatial distribution density and cabling resource utilization index of each grid cell are weighted according to the congestion index coefficient of each grid cell to obtain the congestion index of each grid cell; the congestion index of each grid cell is mapped to the congestion level through a preset mapping table to obtain the congestion level of each grid cell.
[0073] In some embodiments, the congestion index coefficient of each grid cell can be obtained by: obtaining the standard deviation of the pin offset of the grid cell, and obtaining a preset congestion index coefficient formula, wherein the preset congestion index coefficient formula is as follows: ,Should This represents the congestion index coefficient for the grid cell. The standard deviation of the pin offset for this grid cell. As the first coefficient, this The second coefficient is used; based on the preset congestion index coefficient formula, the standard deviation of the pin offset of the grid cell, the first coefficient, and the second coefficient are calculated to obtain the congestion index coefficient of the grid cell. Similarly, the aforementioned steps are performed to calculate the congestion index coefficient of each grid cell. The first and second coefficients can be set according to actual conditions, and this embodiment does not impose specific limitations on them. For example, the first coefficient can be set to 0.5, and the second coefficient can be set to 0.1.
[0074] In some embodiments, the congestion index of each grid cell is obtained by weighting its target spatial distribution density and cabling resource utilization index according to the congestion index coefficient of each grid cell. This can be achieved by obtaining a preset congestion index formula, which is: ,Should As a congestion metric for grid cells, this This is a congestion index coefficient. This is a metric for the utilization of wiring resources in a grid cell. The target spatial distribution density of the grid cell is defined. Based on the preset congestion index formula, the congestion index coefficient, its own target spatial distribution density, and cabling resource utilization index of each grid cell are weighted and calculated to obtain the congestion index of each grid cell.
[0075] In some embodiments, the standard deviation of pin offset and the average pin spacing of each grid cell are obtained; the fluctuation coefficient of the chip is calculated based on the standard deviation of pin offset and the average pin spacing of each grid cell; and a mapping table between congestion indicators and congestion levels is constructed based on the fluctuation coefficient.
[0076] It should be noted that the pin offset standard deviation of this grid cell is the offset standard deviation generated by the offset values of all pins in the grid cell, and the average pin spacing is the average pin spacing of all pins in the grid cell.
[0077] In some embodiments, the fluctuation coefficient of the chip can be calculated based on the standard deviation of pin offset and the average pin spacing of each grid cell as follows: The standard deviation of pin offset for each grid cell is accumulated to obtain the total pin offset standard deviation; the average pin spacing for each grid cell is accumulated to obtain the total average pin spacing; the total pin offset standard deviation is divided by the total average pin spacing to obtain the fluctuation coefficient of the chip. This fluctuation coefficient is between 0 and 1, approaching 0 when pin changes are gradual and approaching 1 when pin changes are drastic.
[0078] In some embodiments, the method for constructing a mapping table between congestion indices and congestion levels based on the volatility coefficient can be as follows: obtaining a first threshold, a second threshold, and a third threshold, and obtaining a volatility coefficient weighting coefficient; multiplying the volatility coefficient weighting coefficient by the volatility coefficient to obtain a congestion threshold adjustment value; subtracting the congestion threshold adjustment value from the first threshold to obtain a target first threshold; subtracting the congestion threshold adjustment value from the second threshold to obtain a target second threshold; if the congestion index is less than or equal to the third threshold, it is determined to be no congestion; if the congestion index is greater than the third threshold and less than or equal to the target second threshold, it is determined to be low-level congestion; if the congestion index is at least greater than the target second threshold and less than or equal to the target first threshold, it is determined to be medium-level congestion; if the congestion index is greater than the target first threshold, it is determined to be severe congestion. The first threshold, second threshold, third threshold, and volatility coefficient weighting coefficient can be set according to actual conditions, and this embodiment does not specifically limit them. For example, the first threshold can be set to 0.9, the second threshold can be set to 0.8, the third threshold can be set to 0.7, and the volatility coefficient weighting coefficient can be set to 0.1.
[0079] For example, the first threshold is 0.9, the second threshold is 0.8, the third threshold is 0.7, the volatility coefficient weighting coefficient is 0.1, and the volatility coefficient is 0.5. A multiplication operation is performed on the volatility coefficient weighting coefficient of 0.1 and the volatility coefficient of 0.5 to obtain a congestion threshold adjustment value of 0.05. The first threshold of 0.9 is subtracted from this congestion threshold adjustment value of 0.05 to obtain a target first threshold of 0.895. The second threshold of 0.8 is subtracted from this congestion threshold adjustment value of 0.05 to obtain a target second threshold of 0.795. A congestion index less than or equal to 0.7 indicates no congestion; a congestion index between 0.7 and 0.795 indicates low congestion; a congestion index between 0.795 and 0.895 indicates moderate congestion; and a congestion index greater than 0.895 indicates severe congestion.
[0080] In some embodiments, the congestion index of each grid cell is retrieved from a preset mapping table to obtain the corresponding congestion level of each grid cell. Using this preset mapping table and the congestion index of each grid cell, the congestion level of each grid cell can be accurately obtained.
[0081] In some embodiments, after obtaining the congestion level of each grid cell, grid cells with no congestion are marked as white, grid cells with low congestion are marked as yellow, grid cells with medium congestion are marked as orange, and grid cells with severe congestion are marked as red, so as to intuitively know the congestion status of each region of the chip, thereby facilitating chip design.
[0082] The routing congestion prediction method provided in the above embodiments acquires basic layout data of the chip, including pin information, pin network information, and routing resource information; and determines the rectangular uniform line density and total pin routing length of each grid cell based on the pin information and pin network information; and determines the routing congestion information of the chip based on the rectangular uniform line density, total pin routing length, and routing resource information of each grid cell, including the congestion level of each grid cell. In this application, the rectangular uniform line density and total pin routing length of each grid cell are calculated using pin information and pin network information, and then the routing congestion information of the chip can be accurately determined using the rectangular uniform line density, total pin routing length, and routing resource information, greatly improving the accuracy of routing congestion prediction.
[0083] Please see Figure 6 , Figure 6 This is a schematic block diagram of a cabling congestion prediction device provided in an embodiment of this application.
[0084] like Figure 6 As shown, the cabling congestion prediction device 200 includes an acquisition module 210 and a determination module 220, wherein: The acquisition module 210 is used to acquire the basic layout data of the chip, which includes pin information, pin network information and routing resource information. The determining module 220 is used to determine the rectangular uniform line density of each grid cell wiring of the chip and the total wiring length of the pins based on the pin information and the pin network information. The determining module is further configured to determine the wiring congestion information of the chip based on the rectangular uniform line density of the wiring of each of the grid cells, the total wiring length of the pins, and the wiring resource information. The wiring congestion information includes the congestion level of each grid cell.
[0085] In some embodiments, the determining module 220 is further configured to: The chip is divided into multiple grid units by a preset granularity; The wiring density of each grid cell is calculated based on the pin information and the pin network information to obtain the rectangular uniform line density of the wiring in each grid cell; The wiring length of all pins in each grid cell is calculated based on the pin information and the pin network information to obtain the total wiring length of the pins in each grid cell.
[0086] In some embodiments, the determining module 220 is further configured to: Obtain the pin offset coefficient and the standard deviation of the pin offset; The boundary coordinates of each pin network are determined based on the pin offset coefficient, the pin offset standard deviation, the index table, and the pin coordinates of each pin. The rectangular uniform line density of the wiring for each of the pin networks is determined based on the boundary coordinates of each pin network.
[0087] In some embodiments, the determining module 220 is further configured to: The wiring density of each pin network is calculated based on the boundary coordinates to obtain the sub-rectangular uniform line density of each pin network; The rectangular uniform line density of the wiring in each grid cell is obtained by weighted summation of the sub-rectangular uniform line densities of each pin network contained in each grid cell.
[0088] In some embodiments, the determining module 220 is further configured to: Based on the pin coordinates of each pin and the index table, determine the wiring lengths of all pins in each pin network; The total pin wiring length of each grid cell is obtained by weighted summing of the wiring lengths of each pin network contained in each grid cell.
[0089] In some embodiments, the determining module 220 is further configured to: Determine the number of pins for each of the pin networks; If the number of pins in the pin network is less than or equal to the preset number of pins, the pin coordinates of each pin in the pin network are predicted using the preset minimum right-angle Steiner tree algorithm to obtain the wiring length of all pins in the pin network. If the number of pins in the pin network is greater than the preset number of pins, then the pins in the pin network are clustered to obtain multiple pin clusters; The wiring lengths of all pins in the pin network are predicted by using a preset minimum right-angle Steiner tree algorithm.
[0090] In some embodiments, the determining module 220 is further configured to: The cluster center coordinates of each pin cluster are determined, and the wiring length is predicted by the cluster center coordinates of each pin cluster using a preset minimum right-angle Steiner tree algorithm to obtain the first wiring length. The pin coordinates of each pin in each pin cluster are predicted using a preset minimum right-angle Steiner tree algorithm to obtain the second wiring length of each pin cluster. The wiring lengths of all pins in the pin network are obtained by summing the first wiring length and the second wiring length of each pin cluster.
[0091] In some embodiments, the determining module 220 is further configured to: Determine whether a clock pin network exists in the grid cell, and obtain the preset line length adjustment parameters for each grid cell; If there is no clock pin network in the grid cell, the wiring length of each pin network in the grid cell is weighted and summed by a preset line length adjustment parameter to obtain the total wiring length of the pins in the grid cell. If a clock pin network exists in the grid cell, the wiring length of the clock pin network is multiplied by a preset coefficient to obtain the target wiring length. The total pin wiring length of the grid cell is obtained by weighted summing the wiring length of the non-clock pin network and the target wiring length of the clock pin network using preset line length adjustment parameters.
[0092] In some embodiments, the determining module 220 is further configured to: Based on the total pin wiring length of each grid cell and the wiring resource information, determine the wiring resource utilization index of each grid cell; The rectangular uniform line density of the wiring in each grid cell is normalized to obtain the target spatial distribution density of the wiring in each grid cell. The congestion level of each grid cell is determined based on the target spatial distribution density and cabling resource utilization index of each grid cell.
[0093] In some embodiments, the determining module 220 is further configured to: Obtain the congestion index coefficient for each of the grid cells, the congestion index coefficient being determined based on the standard deviation of pin offsets within the grid cell; The congestion index of each grid cell is obtained by weighting its target spatial distribution density and cabling resource utilization index according to the congestion index coefficient of each grid cell. By mapping the congestion index of each grid cell to a congestion level using a preset mapping table, the congestion level of each grid cell is obtained.
[0094] It should be noted that those skilled in the art will understand that, for the sake of convenience and brevity, the specific working process of the above-mentioned cabling congestion prediction device can be referred to the corresponding process in the aforementioned cabling congestion prediction method embodiment, and will not be repeated here.
[0095] Please see Figure 7 , Figure 7 This is a schematic block diagram of the structure of a computer device provided in an embodiment of this application.
[0096] like Figure 7 As shown, the computer device 300 includes a processor 302 and a memory 303 connected via a system bus 301, wherein the memory 303 may include a storage medium and internal memory.
[0097] The storage medium may store the operating system and computer programs. The computer programs include program instructions that, when executed, cause the processor to perform any wiring congestion prediction method.
[0098] The processor 303 provides computing and control capabilities to support the operation of the entire computer device.
[0099] Internal memory provides an environment for the execution of computer programs stored in the storage medium. When these computer programs are executed by the processor, the processor can perform any wiring congestion prediction method.
[0100] Those skilled in the art will understand that Figure 7The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.
[0101] It should be understood that processor 303 can be a Central Processing Unit (CPU), but it can also be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. Among these, a general-purpose processor can be a microprocessor or any conventional processor.
[0102] In one embodiment, the processor is configured to run a computer program stored in memory to perform the following steps: Obtain the basic layout data of the chip, which includes pin information, pin network information and routing resource information; Based on the pin information and the pin network information, determine the rectangular uniform line density of each grid cell wiring of the chip and the total pin wiring length; Based on the rectangular uniform line density of each grid cell, the total pin wiring length, and the wiring resource information, the wiring congestion information of the chip is determined, including the congestion level of each grid cell.
[0103] In one embodiment, when the processor 303 determines the rectangular uniform line density of each grid cell wiring and the total pin wiring length based on the pin information and the pin network information, it is configured to: The chip is divided into multiple grid units by a preset granularity; The wiring density of each grid cell is calculated based on the pin information and the pin network information to obtain the rectangular uniform line density of the wiring in each grid cell; The wiring length of all pins in each grid cell is calculated based on the pin information and the pin network information to obtain the total wiring length of the pins in each grid cell.
[0104] In one embodiment, the pin information includes the pin coordinates of each pin, and the pin network information includes the name of each pin network and an index table between each pin network and each pin; the processor 303, when implementing the calculation of the wiring density of each grid cell based on the pin information and the pin network information to obtain the rectangular uniform line density of the wiring of each grid cell, is configured to: Obtain the pin offset coefficient and the standard deviation of the pin offset; The boundary coordinates of each pin network are determined based on the pin offset coefficient, the pin offset standard deviation, the index table, and the pin coordinates of each pin. The rectangular uniform line density of the wiring for each of the pin networks is determined based on the boundary coordinates of each pin network.
[0105] In one embodiment, when implementing the process of determining the rectangular uniform line density of the wiring for each mesh cell based on the boundary coordinates of each pin network, the processor 303 is configured to: The wiring density of each pin network is calculated based on the boundary coordinates to obtain the sub-rectangular uniform line density of each pin network; The rectangular uniform line density of the wiring in each grid cell is obtained by weighted summation of the sub-rectangular uniform line densities of each pin network contained in each grid cell.
[0106] In one embodiment, the pin information includes the pin coordinates of each pin, and the pin network information includes the name of each pin network and an index table of each pin network and each pin; when the processor 303 calculates the wiring length of all pins in each grid cell based on the pin information and the pin network information to obtain the total wiring length of the pins in each grid cell, it is configured to: Based on the pin coordinates of each pin and the index table, determine the wiring lengths of all pins in each pin network; The total pin wiring length of each grid cell is obtained by weighted summing of the wiring lengths of each pin network contained in each grid cell.
[0107] In one embodiment, when the processor 303 determines the wiring length of all pins in each pin network based on the pin coordinates of each pin and the index table, it is configured to: Determine the number of pins for each of the pin networks; If the number of pins in the pin network is less than or equal to the preset number of pins, the pin coordinates of each pin in the pin network are predicted using the preset minimum right-angle Steiner tree algorithm to obtain the wiring length of all pins in the pin network. If the number of pins in the pin network is greater than the preset number of pins, then the pins in the pin network are clustered to obtain multiple pin clusters; The wiring lengths of all pins in the pin network are predicted by using a preset minimum right-angle Steiner tree algorithm.
[0108] In one embodiment, when the processor 303 performs the step of predicting the wiring length of the plurality of pin clusters of the pin network using a preset minimum right-angle Steiner tree algorithm to obtain the wiring length of all pins in the pin network, it is configured to: The cluster center coordinates of each pin cluster are determined, and the wiring length is predicted by the cluster center coordinates of each pin cluster using a preset minimum right-angle Steiner tree algorithm to obtain the first wiring length. The pin coordinates of each pin in each pin cluster are predicted using a preset minimum right-angle Steiner tree algorithm to obtain the second wiring length of each pin cluster. The wiring lengths of all pins in the pin network are obtained by summing the first wiring length and the second wiring length of each pin cluster.
[0109] In one embodiment, when the processor 303 performs the weighted summation of the wiring lengths of each pin network contained in each of the grid cells to obtain the total wiring length of the pins in each of the grid cells, it is configured to: Determine whether a clock pin network exists in the grid cell, and obtain the preset line length adjustment parameters for each grid cell; If there is no clock pin network in the grid cell, the wiring length of each pin network in the grid cell is weighted and summed by a preset line length adjustment parameter to obtain the total wiring length of the pins in the grid cell. If a clock pin network exists in the grid cell, the wiring length of the clock pin network is multiplied by a preset coefficient to obtain the target wiring length. The total pin wiring length of the grid cell is obtained by weighted summing the wiring length of the non-clock pin network and the target wiring length of the clock pin network using preset line length adjustment parameters.
[0110] In one embodiment, when the processor 303 determines the wiring congestion information of the chip based on the rectangular uniform line density of each of the grid cell wirings, the total pin wiring length, and the wiring resource information, it is configured to: Based on the total pin wiring length of each grid cell and the wiring resource information, determine the wiring resource utilization index of each grid cell; The rectangular uniform line density of the wiring in each grid cell is normalized to obtain the target spatial distribution density of the wiring in each grid cell. The congestion level of each grid cell is determined based on the target spatial distribution density and cabling resource utilization index of each grid cell.
[0111] In one embodiment, when the processor 303 determines the congestion level of each grid cell based on the target spatial distribution density and wiring resource utilization index of each grid cell, it is configured to: Obtain the congestion index coefficient for each of the grid cells, the congestion index coefficient being determined based on the standard deviation of pin offsets within the grid cell; The congestion index of each grid cell is obtained by weighting its target spatial distribution density and cabling resource utilization index according to the congestion index coefficient of each grid cell. By mapping the congestion index of each grid cell to a congestion level using a preset mapping table, the congestion level of each grid cell is obtained.
[0112] It should be noted that those skilled in the art will understand that, for the sake of convenience and brevity, the specific working process of the computer equipment described above can be referred to the corresponding process in the aforementioned wiring congestion prediction method embodiment, and will not be repeated here.
[0113] This application also provides a computer-readable storage medium storing a computer program, the computer program including program instructions, and the method implemented when the program instructions are executed can refer to various embodiments of the wiring congestion prediction method of this application.
[0114] The computer-readable storage medium can be an internal storage unit of the computer device described in the foregoing embodiments, such as a hard disk or memory of the computer device. The computer-readable storage medium can be non-volatile or volatile. Alternatively, the computer-readable storage medium can be an external storage device of the computer device, such as a plug-in hard disk, Smart Media Card (SMC), Secure Digital (SD) card, or Flash Card equipped on the computer device.
[0115] It should be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the scope of the application. As used in this specification, unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “the” are intended to include the plural forms.
[0116] It should also be understood that the term "and / or" as used in this specification refers to any combination and all possible combinations of one or more of the associated listed items, and includes such combinations. It should be noted that, herein, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or system. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or system that includes that element.
[0117] The sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments. The above descriptions are merely specific implementations of this application, but the protection scope of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the protection scope of this application.
Claims
1. A method of wiring congestion prediction, characterized by, include: Obtain the basic layout data of the chip, which includes pin information, pin network information and routing resource information; Based on the pin information and the pin network information, determine the rectangular uniform line density of each grid cell wiring of the chip and the total pin wiring length; Based on the rectangular uniform line density of each grid cell, the total pin wiring length, and the wiring resource information, the wiring congestion information of the chip is determined, including the congestion level of each grid cell.
2. The cabling congestion prediction method as described in claim 1, characterized in that, The step of determining the rectangular uniform line density of each grid cell wiring and the total wiring length of the pins based on the pin information and the pin network information includes: The chip is divided into multiple grid units by a preset granularity; The wiring density of each grid cell is calculated based on the pin information and the pin network information to obtain the rectangular uniform line density of the wiring in each grid cell; The wiring length of all pins in each grid cell is calculated based on the pin information and the pin network information to obtain the total wiring length of the pins in each grid cell.
3. The wiring congestion prediction method according to claim 2, wherein The pin information includes the pin coordinates of each pin, and the pin network information includes the name of each pin network and an index table between each pin network and each pin; the step of calculating the wiring density of each grid cell based on the pin information and the pin network information to obtain the rectangular uniform line density of the wiring in each grid cell includes: Obtain the pin offset coefficient and the standard deviation of the pin offset; The boundary coordinates of each pin network are determined based on the pin offset coefficient, the pin offset standard deviation, the index table, and the pin coordinates of each pin. The rectangular uniform line density of the wiring for each of the pin networks is determined based on the boundary coordinates of each pin network.
4. The wiring congestion prediction method according to Claim 3, wherein The step of determining the rectangular uniform line density of the wiring for each mesh cell based on the boundary coordinates of each pin network includes: The wiring density of each pin network is calculated based on the boundary coordinates to obtain the sub-rectangular uniform line density of each pin network; The rectangular uniform line density of the wiring in each grid cell is obtained by weighted summation of the sub-rectangular uniform line densities of each pin network contained in each grid cell.
5. The wiring congestion prediction method according to Claim 2, wherein The pin information includes the pin coordinates of each pin, and the pin network information includes the name of each pin network and an index table of each pin network and each pin; the step of calculating the wiring length of all pins in each grid cell based on the pin information and the pin network information to obtain the total wiring length of the pins in each grid cell includes: Based on the pin coordinates of each pin and the index table, determine the wiring lengths of all pins in each pin network; The total pin wiring length of each grid cell is obtained by weighted summing of the wiring lengths of each pin network contained in each grid cell.
6. The wiring congestion prediction method according to Claim 5, wherein The step of determining the wiring length of all pins in each pin network based on the pin coordinates of each pin and the index table includes: Determine the number of pins for each of the pin networks; If the number of pins in the pin network is less than or equal to the preset number of pins, the pin coordinates of each pin in the pin network are predicted by the preset minimum right-angle Steiner tree algorithm to obtain the wiring length of all pins in the pin network. If the number of pins in the pin network is greater than the preset number of pins, then the pins in the pin network are clustered to obtain multiple pin clusters; The wiring lengths of all pins in the pin network are predicted by using a preset minimum right-angle Steiner tree algorithm.
7. The wiring congestion prediction method according to Claim 6, wherein The step of predicting the wiring length of the multiple pin clusters of the pin network using a preset minimum right-angle Steiner tree algorithm to obtain the wiring length of all pins in the pin network includes: The cluster center coordinates of each pin cluster are determined, and the wiring length is predicted by the cluster center coordinates of each pin cluster using a preset minimum right-angle Steiner tree algorithm to obtain the first wiring length. The pin coordinates of each pin in each pin cluster are predicted using a preset minimum right-angle Steiner tree algorithm to obtain the second wiring length of each pin cluster. The wiring lengths of all pins in the pin network are obtained by summing the first wiring length and the second wiring length of each pin cluster.
8. The wiring congestion prediction method according to Claim 5, wherein The step of weighted summing of the wiring lengths of each pin network contained in each of the grid cells to obtain the total wiring length of the pins in each grid cell includes: Determine whether a clock pin network exists in the grid cell, and obtain the preset line length adjustment parameters for each grid cell; If there is no clock pin network in the grid cell, the wiring length of each pin network in the grid cell is weighted and summed by a preset line length adjustment parameter to obtain the total wiring length of the pins in the grid cell. If a clock pin network exists in the grid cell, the wiring length of the clock pin network is multiplied by a preset coefficient to obtain the target wiring length. The total pin wiring length of the grid cell is obtained by weighted summing the wiring length of the non-clock pin network and the target wiring length of the clock pin network using preset line length adjustment parameters.
9. The cabling congestion prediction method as described in claim 1, characterized in that, The step of determining the wiring congestion information of the chip based on the rectangular uniform line density of each of the grid cells, the total pin wiring length, and the wiring resource information includes: Based on the total pin wiring length of each grid cell and the wiring resource information, determine the wiring resource utilization index of each grid cell; The rectangular uniform line density of the wiring in each grid cell is normalized to obtain the target spatial distribution density of the wiring in each grid cell. The congestion level of each grid cell is determined based on the target spatial distribution density and cabling resource utilization index of each grid cell.
10. The cabling congestion prediction method as described in claim 9, characterized in that, The step of determining the congestion level of each grid cell based on the target spatial distribution density and cabling resource utilization index of each grid cell includes: Obtain the congestion index coefficient for each of the grid cells, the congestion index coefficient being determined based on the standard deviation of pin offsets within the grid cell; The congestion index of each grid cell is obtained by weighting its target spatial distribution density and cabling resource utilization index according to the congestion index coefficient of each grid cell. By mapping the congestion index of each grid cell to a congestion level using a preset mapping table, the congestion level of each grid cell is obtained.
11. A cabling congestion prediction device, characterized in that, The cabling congestion prediction device includes an acquisition module and a determination module, wherein: The acquisition module is used to acquire the basic layout data of the chip, which includes pin information, pin network information and routing resource information. The determining module is used to determine the rectangular uniform line density of each grid cell wiring of the chip and the total wiring length of the pins based on the pin information and the pin network information. The determining module is further configured to determine the wiring congestion information of the chip based on the rectangular uniform line density of the wiring of each of the grid cells, the total wiring length of the pins, and the wiring resource information. The wiring congestion information includes the congestion level of each grid cell.
12. A computer device, characterized in that, The computer device includes a processor, a memory, and a computer program stored in the memory and executable by the processor, wherein when the computer program is executed by the processor, it implements the steps of the cabling congestion prediction method as described in any one of claims 1 to 10.
13. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, wherein when the computer program is executed by a processor, it implements the steps of the cabling congestion prediction method as described in any one of claims 1 to 10.