A method, apparatus and device for subsynchronous oscillation suppression

Abstract

This application discloses a method, apparatus, and device for suppressing subsynchronous oscillations, relating to the field of new energy power generation technology. The method includes: acquiring a voltage reference value, an actual voltage value, and an actual current value; wherein the voltage reference value is generated by a virtual synchronous generator power outer loop, the actual voltage value is obtained by sampling and coordinate transformation of the voltage of the filter capacitor at the inverter output, and the actual current value is obtained by sampling and coordinate transformation of the current of the filter inductor on the inverter side; performing disturbance estimation and compensation on the actual voltage value using a first linear active disturbance rejection controller to obtain the current reference value; performing disturbance estimation and compensation on the actual current value using a second linear active disturbance rejection controller to obtain a voltage modulation signal; wherein the first and second linear active disturbance rejection controllers are cascaded; performing an inverse coordinate transformation on the voltage modulation signal to obtain a three-phase modulation voltage; and performing pulse width modulation on the three-phase modulation voltage to obtain control pulses driving the inverter power switches. This method can effectively suppress subsynchronous oscillations.

Description

Technical Field

[0001] This application relates to the field of new energy power generation technology, and in particular to a method, apparatus and equipment for suppressing subsynchronous oscillations. Background Technology

[0002] With the rapid development of new energy power generation technologies, distributed energy sources such as photovoltaic and wind power are being connected to the grid on a large scale through inverters. Grid-mounted inverters, due to their voltage / frequency support capabilities, have become important equipment for new energy grid connection and are widely used in power systems. However, power systems contain a large number of capacitive components such as series capacitor compensation and long-distance transmission lines, which interact with the inductive impedance of the inverter, easily causing subsynchronous oscillation problems. This problem can lead to inverter output current distortion and power fluctuations, and in severe cases, it can even damage power equipment and threaten the stable operation of the power grid. Therefore, effectively suppressing subsynchronous oscillations has become an important research topic in the field of grid-mounted inverter grid connection control.

[0003] Currently, grid-connected inverters mostly employ a Virtual Synchronous Generator (VSG) control strategy combined with PI-PI cascaded dual-loop control to achieve grid-connected regulation. The VSG power outer loop simulates the inertia, damping, and droop characteristics of a synchronous generator, providing voltage and frequency support to the grid. The voltage and current loops use PI (Proportional-Integral) controllers to track the output voltage and inductor current, respectively. However, existing control methods have significant limitations, such as strong dependence on the system model, slow dynamic response, and low control accuracy, thus failing to effectively suppress subsynchronous oscillations.

[0004] Therefore, there is an urgent need for a method that can effectively suppress subsynchronous oscillations. Summary of the Invention

[0005] This application provides a method, apparatus, and device for suppressing subsynchronous oscillations, which can effectively suppress subsynchronous oscillations.

[0006] To achieve the above objectives, this application adopts the following technical solution: In a first aspect, this application provides a method for suppressing subsynchronous oscillations, comprising: The system acquires voltage reference value, actual voltage value, and actual current value. The voltage reference value is generated by the virtual synchronous generator power outer loop. The actual voltage value is obtained by sampling and transforming the voltage of the filter capacitor at the inverter output. The actual current value is obtained by sampling and transforming the current of the filter inductor on the inverter side. The actual voltage value is estimated and compensated by the first linear active disturbance rejection controller to obtain the current reference value. The voltage modulation signal is obtained by estimating and compensating for the disturbance of the actual current value through the second linear active disturbance rejection controller; wherein the first linear active disturbance rejection controller and the second linear active disturbance rejection controller are cascaded. The three-phase modulated voltage is obtained by performing an inverse coordinate transformation on the voltage modulation signal. The three-phase modulation voltage is pulse-width modulated to obtain the control pulses that drive the power switching transistors of the inverter.

[0007] In some possible implementations, a first linear active disturbance rejection controller is used to estimate and compensate for disturbances in the actual voltage value to obtain a current reference value, including: The actual voltage value is estimated by the linear extended state observer inside the first linear active disturbance rejection controller, and the estimated voltage state variable and the first total disturbance value are obtained. The first virtual control quantity is obtained based on the error between the voltage reference value and the voltage state variable estimate; Active compensation is performed by subtracting the first total disturbance estimate from the first virtual control value to obtain the current reference value.

[0008] In some possible implementations, a voltage modulation signal is obtained by estimating and compensating for the disturbance in the actual current value using a second linear active disturbance rejection controller, including: The actual current value is estimated by the linear extended state observer inside the second linear active disturbance rejection controller, and the estimated value of the current state variable and the second total disturbance are obtained. A second virtual control variable is generated based on the error between the current reference value and the estimated current state variable. Active compensation is performed by subtracting the second total disturbance estimate from the second virtual control value to generate a voltage modulation signal.

[0009] In some possible implementations, the transformation phase angle used for coordinate transformation and inverse coordinate transformation is generated by the power outer loop of the virtual synchronous generator, and the transformation phase angle is obtained by integrating the angular frequency output by the rotor motion equation of the virtual synchronous generator.

[0010] In some possible implementations, both the first linear active disturbance rejection controller and the second linear active disturbance rejection controller adopt a second-order linear active disturbance rejection control structure. The linear extended state observer inside the first linear active disturbance rejection controller and the second linear active disturbance rejection controller is a third-order observer, and the gain of the third-order observer is configured by the bandwidth method.

[0011] In some possible implementations, the feedback control law inside both the first and second linear active disturbance rejection controllers adopts a proportional-derivative control structure.

[0012] Among the possible implementations are: Using a harmonic linearization method, a positive and negative sequence impedance model of the inverter under traditional voltage-current proportional-integral dual-loop control under virtual synchronous generator control is established as a comparison benchmark. Based on the Nyquist impedance stability criterion, the phase margin at the intersection of the inverter output impedance and the grid impedance under voltage-current proportional-integral dual-loop control is calculated. The system stability margin is determined based on the phase margin, and it is found that traditional voltage-current proportional-integral dual-loop control cannot effectively suppress subsynchronous oscillations in the subsynchronous frequency band under high grid short-circuit conditions due to insufficient phase margin. The inverter output impedance characteristics formed by the dual-loop control structure composed of the cascaded first linear active disturbance rejection controller and the second linear active disturbance rejection controller are compared with the output impedance characteristics of voltage-current proportional-integral dual-loop control to prove that the dual-loop control structure composed of the cascaded first linear active disturbance rejection controller and the second linear active disturbance rejection controller improves the phase margin and achieves subsynchronous oscillation suppression.

[0013] Among some possible implementations, a positive and negative sequence impedance model of the inverter under traditional voltage-current proportional-integral dual-loop control under virtual synchronous generator control is established, including: Considering phase angle disturbance and mirror frequency coupling effect, small-signal modeling is performed on the virtual synchronous generator power outer loop, the traditional voltage loop proportional-integral control, and the traditional current loop proportional-integral control to obtain the positive-sequence output impedance and negative-sequence output impedance of the inverter.

[0014] Secondly, this application provides a subsynchronous oscillation suppression device, comprising: The acquisition module is used to acquire the voltage reference value, the actual voltage value, and the actual current value. The voltage reference value is generated by the virtual synchronous generator power outer loop, the actual voltage value is obtained by sampling and transforming the voltage of the filter capacitor at the inverter output, and the actual current value is obtained by sampling and transforming the current of the filter inductor on the inverter side. The compensation module is used to estimate and compensate for the disturbance of the actual voltage value through the first linear active disturbance rejection controller to obtain the current reference value; and to estimate and compensate for the disturbance of the actual current value through the second linear active disturbance rejection controller to obtain the voltage modulation signal; wherein the first linear active disturbance rejection controller and the second linear active disturbance rejection controller are cascaded. The transformation module is used to perform inverse coordinate transformation on the voltage modulation signal to obtain the three-phase modulation voltage; The modulation module is used to perform pulse width modulation on the three-phase modulation voltage to obtain control pulses to drive the power switching transistors of the inverter.

[0015] Thirdly, this application provides a computing device, including a memory and a processor; The memory stores one or more computer programs, the one or more computer programs including instructions; when the instructions are executed by the processor, the computing device performs the method as described in any one of the first aspects.

[0016] Fourthly, this application provides a computer-readable storage medium for storing a computer program for performing the method as described in any one of the first aspects.

[0017] Fifthly, this application provides a computer program product comprising one or more computer instructions, wherein when the computer instructions are executed by a computer, the computer performs the method as described in any one of the first aspects.

[0018] As can be seen from the above technical solution, this application has at least the following beneficial effects: In this application, a voltage reference value is generated through a virtual synchronous generator (VSG) power outer loop. Simultaneously, the voltage of the inverter output filter capacitor and the current of the inverter-side filter inductor are sampled and transformed using coordinates to obtain the actual voltage and current values. On one hand, the VSG power outer loop can simulate the inertia, damping, and droop characteristics of a synchronous generator, enabling the voltage reference value to naturally support the grid voltage and frequency, meeting the grid connection requirements of grid-connected inverters. On the other hand, accurate sampling and dq coordinate transformation of the filter capacitor voltage and filter inductor current decouple the three-phase AC quantities into direct-axis (d-axis) and quadrature-axis (q-axis) DC components, simplifying the computational complexity of subsequent control algorithms and enabling independent control of the d- and q-axis components. A first linear active disturbance rejection controller is used to estimate and compensate for disturbances in the actual voltage value, generating the current reference value. Compared to traditional PI controllers, Linear Active Disturbance Rejection Controllers (LADRCs) can estimate and compensate for internal system parameter perturbations (such as filter element parameter drift) and external power grid disturbances (such as voltage drops and harmonic injection) in real time through Linear Extended State Observer (LESO). This can quickly eliminate the deviation between the actual voltage value and the reference value, making the current reference value more in line with the dynamic requirements of the system. At the same time, in the cascaded structure, the voltage loop LADRC, as the outer loop, can prioritize the stable tracking of the filter capacitor voltage, defining a clear target boundary for the subsequent current loop control, avoiding voltage fluctuations from being directly transmitted to the current control loop, and improving the overall control's disturbance rejection robustness.

[0019] By employing a second linear active disturbance rejection controller (ALDC) to estimate and compensate for disturbances in the actual current value, a voltage modulation signal is generated, forming a cascaded dual-LADRC structure with the voltage loop LADRC. The current loop LADRC can further accurately correct the dynamic deviation of the filter inductor current, quickly offsetting current disturbances caused by factors such as changes in grid impedance and switching nonlinearity, ensuring that the actual current value strictly tracks the current reference value output by the voltage loop. The dual-LADRC cascaded design realizes a hierarchical control logic of "voltage stability - precise current regulation," which retains the LADRC's ability to actively observe and compensate for total disturbances, while clearly defining the control objectives of each controller through hierarchical division, avoiding excessive burden on a single controller. Compared with PI-PI cascaded control, it can improve the system's ability to suppress high-frequency disturbances and optimize the inverter's output impedance characteristics.

[0020] The voltage modulation signal in the dq coordinate system is inversely transformed to restore the modulation voltage in the three-phase stationary coordinate system. The inverse transformation between dq and abc coordinates converts the DC modulation signal generated by the control algorithm into a three-phase AC signal with the same frequency as the power grid, ensuring phase and amplitude matching between the modulation voltage and the inverter output voltage. At the same time, this transformation process has no information loss and can completely preserve the disturbance compensation effect of the dual LADRC controller, so that the three-phase modulation voltage accurately reflects the control strategy's intention to regulate voltage and current.

[0021] Pulse Width Modulation (PWM) converts the three-phase modulated voltage into control pulses to drive the inverter's power switches. PWM discretizes the continuous three-phase modulated voltage into a high-frequency pulse sequence, efficiently driving the power switches to achieve DC-AC energy conversion while ensuring the inverter's output voltage harmonic content meets grid connection standards. Combined with the disturbance compensation effect of dual LADRC controllers, this step accurately translates the optimized control commands into hardware-executable drive signals, ultimately achieving stable grid-connected operation of the inverter under complex grid conditions. Simultaneously, it suppresses instability risks such as subsynchronous oscillations, improving the system's grid-connected robustness. Ultimately, it effectively suppresses subsynchronous oscillations.

[0022] It should be understood that the descriptions of technical features, technical solutions, beneficial effects, or similar language in this application do not imply that all features and advantages can be achieved in any single embodiment. Rather, it is understood that the description of a feature or beneficial effect means that a specific technical feature, technical solution, or beneficial effect is included in at least one embodiment. Therefore, the descriptions of technical features, technical solutions, or beneficial effects in this specification do not necessarily refer to the same embodiment. Furthermore, the technical features, technical solutions, and beneficial effects described in this embodiment can be combined in any suitable manner. Those skilled in the art will understand that embodiments can be implemented without one or more specific technical features, technical solutions, or beneficial effects of a particular embodiment. In other embodiments, additional technical features and beneficial effects may be identified in specific embodiments that do not embody all embodiments. Attached Figure Description

[0023] Figure 1 An application environment diagram for a subsynchronous oscillation suppression method provided in this application embodiment; Figure 2 A flowchart illustrating a subsynchronous oscillation suppression method provided in this application embodiment; Figure 3 A structural diagram of a subsynchronous oscillation suppression device provided in an embodiment of this application; Figure 4 This is a schematic diagram of a computing device provided in an embodiment of this application. Detailed Implementation

[0024] The terms "first," "second," and "third," etc., used in this application specification and accompanying drawings are used to distinguish different objects, not to limit a specific order.

[0025] In the embodiments of this application, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design that is described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0026] To ensure clarity and conciseness in the description of the following embodiments, a brief introduction to the related technologies is given first: The Virtual Synchronous Generator (VSG) is an important control strategy for grid-connected inverters. By simulating the rotor motion equations, active power-frequency droop characteristics, and reactive power-voltage droop characteristics of a traditional synchronous generator, it replaces the phase-locked loop of the grid-connected converter, enabling the inverter to have grid-connection capabilities and adapt to the grid connection requirements of distributed new energy generation. Its power outer loop is the main unit for generating the voltage loop control reference value of the inverter.

[0027] Linear Active Disturbance Rejection Control (LADRC) is a robust control algorithm that does not rely on an accurate system model. It consists of a linear extended state observer (LESO), an error feedback control law (IEFCL), and a disturbance compensation loop. It can estimate the total disturbance caused by internal parameter perturbations and external disturbances in real time, and actively compensate for the disturbance. Compared with traditional proportional-integral (PI) control, it has better disturbance rejection and dynamic response.

[0028] Dual-loop control of inverters is a classic control architecture for grid-connected inverters. It consists of an outer voltage loop and an inner current loop. The voltage loop aims to stabilize the inverter's output voltage, while the current loop aims to accurately track the current reference value output by the voltage loop. Traditional solutions often use a PI-PI cascade structure, which is the foundation for inverters to achieve DC-AC energy conversion and stable grid connection.

[0029] The dq coordinate transformation / inverse transformation includes the abc→dqClark+Park transformation and the dq→abc inverse transformation. It is a commonly used coordinate transformation technique in power electronic control. It can decouple the AC voltage and current in the three-phase stationary coordinate system into DC quantities in the dq synchronous rotating coordinate system, simplifying the computational complexity of the linear control algorithm and realizing independent control of the d and q axis components. The phase angle required for the transformation is generated by the VSG power outer loop, ensuring the synchronicity and accuracy of the transformation.

[0030] Pulse width modulation (PWM) is a technique that converts the modulated voltage signal generated by the control algorithm into high-frequency switching pulses. It can drive the inverter power switching transistors to turn on and off, realize the conversion of DC-side electrical energy to AC-side electrical energy, and at the same time ensure that the harmonic content of the output voltage meets the grid connection standards.

[0031] Against the backdrop of large-scale grid connection of new energy power generation, grid-connected inverters, while possessing grid support capabilities through VSG control, are prone to subsynchronous oscillations due to the interaction between capacitive components in the power system, such as series capacitor compensation and long-distance transmission lines, and the inverter's inductive impedance. Existing technologies often employ a VSG power outer loop combined with PI-PI cascaded dual-loop control. This approach has significant technical drawbacks: First, PI controller parameter tuning relies on a precise system model. When grid conditions change (e.g., changes in grid impedance or voltage drops) or inverter internal parameters drift, control robustness decreases drastically, failing to effectively suppress internal and external disturbances. Second, the PI-PI cascaded structure has a slow dynamic response, insufficient suppression of high-frequency subsynchronous disturbances, and the coupling effect between the voltage and current loops easily reduces control accuracy. Third, traditional control schemes do not effectively reshape the inverter's output impedance, failing to fundamentally solve the oscillation problem caused by the interaction of capacitive and inductive impedances, ultimately leading to inverter output current distortion and power fluctuations, seriously threatening the stable operation of the power grid.

[0032] In view of this, embodiments of this application provide a method for suppressing subsynchronous oscillations. To make the technical solution of this application clearer and easier to understand, the application scenarios of the technical solution of this application are described below with reference to the accompanying drawings. Figure 1 As shown, this figure is an application environment diagram provided by an embodiment of this application.

[0033] In this application environment, server 104 receives inverter operation data collected by sensors in real time and executes various control logics and calculations for subsynchronous oscillation suppression through built-in algorithms. Terminal 102 establishes a communication connection with server 104 and can send operation commands such as control parameter configuration and start / stop commands to server 104. At the same time, server 104 will feed back information such as the operating status, monitoring data, and control results of subsynchronous oscillation suppression to terminal 102 in real time for maintenance personnel to view, monitor, and adjust.

[0034] To make the technical solution of this application clearer and easier to understand, the following describes a subsynchronous oscillation suppression method provided by an embodiment of this application, using server 104 as the execution subject, in conjunction with the above application scenario. Figure 2 As shown, this figure is a schematic flowchart of a subsynchronous oscillation suppression method provided in an embodiment of this application. The subsynchronous oscillation suppression method includes: S201. Obtain the voltage reference value, the actual voltage value, and the actual current value.

[0035] The voltage reference value is generated by the virtual synchronous generator (VSG) power outer loop. The actual voltage value is obtained by sampling and transforming the voltage of the filter capacitor at the inverter output, and the actual current value is obtained by sampling and transforming the current of the filter inductor on the inverter side. The voltage reference value is the desired target value for the voltage loop control of the grid-connected inverter. It is calculated and generated by the VSG power outer loop control module and presented in component form in the dq synchronous rotating coordinate system. It serves as the benchmark for the inverter output voltage to track, and its value is dynamically adjusted by the power outer loop based on factors such as grid power demand and voltage frequency support requirements. The actual voltage value refers to the true voltage value at the output filter capacitor during actual inverter operation. It is also presented in component form in the dq synchronous rotating coordinate system and is a physical quantity reflecting the actual voltage output state of the inverter, serving as the feedback basis for voltage loop control. The actual current value refers to the actual current flowing through the filter inductor on the inverter side during operation. It is presented as a component in the dq synchronous rotating coordinate system, reflecting the true operating state of the inverter's inductor current and serving as the feedback physical quantity for current loop control. The Virtual Synchronous Generator (VSG) power outer loop is the outer control layer of a grid-connected inverter, replacing the phase-locked loop of a grid-connected converter. It simulates the power-frequency and reactive-voltage droop characteristics of a synchronous generator, calculating and outputting the voltage reference value required by the voltage loop based on the active and reactive power demands of the grid, while providing voltage and frequency support to the grid. The filter capacitor is a passive filter element at the inverter output, used to filter out harmonic components in the inverter output voltage, making the output voltage closer to a sine wave, and stabilizing the inverter output voltage. It is the object of sampling for the actual voltage value. The filter inductor is a passive filter element on the inverter side, working in conjunction with the filter capacitor to form an LC filter circuit. It filters out harmonics in the inverter output current and limits the rate of change of the inverter's output current, and is also the object of sampling for the actual current value. Coordinate transformation (abc→dq) is the process of converting the physical quantities of voltage and current in the three-phase stationary coordinate system (abc coordinate system) into the direct axis (d-axis) and quadrature axis (q-axis) components in the synchronous rotating coordinate system dq through Clark transformation and Park transformation. After the transformation, the AC quantity can be converted into the DC quantity, which is convenient for control using linear control algorithms.

[0036] For example, the voltage reference value is actively generated by the virtual synchronous generator power outer loop, while the actual voltage and current values ​​are obtained by sampling and coordinate transformation of the physical quantities at the corresponding locations of the inverter. The acquisition processes of the three physical quantities are independent and synchronous, as detailed below: To generate a voltage reference value, the inverter's virtual synchronous generator power outer loop collects the voltage and current signals output by the inverter in real time, calculates the actual output active and reactive power, and then, in conjunction with the synchronous generator's rotor motion equations, active-frequency droop control, and reactive-voltage droop control strategies, dynamically calculates and generates a voltage reference value in the dq synchronous rotating coordinate system based on the power balance requirements and voltage-frequency support requirements of the power grid. This value serves as the reference input for the voltage loop LADRC controller, guiding the inverter's voltage output.

[0037] Furthermore, in order to acquire and convert the actual voltage value, a voltage sampling element can be arranged at the filter capacitor at the output of the inverter to acquire the physical quantity of the three-phase voltage of the filter capacitor in the three-phase stationary coordinate system (abc coordinate system) in real time. The acquired three-phase voltage signal in the abc coordinate system is input to the coordinate transformation module, and through the abc→dq coordinate transformation, it is converted into the actual voltage value in the dq synchronous rotating coordinate system. This value is used as the feedback input of the voltage loop LADRC controller to reflect the actual voltage output state of the inverter.

[0038] To achieve the acquisition and conversion of actual current values, a current sampling element can be arranged at the filter inductor on the inverter side to acquire the physical quantity of the three-phase current of the filter inductor in real time in the three-phase stationary coordinate system (abc coordinate system). The acquired three-phase current signal in the abc coordinate system is input to the coordinate transformation module, and through the abc→dq coordinate transformation, it is converted into the actual current value in the dq synchronous rotating coordinate system. This value is used as the feedback input of the current loop LADRC controller to reflect the actual operating status of the inverter inductor current.

[0039] In the above process, the voltage reference value provides the target benchmark for control, while the actual voltage and current values ​​provide the real feedback state for control. Together, these three constitute the input basis for the cascaded LADRC dual-loop control (voltage loop and current loop) of the grid-connected inverter, ensuring that the control algorithm can adjust according to the deviation between the actual state and the reference target.

[0040] It should be noted that the dual PI control is replaced with dual LADRC control, i.e., LADRC-LADRC, which are the voltage loop LADRC controller and the current loop LADRC controller, respectively. The acquisition and transformation of voltage and current signals are performed synchronously. The actual voltage value and the actual current value are sampled at the same time and calculated under the same coordinate transformation phase, so that the two sets of feedback signals are consistent in time and phase.

[0041] Optionally, in the control of the virtual synchronous generator, distributed energy sources such as batteries and photovoltaic panels are equivalently represented as a DC power source, denoted as . ; For filtering inductors, For capacitors; It is the series equivalent resistance of the filter inductor. It is the series equivalent resistance of the capacitor; the current flowing through the three-phase inductors are respectively expressed as... , and ,and , and This represents the three-phase current at the inverter output. , and This represents the three-phase voltage on the inverter side. , and This represents the three-phase voltage at the inverter output. Indicates the grid-side filter inductance; This represents the equivalent impedance on the grid side; w represents the rated angular frequency of the grid (also the fundamental angular frequency). The virtual synchronous generator control loop includes a power outer loop, a voltage loop, and a current inner loop.

[0042] The power outer loop collects the voltage and current output of the inverter and calculates the active power output of the inverter. and reactive power They are used as input variables for the virtual synchronous generator control loop.

[0043] By controlling a virtual synchronous generator, the reference voltage amplitude E and phase angle can be obtained. This forms the reference voltage for the voltage loop control. The voltage loop in this study employs a proportional-integral (PI) control algorithm to ensure the output voltage... (x=d,q) can closely track the reference voltage. (x=d,q), and output the reference value of the current loop. (x=d,q).

[0044] The current loop uses a linear active disturbance rejection control algorithm to ensure the inductor current. (x=d,q) closely follows the reference current (x=d,q), and output inverter modulated voltage. (x=d,q).

[0045] The mathematical model of the inverter based on the virtual synchronous generator (VSG) is as follows:

[0046] Multiplying the above equation by the Park matrix on the left, we get:

[0047]

[0048] in, (x=d,q) means Differentiating the components of (x=a,b,c) on the dq axis and substituting them, we get:

[0049] Both the voltage loop LADRC controller and the current loop LADRC controller are controlled in the dq synchronous rotating coordinate system, and the d-axis and q-axis are configured with LADRC controllers independently.

[0050] Both the voltage loop LADRC controller and the current loop LADRC controller include a linear extended state observer (LESO), an error feedback control law (IEFCL), and a disturbance compensation circuit.

[0051] The Linear Extended State Observer (LESO) is used to estimate the system state variables and the total disturbance term, including internal dynamic uncertainties and external disturbances, based on the inputs and outputs of the controlled object. The D-axis control model is a second-order mathematical model in the time domain, which can be specifically expressed as:

[0052] Because the D-axis control model is a second-order mathematical model in the time domain, a second-order LADRC controller needs to be designed. We can set:

[0053] in, Let the state variable be 1; Let 2 be the state variable.

[0054] The state-space equations then transform into:

[0055] in, State variables The derivative is ; It is obtained directly from the second-order differential equation, that is .

[0056] To simplify LADRC controller design, all terms except control inputs are packaged into a lumped disturbance. f , can be represented as:

[0057] At this point, the state equation can be simplified to:

[0058] in, , .

[0059] Extending the original second-order system and the total disturbance f into a third-order state-space model can be expressed as:

[0060] in, The original system state is 1, corresponding to ; The original system state is 21, corresponding to ; The extended state represents the total disturbance f, i.e. =f; , , For each state variable, the time derivatives are given. To control the input, corresponding The scaled equivalent control quantity; h is the time derivative of the total disturbance f, i.e. ; To control the input gain, corresponding ; y is the system output, i.e., the observed quantity (y= ).

[0061] The third-order LESO (Linear Extended State Observer) can be represented as:

[0062] in, , , Gain for LESO , , These are estimates of the state variables; The time derivatives of each estimate are given. By selecting an appropriate gain... , , LESO can achieve real-time tracking of state variables with minimal steady-state error.

[0063] The control law can be expressed as:

[0064] in, The reference control quantity output by the controller (such as the output of a basic controller like PD / PI).

[0065] Therefore, the characteristic equation of LESO is:

[0066] in, is the characteristic polynomial of LESO (describing the dynamic characteristics of the observer); s is the Laplace operator (frequency domain analysis variable). The observation gain for LESO (uniquely determined by bandwidth w0).

[0067] Configure the characteristic equation as ,but , This refers to the bandwidth of LESO.

[0068] The Error Feedback Control Law (IEFCL) is used to generate a virtual control quantity based on the error between the reference signal and the LESO estimated state. If the estimation error is ignored, the system can be simplified to a dual-integral cascade structure, which can be expressed as:

[0069] in, The second derivative of the system output y (y=x1, i.e.) ); The extended state is the total disturbance; u is the actual control input. It is a virtual control quantity (the equivalent control input after disturbance compensation).

[0070] The PD controller is designed as follows:

[0071] in, For system reference input (expected) (value), that is, the given signal, The proportional gain of the PD controller; This is the differential gain of the PD controller.

[0072] The closed-loop transfer function of the system is:

[0073] in, Let be the closed-loop transfer function of the system after disturbance compensation.

[0074] Configure the control system as a standard second-order system:

[0075] in, For controller bandwidth, This is the damping ratio. To avoid oscillation, [the damping ratio will be used]. Set it to 1.

[0076] The disturbance compensation stage uses the total disturbance term estimated by LESO to compensate the virtual control quantity and generate the final control output signal.

[0077] The transfer functions of z1, z2, and z3 can be expressed as:

[0078] PD control law With disturbance compensation control law Combining these, we obtain the final explicit control law, which can be expressed as:

[0079] Substituting the transfer functions of z1, z2, and z3 into the equation, we get:

[0080] Therefore, the voltage loop control equation of LADRC can be expressed as:

[0081] in, The d / q axis components of the inverter bridge arm output voltage (control output quantity); This is the d / q axis reference value for the output voltage (desired voltage).

[0082] function and The expression is as follows:

[0083]

[0084] in, The bandwidth angular frequency of the LADRC controller determines the tracking performance and disturbance rejection capability of the closed-loop system; This is the transfer function from the reference signal to the control output in LADRC; This is the transfer function in LADRC that feeds the controlled variable back to the control output.

[0085] and The small signal components are:

[0086] in, for Small signal perturbation components; for Small signal disturbance components; The small-signal disturbance component of the reference voltage; This refers to the small-signal disturbance component of the output voltage.

[0087] The obtained LADRC positive sequence output impedance expression is as follows:

[0088] in, It is the positive sequence output impedance of the inverter under LADRC control, where j is the imaginary unit; For positive-sequence perturbation angular frequency; intermediate variable , , , , , The expression is as follows:

[0089] variable - The expression is as follows:

[0090] in, The fundamental angular frequency of the power grid; It is a linear combination of intermediate variables defined to simplify the impedance expression; its essence is a linear operation of Y1 to Y8.

[0091] By utilizing the conversion relationship between the positive-sequence and negative-sequence impedances of the inverter output, the formula for the negative-sequence impedance can be derived. .in, This is the negative sequence output impedance of the inverter. This is the positive sequence output impedance of the inverter; To invert the complex frequency variable, replace s in the positive sequence impedance expression with... s; First, the positive sequence impedance is... Replace s in (s) with s, and then take the complex conjugate of the result to obtain the negative sequence impedance.

[0092] S202. The actual voltage value is estimated and compensated by the first linear active disturbance rejection controller to obtain the current reference value.

[0093] An implementable method involves estimating the actual voltage value using a linear extended state observer within a first linear active disturbance rejection controller to obtain an estimated voltage state variable and a first total disturbance estimate; obtaining a first virtual control quantity based on the error between the voltage reference value and the estimated voltage state variable; and actively compensating by subtracting the first total disturbance estimate from the first virtual control quantity to obtain a current reference value.

[0094] The first linear active disturbance rejection controller (LADRC), also known as the grid-type inverter voltage loop LADRC controller, is the outer controller of the cascaded LADRC dual-loop control system. It is specifically designed for the control requirements of the voltage loop, tracking the inverter output voltage through disturbance estimation and compensation, and ultimately outputting the current reference value required by the current loop. Disturbance estimation and compensation are crucial functions of the LADRC controller. First, the internal module estimates the total disturbance term formed by all internal and external disturbances in the system. Then, this disturbance term is canceled out from the control quantity, thereby eliminating the impact of disturbances on the controlled object and improving the anti-interference capability and accuracy of the control. The Linear Extended State Observer (LESO) is a key component of the first LADRC controller. It is a state observation module that can estimate the system's state variables in real time based on the input and output signals of the controlled object. Simultaneously, it integrates internal dynamic uncertainties (such as circuit parameter deviations and coupling effects) and external disturbances (such as grid voltage fluctuations) into a single total disturbance term. The voltage state variable estimate is obtained by LESO after estimating the actual voltage value. It is a real-time estimate of important state variables such as the state of the filter capacitor voltage and the rate of change of voltage in the inverter voltage loop, reflecting the actual operating state characteristics of the voltage. The first total disturbance estimate is the total disturbance term at the voltage loop level estimated by LESO, including cross-coupling terms within the voltage loop, grid voltage disturbances, circuit parameter drift, and other internal and external disturbances affecting voltage control. The voltage reference value is the expected target voltage value in the dq coordinate system generated by the VSG power outer loop. It is the benchmark for voltage loop control, and the first LADRC controller aims to track this value. The first virtual control quantity is a preliminary control quantity calculated by the state error feedback control law based on the error between the voltage reference value and the voltage state variable estimate. It does not consider the influence of disturbances and is the basic control signal for achieving voltage tracking. Dynamic compensation is the operation of subtracting the total disturbance estimate from the virtual control quantity. By actively canceling the influence of disturbances, the final control quantity can accurately drive the controlled object to track the reference value. The current reference value is the result output by the first LADRC controller after completing disturbance estimation and compensation, and it is the control target value of the inverter current loop.

[0095] It should be noted that the first linear active disturbance rejection controller continuously receives the voltage reference value and the actual voltage value. The internal observer performs parallel estimation of the voltage state and the total disturbance in real time. The controller generates a virtual control quantity based on the state deviation and completes disturbance compensation, so that the output current reference value can quickly follow the voltage control target in dynamic changes, realizing the adaptive adjustment of the voltage loop to external disturbances and internal parameter changes.

[0096] For example, the first linear active disturbance rejection controller (LESO), as the main control unit of the voltage loop, aims to track the voltage reference value and counteract internal and external disturbances in the voltage loop. Through three key steps—state and disturbance estimation using an internal linear extended state observer, virtual control quantity generation based on state error feedback, and active disturbance compensation—it transforms the control requirements at the voltage level into the current reference value for the current loop. Specifically, the process is as follows: First, the linear extended state observer (LESO) inside the first LESO receives the actual voltage value at the inverter output. Based on this feedback signal, it performs real-time state estimation. On one hand, it obtains an estimated voltage state variable value that reflects the actual operating state of the voltage. On the other hand, it integrates all internal and external disturbances existing in the voltage loop, such as cross-coupling, grid voltage fluctuations, and circuit parameter deviations, to accurately estimate the first total disturbance value, thus completing the dual perception of the voltage loop state and disturbances. Then… The controller compares the voltage reference value sent from the VSG power outer loop with the voltage state variable estimate obtained from LESO, calculates the error between the two, and then performs proportional-derivative (PD) calculation on the error through the internal state error feedback control law (IEFCL) to generate a first virtual control quantity for tracking the voltage reference value. This control quantity is a preliminary control signal that does not consider the influence of disturbances. Finally, in order to eliminate the influence of disturbances on voltage control, the controller performs an active compensation operation, subtracting the first total disturbance estimate estimated by LESO from the generated first virtual control quantity. This operation cancels out the effect of all disturbances, so that the compensated control quantity can accurately guide the control of the current loop. The final result is the current reference value, which will be used as the main command input to the second linear active disturbance rejection controller (current loop LADRC) to realize the transmission of the voltage loop control target to the current loop.

[0097] S203. The actual current value is estimated and compensated for by the second linear active disturbance rejection controller to obtain the voltage modulation signal.

[0098] The first linear active disturbance rejection controller and the second linear active disturbance rejection controller are cascaded.

[0099] An implementable method involves estimating the actual current value using a linear extended state observer within a second linear active disturbance rejection controller to obtain an estimated current state variable and a second total disturbance estimate; generating a second virtual control quantity based on the error between the current reference value and the estimated current state variable; and actively compensating by subtracting the second total disturbance estimate from the second virtual control quantity to generate a voltage modulation signal.

[0100] It should be noted that both the first and second linear active disturbance rejection controllers employ a second-order linear active disturbance rejection control structure. The linear extended state observers within both controllers are third-order observers, with the gain configured using the bandwidth method. The feedback control laws within both controllers employ a proportional-derivative control structure. The second linear active disturbance rejection controller receives the current reference value from the preceding stage and simultaneously acquires the actual value of the filter inductor current. Through its internal observer, it observes the current state and disturbances. Based on the current tracking error, the controller generates a control quantity and performs disturbance cancellation, enabling the output voltage modulation signal to quickly correct the current deviation and ensure stable current tracking under complex operating conditions.

[0101] The second linear active disturbance rejection controller (ALDRC), also known as the grid-type inverter current loop LADRC controller, is the inner controller of the cascaded LADRC dual-loop control system. It receives the current reference value output from the voltage loop, performs disturbance estimation and compensation on the actual current value, and ultimately outputs a voltage modulation signal to drive the inverter. This signal works in conjunction with the first LADRC controller to achieve accurate inverter control. The voltage modulation signal is the final output of the second LADRC controller, presented as d- and q-axis components in a synchronous rotating coordinate system. The cascaded structure refers to the sequential control relationship between the first LADRC controller (voltage loop) and the second LADRC controller (current loop). The output of the voltage loop serves as the input of the current loop, forming a hierarchical control link from voltage control to current control. The current state variable estimate is obtained by the LESO within the second LADRC through state estimation of the actual current value. The second total disturbance estimate is the total disturbance term at the current loop level estimated by the LESO within the second LADRC, including a comprehensive estimate of all internal and external disturbances affecting current control, such as hardware dead-zone effects within the current loop, grid impedance changes, and circuit parameter drift. The second virtual control quantity is a preliminary control quantity calculated using a state error feedback control law based on the error between the current reference value and the estimated current state variable, without considering the impact of disturbances. The second-order linear active disturbance rejection control structure refers to the control architecture designed for the second-order mathematical model of the controlled object by the LADRC controller. The third-order observer, also known as the third-order linear extended state observer (LESO), is an observer designed to complement the second-order LADRC controller. It adds the estimation dimension of the total disturbance term to the estimation of the second-order state variables of the controlled object. The bandwidth method is a parameter configuration method for LADRC controllers. By setting the observer bandwidth, the characteristic equation of LESO is configured in a specified form, thereby determining the gain parameter of the third-order observer. The proportional-derivative (PD) control structure is the control form used in the state error feedback control law. It generates a virtual control quantity by performing proportional and derivative operations on the error between the reference value and the estimated value.

[0102] For example, the second linear active disturbance rejection controller (LADRC), as the main control unit of the current loop, forms a cascaded control structure with the first LADRC. Both adopt a second-order linear active disturbance rejection control structure, internally configured with a third-order linear extended state observer (LESO) with gain configured using the bandwidth method, and both have proportional-derivative control (PDC) feedback laws. This controller aims to track the current reference value output by the first LADRC and counteract internal and external disturbances in the current loop. Through three main stages—state and disturbance estimation, virtual control quantity generation, and active disturbance compensation—it transforms the current-level control requirements into voltage modulation signals for the inverter. Specifically, the second LADRC receives the current reference value output by the first LADRC and simultaneously acquires the actual current value after abc→dq coordinate transformation. Its internal third-order linear extended state observer (LESO) uses the actual current value as input for real-time state estimation. On the one hand, it accurately obtains the estimated current state variables reflecting the operating state of the filter inductor current; on the other hand, it incorporates all internal factors in the current loop, such as hardware dead-time effects, grid impedance changes, and internal parameter drift. External disturbances are integrated and estimated to obtain a second total disturbance estimate, achieving accurate dual perception of the current loop state and disturbances. Next, the controller compares the current reference value with the current state variable estimate output by LESO, calculates the deviation between the two, and then performs proportional and derivative operations on the deviation using an internal state error feedback control law with a proportional-derivative (PD) control structure to generate a second virtual control quantity for tracking the current reference value. This control quantity is a preliminary control signal that does not consider the impact of disturbances. Finally, to completely eliminate the impact of disturbances on current control, the controller performs an active compensation operation, subtracting the second total disturbance estimate estimated by LESO from the generated second virtual control quantity. This operation cancels out the effect of all disturbances on the current loop, enabling the compensated control quantity to accurately drive the inverter to achieve current tracking. The final result is the voltage modulation signal (Vid, Viq) in the dq coordinate system. This signal, as the final output of the cascaded LADRC dual-loop control, will enter the subsequent coordinate transformation and SVPWM modulation stage, providing the main drive signal for the inverter's grid-connected operation.

[0103] S204. Perform coordinate inverse transformation on the voltage modulation signal to obtain the three-phase modulation voltage, and perform pulse width modulation on the three-phase modulation voltage to obtain the control pulses driving the power switching transistors of the inverter.

[0104] It should be noted that the transformation phase angle used in the coordinate transformation and inverse coordinate transformation is generated by the power outer loop of the virtual synchronous generator, and the transformation phase angle is obtained by integrating the angular frequency output by the rotor motion equation of the virtual synchronous generator.

[0105] The inverse coordinate transformation (dq→abc) is the transformation process corresponding to the abc→dq coordinate transformation. It refers to the operation of converting DC quantities such as voltage and current in the dq synchronous rotating coordinate system into AC quantities in the three-phase stationary coordinate system (abc coordinate system). The three-phase modulated voltage is the voltage signal in the three-phase stationary coordinate system obtained after the inverse coordinate transformation. Pulse width modulation (PWM) is a modulation technique that encodes voltage signals. It uses the pulse width to equivalently simulate the required AC voltage amplitude and frequency. For example, space vector pulse width modulation (SVPWM) can be used. The control pulses driving the inverter power switches are high-frequency switching pulse signals generated after PWM modulation, which can directly drive the IGBT, MOSFET, and other power switches of the inverter to turn on and off. The transformation phase angle is the main phase parameter required in the coordinate transformation and inverse coordinate transformation processes. It is generated by the VSG power outer loop and is used to determine the phase correspondence between the dq synchronous rotating coordinate system and the abc three-phase stationary coordinate system, ensuring the accuracy of the coordinate transformation. The rotor motion equation of the virtual synchronous generator is the main mathematical equation of the VSG power outer loop. It can simulate the rotor inertia and damping characteristics of a traditional synchronous generator and output the inverter's operating angular frequency according to the changes in the active power of the grid. The angular frequency is output by the VSG rotor motion equation, reflecting the frequency characteristics of the inverter's output AC voltage. It is the fundamental physical quantity for generating the transformation phase angle, and its value is dynamically adjusted according to the balance state of the grid's active power.

[0106] For example, by transforming the electrical signal output from the cascaded LADRC dual-loop control into a crucial step of driving the physical switching signal of the inverter hardware, the implementation from control algorithm to hardware execution is achieved. Furthermore, the phase reference for coordinate transformation and inverse transformation is uniformly generated by the VSG power outer loop, ensuring phase synchronization of the entire control system. Specifically, the process is as follows: First, the voltage modulation signal in the dq synchronous rotating coordinate system output by the second linear active disturbance rejection controller is acquired. Simultaneously, the transformation phase angle generated by the VSG power outer loop is retrieved—this phase angle is obtained by integrating the inverter operating angular frequency output from the rotor motion equation through the VSG power outer loop, serving as the main phase reference for the inverse coordinate transformation. This phase angle is also synchronously used in the earlier abc→dq coordinate transformation, ensuring phase consistency between the forward and inverse transformations. Subsequently, the voltage modulation signal is input to… The dq→abc coordinate inverse transformation module uses the transformation phase angle generated by the VSG power outer loop as a reference to complete the conversion from dq DC to abc three-phase AC, obtaining a three-phase modulated voltage adapted to the inverter's three-phase topology. Finally, the three-phase modulated voltage is input to the Space Vector Pulse Width Modulation (SVPWM) module. The SVPWM module generates a series of high- and low-level high-frequency pulse signals according to the amplitude and frequency requirements of the three-phase modulated voltage, which are the control pulses driving the inverter's power switches. These control pulses directly act on the inverter's power switches, controlling them to turn on and off according to a set rule, thereby converting the DC power of the inverter into three-phase AC power that meets the grid requirements, achieving stable grid connection. At the same time, combined with the impedance reshaping effect of the previous LADRC, the suppression of subsynchronous oscillation is completed at the hardware execution level.

[0107] Based on the above, the subsynchronous oscillation suppression method generates a voltage reference value through a virtual synchronous generator (VSG) power outer loop. Simultaneously, it samples and transforms the voltage of the inverter output filter capacitor and the current of the inverter-side filter inductor to obtain the actual voltage and current values. On one hand, the VSG power outer loop can simulate the inertia, damping, and droop characteristics of a synchronous generator, enabling the voltage reference value to naturally support the grid voltage and frequency, meeting the grid connection requirements of grid-connected inverters. On the other hand, the precise sampling and dq coordinate transformation of the filter capacitor voltage and filter inductor current decouples the three-phase AC quantities into direct-axis (d-axis) and quadrature-axis (q-axis) DC components, simplifying the computational complexity of the subsequent control algorithm and enabling independent control of the d-axis and q-axis components.

[0108] By employing a first linear active disturbance rejection controller (LADRC) to estimate and compensate for disturbances in the actual voltage value, a current reference value is generated. Compared to traditional PI controllers, the LADRC, through a linear extended state observer (LESO), can estimate and compensate for internal system parameter perturbations (such as filter element parameter drift) and external grid disturbances (such as voltage dips and harmonic injection) in real time. This quickly eliminates the deviation between the actual voltage value and the reference value, making the current reference value more closely match the dynamic requirements of the system. Simultaneously, in the cascaded structure, the voltage loop LADRC, as the outer loop, can prioritize the stable tracking of the filter capacitor voltage, defining a clear target boundary for subsequent current loop control, preventing voltage fluctuations from being directly transmitted to the current control loop, and improving the overall control's disturbance rejection robustness.

[0109] By employing a second linear active disturbance rejection controller (ALDC) to estimate and compensate for disturbances in the actual current value, a voltage modulation signal is generated, forming a cascaded dual-LADRC structure with the voltage loop LADRC. The current loop LADRC can further accurately correct the dynamic deviation of the filter inductor current, quickly offsetting current disturbances caused by factors such as changes in grid impedance and switching nonlinearity, ensuring that the actual current value strictly tracks the current reference value output by the voltage loop. The dual-LADRC cascaded design realizes a hierarchical control logic of "voltage stability - precise current regulation," which retains the LADRC's ability to actively observe and compensate for total disturbances, while clearly defining the control objectives of each controller through hierarchical division, avoiding excessive burden on a single controller. Compared with PI-PI cascaded control, it can improve the system's ability to suppress high-frequency disturbances and optimize the inverter's output impedance characteristics.

[0110] The voltage modulation signal in the dq coordinate system is inversely transformed to restore the modulation voltage in the three-phase stationary coordinate system. The inverse transformation between dq and abc coordinates converts the DC modulation signal generated by the control algorithm into a three-phase AC signal with the same frequency as the power grid, ensuring phase and amplitude matching between the modulation voltage and the inverter output voltage. At the same time, this transformation process has no information loss and can completely preserve the disturbance compensation effect of the dual LADRC controller, so that the three-phase modulation voltage accurately reflects the control strategy's intention to regulate voltage and current.

[0111] Pulse Width Modulation (PWM) converts the three-phase modulated voltage into control pulses to drive the inverter's power switches. PWM discretizes the continuous three-phase modulated voltage into a high-frequency pulse sequence, efficiently driving the power switches to achieve DC-AC energy conversion while ensuring the inverter's output voltage harmonic content meets grid connection standards. Combined with the disturbance compensation effect of dual LADRC controllers, this step accurately translates the optimized control commands into hardware-executable drive signals, ultimately achieving stable grid-connected operation of the inverter under complex grid conditions. Simultaneously, it suppresses instability risks such as subsynchronous oscillations, improving the system's grid-connected robustness. Ultimately, it effectively suppresses subsynchronous oscillations.

[0112] Based on the above embodiments, this embodiment provides a detailed explanation of constructing the comparative benchmark model, including: Using a harmonic linearization method, a positive and negative sequence impedance model of the inverter under traditional voltage-current proportional-integral dual-loop control under virtual synchronous generator control is established as a comparison benchmark. Based on the Nyquist impedance stability criterion, the phase margin at the intersection of the inverter output impedance and the grid impedance under voltage-current proportional-integral dual-loop control is calculated. The system stability margin is determined based on the phase margin, and it is found that traditional voltage-current proportional-integral dual-loop control cannot effectively suppress subsynchronous oscillations in the subsynchronous frequency band under high grid short-circuit conditions due to insufficient phase margin. The inverter output impedance characteristics formed by the dual-loop control structure composed of the cascaded first linear active disturbance rejection controller and the second linear active disturbance rejection controller are compared with the output impedance characteristics of voltage-current proportional-integral dual-loop control to prove that the dual-loop control structure composed of the cascaded first linear active disturbance rejection controller and the second linear active disturbance rejection controller improves the phase margin and achieves subsynchronous oscillation suppression.

[0113] Optionally, considering phase angle disturbance and mirror frequency coupling effect, small-signal modeling is performed on the virtual synchronous generator power outer loop, the traditional voltage loop proportional-integral control, and the traditional current loop proportional-integral control to obtain the positive-sequence output impedance and negative-sequence output impedance of the inverter.

[0114] Harmonic linearization is a processing method for small-signal characteristic analysis of power electronic closed-loop systems, which can transform nonlinear systems into linear models near the steady-state operating point. The Nyquist impedance stability criterion is an analytical basis for judging the stability of a grid-connected system based on the amplitude and phase relationship between frequency domain impedance curves. Phase margin is an indicator that measures the stability margin of a system at crossover frequencies, directly reflecting the system's ability to resist oscillations. Phase angle disturbance is the phase shift that occurs when the system is subjected to external disturbances. Image frequency coupling effect is the phenomenon where positive and negative sequence disturbances map each other on the frequency coordinates, creating a cross-effect. Small-signal modeling is the process of applying small-amplitude disturbances to the system and establishing a linearized dynamic model. Positive-sequence output impedance is the equivalent impedance characteristic of the inverter to the positive-sequence components of the system. Negative-sequence output impedance is the equivalent impedance characteristic of the inverter to the negative-sequence components of the system.

[0115] Optionally, the robust stability condition can be set as a phase margin greater than 30°; when the phase margin is less than 0°, the system will experience subsynchronous oscillation; when the phase margin is between 0° and 30°, the system is not robust enough.

[0116] For example, the verification and analysis of the control effect can be completed by establishing a comparative model. The traditional control structure can be transformed by using harmonic linearization. The power outer loop, voltage loop and current loop of the virtual synchronous generator are modeled with small signals respectively, and the phase angle disturbance and image frequency coupling effect are incorporated into the model. Finally, the positive sequence and negative sequence output impedance of the inverter corresponding to the traditional control method are obtained.

[0117] Furthermore, stability analysis can be performed using the Nyquist impedance stability criterion. The inverter output impedance and grid impedance are compared in the frequency domain to determine the intersection of their amplitude curves and calculate the corresponding phase margin. The phase margin is calculated as the difference between the phase of the grid impedance and the phase of the inverter output impedance at the amplitude intersection frequency, reflecting the system's stability margin against oscillations at the crossover frequency.

[0118] The stability level of traditional control methods can be judged by the phase margin value. There is a direct mapping relationship between the two. For example, a phase margin greater than zero indicates that the system has basic stability, while a phase margin less than zero indicates that the system will experience subsynchronous oscillations. A phase margin greater than 30 degrees indicates that the system meets the requirements for robust stability, while a phase margin between 0 and 30 degrees indicates that the system has insufficient stability.

[0119] Furthermore, comparing this result with the impedance characteristics formed by the bilinear active disturbance rejection controller used in this application, the traditional voltage-current proportional-integral dual-loop control exhibits capacitive characteristics in the positive sequence impedance within the subsynchronous frequency band, interacting with the inductive impedance of the grid, resulting in a low or even negative phase margin. This application employs a dual-loop control structure composed of a cascaded first and second linear active disturbance rejection controller, which can reshape the inverter output impedance to maintain inductive or resistive characteristics within the subsynchronous frequency band, improving the phase margin and maintaining it within the robust stability range. Therefore, the difference in impedance characteristics and phase margin between the two control methods is confirmed, thus demonstrating that the cascaded bilinear active disturbance rejection control structure of this application possesses stronger subsynchronous oscillation suppression capabilities.

[0120] For example, the inverter output impedance can be reshaped by cascading the first linear active disturbance rejection controller and the second linear active disturbance rejection controller, thereby increasing the positive sequence impedance phase margin in the subsynchronous frequency band to more than 30°, thus achieving subsynchronous oscillation suppression under all grid strength conditions.

[0121] This embodiment compares the impedance characteristics and stability margin of the control method of this application with those of the traditional control method to analyze the beneficial effect of the subsynchronous oscillation suppression. The results show that the cascaded bilinear active disturbance rejection control structure adopted in this application can effectively improve the phase margin of the system, realize the suppression of subsynchronous oscillation under the full power grid strength, and has stronger stability and robustness.

[0122] The above text combined Figures 1 to 2The subsynchronous oscillation suppression method provided in the embodiments of this application has been described in detail. The apparatus and equipment provided in the embodiments of this application will be described below with reference to the accompanying drawings.

[0123] This application also provides a subsynchronous oscillation suppression device, such as... Figure 3 As shown in the figure, this is a schematic diagram of a subsynchronous oscillation suppression device provided in an embodiment of this application. The device includes: The acquisition module 301 is used to acquire the voltage reference value, the actual voltage value, and the actual current value. The voltage reference value is generated by the virtual synchronous generator power outer loop, the actual voltage value is obtained by sampling and transforming the voltage of the filter capacitor at the inverter output, and the actual current value is obtained by sampling and transforming the current of the filter inductor on the inverter side. The compensation module 302 is used to estimate and compensate for the disturbance of the actual voltage value through the first linear active disturbance rejection controller to obtain the current reference value; and to estimate and compensate for the disturbance of the actual current value through the second linear active disturbance rejection controller to obtain the voltage modulation signal; wherein the first linear active disturbance rejection controller and the second linear active disturbance rejection controller are cascaded. The transformation module 303 is used to perform an inverse coordinate transformation on the voltage modulation signal to obtain a three-phase modulation voltage. The modulation module 304 is used to perform pulse width modulation on the three-phase modulation voltage to obtain control pulses to drive the power switching transistors of the inverter.

[0124] In some possible implementations, the compensation module 302 is specifically used for: The actual voltage value is estimated by the linear extended state observer inside the first linear active disturbance rejection controller, and the estimated voltage state variable and the first total disturbance value are obtained. The first virtual control quantity is obtained based on the error between the voltage reference value and the voltage state variable estimate; Active compensation is performed by subtracting the first total disturbance estimate from the first virtual control value to obtain the current reference value.

[0125] In some possible implementations, the compensation module 302 is specifically used for: The actual current value is estimated by the linear extended state observer inside the second linear active disturbance rejection controller, and the estimated value of the current state variable and the second total disturbance are obtained. A second virtual control variable is generated based on the error between the current reference value and the estimated current state variable. Active compensation is performed by subtracting the second total disturbance estimate from the second virtual control value to generate a voltage modulation signal.

[0126] In some possible implementations, the transformation phase angle used for coordinate transformation and inverse coordinate transformation is generated by the power outer loop of the virtual synchronous generator, and the transformation phase angle is obtained by integrating the angular frequency output by the rotor motion equation of the virtual synchronous generator.

[0127] In some possible implementations, both the first linear active disturbance rejection controller and the second linear active disturbance rejection controller adopt a second-order linear active disturbance rejection control structure. The linear extended state observer inside the first linear active disturbance rejection controller and the second linear active disturbance rejection controller is a third-order observer, and the gain of the third-order observer is configured by the bandwidth method.

[0128] In some possible implementations, the feedback control law inside both the first and second linear active disturbance rejection controllers adopts a proportional-derivative control structure.

[0129] In some possible implementations, the subsynchronous oscillation suppression device includes: The comparison module is used to establish the positive and negative sequence impedance models of the inverter under traditional voltage-current proportional-integral dual-loop control under virtual synchronous generator control using the harmonic linearization method, serving as a comparison benchmark. Based on the Nyquist impedance stability criterion, the phase margin at the intersection of the inverter output impedance and the grid impedance under the voltage-current proportional-integral dual-loop control is calculated. The system stability margin is determined based on the phase margin, confirming that the traditional voltage-current proportional-integral dual-loop control cannot effectively suppress subsynchronous oscillations in the subsynchronous frequency band under high grid short-circuit conditions due to insufficient phase margin. The inverter output impedance characteristics formed by the dual-loop control structure composed of the cascaded first linear active disturbance rejection controller and the second linear active disturbance rejection controller are compared with the output impedance characteristics of the voltage-current proportional-integral dual-loop control to prove that the dual-loop control structure composed of the cascaded first linear active disturbance rejection controller and the second linear active disturbance rejection controller improves the phase margin and achieves subsynchronous oscillation suppression.

[0130] In some possible implementations, the comparison module is specifically used for: Considering phase angle disturbance and mirror frequency coupling effect, small-signal modeling is performed on the virtual synchronous generator power outer loop, the traditional voltage loop proportional-integral control, and the traditional current loop proportional-integral control to obtain the positive-sequence output impedance and negative-sequence output impedance of the inverter.

[0131] The subsynchronous oscillation suppression device according to the embodiments of this application can correspond to the execution of the method described in the embodiments of this application, and the other operations and / or functions of each module / unit of the subsynchronous oscillation suppression device are respectively for implementing Figure 2 For the sake of brevity, the corresponding processes of each method in the illustrated embodiments will not be described in detail here.

[0132] This application also provides a computing device. For example... Figure 4As shown in the figure, this is a schematic diagram of a computing device provided in an embodiment of this application. The computing device 400 includes a bus 401, a processor 402, a communication interface 403, and a memory 404. The processor 402, the memory 404, and the communication interface 403 communicate with each other via the bus 401.

[0133] Bus 401 can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of representation, Figure 4 The bus is represented by a single thick line, but this does not mean that there is only one bus or one type of bus.

[0134] Processor 402 can be any one or more of the following processors: central processing unit (CPU), graphics processing unit (GPU), microprocessor (MP), or digital signal processor (DSP).

[0135] Communication interface 403 is used for communication with external devices.

[0136] Memory 404 may include volatile memory, such as random access memory (RAM). Memory 404 may also include non-volatile memory, such as read-only memory (ROM), flash memory, hard disk drive (HDD), or solid state drive (SSD).

[0137] The memory 404 stores executable code, and the processor 402 executes the executable code to perform the aforementioned subsynchronous oscillation suppression method.

[0138] Specifically, in achieving Figure 3 In the case of the illustrated embodiment, and Figure 3 When the modules or units of the subsynchronous oscillation suppression device described in the embodiments are implemented by software, the following applies: Figure 3The software or program code required for the functions of each module / unit can be partially or entirely stored in memory 404. Processor 402 executes the program code corresponding to each unit stored in memory 404 and performs the aforementioned subsynchronous oscillation suppression method.

[0139] This application also provides a computer-readable storage medium. The computer-readable storage medium can be any available medium that a computing device can store, or a data storage device such as a data center containing one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid-state drive). The computer-readable storage medium includes instructions that instruct the computing device to perform the aforementioned subsynchronous oscillation suppression method.

[0140] This application also provides a computer program product comprising one or more computer instructions. When the computer instructions are loaded and executed on a computing device, all or part of the processes or functions described in this application are generated.

[0141] The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions may be transmitted from one website, computer, or data center to another website, computer, or data center via wired (e.g., coaxial cable, fiber optic) or wireless (e.g., infrared, wireless, microwave, etc.) means.

[0142] When the computer program product is executed by a computer, the computer performs any of the aforementioned subsynchronous oscillation suppression methods. The computer program product can be a software installation package; when any of the aforementioned subsynchronous oscillation suppression methods is required, the computer program product can be downloaded and executed on the computer.

[0143] The descriptions of the processes or structures corresponding to the above figures each have their own emphasis. For parts of a process or structure that are not described in detail, please refer to the relevant descriptions of other processes or structures.

[0144] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions within the technical scope disclosed in this application should be covered within the scope of protection of this application.

Claims

1. A method of subsynchronous oscillation suppression, characterized by, The method includes: The voltage reference value, actual voltage value, and actual current value are obtained; wherein, the voltage reference value is generated by the virtual synchronous generator power outer loop, the actual voltage value is obtained by sampling and coordinate transformation of the voltage of the filter capacitor at the inverter output, and the actual current value is obtained by sampling and coordinate transformation of the current of the filter inductor on the inverter side. The actual voltage value is estimated and compensated for by the first linear active disturbance rejection controller to obtain the current reference value. The voltage modulation signal is obtained by performing disturbance estimation and compensation on the actual current value through a second linear active disturbance rejection controller; wherein the first linear active disturbance rejection controller and the second linear active disturbance rejection controller are cascaded. The voltage modulation signal is subjected to inverse coordinate transformation to obtain the three-phase modulation voltage; The three-phase modulation voltage is pulse-width modulated to obtain the control pulses that drive the power switching transistors of the inverter.

2. The method of claim 1, wherein, The step of estimating and compensating for disturbances in the actual voltage value using a first linear active disturbance rejection controller to obtain a current reference value includes: The actual voltage value is estimated by the linear extended state observer inside the first linear active disturbance rejection controller, and the voltage state variable estimate and the first total disturbance estimate are obtained. The first virtual control quantity is obtained based on the error between the voltage reference value and the estimated voltage state variable; Active compensation is performed by subtracting the first total disturbance estimate from the first virtual control value to obtain the current reference value.

3. The method of claim 1, wherein, The step of estimating and compensating for disturbances in the actual current value using a second linear active disturbance rejection controller to obtain a voltage modulation signal includes: The actual current value is estimated by the linear extended state observer inside the second linear active disturbance rejection controller, and the estimated value of the current state variable and the second total disturbance are obtained. A second virtual control quantity is generated based on the error between the current reference value and the estimated current state variable value. Active compensation is performed by subtracting the second total disturbance estimate from the second virtual control quantity to generate a voltage modulation signal.

4. The method of claim 1, wherein, The transformation phase angle used in the coordinate transformation and inverse coordinate transformation is generated by the power outer loop of the virtual synchronous generator. The transformation phase angle is obtained by integrating the angular frequency output by the rotor motion equation of the virtual synchronous generator.

5. The method of claim 1, wherein, Both the first linear active disturbance rejection controller and the second linear active disturbance rejection controller adopt a second-order linear active disturbance rejection control structure. The linear extended state observer inside the first linear active disturbance rejection controller and the second linear active disturbance rejection controller is a third-order observer, and the gain of the third-order observer is configured by the bandwidth method.

6. The method of claim 1, wherein, The feedback control law inside both the first and second linear active disturbance rejection controllers adopts a proportional-derivative control structure.

7. The method of claim 1, wherein, The method further includes: Using the harmonic linearization method, a positive and negative sequence impedance model of an inverter under traditional voltage-current proportional-integral dual-loop control under virtual synchronous generator control is established as a comparison benchmark. Based on the Nyquist impedance stability criterion, the phase margin at the intersection of the inverter output impedance and the grid impedance under the voltage-current proportional-integral dual-loop control is calculated. Based on the phase margin, the stability margin of the system is determined. It is found that the traditional voltage-current proportional-integral dual-loop control cannot effectively suppress subsynchronous oscillations in the subsynchronous frequency band under high grid short-circuit conditions due to insufficient phase margin. The inverter output impedance characteristics formed by the dual-loop control structure consisting of the cascaded first linear active disturbance rejection controller and the second linear active disturbance rejection controller are compared with the output impedance characteristics of the voltage-current proportional-integral dual-loop control to prove that the dual-loop control structure consisting of the cascaded first linear active disturbance rejection controller and the second linear active disturbance rejection controller improves the phase margin and achieves subsynchronous oscillation suppression.

8. The method according to claim 7, characterized in that, The establishment of the positive and negative sequence impedance model of the inverter under traditional voltage-current proportional-integral dual-loop control under virtual synchronous generator control includes: Considering phase angle disturbance and mirror frequency coupling effect, small-signal modeling is performed on the virtual synchronous generator power outer loop, the traditional voltage loop proportional-integral control, and the traditional current loop proportional-integral control to obtain the positive-sequence output impedance and negative-sequence output impedance of the inverter.

9. A subsynchronous oscillation suppression device, characterized in that, The device includes: The acquisition module is used to acquire voltage reference value, actual voltage value, and actual current value; wherein, the voltage reference value is generated by the virtual synchronous generator power outer loop, the actual voltage value is obtained by sampling and coordinate transformation of the voltage of the filter capacitor at the inverter output terminal, and the actual current value is obtained by sampling and coordinate transformation of the current of the filter inductor on the inverter side; The compensation module is used to estimate and compensate for the disturbance of the actual voltage value through a first linear active disturbance rejection controller to obtain a current reference value; and to estimate and compensate for the disturbance of the actual current value through a second linear active disturbance rejection controller to obtain a voltage modulation signal; wherein the first linear active disturbance rejection controller and the second linear active disturbance rejection controller are cascaded. The transformation module is used to perform an inverse coordinate transformation on the voltage modulation signal to obtain a three-phase modulation voltage; The modulation module is used to perform pulse width modulation on the three-phase modulation voltage to obtain control pulses for driving the power switching transistors of the inverter.

10. A computing device, characterized in that, Including memory and processor; The memory stores one or more computer programs, the one or more computer programs including instructions; when the instructions are executed by the processor, the computing device performs the method as described in any one of claims 1 to 8.

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