RLL(1,4) encoding and decoding method and device for optical storage and optical storage system

Abstract

The application discloses an RLL(1,4) encoding and decoding method and device for optical storage and an optical storage system, and belongs to the technical field of optical storage, and comprises the following steps: in the encoding process, four-block joint encoding, three-block joint encoding, double-block joint encoding and single-block encoding are sequentially performed on user data according to a pre-established mapping table, so that every 3-bit user data is encoded into 5-bit channel symbols; in the mapping table of multi-block joint encoding, the first 5-bit sub-block of a code word starts with a bit '0' or is a specific 5-bit sequence starting with a bit '1'; in the decoding process, the 5-bit sub-block starting with a bit '1' is first identified as a boundary to complete a division, and then the specific 5-bit sub-block starting with a bit '1' is identified as a boundary to complete a secondary division; and the code word obtained through the division is demapped into a user data block according to the mapping table. The application can improve the encoding and decoding throughput of optical storage, suppress error propagation in the encoding and decoding process, and improve the performance and reliability of optical storage.

Description

Technical Field

[0001] This invention belongs to the field of optical storage technology, and more specifically, relates to an RLL(1,4) encoding and decoding method, apparatus and optical storage system for optical storage. Background Technology

[0002] Run-length limited (RLL) coding is widely used in magnetic storage, optical storage, and high-speed optical communication systems. A specific (d, k) sequence restricts the number of "0"s between any two adjacent "1"s to the range [d, k]. The lower limit d is used to suppress inter-symbol interference (ISI), while the upper limit k ensures sufficient signal transition edges, enabling the system's phase-locked loop (PLL) to perform accurate time clock recovery.

[0003] With the rapid development of AI technology, large model parameters and massive training data have triggered an exponential expansion in the demand for "cold data" storage. Optical storage media (especially Blu-ray discs) have become ideal carriers for AI cold data centers due to their long lifespan, high data security, and extremely low power consumption. However, due to the massive amount of data and for encoding and decoding cost considerations, current standard Blu-ray systems generally adopt the traditional low-cost 17PP (d=1, k=7) modulation scheme. This scheme has many inherent bottlenecks in decoding throughput and parallel processing capabilities. 1. Indeterminate Boundaries and Serial Dependency: 17PP is a non-prefix code, with severe bit pattern overlap (e.g., `000` can appear at the beginning of a codeword or in the center of other valid sequences). Because codeword boundaries cannot be determined instantaneously, and the subsequent encoding result depends on the last bit of the preceding channel symbols, the decoding process corresponding to 17PP encoding can only be performed serially, resulting in low decoding efficiency and thus limiting the read / write concurrency of optical storage media.

[0004] 2. Error Propagation: Due to the state machine coupling characteristics of variable-length codes, once a single bit error occurs in the channel, it often leads to the loss of decoder state for a long time, which in turn causes subsequent decoding errors to accumulate continuously.

[0005] These limitations restrict the encoding / decoding throughput and error rate of optical storage, making it unable to meet the requirements of modern AI data centers for high-concurrency reading and ultra-fast decoding of massive amounts of optical storage data. Summary of the Invention

[0006] In view of the shortcomings of the prior art and the need for improvement, the present invention provides an RLL(1,4) encoding and decoding method, apparatus and optical storage system for optical storage. The purpose is to improve the encoding and decoding throughput of optical storage, suppress error propagation in the encoding and decoding process, and improve the performance and reliability of optical storage.

[0007] To achieve the above objectives, according to one aspect of the present invention, an RLL(1,4) encoding / decoding method for optical storage is provided, comprising: an encoding step; the encoding step includes: The binary user data to be stored is divided into user data blocks of 3 bits in length, resulting in a sequence of user data blocks; The user data block sequence is sequentially encoded using four-block joint encoding, three-block joint encoding, two-block joint encoding, and single-block encoding, according to the pre-established four-block joint encoding mapping table, three-block joint encoding mapping table, two-block joint encoding mapping table, and single-block encoding mapping table. The channel symbols obtained by encoding are concatenated in sequence to obtain the encoded channel symbol sequence. The single-block coding mapping table records the one-to-one mapping relationship between seven user data blocks "000", "001", "010", "011", "100", "101", "110", and "111" and the channel symbols "10001", "00010", "01000", "00101", "00100", "01001", and "01010". For the remaining user data blocks, if their preceding channel symbol ends with a bit "1", they are mapped to the channel symbol "00001"; if their preceding channel symbol ends with a bit "0", they are mapped to the channel symbol "10101". The dual-block joint coding mapping table is used to record the mapping relationship between two consecutive user data blocks that cannot be encoded according to the single-block coding mapping table under run-length constraints and the 10-bit channel symbol. The three-block joint coding table... The code mapping table is used to record the mapping relationship between three consecutive user data blocks that cannot be encoded according to the single-block coding mapping table and the double-block joint coding mapping table under run-length constraint and 15-bit channel symbols; the four-block joint coding mapping table is used to record the mapping relationship between four consecutive user data blocks that cannot be encoded according to the single-block coding mapping table, the double-block joint coding mapping table and the triple-block joint coding mapping table under run-length constraint and 20-bit channel symbols; the run-length constraint is: the number of bits "0" between any two adjacent bits "1" in the channel symbol sequence is in the range of [1,4]; in the double-block joint coding mapping table, the triple-block joint coding mapping table and the four-block joint coding mapping table, the 5-bit channel symbol sequence starting with bit "0" is located at the beginning of the channel symbol, and the subsequent 5-bit channel symbol sequence is "10010" or "10100".

[0008] Furthermore, the mapping relationships recorded in the single-block encoding mapping table are as follows: “000”→“10001”; “001”→“00010”; “010”→“01000”; “011”→“00101”; “100”→“00100”; “101”→“01001”; “110”→“01010”; When the preceding channel code ends with a bit “1”, “111”→“00001”; When the preceding channel code ends with a bit “0”, “111”→“10101”; The mapping relationships recorded in the dual-block joint encoding mapping table are as follows: “000 000” → “01010 10100”; “010 001” → “01000 10010”; “010 100” → “0101010010”; “011 000” → “00100 10100”; “101 000” → “00100 10010”; “111 000” → “0100010100”; When the preceding channel code ends with a bit “1”, “010 011” → “00010 10010”; When the preceding channel code ends with a bit “0”, “010 011” → “10000 10010”; When the preceding channel code ends with a bit “1”, “100 001” → “00010”. "10100", when the preceding channel symbol ends with a bit "0", "100 001" → "10000 10100"; The mapping relationships recorded in the three combined encoding mapping tables are as follows: “000 000 001”→“01010 10100 10100”;“010 011 000”→“01000 1001010010”;“010 101 000”→“01010 10010 10010”;“011 000 001”→“01010 10100 10010”;“100 001 001”→“01000 10100 10100”;“111 000 001”→“01000 10100 10010”; The mapping relationships recorded in the four combined encoding mapping tables are as follows: “000 000 001 001” → “01000 10010 10010 10010”; “100 001 001 001” → “01000 10010 10100 10010”; Here, "→" indicates mapping to.

[0009] Furthermore, the RLL(1,4) encoding / decoding method for optical storage provided by the present invention further includes: a parallel decoding step; the parallel decoding step includes: The channel symbol sequence to be decoded is divided into channel symbol blocks of length 5, resulting in a channel symbol block sequence; Traverse the channel symbol block sequence, and use the channel symbol blocks that start with bit "0" as boundaries to serialize the channel symbol blocks into multiple channel symbol segments; In parallel, the channel symbol segment is identified to start with a bit "1". If it exists, the corresponding channel symbol segment is further divided into multiple codewords based on the channel symbol segment starting with a bit "1". Otherwise, the channel symbol segment is directly used as a codeword. Based on the number of 5-bit channel symbol sequences contained in each codeword, each codeword is demapped into user data blocks in parallel according to the corresponding mapping table; By concatenating user data blocks in sequence, the decoded user data is obtained.

[0010] According to another aspect of the present invention, an RLL(1,4) encoding / decoding apparatus for optical storage is provided, comprising: an encoding module; the encoding module comprising: The user data partitioning unit is used to divide the binary user data to be stored into user data blocks of 3 bits in length, so as to obtain a user data block sequence. The encoding unit is used to perform four-block joint encoding, three-block joint encoding, two-block joint encoding and single-block encoding on the user data block sequence in sequence according to the pre-established four-block joint encoding mapping table, three-block joint encoding mapping table, two-block joint encoding mapping table and single-block encoding mapping table; And a channel symbol splicing unit, used to sequentially splice the encoded channel symbols to obtain the encoded channel symbol sequence; The single-block coding mapping table records the one-to-one mapping relationship between seven user data blocks "000", "001", "010", "011", "100", "101", "110", and "111" and the channel symbols "10001", "00010", "01000", "00101", "00100", "01001", and "01010". For the remaining user data blocks, if their preceding channel symbol ends with a bit "1", they are mapped to the channel symbol "00001"; if their preceding channel symbol ends with a bit "0", they are mapped to the channel symbol "10101". The dual-block joint coding mapping table is used to record the mapping relationship between two consecutive user data blocks that cannot be encoded according to the single-block coding mapping table under run-length constraints and the 10-bit channel symbol. The three-block joint coding table... The code mapping table is used to record the mapping relationship between three consecutive user data blocks that cannot be encoded according to the single-block coding mapping table and the double-block joint coding mapping table under run-length constraint and 15-bit channel symbols; the four-block joint coding mapping table is used to record the mapping relationship between four consecutive user data blocks that cannot be encoded according to the single-block coding mapping table, the double-block joint coding mapping table and the triple-block joint coding mapping table under run-length constraint and 20-bit channel symbols; the run-length constraint is: the number of bits "0" between any two adjacent bits "1" in the channel symbol sequence is in the range of [1,4]; in the double-block joint coding mapping table, the triple-block joint coding mapping table and the four-block joint coding mapping table, the 5-bit channel symbol sequence starting with bit "0" is located at the beginning of the channel symbol, and the subsequent 5-bit channel symbol sequence is "10010" or "10100".

[0011] Furthermore, the mapping relationships recorded in the single-block encoding mapping table are as follows: “000”→“10001”; “001”→“00010”; “010”→“01000”; “011”→“00101”; “100”→“00100”; “101”→“01001”; “110”→“01010”; When the preceding channel code ends with a bit “1”, “111”→“00001”; When the preceding channel code ends with a bit “0”, “111”→“10101”; The mapping relationships recorded in the dual-block joint encoding mapping table are as follows: “000 000” → “01010 10100”; “010 001” → “01000 10010”; “010 100” → “0101010010”; “011 000” → “00100 10100”; “101 000” → “00100 10010”; “111 000” → “0100010100”; When the preceding channel code ends with a bit “1”, “010 011” → “00010 10010”; When the preceding channel code ends with a bit “0”, “010 011” → “10000 10010”; When the preceding channel code ends with a bit “1”, “100 001” → “00010”. "10100", when the preceding channel symbol ends with a bit "0", "100 001" → "10000 10100"; The mapping relationships recorded in the three combined encoding mapping tables are as follows: “000 000 001”→“01010 10100 10100”;“010 011 000”→“01000 1001010010”;“010 101 000”→“01010 10010 10010”;“011 000 001”→“01010 10100 10010”;“100 001 001”→“01000 10100 10100”;“111 000 001”→“01000 10100 10010”; The mapping relationships recorded in the four combined encoding mapping tables are as follows: “000 000 001 001” → “01000 10010 10010 10010”; “100 001 001 001” → “01000 10010 10100 10010”; Here, "→" indicates mapping to.

[0012] Furthermore, the RLL(1,4) encoding / decoding apparatus for optical storage provided by the present invention further includes: a parallel decoding module; the parallel decoding module includes: The channel symbol partitioning unit is used to divide the channel symbol sequence to be decoded into channel symbol blocks of length 5 bits to obtain the channel symbol block sequence. The first boundary identification unit is used to traverse the channel symbol block sequence, take the channel symbol blocks that start with bit "0" as the boundary, and serialize the channel symbol blocks into multiple channel symbol segments. The second boundary identification unit is used to identify the channel symbol start point that starts with bit "1" in each channel symbol segment in parallel. If it exists, the corresponding channel symbol segment is further divided into multiple codewords based on the channel symbol start point that starts with bit "1"; otherwise, the channel symbol segment is directly used as a codeword. The parallel decoding unit is used to demap each codeword into user data blocks in parallel according to the number of 5-bit channel symbol sequences contained in each codeword and the corresponding mapping table. And a user data splicing unit, used to splice user data blocks in sequence to obtain decoded user data.

[0013] Furthermore, the parallel decoding unit includes n hardware decoding channels, each of which is used to input codewords from the second boundary recognition unit, demap them, and output user data blocks; The codeword input, demapping, and user data block output of n hardware decoding channels are executed in a pipeline manner. Where n is a positive integer.

[0014] Furthermore, the RLL(1,4) encoding and decoding device for optical storage provided by the present invention further includes a parallel decoding module: a front-end receiving buffer unit for receiving and buffering continuous channel symbol sequences.

[0015] According to another aspect of the present invention, an optical storage system is provided, comprising: an optical storage medium and an RLL(1,4) encoding / decoding device for optical storage provided by the present invention.

[0016] In summary, the above-described technical solutions conceived in this invention can achieve the following beneficial effects: (1) The present invention uses a combination of single-block coding and multi-block joint coding, which can better meet the global run-length constraint. On this basis, the present invention forcibly introduces a deterministic block header alignment mechanism in multi-block joint coding. That is, in the multi-block joint coding table (double-block joint coding mapping table, triple-block joint coding mapping table and quadruple-block joint coding mapping table), the 5-bit channel code sequence starting with bit "0" is located at the beginning of the channel code. At the same time, the subsequent 5-bit channel code sequence is strictly constrained to the two feature blocks "10010" or "10100". Based on the determined codeword boundary, the present invention can quickly perform codeword segmentation during the decoding process. The demapping process of each codeword does not depend on the demapping result of the preceding codeword. Therefore, on the one hand, the demapping process of each codeword can be executed in parallel, which greatly improves the throughput of encoding and decoding. On the other hand, the impact of single-bit error is limited to a single codeword and will not spread backward, thereby greatly improving the reliability of optical storage.

[0017] (2) The RLL(1,4) code implemented in this invention is a second-order modulation code with low encoding and decoding costs. Compared with the traditional 17PP encoding, its specification parameters are optimized from k=7 (maximum interval of 8 clock edges) to k=4, which forces the effective coding stream on the channel to have at least one charging flip every 5 symbol bits. As a result, the PLL in the receiving circuit can capture much higher frequency and denser homogeneous calibration scale lines, and effectively filter out the low-frequency drift components that are extremely difficult to deal with in the signal transmission link, achieving excellent clock recovery feedback and greatly suppressing low-frequency energy. Attached Figure Description

[0018] Figure 1 A flowchart of the RLL(1,4) encoding and decoding method for optical storage provided in an embodiment of the present invention.

[0019] Figure 2 This is a schematic diagram of parallel decoding provided in an embodiment of the present invention.

[0020] Figure 3 This is a schematic diagram illustrating the single-bit error propagation scenario provided in an embodiment of the present invention.

[0021] Figure 4 This is an architecture diagram of the parallel decoding unit provided in an embodiment of the present invention.

[0022] Figure 5 This is a schematic diagram illustrating the mechanism of pipelined decoupling of spatiotemporal decoupling within the parallel decoding unit provided in this embodiment of the invention.

[0023] Figure 6 This is a schematic diagram comparing the clock cycles consumed by different encoding and decoding methods provided in the embodiments of the present invention.

[0024] Figure 7 This is a schematic diagram comparing the throughput of different encoding and decoding methods provided in the embodiments of the present invention.

[0025] Figure 8 This diagram illustrates the comparison of LUT / FF utilization rates for different encoding / decoding methods provided in embodiments of the present invention.

[0026] Figure 9 This is a schematic diagram comparing the energy consumption of different encoding and decoding methods provided in the embodiments of the present invention. Detailed Implementation

[0027] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. Furthermore, the technical features involved in the various embodiments of this invention described below can be combined with each other as long as they do not conflict with each other.

[0028] In this invention, the terms "first," "second," etc. (if present) in the invention and the accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0029] To address the shortcomings of traditional 17PP modulation schemes, such as nondeterministic boundaries, serial dependencies, and error propagation, which prevent them from meeting the high-concurrency reading and ultra-fast decoding requirements of modern AI cold data centers for massive optical storage data, this invention provides an RLL(1,4) encoding and decoding method, apparatus, and optical storage system for optical storage. The basic concept is to forcibly introduce a deterministic block header alignment mechanism in multi-block (two-block, three-block, four-block) joint encoding, thereby constructing a strictly prefix-free joint code table.

[0030] First, the run-length constraint conditions set in this invention are d=1 and k=4, meaning that the number of "0" bits between any two adjacent "1" bits in the channel symbol sequence is within the range of [1,4]. Further, this invention determines the basic coding rate based on a comprehensive trade-off between theoretical limit matching and engineering benefits: First, the Shannon capacity for the RLL(1,4) constraint can be solved using the characteristic equation. Substituting this into the binary scenario of d=1 and k=4, the maximum theoretical capacity is C(1,4)≈0.617, while the code rate of 3 / 5=0.6 is close to this theoretical upper limit, achieving a capacity utilization rate of 97.17%, with only a very small theoretical redundancy loss. Meanwhile, this fixed code rate eliminates the need for complex variable-length coding mechanisms, avoiding increased hardware complexity caused by redundant state transitions. It also provides constraint space for subsequent coding structure design that supports unambiguous prefixes and parallel decoding—by handling boundary conflicts with only a small number of blocks of joint coding, the prefix overlap problem of traditional 17PP coding can be completely eliminated while maintaining near-full capacity. This lays the foundation for the core advantages of parallel decoding and low error propagation, achieving optimal overall coding efficiency and system performance. Based on this, the basic coding code rate in this invention is 3 / 5, and correspondingly, every 3 user data bits are fixedly mapped to 5 channel coding bits.

[0031] To maintain low encoding and decoding costs, the RLL(1,4) code provided in this invention is a second-order modulation code. Under the corresponding basic code rate and run-length constraints, the design principle of the deterministic block header alignment mechanism introduced in this invention is as follows: In the multi-block (double / triple / quadruple) 5-bit joint coding block generated by continuous mapping, the starting bit of the first 5-bit sub-block is forcibly guaranteed to be constant with a feature value of 0. At the same time, after the first 5-bit sub-block, the patterns of the subsequent 5-bit sub-blocks are strictly constrained to the two feature blocks of "10010" and "10100". In some special cases, the 5-bit sub-block starting with bit "0" is occupied by other mapping rules. Since the pattern of the subsequent 5-bit sub-blocks is fixed in this invention, when it is impossible to select a suitable 5-bit sub-block starting with bit "0" as the first 5-bit sub-block, a sub-block starting with bit "1" but not used by other codewords can be selected as the first 5-bit sub-block.

[0032] Based on this block header alignment mechanism, this invention naturally eliminates boundary ambiguity during decoding while maintaining an extremely high approximation of the upper limit capacity (97.17% Shannon limit efficiency).

[0033] Single-block coding is notoriously difficult to design because it prevents run-length constraints from being violated at block connections, resulting in low coding efficiency. Multi-block joint coding, when converting raw data to RLL codes, does not target a single fixed-length data block (3-bit block) at a time, but rather considers multiple consecutive data blocks simultaneously, treating them as a whole to find the corresponding, typically longer, RLL codeword. Therefore, to improve coding efficiency, better satisfy run-length constraints, and reduce error propagation, a combination of single-block and multi-block joint coding is commonly used. This invention combines single-block, dual-block, triple-block, and quadruple-block joint coding, and correspondingly establishes single-block, dual-block, triple-block, and quadruple-block joint coding mapping tables.

[0034] In some optional embodiments, the established block encoding mapping table is shown in Table 1 below.

[0035] Table 1 Single Block Encoding Mapping Table

[0036] It should be noted that Table 1 above is only one optional implementation of the single-block coding mapping table. When designing the single-block coding mapping table, a one-to-one mapping relationship is established between the seven user data blocks “000”, “001”, “010”, “011”, “100”, “101”, “110”, and “111” and the channel symbols “10001”, “00010”, “01000”, “00101”, “00100”, “01001”, and “01010”. For the remaining user data blocks, if their preceding channel symbols end with a bit “1”, they are mapped to the channel symbol “00001”; if their preceding channel symbols end with a bit “0”, they are mapped to the channel symbol “10101”. For example, based on Table 1 above, the mapping rules for user data blocks "000" and "111" can be interchanged. That is, user data block "111" can be mapped to the symbol sequence "10001", while user data block "000" can be mapped to the symbol sequence "00001" or "00001" based on the last bit of the preceding channel symbol. More examples will not be listed here. For ease of description, Table 1 will be used as an example in the following embodiments. In addition, in Table 1, if the encoding conditions are not listed, it means that the encoding result is not affected by the last bit of the preceding channel symbol.

[0037] If single-block encoding is performed solely according to the single-block coding mapping table shown in Table 1, the run-length constraint may not be satisfied when encoding two consecutive user data blocks. For example, for two consecutive user data blocks "000000", the encoding result after encoding according to Table 1 is "10001 10001", which does not satisfy the condition that the lower limit of run length d=1; as another example, for two consecutive user data blocks "010 001", the encoding result after encoding according to Table 1 is "1000100010", which does not satisfy the condition that the upper limit of run length k=4. Therefore, this invention designs corresponding encoding rules for two consecutive user data blocks that cannot be encoded according to the single-block coding mapping table under the run-length constraint, to map the two user data blocks to 10-bit channel symbols under the run-length constraint, thereby establishing a dual-block joint coding mapping table, as shown in Table 2.

[0038] Table 2 Dual-block Joint Encoding Mapping Table

[0039] It is easy to understand that when changes occur in Table 1, the user data blocks that require dual-block joint encoding will also change.

[0040] Similarly, when encoding three consecutive user data blocks according to Tables 1 and 2, situations may arise where the run length constraint is not met. Therefore, this invention designs corresponding encoding rules for three consecutive user data blocks that cannot be encoded according to single-block encoding mapping tables and dual-block joint encoding mapping tables under run length constraints. These rules are used to map the three user data blocks to 15-bit channel symbols under run length constraints, thereby establishing a three-block joint encoding mapping table, as shown in Table 3.

[0041] Table 3 Three-block joint coding mapping table

[0042] Similarly, when encoding four consecutive user data blocks according to Tables 1-3, situations may arise where the run length constraint is not met. Therefore, this invention designs corresponding encoding rules for four consecutive user data blocks that cannot be encoded according to single-block encoding mapping tables, dual-block joint encoding mapping tables, and triple-block joint encoding mapping tables under run length constraints. These rules are used to map the four user data blocks to 20-bit channel symbols under run length constraints, thereby establishing a four-block joint encoding mapping table, as shown in Table 4.

[0043] Table 4 Four-block joint coding mapping table

[0044] Based on Tables 1-4, encoding can be completed under run-length constraints for any number of consecutive user data blocks. Furthermore, based on Tables 1-4, the 5-bit sequence patterns at the beginning of each codeword are known, specifically including 5-bit sequences starting with bit "0", as well as "10001", "10101", and "10000". These 5-bit sequences constitute clear codeword boundaries.

[0045] The following is an example.

[0046] Example 1: A method for RLL(1,4) encoding and decoding for optical storage, such as Figure 1 As shown, it includes: encoding steps; the encoding steps include: The binary user data to be stored is divided into user data blocks of 3 bits in length, resulting in a sequence of user data blocks; The user data block sequence is sequentially encoded using four-block joint encoding, three-block joint encoding, two-block joint encoding, and single-block encoding, according to the pre-established four-block joint encoding mapping table, three-block joint encoding mapping table, two-block joint encoding mapping table, and single-block encoding mapping table. By sequentially concatenating the encoded channel symbols, the encoded channel symbol sequence is obtained.

[0047] In this embodiment, the single-block encoding mapping table, the two-block joint encoding mapping table, the three-block joint encoding mapping table, and the four-block joint encoding mapping table are shown in Tables 1 to 4, respectively.

[0048] The four-block joint encoding of a user data block sequence can be performed as follows: The user data block sequence is scanned using a first sliding window of size 12 bits (i.e., the length of four user data blocks). During the scan, for each sliding window position, an attempt is made to encode the 12-bit user data in the first sliding window into a 20-bit channel symbol according to the four-block joint coding mapping table. If the encoding is successful, the first sliding window is moved forward 12 bits; if the encoding is unsuccessful, the first sliding window is moved forward 3 bits. In this way, four consecutive user data blocks that satisfy the four-block joint coding rules are encoded into 20-bit channel symbols.

[0049] The remaining user data block after four blocks of joint encoding can be combined with three blocks of joint encoding, which can be done as follows: A second sliding window of size 9 bits (i.e., the length of three user data blocks) is used to scan each consecutive user data block. During the scan, for each sliding window position, an attempt is made to encode the 9 bits of user data within the second sliding window into 15-bit channel symbols according to the three-block joint coding mapping table. If the encoding is successful, the second sliding window is moved forward 9 bits; if the encoding fails, the second sliding window is moved forward 3 bits. Thus, three consecutive user data blocks that satisfy the three-block joint coding rules are encoded into 15-bit channel symbols from the remaining user data blocks. The scanning and encoding of multiple consecutive user data blocks can be performed in parallel.

[0050] The remaining user data block after three blocks of joint encoding can be combined into two blocks using the following steps: A third sliding window of size 6 bits (i.e., the length of two user data blocks) is used to scan each consecutive user data block. During the scan, for each sliding window position, an attempt is made to encode the 6 bits of user data within the third sliding window into 10 bits of channel code according to a pre-established dual-block joint coding mapping table. If the encoding is successful, the third sliding window is moved forward 6 bits; if the encoding fails, it is moved forward 3 bits. Thus, two consecutive user data blocks that satisfy dual-block joint coding are encoded into 10 bits of channel code in the remaining user data blocks. The scanning and encoding of multiple consecutive user data blocks can be performed in parallel.

[0051] like Figure 1 As shown, this embodiment also includes: a parallel decoding step; the parallel decoding step includes: The channel symbol sequence to be decoded is divided into channel symbol blocks of length 5, resulting in a channel symbol block sequence; Traverse the channel symbol block sequence, and use the channel symbol blocks that start with bit "0" as boundaries to serialize the channel symbol blocks into multiple channel symbol segments; In parallel, the channel symbol segment is identified to start with a bit "1". If it exists, the corresponding channel symbol segment is further divided into multiple codewords based on the channel symbol segment starting with a bit "1". Otherwise, the channel symbol segment is directly used as a codeword. Based on the number of 5-bit channel symbol sequences contained in each codeword, each codeword is demapped into user data blocks in parallel according to the corresponding mapping table; By concatenating user data blocks in sequence, the decoded user data is obtained.

[0052] Figure 2 The image shows an example of parallel decoding based on the RLL(1,4) encoding / decoding method for optical storage provided in this embodiment. Figure 2 As shown, a channel symbol block sequence is obtained after dividing the data into 5-bit segments. The channel symbol block sequence is traversed, and the channel symbol blocks starting with bit "0" are used as boundaries to serialize the channel symbol blocks into multiple channel symbol segments, completing the first level of partitioning. Next, within each channel symbol segment, the codeword header starting with bit "1" is identified, dividing the channel symbol segment into multiple codewords. For channel symbol segments that do not contain other codeword headers starting with bit "1", they are directly treated as a single codeword, thus completing the second level of partitioning and obtaining multiple codewords. According to the corresponding mapping table, each codeword is demapped into user data blocks. The user data blocks are then concatenated sequentially to complete the decoding process.

[0053] As shown in Table 2, the specific decoding process allows for the direct division of all codewords based on defined codeword boundaries. Furthermore, the demapping process for each codeword is executed in parallel, fundamentally eliminating serial dependencies and significantly improving the encoding / decoding throughput. Additionally, as... Figure 3 As shown, since this embodiment eliminates serial dependency, the impact of bit errors (such as single-bit errors) within a single codeword is strictly limited to the corresponding codeword and will not propagate backward.

[0054] Overall, based on the designed deterministic block header alignment mechanism, this embodiment fundamentally eliminates serial dependency, greatly improves the throughput of encoding and decoding, effectively limits error propagation, and improves the performance and reliability of optical storage. It can effectively meet the requirements of modern AI data centers for high-concurrency reading and ultra-fast decoding of massive optical storage data.

[0055] Example 2: An RLL(1,4) encoding / decoding device for optical storage includes: an encoding module; the encoding module includes: The user data partitioning unit is used to divide the binary user data to be stored into user data blocks of 3 bits in length, so as to obtain a user data block sequence. The encoding unit is used to perform four-block joint encoding, three-block joint encoding, two-block joint encoding and single-block encoding on the user data block sequence in sequence according to the pre-established four-block joint encoding mapping table, three-block joint encoding mapping table, two-block joint encoding mapping table and single-block encoding mapping table; And a channel symbol splicing unit, used to sequentially splice the encoded channel symbols to obtain the encoded channel symbol sequence.

[0056] In this embodiment, the single-block encoding mapping table, the two-block joint encoding mapping table, the three-block joint encoding mapping table, and the four-block joint encoding mapping table are shown in Tables 1 to 4, respectively.

[0057] This embodiment also includes: a parallel decoding module; the parallel decoding module includes: The channel symbol partitioning unit is used to divide the channel symbol sequence to be decoded into channel symbol blocks of length 5 bits to obtain the channel symbol block sequence. The first boundary identification unit is used to traverse the channel symbol block sequence, take the channel symbol blocks that start with bit "0" as the boundary, and serialize the channel symbol blocks into multiple channel symbol segments. The second boundary identification unit is used to identify the channel symbol start point that starts with bit "1" in each channel symbol segment in parallel. If it exists, the corresponding channel symbol segment is further divided into multiple codewords based on the channel symbol start point that starts with bit "1"; otherwise, the channel symbol segment is directly used as a codeword. The parallel decoding unit is used to demap each codeword into user data blocks in parallel according to the number of 5-bit channel symbol sequences contained in each codeword and the corresponding mapping table. And a user data splicing unit, used to splice user data blocks in sequence to obtain decoded user data.

[0058] like Figure 4 As shown, the parallel decoding unit includes N hardware decoding channels. Each hardware decoding channel is used to input codewords from the second boundary recognition unit, demap them, and output user data blocks; as shown... Figure 5 As shown, in this embodiment, the hardware decoding channels perform codeword input, demapping, and user data block output through different hardware functional units. Furthermore, in order to further improve throughput, in this embodiment, the codeword input, demapping, and user data block output of the N hardware decoding channels are executed in a pipeline manner. Where N is a positive integer; the number of hardware decoding channels N is closely related to the final encoding and decoding throughput. In practical applications, the number of hardware decoding channels can be set according to specific performance requirements and hardware resources.

[0059] In this embodiment, the parallel decoding module further includes a front-end receiving buffer unit, used to receive and buffer a continuous channel symbol sequence.

[0060] Overall, based on the designed deterministic block header alignment mechanism, this embodiment fundamentally eliminates serial dependency, significantly improves encoding and decoding throughput, effectively limits error propagation, and enhances the performance and reliability of optical storage. It can effectively meet the requirements of modern AI data centers for high-concurrency reading and ultra-fast decoding of massive optical storage data. Furthermore, compared to traditional 17PP encoding, in this embodiment, the run length specification parameter is extremely compressed and optimized from k=7 (maximum interval of 8 clock edges) to k=4, forcing at least one charge-over-flight in each 5-symbol interval of the effective encoded stream on the channel. Therefore, the PLL in the receiving circuit can capture much higher frequency and denser homogeneous calibration lines, naturally filtering out the extremely difficult-to-handle low-frequency drift components in the signal transmission link.

[0061] Example 3: An optical storage system, comprising: an optical storage medium and an RLL(1,4) encoding / decoding device for optical storage provided in Example 2 above.

[0062] The following comparison of the performance and resource utilization of different encoding and decoding methods further explains the beneficial effects achieved by this embodiment. A diagram comparing the clock cycles consumed by different encoding and decoding methods is shown below. Figure 6 As shown in the diagram, the throughput of different encoding and decoding methods is compared. Figure 7 As shown in the diagram, the hardware resource (LUT / FF) utilization of different encoding and decoding methods is compared. Figure 8 As shown in the diagram, the energy consumption of different encoding and decoding methods is compared. Figure 9 As shown. Figures 6-9In the diagram, "Proposed17PP-Pipelined" represents a basic pipelined decoding architecture using the traditional Blu-ray standard RLL(1,7)17PP modulation and coding, implemented based on serial dependency logic. This is the traditional baseline scheme for this experiment, but it suffers from strong front-end and back-end coupling and requires look-ahead buffering. "ProposedRLL(1,4)Serial" represents a serial decoding architecture using the RLL(1,4) modulation and coding of this invention without parallel design, used to verify the performance benchmark of the new coding itself. "ProposedRLL(1,4)-Pipelined" represents a decoding architecture using the RLL(1,4) modulation and coding of this invention, with only single-channel pipeline optimization and without enabling multi-channel parallel expansion; this serves as the baseline for comparison with parallel schemes. "ProposedParallelism5" represents a parallel pipelined decoding architecture using the RLL(1,4) modulation and coding of this invention, configured with 5 independent parallel decoding channels. "ProposedParallelism10" represents a parallel pipelined decoding architecture using the RLL(1,4) modulation and coding of this invention, configured with 10 independent parallel decoding channels. "ProposedParallelism20" represents a parallel pipelined decoding architecture using the RLL(1,4) modulation and coding of this invention, configured with 20 independent parallel decoding channels. "ProposedParallelism30" represents a parallel pipelined decoding architecture using the RLL(1,4) modulation and coding of this invention, configured with 30 independent parallel decoding channels. "ProposedParallelism35" represents a parallel pipelined decoding architecture using the RLL(1,4) modulation and coding of this invention, configured with 35 independent parallel decoding channels. "ProposedParallelism40" represents a parallel pipelined decoding architecture using the RLL(1,4) modulation and coding of this invention, configured with 40 independent parallel decoding channels. Figure 8 In this context, LUT stands for Lookup Table and FF stands for Flip-Flop; both are FPGA hardware resources.

[0063] Table 5 shows a horizontal comparison of different decoding architectures (traditional 17PP pipeline, the RLL(1,4) baseline and pipeline of this invention) in terms of resource consumption (LUT / FF), processing cycles (Cycles), throughput (Gbps), and energy consumption per processing cycle (Energy), intuitively demonstrating the significant optimization of the architecture of this invention in terms of hardware overhead and decoding efficiency. Table 6 shows the comprehensive performance indicators of the RLL(1,4) pipeline decoding architecture of this invention under different parallelism (i.e., n values ​​of 5, 10, 20, 30, 35, and 40), quantitatively demonstrating the changing trends of system throughput, energy efficiency ratio (Gbps / W), and energy consumption per frame processing as the number of parallel channels increases, used to evaluate the scalability of the architecture.

[0064] Table 5

[0065] Table 6

[0066] based on Figures 6-9 As shown in Tables 5 and 6, under the same Xilinx UltraScale+ operating environment, the traditional 17PP requires approximately 40.73M total clock cycles for end-to-end processing due to complex lookup addressing, resulting in high power consumption (approximately 34.21 mJ in testing). This invention, utilizing the aforementioned pure algebraic Boolean logic derivation, not only drastically reduces the processing clock to 0.6M cycles at a single-clock 40-track open parallel scale, increasing the total end-to-end throughput to 3.0 Gbps (the internal maximum lookup parallel limit is 12.0 Gbps), but also, due to the reduced time spent in the active state, the overall logic power consumption drops to approximately 1.09 mJ, demonstrating significant green energy computation optimization. Furthermore, even if the current block is corrupted due to garbled characters and decryption errors, because the system does not record multi-layer cumulative states, the first bit of the next block, combined with the second half of the marker, allows the parsing core to instantly return to a definite starting line, successfully limiting the bit error amplification factor (ETC - Error Transmission Coefficient) to only approximately 2.7 to 3.3. This greatly reduces the computational load on backend applications (such as Low-Density Parity-Check Code LDPC) before hard decision-making.

[0067] Those skilled in the art will readily understand that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A RLL (1, 4) encoding and decoding method for optical storage, characterized by, include: Encoding steps; The encoding steps include: The binary user data to be stored is divided into user data blocks of 3 bits in length, resulting in a sequence of user data blocks; The user data block sequence is sequentially encoded using four-block joint encoding, three-block joint encoding, two-block joint encoding, and single-block encoding according to the pre-established four-block joint encoding mapping table, three-block joint encoding mapping table, two-block joint encoding mapping table, and single-block encoding mapping table; The channel symbols obtained by encoding are concatenated in sequence to obtain the encoded channel symbol sequence. The single-block coding mapping table records the one-to-one mapping relationship between seven user data blocks "000", "001", "010", "011", "100", "101", "110", and "111" and the channel symbols "10001", "00010", "01000", "00101", "00100", "01001", and "01010". For the remaining user data blocks, if their preceding channel symbol ends with a bit "1", they are mapped to the channel symbol "00001"; if their preceding channel symbol ends with a bit "0", they are mapped to the channel symbol "10101". The double-block joint coding mapping table is used to record the mapping relationship between two consecutive user data blocks that cannot be encoded according to the single-block coding mapping table under run-length constraints and the 10-bit channel symbol. The triple-block joint coding mapping table is used for... The system records the mapping relationship between three consecutive user data blocks that cannot be encoded under run-length constraints according to the single-block coding map table and the dual-block joint coding map table, and 15-bit channel symbols. The four-block joint coding map table is used to record the mapping relationship between four consecutive user data blocks that cannot be encoded under run-length constraints according to the single-block coding map table, the dual-block joint coding map table, and the triple-block joint coding map table, and 20-bit channel symbols. The run-length constraint condition is that the number of bits "0" between any two adjacent bits "1" in the channel symbol sequence is in the range of [1,4]. In the dual-block joint coding map table, the triple-block joint coding map table, and the four-block joint coding map table, the 5-bit channel symbol sequence starting with bit "0" is located at the beginning of the channel symbol, and the subsequent 5-bit channel symbol sequence is "10010" or "10100".

2. The RLL(1,4) encoding / decoding method for optical storage as described in claim 1, characterized in that, The mapping relationships recorded in the single-block encoding mapping table are as follows: "000"→"10001";"001"→"00010";"010"→"01000";"011"→"00101";"100"→"00100";"101"→"01001";"110"→"01010";When the preceding channel code ends with a bit "1", "111"→"00001";When the preceding channel code ends with a bit "0", "111"→"10101"; The mapping relationships recorded in the dual-block joint encoding mapping table are as follows: "000 000" → "01010 10100"; "010 001" → "01000 10010"; "010 100" → "0101010010"; "011 000" → "00100 10100"; "101 000" → "00100 10010"; "111 000" → "0100010100"; When the preceding channel code ends with a bit "1", "010 011" → "00010 10010"; When the preceding channel code ends with a bit "0", "010 011" → "10000 10010"; When the preceding channel code ends with a bit "1", "100 001" → "00010" "10100", when the preceding channel symbol ends with bit "0", "100 001" → "10000 10100"; The mapping relationships recorded in the three joint encoding mapping tables are as follows: "000 000 001”→"01010 10100 10100；"010 011 000”→"01000 10010 10010”；"010101 000”→"01010 10010 10010”；"011 000 001”→"01010 10100 10010”；"100 001001”→"01000 10100 10100”；"111 000 001”→"01000 10100 10010”； The mapping relationships recorded in the four joint encoding mapping tables are as follows: "000 000 001 001”→"01000 10010 10010 10010”；"100 001 001 001”→"0100010010 10100 10010”； Here, "→" indicates mapping to.

3. The RLL(1,4) encoding / decoding method for optical storage as described in claim 1 or 2, characterized in that, Also includes: Parallel decoding steps; The parallel decoding steps include: The channel symbol sequence to be decoded is divided into channel symbol blocks of length 5, resulting in a channel symbol block sequence. Traverse the channel symbol block sequence, and use the channel symbol blocks that start with bit "0" as boundaries to serialize the channel symbol blocks into multiple channel symbol segments; In parallel, the channel symbol start point starting with bit "1" is identified in each channel symbol segment. If it exists, the corresponding channel symbol segment is further divided into multiple codewords based on the channel symbol start point starting with bit "1". Otherwise, the channel symbol segment is directly used as a codeword. Based on the number of 5-bit channel symbol sequences contained in each codeword, each codeword is demapped into user data blocks in parallel according to the corresponding mapping table; By concatenating user data blocks in sequence, the decoded user data is obtained.

4. An RLL(1,4) encoding / decoding device for optical storage, characterized in that, include: Encoding module; The encoding module includes: The user data partitioning unit is used to divide the binary user data to be stored into user data blocks of 3 bits in length, so as to obtain a sequence of user data blocks; The encoding unit is used to sequentially perform four-block joint encoding, three-block joint encoding, two-block joint encoding, and single-block encoding on the user data block sequence according to a pre-established four-block joint encoding mapping table, three-block joint encoding mapping table, two-block joint encoding mapping table, and single-block encoding mapping table; And a channel symbol splicing unit, used to sequentially splice the encoded channel symbols to obtain the encoded channel symbol sequence; The single-block coding mapping table records the one-to-one mapping relationship between seven user data blocks "000", "001", "010", "011", "100", "101", "110", and "111" and the channel symbols "10001", "00010", "01000", "00101", "00100", "01001", and "01010". For the remaining user data blocks, if their preceding channel symbol ends with a bit "1", they are mapped to the channel symbol "00001"; if their preceding channel symbol ends with a bit "0", they are mapped to the channel symbol "10101". The double-block joint coding mapping table is used to record the mapping relationship between two consecutive user data blocks that cannot be encoded according to the single-block coding mapping table under run-length constraints and the 10-bit channel symbol. The triple-block joint coding mapping table is used for... The system records the mapping relationship between three consecutive user data blocks that cannot be encoded under run-length constraints according to the single-block coding map table and the dual-block joint coding map table, and 15-bit channel symbols. The four-block joint coding map table is used to record the mapping relationship between four consecutive user data blocks that cannot be encoded under run-length constraints according to the single-block coding map table, the dual-block joint coding map table, and the triple-block joint coding map table, and 20-bit channel symbols. The run-length constraint condition is that the number of bits "0" between any two adjacent bits "1" in the channel symbol sequence is in the range of [1,4]. In the dual-block joint coding map table, the triple-block joint coding map table, and the four-block joint coding map table, the 5-bit channel symbol sequence starting with bit "0" is located at the beginning of the channel symbol, and the subsequent 5-bit channel symbol sequence is "10010" or "10100".

5. The RLL(1,4) codec for optical storage as described in claim 4, characterized in that, The mapping relationships recorded in the single-block encoding mapping table are as follows: "000"→"10001";"001"→"00010";"010"→"01000";"011"→"00101";"100"→"00100";"101"→"01001";"110"→"01010";When the preceding channel code ends with a bit "1", "111"→"00001";When the preceding channel code ends with a bit "0", "111"→"10101"; The mapping relationships recorded in the dual-block joint encoding mapping table are as follows: "000 000" → "01010 10100"; "010 001" → "01000 10010"; "010 100" → "0101010010"; "011 000" → "00100 10100"; "101 000" → "00100 10010"; "111 000" → "0100010100"; When the preceding channel code ends with a bit "1", "010 011" → "00010 10010"; When the preceding channel code ends with a bit "0", "010 011" → "10000 10010"; When the preceding channel code ends with a bit "1", "100 001" → "00010" "10100", when the preceding channel symbol ends with bit "0", "100 001" → "10000 10100"; The mapping relationships recorded in the three joint encoding mapping tables are as follows: "000 000 001”→"01010 10100 10100”；"010 011 000”→"01000 10010 10010”；"010 101 000”→"01010 10010 10010”；"011 000 001”→"01010 10100 10010”；"100001 001”→"01000 10100 10100”；"111 000 001”→"01000 10100 10010”； The mapping relationships recorded in the four joint encoding mapping tables are as follows: "000 000 001 001”→"01000 10010 10010 10010”；"100 001 001 001”→"0100010010 10100 10010”； Here, "→" indicates mapping to.

6. The RLL(1,4) codec for optical storage as described in claim 4 or 5, characterized in that, Also includes: Parallel decoding module; The parallel decoding module includes: The channel symbol partitioning unit is used to divide the channel symbol sequence to be decoded into channel symbol blocks of length 5 bits to obtain the channel symbol block sequence. The first boundary identification unit is used to traverse the channel symbol block sequence, take the channel symbol blocks that start with bit "0" as the boundary, and serialize the channel symbol blocks into multiple channel symbol segments. The second boundary identification unit is used to identify the channel symbol start point that starts with bit "1" in each channel symbol segment in parallel. If it exists, the corresponding channel symbol segment is further divided into multiple codewords based on the channel symbol start point that starts with bit "1"; otherwise, the channel symbol segment is directly used as a codeword. The parallel decoding unit is used to demap each codeword into user data blocks in parallel according to the number of 5-bit channel symbol sequences contained in each codeword and the corresponding mapping table. And a user data splicing unit, used to splice user data blocks in sequence to obtain decoded user data.

7. The RLL(1,4) codec for optical storage as described in claim 6, characterized in that, The parallel decoding unit includes n hardware decoding channels. Each hardware decoding channel is used to input codewords from the second boundary recognition unit, demap them, and output user data blocks. The codeword input, demapping, and user data block output of the n hardware decoding channels are executed in a pipeline manner. Where n is a positive integer.

8. The RLL(1,4) codec for optical storage as described in claim 6, characterized in that, The parallel decoding module further includes a front-end receiving buffer unit for receiving and buffering continuous channel symbol sequences.

9. An optical storage system, characterized in that, include: Optical storage medium and the RLL(1,4) encoding / decoding apparatus for optical storage as described in any one of claims 4 to 8.

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