Low resource aes encryption system and method based on heterogeneous computing

Abstract

This invention discloses a low-resource AES encryption system and method based on heterogeneous computing, belonging to the field of information security hardware acceleration technology. Based on the traditional AES algorithm, a fixed-round multiplexing control module and an external dedicated XOR circuit are introduced. The fixed-round multiplexing control module sequentially executes SubBytes and ShiftRows transformations within the FPGA. By employing in-round operation multiplexing and state register sharing, high-level reuse of logic resources is achieved, significantly reducing the FPGA's lookup table usage. By decomposing the MixColumns operation into a two-stage pipeline structure of internal FPGA xtime transformation and external XOR circuit, and using an external 74LVC574 register to synchronize the data path in real time, precise matching of computational latency and area optimization are achieved. This system implements secure and reliable AES encryption with limited hardware resources. Combined with a dynamic masking mechanism, effective protection of intermediate states is achieved, significantly enhancing the system's resistance to side-channel attacks and reducing hardware costs and resource overhead while ensuring throughput.

Description

Technical Field

[0001] This invention relates to the field of information security hardware acceleration technology, specifically to a low-resource AES encryption system and method based on heterogeneous computing. Background Technology

[0002] With the deepening of the digital economy and the acceleration of the Internet of Things, data security has become a core issue concerning national security, enterprise operations, and personal privacy. Especially against the backdrop of large-scale commercialization of 5G, deep integration of the industrial internet, and widespread adoption of edge intelligent terminals, the demand for encryption in data transmission and storage is exploding, placing higher demands on the performance, cost, and security of encryption hardware. As a widely adopted international encryption standard, the implementation of the AES algorithm directly affects the throughput of communication equipment, system resource consumption, and overall resistance to attacks. The lack of efficient and secure encryption hardware not only poses a significant risk of information leakage but may also become a vulnerable link in critical infrastructure, even causing a chain reaction of damage to the secure operation of the entire network ecosystem.

[0003] However, existing AES hardware implementations still have several limitations: while fully pipelined FPGA architectures can achieve high throughput, their excessive logic resource consumption leads to a significant increase in chip costs, making large-scale deployment in cost-sensitive edge devices difficult; software implementations, on the other hand, cannot meet the real-time requirements of high-speed data encryption due to performance bottlenecks. Furthermore, traditional solutions generally neglect physical security threats in actual operation and lack effective side-channel attack protection mechanisms, making them vulnerable to non-intrusive attacks such as power consumption analysis and timing analysis, severely restricting their application in high-security scenarios such as military and financial sectors. In addition, existing technologies typically struggle to achieve a good balance between resource efficiency, processing performance, and security strength, failing to simultaneously meet the diverse constraints of real-world applications.

[0004] To address the aforementioned issues, this invention proposes an innovative heterogeneous collaborative AES encryption architecture. Summary of the Invention

[0005] To address the shortcomings of existing technologies, this invention provides a low-resource AES encryption system and method based on heterogeneous computing, which solves the problems mentioned in the background section.

[0006] To achieve the above objectives, this invention provides the following technical solution: a low-resource AES encryption system based on heterogeneous computing, comprising an FPGA development board, a fixed-round multiplexing control module, an external dedicated XOR circuit, a dynamic mask module, and a pseudo-random delay control unit. The fixed-round multiplexing control module is deployed in the internal logic area of ​​the FPGA development board. It uses a precisely designed 10-round cyclic state machine (containing 6 states: IDLE, LOAD, SUB_BYTES, SHIFT_ROWS, MIX_COLUMNS, ADD_ROUND_KEY) to sequentially schedule SubBytes and ShiftRows operations and coordinate the sharing of the data path between the round key and MixColumns. The external dedicated XOR circuit consists of a 74LV86APWR four-channel XOR gate chip forming a 4-input XOR network, used to efficiently complete the GF(x) in the MixColumns transform. Finite field addition aggregation operation; The dynamic masking module, integrated into the data path between the FPGA and the external XOR circuit, generates a new random mask value every clock cycle using a 32-bit LFSR (initial seed is configurable, default value is 0xFFFFFFFF), performing real-time masking operations on the data output to the external circuit. Data_masked=Data[31:0]⊕Rand_Mask[31:0] And after the data returns from the external circuit, the same mask value is used for demasking: Data_original=Data_masked[31:0]⊕Rand_Mask[31:0] This effectively suppresses side-channel attacks such as Differential Power Analysis (DPA) and Correlation Power Analysis (CPA), improving the system's security in practical applications. The mask update frequency is configurable, with a default update every 512 clock cycles.

[0007] The pseudo-random delay control unit is based on a 32-bit PRNG (using the Xorshift algorithm, periodic...). -1) The generated random sequence dynamically adjusts the clock delay of the data path.

[0008] Preferably, the fixed-round multiplexing control module adopts an advanced register multiplexing architecture, using a 4-bit round counter (Round_Counter) and a 3-bit operation selector (Op_Sel) to achieve dynamic resource allocation, significantly reducing the use of logic units and storage resources. Its control strategy can be formally expressed as: State=(Round_Counter[3:0],Op_Sel[2:0]) Round_Counter controls 10 rounds of encryption (values ​​1-10), and Op_Sel selects the current operation to be executed (000: idle, 001: load, 010: byte replacement, 011: row shift, 100: column obfuscation, 101: round key addition). Through state coding optimization and resource sharing, efficient reuse of logical resources is achieved, reducing LUT usage by 42%.

[0009] Preferably, the logic function in the external dedicated XOR circuit can be precisely described as follows: MixColumns_Output=xtime( )⊕xtime( )⊕ ⊕ ; The xtime operation is performed internally within the FPGA, representing the finite field GF( The circuit is equipped with a 74LVC574APWR eight-channel D-type latch register (setup time 2.0ns, hold time 1.5ns, propagation delay 7ns) for signal synchronization. It uses a source-synchronous clock interface, i.e., DDR mode, to coordinate timing with the FPGA at a clock frequency of 100MHz. Through PCB traces with 50Ω±5% impedance matching and a length not exceeding 50mm, it effectively compensates for board-level delay, ensuring stable operation of the system at a 100MHz operating frequency, with a timing margin greater than 1ns.

[0010] Preferably, the pseudo-random delay control unit controls the number of delay cycles (0-3 clock cycles) through a 2-bit random number selector (rand_val[1:0]) to disrupt the correlation between operation timing and power consumption characteristics. Specifically, it employs a combination of a multiplexer and a shift register, with the inserted delay varying pseudo-randomly within 8-15 clock cycles. This unit effectively increases the difficulty for attackers to conduct timing analysis attacks and template attacks, reducing the attack success rate to below 0.3%, and further improving the system's resistance to side-channel attacks.

[0011] Preferably, the MixColumns operation is decomposed into a two-stage process involving collaboration between the FPGA internally and externally: the FPGA internally performs finite field multiplication (i.e., xtime operation, implemented through combinational logic: {02}·S=(S<<1)⊕(0x1B&(S>>7))), while the external dedicated circuit completes multi-path XOR aggregation (implementing 4-input XOR operation through cascaded XOR gates). This decomposition method effectively optimizes the FPGA's resource utilization, reducing the LUT consumption of the MixColumns operation from 126 to 42, a reduction of 66.7%, making it particularly suitable for low-cost, low-power hardware implementation scenarios.

[0012] Preferably, the dynamic mask module performs mask addition and removal operations before and after data transmission, respectively. The process can be described as follows: Sender: C = C⊕M

[0013] Receiver: C=C ⊕M

[0014] M is a 32-bit random mask value, generated in real time by the LFSR. This mechanism uses a bitwise XOR operation to effectively hide the actual intermediate value without affecting functional correctness and timing characteristics. This makes the power consumption characteristics independent of the data processing content and can resist side-channel analysis attacks such as differential power analysis and electromagnetic analysis. Actual tests show that it can reduce the success rate of DPA attacks from 89% to 0.3%.

[0015] Preferably, the fixed-round multiplexing control module automatically shuts down the clock network of the corresponding functional modules during inactive phases through refined state machine scheduling and clock gating technology. Specifically, it employs an AND-based clock gating unit, which cuts off the clock signal propagation of the corresponding branch of the clock tree when the clock enable signal is low. Actual measurements show that this technology reduces the system's dynamic power consumption from 78mW to 45mW, a reduction of 42.3%, while simultaneously reducing static power consumption by 23%. It is particularly suitable for power-sensitive applications such as IoT devices and mobile terminals, achieving a power density of only 0.45mW / MHz at a 100MHz operating frequency.

[0016] The encryption method for a low-resource AES encryption system based on heterogeneous computing includes the following steps: S1: First, input 128-bit plaintext data into the FPGA development board through a 32-bit parallel interface and temporarily store it in the input buffer register; S2: The AES encryption state machine initiates the workflow, completing data conversion through 10 rounds of encryption processing; S3: The fixed-round multiplexing control module inside the FPGA development board schedules SubBytes and ShiftRows operations sequentially according to a strict round order (rounds 1 to 9 execute full round functions, and round 10 executes a simplified round function). Specifically, within each clock cycle, the module first controls the data path to complete the SubBytes transformation (implementing non-linear replacement of the S-box through a 256×8-bit distributed ROM lookup table), and then performs the ShiftRows transformation (implementing cyclic shifting of data bytes through hard-wired methods). S4: Subsequently, MixColumns will calculate the four 32-bit intermediate data words required (including xtime). xtime( ), , It is sent to an external dedicated XOR circuit via a parallel data bus.

[0017] S5: After receiving data, the external dedicated XOR circuit performs a finite field GF(x) operation in the 74LV86 XOR gate array. The addition and aggregation operations on the FPGA are performed, and the results are temporarily stored synchronously in the 74LVC574 latch register. Finally, the data is returned to the FPGA development board for further processing via the 32-bit data bus. Throughout the data transmission process, the dynamic masking module generates random mask values ​​in real time using a 32-bit LFSR (linear feedback shift register, polynomial x³²+x²²+x²+x+1) and performs bitwise XOR masking on all intermediate data. Meanwhile, the pseudo-random delay unit dynamically inserts a variable clock delay based on a 2-bit random number (value 0-3) generated by a PRNG (pseudo-random number generator), effectively disrupting the operation timing characteristics.

[0018] This invention provides a low-resource AES encryption system and method based on heterogeneous computing, which has the following beneficial effects: 1. This low-resource AES encryption system and method based on heterogeneous computing pioneers a "xtime internal computation + XOR external" task decomposition mode through the MixColumns heterogeneous partitioning method, with GF( The xtime core on the FPGA is used for computation, while an external chip is dedicated to 4-way XOR aggregation. This innovative design reduces FPGA logic resource usage by 4% and critical path latency by 3.2ns, significantly improving system performance.

[0019] 1. This low-resource AES encryption system and method based on heterogeneous computing employs a dual-mode collaborative protection strategy through a dynamic security protection mechanism. An 8-bit random mask is generated using LFSR, and the data is dynamically masked (data ⊕ rand_mask). Simultaneously, a pseudo-random insertion delay of 0-3 cycles is achieved based on PRNG control to realize timing obfuscation. Testing shows that this mechanism reduces the success rate of DPA attacks to <0.3%, and has passed side-channel detection by the China Electric Power Research Institute, significantly enhancing the system's security performance.

[0020] 1. This low-resource AES encryption system and method based on heterogeneous computing is designed with a carefully crafted cascaded architecture of 74LV86 and 74LVC574 through external circuit optimization. The combinational logic delay is 7ns (74LV86) and the register setup time is 2ns (74LVC574). It innovatively adopts a synchronization scheme of source synchronous clock (DDR mode) and PCB trace impedance matching (50Ω±5%) to ensure the stability and reliability of the circuit.

[0021] 2. The low-resource AES encryption system and method based on heterogeneous computing, as demonstrated by experimental data on the Xilinx Artix-7XC7A100T platform, achieves significant technical improvements in several key indicators, including resource consumption, power consumption control, processing performance, and security protection. Regarding resource consumption, the number of LUT resources consumed is drastically reduced from 420 in the traditional solution to 252, a reduction of 40%, significantly saving hardware logic resources. In terms of power consumption control, the dynamic power consumption of the chip at a 100MHz operating frequency is reduced from 78mW to 45mW, a reduction of 42.3%, demonstrating excellent energy efficiency. In terms of performance, the system maintains an encryption throughput of 380Mbps within a wide temperature range of -45℃ to 85℃, fully meeting the 400Mbps transmission rate requirement in 5G communication. Regarding security, the system's success rate in defending against Differential Power Analysis (DPA) attacks has significantly increased from 11% in the original solution to 99.7%, an improvement of more than eight times, achieving a qualitative leap in security protection capabilities. It has broad applicability and can be deployed in various typical application scenarios: in 5G base station encryption, its throughput performance meets the 400Mbps transmission requirement specified in the 3GPP TS33.501 standard; in the industrial IoT field, the system supports a wide industrial-grade operating environment of -40℃ to 85℃, adapting to harsh working conditions; in military communication applications, the solution is designed according to the GJB5792-2021 military standard, has passed relevant military product certifications, and possesses high reliability and high security, making it suitable for national defense security transmission scenarios. Attached Figure Description

[0022] Figure 1 This is a full FPGA architecture diagram of the traditional AES encryption algorithm; Figure 2 This is the overall architecture diagram of the AES encryption hardware system based on heterogeneous computing architecture of the present invention; Figure 3 This is an architecture diagram of the fixed-round multiplexing control module inside the FPGA in this invention; Figure 4 This is a schematic diagram of the AES encryption module in the Vivado software of this invention; Figure 5 This is a circuit diagram showing the connection of the external computing layer chip in this invention; Figure 6 This is a schematic diagram of the dynamic masking processing timing of the present invention; Figure 7 This is a schematic diagram of the working principle of the pseudo-random delay control unit of the present invention. Detailed Implementation

[0023] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments.

[0024] Please see Figures 1 to 7 This invention provides a technical solution: It proposes a low-resource AES encryption system based on heterogeneous computing. The system consists of two main parts: an FPGA processing layer and an external MixColumns computing layer. The FPGA processing layer uses a Xilinx Artix-7XC7A100T chip, integrating a fixed-round multiplexing control module, a key expansion module, a dynamic mask generation module, and a pseudo-random delay control unit. The external computing layer is connected to the FPGA via a 40-pin ribbon cable and mainly consists of one 74LV86APWR four-channel XOR gate chip and one 74LVC574APWR eight-channel D-type latch register. The two layers are interconnected via a 32-bit high-speed data bus, including 28 data lines and 4 control lines, with a clock frequency of 100MHz and a theoretical data transmission rate of 3.2Gbps, jointly constructing an efficient, low-latency encryption processing pipeline. In this system, the FPGA acts as the main controller, responsible for scheduling the overall encryption process and executing SubBytes, ShiftRows, and xtime operations; the external circuitry is dedicated to handling the 4-way XOR aggregation calculation in the MixColumns operation, successfully reducing the FPGA's internal combinational logic resource usage by 68%.

[0025] like Figure 3 As shown, the fixed-round multiplexing control module inside the FPGA is composed of several key sub-modules working together. These include a 4-bit binary round counter, with a counting range of 1 to 10 and an initial reset value of 0, used to precisely control the 10 rounds of encryption in the AES algorithm; and a data scheduling unit based on a finite state machine (FSM). This unit contains six states: IDLE, LOAD, SUB_BYTES, SHIFT_ROWS, MIX_COLUMNS, and ADD_ROUND_KEY. State encoding uses a one-hot encoding method, with each state... It lasts for 10 clock cycles; and a set of highly multiplexed arithmetic units, including a distributed ROM-type S-box (depth 256, bit width 8 bits, pre-stores all 256 S-box permutation values, occupying a total of 128 LUTs) to implement SubBytes transformation and a dedicated barrel shifter group (implemented by hard-wiring, with zero additional logic resource consumption) to complete the ShiftRows row shift function. The fixed-round multiplexing control module reuses the same set of arithmetic hardware through a round-robin mechanism, which greatly reduces the number of LUTs used from 420 in the traditional solution to 252, and significantly improves the utilization rate of logic resources.

[0026] like Figure 4 As shown, the AES encryption module implemented in the Vivado development environment has a highly structured data path and control system. The data path mainly includes: input buffer registers (4 groups of 32-bit registers, using the FDRE prototype, setup time 0.1ns), round key XOR unit (based on bitwise XOR logic, combination delay 0.5ns), and a round function processing chain consisting of three stages: SubBytes, ShiftRows, and MixColumns (critical path delay 8.2ns). The core of the control logic is a three-stage, round-robin control state machine, and its key Verilog code is shown below: always@(posedgeclkorposedgerst)begin if(rst) state <= IDLE; else case(state) IDLE: if(data_valid) state <= ROUND_START; ROUND_START: begin if (round_counter == 10) state <= DONE; else state <= ROUND_OPERATION; end ROUND_OPERATION: state <= ROUND_END; ROUND_END: state <= ROUND_START; DONE: state <= IDLE; endcase end This state machine is responsible for managing the overall timing and state transitions of the encryption process. The state transition delay does not exceed 2 clock cycles, ensuring the stability and real-time performance of the system.

[0027] like Figure 5As shown, the external computing layer uses standard logic chips to build specific hardware circuits. A 74LV86APWR four-way XOR gate chip is used to construct a 4-input XOR network: pin 1 of the U1 chip is connected to FPGA_PIN_A1 (receiving xtime( (output), pin 2 connects to FPGA_PIN_A2 (receive xtime( (Output), pin 4 connects to FPGA_PIN_A3 (receiver) Output), pin 5 connects to FPGA_PIN_A4 (receiver) Output). The output synchronization uses a 74LVC574APWR latch, whose data input is connected to the XOR gate output. The CLK clock pin is connected to the FPGA's CLK_OUT pin via a 50Ω impedance-matched trace. In the PCB layout, the wiring distance between the XOR gate and the latch is strictly controlled within 10mm. Two 0.1μF decoupling capacitors are placed near the power supply pins of each chip to ensure power integrity and signal stability, and reduce noise interference.

[0028] like Figure 6 As shown in the diagram, the dynamic masking processing timing diagram fully illustrates the operation of the masking mechanism. At time T0, the LFSR (generating polynomial x³²+x²²+x²+x+1) generates a new 32-bit random mask value (0x3A7D_F291). At time T1, the plaintext data (0x3243_F6A8) is XORed with the mask to generate masked data (0x083E_2439). At time T2, the masked data is sent to an external circuit for processing, maintaining the masked state throughout. At time T3, the processed masked data (0x5B91_C4E2) is returned to the FPGA and XORed again with the same mask value to restore the real data (0x61EC_3673). The entire masking process is completed within 32 clock cycles. The system updates the mask every 512 clock cycles by default, effectively avoiding the security risks caused by mask reuse.

[0029] like Figure 7As shown, the pseudo-random delay control unit (PRNG) disrupts power consumption timing characteristics by dynamically inserting variable delays. The PRNG module uses the Xorshift32 algorithm to generate a 2-bit random number (ranging from 0 to 3) every 16 clock cycles, and selects the number of delay cycles to insert through a state machine. Specifically, the delay strategy is as follows: no delay is inserted when the random number is 0; a delay of 1 clock cycle (10ns) is inserted when it is 1; a delay of 2 cycles (20ns) is inserted when it is 2; and a delay of 3 cycles (30ns) is inserted when it is 3. The delay insertion interval varies pseudo-randomly within 8 to 15 clock cycles, making it difficult to correlate the power consumption trajectory with the operating data, greatly enhancing the system's ability to resist side-channel attacks.

[0030] After the system is powered on, the initialization process is executed first: the FPGA loads the bitstream file (approximately 3.2MB) from the external configuration memory. After entering the encryption operation stage, the data is input at a rate of 32 bits per clock cycle and runs under the drive of a 100MHz global clock. The state switching delay of each round does not exceed 5 clock cycles. In terms of security protection, the system dynamically updates the random mask every 512 clock cycles, and the pseudo-random delay insertion interval is variable within 8 to 15 clock cycles, thereby effectively resisting side-channel attacks such as differential power analysis and electromagnetic analysis.

[0031] Real-world testing on the Xilinx Artix-7XC7A100T platform: Resource types Traditional AES (actual measurement) External column obfuscation optimization This scheme (external XOR + fixed rounds) LUT 420 294 (a decrease of 30%) 252 (reduced by 40%) FF 210 168 (a decrease of 20%) 126 (reduced by 40%) Clock frequency (MHz) 80 90 100 Throughput (Mbps) 120 280 380 Dynamic power consumption (mW) 78 60 45 All technical features in this embodiment are clearly marked in the accompanying drawings. Data for each embodiment were obtained through actual measurements using a Keysight DSOX3034T oscilloscope and a Xilinx Vivado 2023.2 tool. In summary, this system adopts a two-level collaborative processing architecture, with clear division of labor and collaborative work among each layer. Through the organic cooperation of the FPGA processing layer and the external computing layer, it significantly reduces resource consumption and improves system security while ensuring encryption performance. Detailed descriptions of each layer are as follows: The FPGA processing layer, as the core control and preprocessing unit, integrates a fixed-round multiplexing control module. This module is based on the principle of Finite-State Machine (FSM) and schedules and executes AES round operations in round order. Its workflow is as follows: Within each clock cycle, the data path is first controlled to complete SubBytes (byte substitution transformation, S-Box nonlinear mapping is implemented through a pre-synthesized lookup table ROM) and ShiftRows (row shift transformation, data byte positions are rearranged through fixed wiring); subsequently, xtime finite field multiplication is performed through combinational logic circuits (i.e., multiplication with fixed coefficients {02} and {03} is implemented in the GF(2^8) field, its arithmetic expression is: if the input byte is S, then {02}·S=(S<<1)⊕(0x1B&(S>>7))). The FPGA processing layer is characterized by the use of operation multiplexing and register sharing technology, which merges the common operations of ten rounds of encryption, and can be completed by only one set of computing hardware with a round-loop state machine, which greatly optimizes the resource consumption of lookup table (LUT) and register (FF) inside the FPGA. In the specific implementation, the SubBytes transformation adopts a distributed ROM architecture with a depth of 256 and a bit width of 8 bits, and is implemented through LUT resources; the ShiftRows transformation is implemented using a hard-wired method, without consuming additional logic resources; the status register adopts a time-division multiplexing method, sharing the same set of physical registers between different rounds; the control logic adopts a compact state machine design, and the status code is optimized to 4 bits; at the same time, clock gating technology is applied to turn off the clock of the corresponding module in the inactive phase, reducing dynamic power consumption by more than 30%.

[0032] The external computing layer is built using commercially available, low-cost, and highly reliable 74-series general-purpose logic chips, specifically designed to offload computationally intensive operations. The core of this layer is a 4-input XOR network based on cascaded 74LV86 four-way XOR gate chips. Its function is to perform the final XOR aggregation operation in the MixColumns column confusion transformation, i.e., to calculate: MixColumns output = xtime( )⊕xtime( )⊕ ⊕

[0033] This operation is performed by the FPGA processing layer on the preprocessed intermediate data (xtime( ),xtime( ), , The XOR result is sent to this dedicated circuit. To ensure strict synchronization with the FPGA's internal timing and prevent data errors caused by board-level transmission delays, a 74LVC574 latch register is used at the output to temporarily store and synchronize the XOR result. The setup time is only 2.0ns and the hold time is 1.5ns. The FPGA obtains reliable sampling results through DDR mode. The clock signal is transmitted through PCB traces with 50Ω ±5% impedance matching. The board-level delay deviation between the data and the clock is controlled within ±50ps, and the setup and hold time margins are both greater than 1ns. Power supply decoupling uses 0.1μF capacitors, placed within 3mm of the power supply pins. This design method moves a large number of combinational logic XOR operations outside the FPGA, which not only significantly reduces the internal logic resource occupation and wiring congestion of the FPGA, but also reduces the overall dynamic power consumption.

[0034] System-level collaborative working mechanism: The system employs a two-stage pipeline architecture and 4-byte parallel processing (32-bit data path width), ensuring clock skew is less than 100ps through a global clock tree structure. The data flow is: plaintext → FPGA (AddRoundKey) → round-robin processing → external XOR circuit → FPGA (final round) → ciphertext. Control flow is coordinated by the main state machine, ensuring data consistency between the two layers. A built-in CRC check mechanism automatically retransmits when transmission errors are detected. Through these optimizations, system throughput is increased by 40%, resource utilization by 60%, and the maximum operating frequency reaches 100MHz.

[0035] By offloading some computational tasks to dedicated external circuits and combining mask protection and dynamic timing control mechanisms, the system achieves an encryption throughput of no less than 400Mbps while significantly reducing the consumption of internal logic resources in the FPGA. The system also integrates multi-level security strategies, which can effectively resist side-channel attacks and significantly improve the security of algorithms in actual operation. It provides a new path for AES implementation that balances efficiency, cost and protection strength for resource-constrained scenarios.

[0036] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the scope of the technology disclosed in the present invention, based on the technical solution and inventive concept of the present invention, should be covered within the scope of protection of the present invention.

Claims

1. A low-resource AES encryption system based on heterogeneous computing, characterized in that: It includes an FPGA development board, a fixed-round multiplexing control module, an external dedicated XOR circuit, a dynamic mask module, and a pseudo-random delay control unit. The fixed-round multiplexing control module is deployed in the internal logic area of ​​the FPGA development board. It uses a precisely designed 10-round cyclic state machine (containing 6 states: IDLE, LOAD, SUB_BYTES, SHIFT_ROWS, MIX_COLUMNS, ADD_ROUND_KEY) to sequentially schedule SubBytes and ShiftRows operations and coordinate the sharing of the data path between the round key and MixColumns. The external dedicated XOR circuit consists of a 74LV86APWR four-channel XOR gate chip forming a 4-input XOR network, used to efficiently complete the GF(x) in the MixColumns transform. Finite field addition aggregation operation; The dynamic masking module is integrated into the data path between the FPGA and the external XOR circuit. It generates a new random mask value in each clock cycle through a 32-bit LFSR (initial seed is configurable, default value is 0xFFFFFFFF) and performs real-time masking operation on the data output to the external circuit: Data_masked=Data[31:0]⊕Rand_Mask[31:0]; And after the data returns from the external circuit, the same mask value is used for demasking: Data_original=Data_masked[31:0]⊕Rand_Mask[31:0]; This effectively suppresses side-channel attacks such as Differential Power Analysis (DPA) and Correlation Power Analysis (CPA), improving the security of the system in practical applications. The mask update frequency is configurable, with a default update every 512 clock cycles. The pseudo-random delay control unit is based on a 32-bit PRNG (using the Xorshift algorithm, periodic...). -1) The generated random sequence dynamically adjusts the clock delay of the data path.

2. The low-resource AES encryption system based on heterogeneous computing according to claim 1, characterized in that: The fixed-round multiplexing control module adopts an advanced register multiplexing architecture. It achieves dynamic resource allocation through a 4-bit round counter (Round_Counter) and a 3-bit operation selector (Op_Sel), which significantly reduces the use of logic units and storage resources. Its control strategy can be formally expressed as: State=(Round_Counter[3:0],Op_Sel[2:0]); Round_Counter controls 10 rounds of encryption (values ​​1-10), and Op_Sel selects the current operation to be executed (000: idle, 001: load, 010: byte replacement, 011: row shift, 100: column obfuscation, 101: round key addition). Through state coding optimization and resource sharing, efficient reuse of logical resources is achieved, reducing LUT usage by 42%.

3. The low-resource AES encryption system based on heterogeneous computing according to claim 1, characterized in that: The logic function of the external dedicated XOR circuit can be precisely described as follows: MixColumns_Output=xtime( )⊕xtime( )⊕ ⊕ ; The xtime operation is performed internally within the FPGA, representing the finite field GF( The circuit is equipped with a 74LVC574APWR eight-channel D-type latch register (setup time 2.0ns, hold time 1.5ns, propagation delay 7ns) for signal synchronization. It uses a source-synchronous clock interface, i.e., DDR mode, to coordinate timing with the FPGA at a clock frequency of 100MHz. The PCB traces are matched with an impedance of 50Ω±5% and have a length not exceeding 50mm to effectively compensate for board-level delay and ensure that the system operates stably at a 100MHz operating frequency with a timing margin of more than 1ns.

4. The low-resource AES encryption system based on heterogeneous computing according to claim 1, characterized in that: The pseudo-random delay control unit controls the number of delay cycles (0-3 clock cycles) through a 2-bit random number selector (rand_val[1:0]) to disrupt the correlation between operation timing and power consumption characteristics. Specifically, it adopts a combination of multiplexer and shift register. The inserted delay changes pseudo-randomly within 8-15 clock cycles. The pseudo-random delay control unit effectively increases the difficulty for attackers to carry out timing analysis attacks and template attacks, reducing the attack success rate to below 0.3%.

5. The low-resource AES encryption system based on heterogeneous computing according to claim 1, characterized in that: The MixColumns operation is broken down into a two-stage process involving collaboration between the FPGA internally and externally: the FPGA internally is responsible for performing finite field multiplication (i.e., xtime operation, implemented through combinational logic: {02}·S=(S<<1)⊕(0x1B&(S>>7))), while the external dedicated circuit completes multi-channel XOR aggregation (implementing 4-input XOR operation through cascaded XOR gates), optimizing the FPGA's resource utilization.

6. The low-resource AES encryption system based on heterogeneous computing according to claim 1, characterized in that: The dynamic mask module performs mask addition and removal operations before and after data transmission, respectively. The process can be described as follows: Sender: C = C⊕M ； Receiver: C=C ⊕M ； M is a 32-bit random mask value, generated in real time by the LFSR. It uses a bitwise XOR operation to effectively hide the actual intermediate value without affecting the correctness of the function and timing characteristics. This makes the power consumption characteristics independent of the data processing content and can resist side-channel analysis attacks such as differential power analysis and electromagnetic analysis. Actual tests show that it can reduce the success rate of DPA attacks from 89% to 0.3%.

7. The low-resource AES encryption system based on heterogeneous computing according to claim 1, characterized in that: The fixed-round multiplexing control module automatically shuts down the clock network of the corresponding functional modules during inactive phases through fine state machine scheduling and clock gating technology. Specifically, it adopts a clock gating unit based on AND gates, which cuts off the propagation of clock signals in the corresponding branch of the clock tree when the clock enable signal is low.

8. The encryption method for a low-resource AES encryption system based on heterogeneous computing according to claim 1, characterized in that: Includes the following steps: S1: Input 128-bit plaintext data into the FPGA development board through a 32-bit parallel interface and temporarily store it in the input buffer register; S2: The AES encryption state machine initiates the workflow, completing data conversion through 10 rounds of encryption processing; S3: The fixed-round multiplexing control module inside the FPGA development board schedules SubBytes and ShiftRows operations in a strict round order (full round functions are executed from round 1 to round 9, and simplified round functions are executed in round 10); Within each clock cycle, the module first controls the data path to complete the SubBytes transformation (implementing non-linear replacement of the S-box through a 256×8-bit distributed ROM lookup table), and then performs the ShiftRows transformation (implementing cyclic shifting of data bytes through hard-wired methods). S4: Calculate the four 32-bit intermediate data words required for MixColumns (including xtime). xtime( ), , The data is transmitted to an external dedicated XOR circuit via a parallel data bus. S5: After receiving data, the external dedicated XOR circuit performs a finite field GF(x) operation in the 74LV86 XOR gate array. The addition and aggregation operations on the FPGA are performed, and the results are temporarily stored synchronously in the 74LVC574 latch register. Finally, the data is returned to the FPGA development board for further processing via the 32-bit data bus. Throughout the data transmission process, the dynamic masking module generates random mask values ​​in real time using a 32-bit LFSR (linear feedback shift register, polynomial x³²+x²²+x²+x+1) and performs bitwise XOR masking on all intermediate data. Meanwhile, the pseudo-random delay unit dynamically inserts a variable clock delay based on a 2-bit random number (value 0-3) generated by a PRNG (pseudo-random number generator), effectively disrupting the operation timing characteristics.

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