Serdes adaptive equalization configuration method and device based on channel loss
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-04-02
- Publication Date
- 2026-07-03
Smart Images
Figure CN122339903A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of SerDes design, and more particularly to a SerDes adaptive equalization configuration method and apparatus based on channel loss. Background Technology
[0002] With the explosive growth of big data, cloud computing and artificial intelligence applications, the demand for high-speed interconnect bandwidth in data centers has increased dramatically, and the channel rate of high-speed serial transceivers (SerDes) has reached 56G, 112G and even 224Gbps.
[0003] During high-frequency signal transmission, due to factors such as the skin effect and dielectric loss, signals experience severe inter-symbol interference (ISI) and jitter after passing through transmission media (i.e., channels) such as PCB traces, backplanes, and cables. To recover the signal, the SerDes receiver (RX) typically integrates multiple equalization techniques, including: CTLE (Continuous Time Linear Equalizer) to compensate for high-frequency attenuation; VGA (Variable Gain Amplifier) to adjust the signal amplitude; FFE (Forward Feedback Equalizer) to eliminate predetermined interference at the transmitting or receiving end; DFE (Decision Feedback Equalizer) to eliminate residual post-cursor interference; and CDR (Clock and Data Recovery) to recover the sampling clock from the received data to achieve data decision and jitter suppression.
[0004] To achieve optimal performance from these equalizers, the system must employ an adaptive algorithm to train and converge the parameters one by one. While existing adaptive state machines can largely perform parameter calibration, they suffer from the following significant problems in practical applications: In complex cabling environments such as data centers, channel lengths vary greatly, ranging from chip-to-chip interconnects of a few centimeters to backplane transmissions of several meters, and even longer distances. Furthermore, the transmission materials used in the channel also have different impacts. Moreover, channel characteristics are not static; changes in ambient temperature and fluctuations in supply voltage (PVT, Process, Voltage, Temperature) all affect channel loss. Existing state machines typically employ a worst-case design, meaning that regardless of channel conditions, all equalizers are sequentially activated for training (e.g., ...). Figure 1(As shown), for example, CTLE→VGA→CDR→FFE→DFE. However, for low-loss short-channel communication, complex DFE training is unnecessary, but the forced execution of a fixed linear sequence results in lengthy link establishment times.
[0005] In high-radius switches, if each of the hundreds or thousands of ports undergoes a full-process calibration during rebooting or hot-plugging, the system recovery time can reach the second level, severely impacting business continuity.
[0006] Furthermore, traditional finite state machines are typically unidirectional and rigid, unable to make intelligent decisions based on intermediate process quality metrics (such as eye diagram opening). For example, if the signal is sufficiently clear after CTLE convergence, the system cannot automatically terminate the adaptive training process prematurely. On the other hand, the system cannot identify unnecessary circuit modules during the adaptive phase, still consuming redundant computational and hardware resources in short-range scenarios, leading to wasted power consumption and potentially introducing additional quantization noise and baseband interference.
[0007] Therefore, there is an urgent need for a method to solve the above problems. Summary of the Invention
[0008] The purpose of this invention is to provide a SerDes adaptive equalization configuration method and apparatus based on channel loss. According to the quality of the coarse received signal, the corresponding equalizer is trained, thereby effectively reducing power consumption, shortening the signal link establishment time, and greatly improving the flexibility and energy efficiency of high-speed interconnect systems.
[0009] To achieve the above objectives, this invention provides a SerDes adaptive equalization configuration method based on channel loss, comprising: setting multiple signal quality levels and configuring an equalization mode for each signal quality level, wherein the better the signal quality corresponding to the signal quality level, the lower the power consumption of the equalization mode; before the signal link is established and the equalizer has not yet undergone adaptive training, detecting and determining the signal quality level of the signal received by the SerDes system, configuring and entering the corresponding equalization mode according to the signal quality level; controlling the equalizers currently enabled in the equalization mode to perform adaptive training sequentially until the parameters of all enabled equalizers have been trained and the signal link is established.
[0010] Preferably, the present invention pre-sets multiple consecutive level intervals for the bit error rate, and sets a one-to-one correspondence between the level intervals and the signal quality level; Meanwhile, the detection and determination of the signal quality level of the Serdes system received signal includes: calculating the bit error rate of the Serdes system received signal, and classifying the received signal into the corresponding signal quality level according to the calculated bit error rate.
[0011] Preferably, the signal quality levels of the received signal are ranked from best to worst as follows: Level 1, Level 2, Level 3, and Level 4. Through graded adaptive training of signal quality, independent adaptive training matching between different channels is achieved for rapid signal link establishment in short channels and convergence of training parameters in long channels.
[0012] Specifically, the bit error rate range corresponding to the first level of signal quality is [0, 10]. -8 The bit error rate range corresponding to the second level of signal quality is
[10] . -8 10 -5 The bit error rate range corresponding to the third level of signal quality is
[10] . -5 10 -2 The bit error rate range corresponding to the fourth level of signal quality is
[10] . -2 (,+∞).
[0013] Specifically, the equalizers are divided into CTLE equalizers, FFE equalizers, and DFE equalizers. In the equalization mode corresponding to the first level of signal quality, only the basic circuit of the CTLE equalizer is turned on, and the FFE and DFE equalizers are bypassed. In the equalization mode corresponding to the second level of signal quality, the CTLE equalizer is fully turned on and the FFE equalizer is partially turned on, and the DFE equalizer is bypassed. In the equalization mode corresponding to the third level of signal quality, the CTLE equalizer and the FFE equalizer are fully turned on, and the key tap circuit of the DFE equalizer is turned on. In the equalization mode corresponding to the fourth level of signal quality, the CTLE equalizer and the FFE equalizer are fully turned on, and all taps of the DFE equalizer are turned on.
[0014] Preferably, in the equalization mode corresponding to the third level of signal quality, the key tap circuits controlling the DFE equalizer to turn on are tap circuit 1, tap circuit 2, and tap circuit 3, and the remaining tap circuits in the DFE equalizer are bypassed.
[0015] Preferably, the steps for calculating the bit error rate of the received signal in a SerDes system include: first calculating the number of bits that erroneously occurred during the transmission of the received signal, and then dividing the number of erroneously occurred bits by the total number of bits in the received signal to obtain the bit error rate of the received signal.
[0016] Preferably, the SerDes adaptive equalization configuration method based on channel loss further includes: real-time monitoring of the signal quality of the received signal, determining whether the signal quality meets the standard, and if so, the signal link is successfully established; otherwise, determining the current signal quality level of the received signal, configuring and entering the corresponding equalization mode according to the signal quality level, and adaptively training the newly activated equalizers in a preset order until all activated equalizer parameters have been trained, at which point the signal link is established. Compared with the prior art, the present invention's real-time monitoring of the signal quality of the received signal also solves the potential error risk. When the fast training path (first-level signal quality / second-level signal quality) attempt fails, the system can automatically degrade to the deep equalization mode (third-level signal quality / fourth-level signal quality) instead of simply reporting an error or crashing. This optimization capability significantly improves the success rate of the first signal link establishment under complex electromagnetic environments and PVT fluctuations, ensuring the system's survivability under extremely harsh channels, and giving the system extremely high reliability and environmental robustness.
[0017] Preferably, when the signal quality level is configured and the corresponding equalization mode is entered, the corresponding equalizer is activated. The equalizer is divided into CTLE equalizer, FFE equalizer, and DFE equalizer, and each of the CTLE equalizer, FFE equalizer, and DFE equalizer has a built-in monitor for monitoring the signal quality of the received signal.
[0018] Preferably, the quality of the received signal is determined by real-time monitoring of the eye diagram quality, whether the CDR frequently loses lock, and whether the bit error rate meets the standard.
[0019] The present invention also discloses a SerDes adaptive equalization configuration device, comprising a computer program, a storage medium, and an actuator. The storage medium is used to store the computer program, and the actuator executes the computer program to implement the channel loss-based SerDes adaptive equalization configuration method described above.
[0020] Compared with existing technologies, this invention breaks through the linear sequence limitation of fixed order in traditional adaptive training. By configuring different equalization modes for the signal quality level of the coarsely received signal, the redundant equalizer adaptive training path is directly bypassed, allowing short channels or high-quality channels to skip time-consuming FFE negotiation and DFE iteration, significantly shortening the link establishment time. At the same time, for scenarios that do not require strong equalization training, the FFE drive branch circuit and DFE tap logic circuit are actively bypassed, effectively reducing the power consumption of the system and greatly improving the flexibility and energy efficiency of the high-speed interconnect system. Attached Figure Description
[0021] Figure 1This is a schematic diagram of a simple linear adaptive training sequence using existing technology.
[0022] Figure 2 This is a schematic diagram of the method steps disclosed in this invention.
[0023] Figure 3 This is a schematic diagram illustrating the process of establishing a signal link using the method disclosed in this invention. Detailed Implementation
[0024] To illustrate the technical content, structural features, objectives, and effects of the present invention in detail, the following description is provided in conjunction with the embodiments and accompanying drawings.
[0025] refer to Figure 2 , Figure 3 This invention provides a SerDes adaptive equalization configuration method based on channel loss, comprising the following steps: Step S10: Set multiple signal quality levels and configure an equalization mode for each signal quality level. The better the signal quality corresponding to the signal quality level, the lower the power consumption of the equalization mode.
[0026] Step S20: Before the signal link is established and the equalizer has not yet undergone adaptive training, the signal quality level of the signal received by the Serdes system is detected and determined, and the system is configured and enters the corresponding equalization mode according to the signal quality level.
[0027] Step S30: Control the equalizers enabled in the current equalization mode to perform adaptive training in sequence until the parameters of all enabled equalizers are trained and the signal link is established.
[0028] In this embodiment, multiple signal quality levels are set based on the bit error rate of the received signal.
[0029] Specifically, step S10 further includes step S11: pre-setting multiple consecutive level intervals for the bit error rate, and setting a one-to-one correspondence between the level intervals and the signal quality level.
[0030] In step S20, detecting and determining the signal quality level of the Serdes system received signal further includes step S21: calculating the bit error rate of the Serdes system received signal, and classifying the received signal into the corresponding signal quality level according to the calculated bit error rate.
[0031] In this embodiment, the signal quality levels of the received signal are ranked from best to worst as follows: Level 1, Level 2, Level 3, and Level 4. Level 1 signal quality is excellent, with a low-loss signal processing path as its equalization mode; Level 2 signal quality is good, with a slightly lossy signal processing path as its equalization mode; Level 3 signal quality is average, with a moderately distorted signal processing path as its equalization mode; and Level 4 signal quality is extremely poor, with a deeply lossy signal processing path as its equalization mode. From Level 1 to Level 4, the power consumption of the corresponding equalization mode increases sequentially. Through graded adaptive training of signal quality, independent adaptive training matching between different channels is achieved for fast signal link establishment in short channels and convergence of training parameters in long channels.
[0032] Specifically, in this embodiment, the bit error rate range corresponding to the first level of signal quality is [0, 10]. -8 The bit error rate range corresponding to the second level of signal quality is
[10] . -8 10 -5 The bit error rate range corresponding to the third level of signal quality is
[10] . -5 10 -2 The bit error rate range corresponding to the fourth level of signal quality is
[10] . -2 (,+∞).
[0033] Specifically, the equalizers are divided into CTLE equalizers, FFE equalizers, and DFE equalizers. In this embodiment, in the equalization mode corresponding to the first level of signal quality, the finite state machine only controls the basic CTLE equalizer for adaptive training and bypasses the FFE and DFE equalizers. In the equalization mode corresponding to the second level of signal quality, the finite state machine controls the CTLE equalizer to be fully on and the FFE equalizer to be partially on, and bypasses the DFE equalizer. In the equalization mode corresponding to the third level of signal quality, the finite state machine controls the CTLE equalizer and the FFE equalizer to be fully on, and enables the critical tap circuit of the DFE equalizer. In the equalization mode corresponding to the fourth level of signal quality, the finite state machine controls the CTLE equalizer and the FFE equalizer to be fully on, and enables all taps of the DFE equalizer. The finite state machine is located in the SerDes system and controls the on / off state of each equalizer.
[0034] Of course, equalizers are not limited to the three types mentioned above, and equalization modes are not limited to the four types mentioned above.
[0035] In the equalization mode corresponding to the third level of signal quality, the key tap circuits for controlling the DFE equalizer to turn on via a finite state machine are tap circuit 1, tap circuit 2, and tap circuit 3, while the remaining tap circuits in the DFE equalizer are bypassed.
[0036] In this embodiment, the steps for calculating the bit error rate of the received signal in the SerDes system include: first calculating the number of bits that erroneously occurred during the transmission of the received signal, and then dividing the number of erroneously occurred bits by the total number of bits in the received signal to obtain the bit error rate of the received signal.
[0037] More specifically, calculating the bit error rate of the received signal in a SerDes system includes the following steps: Step S211, single-bit error identification.
[0038] In each clock cycle, the monitor first performs a bitwise XOR operation between the received signal and a locally generated reference pattern to obtain the bit that was erroneous during the transmission of the received signal in each clock cycle.
[0039]
[0040] The received signal is delayed and aligned so that its bitwise XOR operation with the reference pattern is performed in the same clock cycle.
[0041] Step S212: Calculate the number of bit errors per cycle.
[0042] Sum all the bits that are 1 in the XOR result vector of each clock cycle obtained in step S21 to obtain the number of bit errors in each current clock cycle.
[0043]
[0044] Step S213: Calculate the total number of bit errors.
[0045] The number of bit errors in each clock cycle is accumulated in the register to obtain the total number of bits that erroneously occurred during the transmission of the received signal, i.e., the total number of bit errors.
[0046]
[0047] Step S214: Calculate the bit error rate.
[0048] Divide the total number of bit errors obtained in step S23 by the total number of transmitted bits of the received signal to obtain the bit error rate of the received signal.
[0049]
[0050] refer to Figure 2 , Figure 3The SerDes adaptive equalization configuration method based on channel loss disclosed in this invention also includes: Step S40: Monitor the signal quality of the received signal in real time and determine whether the signal quality meets the standard. If yes, the signal link is successfully established; otherwise, determine the current signal quality level of the received signal, configure and enter the corresponding equalization mode according to the signal quality level, and perform adaptive training on the newly activated equalizers in a preset order until all activated equalizer parameters have been trained, and the signal link is established. Compared with the prior art, the present invention's real-time monitoring of the signal quality of the received signal also solves the potential error risk. When the fast training path (first-level signal quality / second-level signal quality) fails, the system can automatically degrade to the deep equalization mode (third-level signal quality / fourth-level signal quality) instead of simply reporting an error or crashing. This optimization capability significantly improves the success rate of the first signal link establishment under complex electromagnetic environments and PVT fluctuations, ensuring the system's survivability under extremely harsh channels, and giving the system extremely high reliability and environmental robustness.
[0051] In other embodiments, other classification criteria may be used to divide the received signal into several signal quality levels, and this invention does not impose any particular limitation on this. For example, several signal quality levels can be set based on the eye diagram height and eye diagram width of the received signal, and an equalization mode can be configured for each signal quality level. When monitoring the signal quality of the received signal in real time, the bit error rate of the received signal can be used to determine whether its signal quality meets the standard.
[0052] In this embodiment, when the signal quality level is configured and the corresponding equalization mode is entered, the corresponding equalizer is activated. The CTLE equalizer, FFE equalizer, and DFE equalizer each embed a monitor to monitor the signal quality of the received signal. The monitor continuously monitors the signal quality of the received signal and feeds it back to the finite state machine, enabling the finite state machine to make decisions and control the equalization mode based on the information reported by the monitor.
[0053] Specifically, the quality of the received signal is determined by real-time monitoring of the eye diagram quality, the frequency of CDR loss of lock, and whether the bit error rate meets the standard. In this embodiment, the quality of the received signal is comprehensively judged based on the above three dimensions. The quality of the received signal is deemed substandard when the bit error rate of the received signal is substandard, the eye diagram opening is small, or the CDR frequently loses lock.
[0054] Therefore, in this embodiment, when the bit error rate of the received signal is within the preset bit error rate threshold, the eye diagram height and eye diagram width of the received signal exceed the preset opening degree and the CDR lock is stable, that is, when the eye diagram height and eye diagram width of the received signal are both large, the CDR lock is stable and the bit error rate meets the standard, the quality of the received signal is considered to meet the standard.
[0055] Specifically, the eye diagram quality (i.e., eye diagram height and eye diagram width) or CDR of the received signal is monitored for frequent loss of lock. When the eye diagram quality (i.e., eye diagram height and eye diagram width) of the received signal is found to be substandard or the CDR is frequently lost, the quality of the received signal is substandard. At this time, the bit error rate of the received signal is detected to determine the signal quality level of the current received signal, and the corresponding equalization mode is configured and entered according to the signal quality level. The newly enabled equalizers are adaptively trained in a preset order until all enabled equalizer parameters are trained and the signal link is established.
[0056] When the eye diagram quality (i.e., eye height and eye width) of the received signal is found to be up to standard and the CDR lock is stable, the bit error rate (BER) of the received signal still needs to be detected. If the BER is within a preset threshold, i.e., the BER meets the standard, then the signal quality of the received signal meets the standard, and the signal link is successfully established. If the BER does not meet the standard, the signal quality level of the current received signal is determined, and the corresponding equalization mode is configured and entered according to the signal quality level. The newly activated equalizers are adaptively trained in a preset order until the parameters of all activated equalizers are trained, and the signal link is established.
[0057] The aforementioned preset bit error rate threshold is a pre-defined threshold. It can be a value that directly represents the boundary between the second and third level signal quality, or it can be another value. It is preferable to select a value that falls within the bit error rate range corresponding to the second and third level signal quality.
[0058] In this embodiment, the boundary value between the second-level and third-level signal quality is selected. When the bit error rate (BER) is within the BER range corresponding to the first-level or second-level signal quality, the quality of the received signal is considered to meet the standard. In this embodiment, when the received signal is assigned to the first-level signal quality in step S20 and configured to enter the corresponding equalization mode, even if the BER of the received signal rises to the BER range corresponding to the second-level signal quality, the quality of the received signal is still considered to meet the standard, and there is no need to configure it to enter the equalization mode corresponding to the second-level signal quality. Therefore, when the BER is not met, the current received signal is highly likely to be assigned to the third-level or fourth-level signal quality.
[0059] In this embodiment, when the received signal is classified into the first level signal quality or the second level signal quality in step S20, and is configured and enters the corresponding equalization mode, if the bit error rate of the received signal is monitored in real time and found to be within the bit error rate range corresponding to the third level signal quality or the fourth level signal quality, then the signal quality level of the current received signal is determined based on the bit error rate, and the corresponding equalization mode is configured and entered according to the signal quality level. The newly activated equalizers are adaptively trained in a preset order until all activated equalizer parameters are trained and the signal link is established.
[0060] This embodiment also discloses a SerDes adaptive equalization configuration device, including a computer program, a storage medium, and an actuator. The storage medium stores the computer program, and the actuator executes the computer program to implement the channel loss-based SerDes adaptive equalization configuration method described above. The storage medium and actuator of this SerDes adaptive equalization configuration are the memory and processor of a SerDes system. The computer program is loaded into the SerDes system and runs based on the hardware architecture of the SerDes system.
[0061] Compared with existing technologies, this invention breaks through the linear sequence limitation of fixed order in traditional adaptive training. By configuring different equalization modes for the signal quality level of the coarsely received signal, the redundant equalizer adaptive training path is directly bypassed, allowing short channels or high-quality channels to skip time-consuming FFE negotiation and DFE iteration, significantly shortening the link establishment time. At the same time, for scenarios that do not require strong equalization training, the FFE drive branch circuit and DFE tap logic circuit are actively bypassed, effectively reducing the power consumption of the system and greatly improving the flexibility and energy efficiency of the high-speed interconnect system.
[0062] SerDes (Serializer / Deserializer): A serializer / deserializer used to convert between parallel and serial data in high-speed serial links.
[0063] The above-disclosed embodiments are merely preferred embodiments of the present invention and should not be construed as limiting the scope of the present invention. Therefore, any equivalent variations made in accordance with the scope of the present invention are still within the scope of the present invention.
Claims
1. A SerDes adaptive equalization configuration method based on channel loss, characterized in that: include: Multiple signal quality levels are set, and an equalization mode is configured for each signal quality level. The better the signal quality corresponding to the signal quality level, the lower the power consumption of the equalization mode. Before the signal link is established and the equalizer has not yet undergone adaptive training, the signal quality level of the signal received by the Serdes system is detected and determined, and the system is configured and enters the corresponding equalization mode according to the signal quality level. The equalizers currently enabled in the equalization mode are controlled to undergo adaptive training in sequence until the parameters of all enabled equalizers have been trained and the signal link has been established.
2. The SerDes adaptive equalization configuration method based on channel loss as described in claim 1, characterized in that: Multiple consecutive level intervals are pre-set for the bit error rate, and a one-to-one correspondence is established between the level intervals and the signal quality level; The detection and determination of the signal quality level of the SerDes system received signal includes: calculating the bit error rate of the SerDes system received signal, and classifying the received signal into the corresponding signal quality level according to the calculated bit error rate.
3. The SerDes adaptive equalization configuration method based on channel loss as described in claim 2, characterized in that: The signal quality levels of the received signal, ranked from best to worst, are: Level 1, Level 2, Level 3, and Level 4; wherein the bit error rate range corresponding to Level 1 signal quality is [0, 10]. -8 The bit error rate range corresponding to the second level of signal quality is [10]. -8 10 -5 The bit error rate range corresponding to the third level of signal quality is [10]. -5 10 -2 The bit error rate range corresponding to the fourth level of signal quality is [10]. -2 (,+∞).
4. The SerDes adaptive equalization configuration method based on channel loss as described in claim 3, characterized in that: The equalizers are divided into CTLE equalizers, FFE equalizers, and DFE equalizers. In the equalization mode corresponding to the first level of signal quality, only the basic circuit of the CTLE equalizer is turned on, and the FFE and DFE equalizers are bypassed. In the equalization mode corresponding to the second level of signal quality, the CTLE equalizer is fully turned on and the FFE equalizer is partially turned on, and the DFE equalizer is bypassed. In the equalization mode corresponding to the third level of signal quality, the CTLE equalizer and the FFE equalizer are fully turned on, and the key tap circuit of the DFE equalizer is turned on. In the equalization mode corresponding to the fourth level of signal quality, the CTLE equalizer and the FFE equalizer are fully turned on, and all taps of the DFE equalizer are turned on.
5. The SerDes adaptive equalization configuration method based on channel loss as described in claim 4, characterized in that: In the equalization mode corresponding to the third level of signal quality, the key tap circuits controlling the DFE equalizer to turn on are tap circuit 1, tap circuit 2, and tap circuit 3.
6. The SerDes adaptive equalization configuration method based on channel loss as described in claim 2, characterized in that: The steps for calculating the bit error rate of a SerDes system received signal include: first, calculating the number of bits that erroneously occurred during the transmission of the received signal; then, dividing the number of erroneously occurred bits by the total number of bits in the received signal to obtain the bit error rate of the received signal.
7. The SerDes adaptive equalization configuration method based on channel loss as described in claim 1, characterized in that: Also includes: The signal quality of the received signal is monitored in real time to determine whether the signal quality meets the standard. If it does, the signal link is successfully established. Otherwise, determine the signal quality level of the currently received signal, configure and enter the corresponding equalization mode according to the signal quality level, and perform adaptive training on the newly activated equalizers in a preset order until all activated equalizer parameters have been trained, then the signal link is established.
8. The SerDes adaptive equalization configuration method based on channel loss as described in claim 7, characterized in that: When the signal quality level is configured and the corresponding equalization mode is entered, the corresponding equalizer is turned on. The equalizer is divided into CTLE equalizer, FFE equalizer and DFE equalizer. Each of the CTLE equalizer, FFE equalizer and DFE equalizer has a built-in monitor to monitor the signal quality of the received signal.
9. The SerDes adaptive equalization configuration method based on channel loss as described in claim 7, characterized in that: The quality of the received signal is determined by real-time monitoring of the eye diagram quality, whether the CDR frequently loses lock, and whether the bit error rate meets the standard.
10. A SerDes adaptive equalization configuration device, characterized in that: It includes a computer program, a storage medium, and an actuator, wherein the storage medium stores the computer program, and the actuator executes the computer program to implement the channel loss-based SerDes adaptive equalization configuration method as described in claims 1-9.