Digital acquisition and online judging system and method for digital circuit experiment box

Abstract

The application relates to the technical field of data processing, in particular to a digital acquisition and online judgment system and method for a digital circuit experiment box. The application is constructed by a digital circuit experiment box, a parallel digital acquisition device, an upper computer terminal application, an experiment configuration and authentication server and a result submission server, wherein the parallel digital acquisition device comprises an input interface and a front-end protection subcomponent, an MCU control subcomponent, a communication transmission subcomponent, a display subcomponent and a power supply and reference subcomponent, realizes parallel acquisition, stable judgment, local display and data uploading of the relevant digital signals of the experiment; the upper computer terminal application is used for receiving the experiment configuration, analyzing the data frame and executing combined logic or time sequence logic judgment, so that online detection and submission of the digital circuit experiment result are realized. The application has the advantages of good acquisition synchronization, high judgment accuracy, strong teaching adaptability and convenient online scoring.

Description

Technical Field

[0001] This invention relates to the field of data processing technology, and in particular to a digital acquisition and online judgment system and method for digital circuit experimental boxes. Background Technology

[0002] Existing digital circuit experiment teaching models face numerous challenges. On the one hand, traditional manual inspection and monitoring are inefficient, making it difficult for teachers to conduct real-time, detailed monitoring and evaluation of the experimental progress and results of a large number of students. This is especially true in experiments involving complex sequential logic, where visual observation or simple measurement tools alone are insufficient to accurately determine the timing characteristics of the circuit. On the other hand, while professional digital signal measurement tools such as general-purpose logic analyzers or data acquisition cards (DAQs) exist, these tools are typically expensive, complex to operate, and primarily focused on continuous high-speed sampling and protocol analysis, making them difficult to tightly integrate with the "experiment timing / scoring process" of teaching-oriented digital circuit experiment boxes. Specifically:

[0003] High cost and complexity: General-purpose logic analyzers or DAQ devices often employ high-performance FPGAs or complex bus interfaces, resulting in high costs and making them unsuitable for large-scale application in teaching experiments. Their complex software interfaces and operating procedures also increase the learning burden on students, deviating from the original purpose of experimental teaching.

[0004] Unsuitable for teaching scenarios: These general-purpose tools typically focus on continuous high-bandwidth streaming sampling, while teaching scenarios often require event-triggered single-shot captures based on external experimental clocks. For example, in sequential logic experiments, students may need to observe the circuit state after a specific clock edge is triggered. General-purpose tools are cumbersome and inflexible in meeting this teaching requirement of "clock-stepping, single-shot capture, and real-time judgment."

[0005] Lack of integration with online assessment: Existing general-purpose tools mostly present data as waveforms or data streams, which typically lack the ability to directly integrate with real-time error assessment, automatic scoring, and prompting functions on PC web front-ends, failing to provide the real-time feedback mechanism required for teaching. Achieving similar functionality would require significant secondary development, and balancing high performance with low cost would be difficult.

[0006] Interface and compatibility issues: The interface standards between existing experimental boxes and measuring tools are inconsistent, and general-purpose tools lack compatibility design with the characteristics of experimental boxes such as power supply voltage, signal level range, and signal jitter, which can easily lead to misjudgment or damage.

[0007] In summary, there is currently a lack of a low-cost, easy-to-use dedicated device and method specifically designed for digital circuit experimental teaching scenarios, capable of achieving sub-50ns level channel synchronous parallel acquisition, supporting external CLK gating for single capture, and tightly coupled with a real-time web-based scoring process. Therefore, this invention proposes a digital acquisition and online scoring system and method for digital circuit experimental boxes. Summary of the Invention

[0008] To address the shortcomings of existing technologies, this invention provides a digital acquisition and online judgment system and method for digital circuit experimental boxes, thereby solving the technical problems mentioned in the background art.

[0009] To achieve the above objectives, the present invention provides the following technical solution:

[0010] A parallel digital acquisition and online judgment system for digital circuit experiment boxes includes:

[0011] Digital circuit experiment box, used to output experimental digital signals, clock signals and reference level signals;

[0012] A parallel digital acquisition device is connected to the digital circuit experimental box and is used to perform parallel acquisition, stability determination, local display, and data upload of the digital signal; the parallel digital acquisition device includes an input interface and front-end protection sub-component, an MCU control sub-component, a communication transmission sub-component, a display sub-component, and a power supply and reference sub-component;

[0013] The host computer application communicates with the parallel digital acquisition device to receive experimental configurations, interact with the parallel digital acquisition device to receive data, parse data frames, and perform logical judgments.

[0014] The experiment configuration and authentication server communicates with the host computer application to complete device authentication and distribute experiment configurations; and

[0015] The results are submitted to the server, which communicates with the host computer application to receive the experimental results and return submission feedback.

[0016] Furthermore, the input interface and front-end protection sub-component include:

[0017] The multi-input wiring module provides 16 digital input channels for connecting to experimental signal ports;

[0018] The reference wiring module provides VCC and GND ports to establish a reference level and ground relationship;

[0019] The clock input module provides a CLK port for receiving external clock signals in sequential logic mode.

[0020] The level compatibility module enables the 16 digital inputs to have 5V tolerance and is compatible with 3.3V / 5V logic levels;

[0021] The Schmitt trigger buffer module provides hysteresis characteristics to the input signal to suppress jitter and glitches;

[0022] The front-end protection module includes a series current-limiting resistor and ESD / TVS protection device for each input to prevent overvoltage, overcurrent, and electrostatic damage; and

[0023] Reverse connection protection circuit to prevent VCC and GND from being reversed and burning out the circuit board.

[0024] Furthermore, the MCU control sub-component includes:

[0025] The mode switching module responds to read commands in combinational logic mode and trigger enable / trigger disable commands in sequential logic mode.

[0026] The parallel sampling module reads one or more GPIO input registers and combines them into a 16-bit sample;

[0027] The synchronous latch module utilizes register reads within adjacent instruction cycles to ensure that the sampling time difference between multiple channels does not exceed 50ns;

[0028] The stability decision module performs consistency judgment on continuous sampling results, and determines a valid sample if it is consistent for 5 consecutive times.

[0029] The clock edge detection module detects the preset edge of CLK and triggers sampling in sequential logic mode; and

[0030] The timing reference module generates periodic interrupts through a timer, which serve as the time reference for sampling, debouncing, and throttling reporting.

[0031] Furthermore, the communication transmission sub-component includes:

[0032] The USB interface module completes the physical connection with the host computer and also provides power supply and communication.

[0033] The downlink command receiving module receives sampling request commands, trigger enable commands, and trigger disable commands.

[0034] The command buffer parsing module writes the received data into a circular buffer and parses it in the main loop, avoiding blocking the sampling task.

[0035] The sample frame construction module encapsulates valid samples into a fixed frame format;

[0036] The uplink transmission module uploads data frames when the USB CDC transmit interface is not busy; and

[0037] The upload throttling module controls the upload frequency to no higher than 100Hz to adapt to real-time judgment on the web page.

[0038] Furthermore, the display sub-component includes:

[0039] The display hardware module uses an ST7789 controller for the TFT LCD display screen;

[0040] The SPI interface module communicates with the MCU via SCK, MOSI, and DC signals.

[0041] The display initialization module completes reset, wake-up, and RGB565 pixel format and landscape orientation settings.

[0042] The interface layout module divides the display area into a title area and a waveform area;

[0043] The channel layout module automatically selects between single-column or double-column display based on the number of channels.

[0044] The sampling cache module temporarily caches the periodic sampling results and maintains the historical sampling sequence;

[0045] The waveform generation module converts historical samples into high and low level lines and transition vertical lines;

[0046] The refresh control module performs screen refresh based on a refresh flag in the main loop or background task; and

[0047] The DMA block refresh module divides the waveform into an upper half window and a lower half window, which are written to RAM separately to reduce refresh blocking.

[0048] Furthermore, the power supply and reference sub-component includes:

[0049] The USB power supply module supplies power to the MCU, display screen and interface circuits via a USB interface.

[0050] The common ground module establishes a common ground with the experimental box via GND to ensure consistent sampling references; and

[0051] The power supply module of the experimental box draws power from the VCC and GND ports of the digital circuit experimental box as an alternative power supply method.

[0052] Furthermore, the host computer application includes:

[0053] Configure the receiving and authentication module, establish a connection between the host computer and the WebSocket server, complete device authentication and obtain the authorization identifier, and then receive the experimental configuration;

[0054] The truth table parsing and channel determination module parses the truth table in the experimental configuration into a multi-row bit sequence and determines the number of channels N in this experiment based on the number of bits in a single row; when N is less than 16, only the first N channels are displayed, parsed, and determined.

[0055] The serial communication module establishes a communication connection with the acquisition device, sends read commands, start commands, stop commands, and channel display configuration commands to the device, and is responsible for continuously receiving sample frames;

[0056] The frame synchronization and bit mapping module performs frame synchronization based on the start and end flags, recovers the channel state from the load, and outputs the target bit sequence in order so that it corresponds to the order of the truth table columns.

[0057] The combinational logic determination module reads a frame of data within a timeout window each time a read command is sent during the combinational logic experiment. After parsing, it compares the data bit by bit with the specified row of the truth table and records the read value of that row.

[0058] The timing logic determination module, in the timing logic experiment, first sends a start command to put the device into continuous upload mode, then uses an event-driven approach to trigger parsing and determination when a new frame arrives, and finally sends a stop command after completion; and

[0059] The result recording and submission module records the target bit sequence for each row or state, concatenates them into a result string in row order, and submits it to the result server.

[0060] Furthermore, the experimental configuration and authentication server includes:

[0061] The authentication module receives authentication information such as device type, device identifier, and serial number, and returns an authorization identifier.

[0062] The experiment configuration distribution module distributes the experiment configuration, including Config and Address, to the host computer.

[0063] The logic type identification module distinguishes between combinational logic and sequential logic based on fields in the experimental configuration; and

[0064] The channel number configuration module determines the number of channels N based on the length of the truth table and provides the host computer with further channel display configurations.

[0065] The method applied to the above-mentioned parallel digital acquisition and online judgment system includes the following steps:

[0066] Includes the following steps:

[0067] S1: Establish hardware connections and complete power supply and reference configuration:

[0068] Connect the parallel digital acquisition device to the digital circuit experimental box;

[0069] S2: Complete device certification and receive experimental configuration:

[0070] The host computer application establishes a communication connection with the experimental configuration and authentication server through the configuration receiving and authentication module, and the experimental configuration and authentication server sends the experimental configuration to the host computer application through the experimental configuration sending module.

[0071] S3: Analyze the experimental configuration and determine the valid acquisition channels:

[0072] The truth table parsing and channel determination module in the host computer application parses the truth table in the experimental configuration, parses the truth table into a multi-row target bit sequence, and determines the actual number of channels N used in this experiment based on the number of bits in a single-row target bit sequence.

[0073] S4: Establish the communication and control relationship between the host computer application and the parallel digital acquisition device:

[0074] The host computer application establishes a USB CDC virtual serial port communication with the communication transmission sub-component in the parallel digital acquisition device through the serial communication module; the downlink command receiving module in the communication transmission sub-component is used to receive control commands from the host computer application, and the command buffer parsing module is used to write the received control commands into the buffer and parse them to avoid blocking the sampling task.

[0075] S5: Detection sampling trigger condition:

[0076] The MCU control sub-component in the parallel digital acquisition device serves as the core control unit, detecting the sampling trigger conditions. When the experiment is in combinational logic mode, the mode switching module responds to the sampling request instruction to trigger a sampling event.

[0077] S6: Perform parallel digital acquisition and generate synchronous samples:

[0078] After detecting the sampling trigger condition, the parallel sampling module in the MCU control sub-component immediately reads one or more GPIO input data registers and combines the reading results into 16-bit sample data to obtain the logic state of each input channel under this sampling event.

[0079] S7: Perform a stabilization decision on the synchronized samples and obtain valid samples:

[0080] The stability decision module in the MCU control sub-component performs validity determination on the synchronization sample to filter out invalid state changes caused by contact jitter, glitches or transient disturbances. Under the periodic sampling beat provided by the timing reference module, the stability decision module performs consistency comparison on the results of multiple consecutive samplings. When the results of I consecutive samplings are consistent, the current sample is determined to be a valid sample.

[0081] S8: Construct a data frame and upload it to the host computer application:

[0082] After obtaining a valid sample, the sample frame construction module in the communication transmission sub-component encapsulates the valid sample into a data frame and uploads it to the host computer application via the USB CDC virtual serial port through the uplink transmission module.

[0083] S9: Perform local display and status prompts:

[0084] During the sampling and uploading process, the display sub-component in the parallel digital acquisition device displays the sampling results locally;

[0085] S10: Parse the data frame and perform logical judgment:

[0086] After the host computer application receives the data frame, the frame synchronization and bit mapping module performs frame synchronization based on the frame header 0x5A and the frame tail 0x5B, recovers the logic state of each channel from the sample data field, and outputs the target bit sequence in the order of K_N to K1 to correspond to the order of the truth table column in the experimental configuration.

[0087] S11: Record and submit the experimental results:

[0088] The result recording and submission module in the host computer application records the target bit sequence corresponding to each row or state and concatenates them into a result string in a predetermined order. After the experiment is completed, the host computer application submits the result string to the result submission server, which receives the experimental results and returns submission feedback to complete the submission of the digital circuit experiment results.

[0089] Beneficial effects compared to existing technologies:

[0090] 1. Existing logic analyzers or related products used in teaching typically focus on multi-channel digital signal sampling, waveform display, and basic data analysis functions. While they can provide visual waveforms to help students understand signal changes, they generally lack online error correction functions driven by specific experimental questions and grading rules, as well as a complete online web-based grading system. These products exist more as a "measurement tool" than an "intelligent teaching aid system," unable to provide real-time, automatic feedback, and difficult to deeply integrate with modern teaching platforms. This invention, however, treats data acquisition, mode switching, and online grading as an inseparable integrated technical solution, achieving high-precision synchronous acquisition and web-based error correction at low cost.

[0091] 2. Existing experimental kits or remote experimental systems typically emphasize high-performance hardware boards, complex remote control functions, or the construction of comprehensive experimental platforms. These systems may involve complex technologies such as board design, FPGA programming, or network communication, but their core focus is on providing a remote experimental environment or rich hardware functions. They do not delve into the in-depth research and implementation of "device-side gated sampling (especially single-shot capture of external CLK gating) and real-time error detection by the browser" as a core, low-cost, and optimized overall technical solution adapted to teaching scenarios. This invention focuses on accurate sampling at the device end (especially gated capture of timing logic in teaching scenarios) and seamless error detection feedback on the host computer web page, forming a lighter, more targeted, and more cost-effective solution. Attached Figure Description

[0092] The above description is merely an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention and to implement it in accordance with the contents of the specification, the preferred embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0093] Figure 1 This is the overall flowchart of the present invention. Detailed Implementation

[0094] Preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings; however, the present invention may be implemented in various different forms, and therefore the present invention is not limited to the embodiments described below.

[0095] To address the problems described in the background, this invention provides a parallel digital acquisition and online judgment system for a digital circuit experimental box. The system preferably comprises a digital circuit experimental box, a parallel digital acquisition device, a host computer application, an experimental configuration and authentication server, and a result submission server. Specifically, the digital circuit experimental box outputs experimentally relevant digital signals, clock signals, and reference level signals; the parallel digital acquisition device performs parallel acquisition, stability judgment, local display, and data upload of the digital signals; the host computer application receives experimental configurations, communicates with the parallel digital acquisition device, parses data frames, and performs logical judgments; the experimental configuration and authentication server completes device authentication and issues experimental configurations; and the result submission server receives experimental results and returns submission feedback. The parallel digital acquisition device preferably includes an input interface and front-end protection sub-component, an MCU control sub-component, a communication transmission sub-component, a display sub-component, a status indication sub-component, and a power supply and reference sub-component. Each sub-component performs its corresponding function through modules such as level compatibility, Schmitt triggering, parallel sampling, stability decision, data frame construction, screen refresh, and status prompts, thereby forming a complete acquisition and online judgment scheme for digital circuit experimental teaching.

[0096] Digital circuit experiment box components

[0097] As the object under test, it is used to output the input signals, output signals, clock signals, and reference level signals involved in this experiment, for the acquisition device to access and read. Combinational logic experiments are usually connected to the input / output ports involved in the decision and GND; sequential logic experiments, in addition to the relevant ports, also need to connect to CLK.

[0098] Parallel digital acquisition device components

[0099] As the core hardware of the system, it connects to the digital circuit experiment box to perform parallel acquisition, validity determination, local display, and uplink transmission of multiple digital signals from the experiment box. This device is the main executor of "accurate acquisition, effective transmission, and visible display".

[0100] This component is internally divided into 5 sub-components: input interface and front-end protection sub-component, MCU control sub-component, communication transmission sub-component, display sub-component, and power supply and reference sub-component.

[0101] 1. The input interface and front-end protection sub-component are used to complete the physical connection between the device and the digital circuit experimental box, and to ensure the compatibility and robustness of the input signals. Existing solutions have clearly defined the input interface as including 16 digital input terminals, as well as VCC, GND, and CLK terminals.

[0102] This sub-component integrates or has the following features:

[0103] Multi-input wiring module: Provides 16 digital input channels for connecting to experimental signal ports;

[0104] Reference wiring module: Provides VCC and GND ports to establish a reference level and ground relationship;

[0105] Clock input module: Provides a CLK port for connecting an external clock in sequential logic mode;

[0106] Level compatibility module: Enables 16 digital inputs to tolerate 5V and is compatible with 3.3V / 5V logic levels;

[0107] Schmitt trigger buffer module: provides hysteresis characteristics to the input signal to suppress jitter and glitches;

[0108] Front-end protection module: Each input is equipped with a series current-limiting resistor and an ESD / TVS protection device to prevent overvoltage, overcurrent and electrostatic damage.

[0109] Reverse connection protection circuit; prevents VCC and GND from being reversed and burning out the circuit board.

[0110] 2. The MCU control sub-component serves as the core control unit of the device, responsible for sampling triggering, parallel reading, stability decision-making, data encapsulation, and task scheduling. Existing solutions clearly define that multiple GPIOs of the MCU are connected in parallel to 16 input terminals, and sample reading and combination are completed within the same sampling event.

[0111] This sub-component can be integrated or configured with:

[0112] Mode switching module: Responds to read commands in combinational logic mode and trigger enable / trigger disable commands in sequential logic mode;

[0113] Parallel sampling module: Reads one or more GPIO input registers and combines them into a 16-bit sample;

[0114] Synchronous latch module: Utilizes register reads within adjacent instruction cycles to ensure that the sampling time difference between multiple channels does not exceed 50ns;

[0115] Stable decision module: performs consistency judgment on continuous sampling results, and selects a valid sample only if it is consistent for 5 consecutive times;

[0116] Clock edge detection module: Detects the preset edge of CLK and triggers sampling in sequential logic mode;

[0117] Timing reference module: Generates periodic interrupts through a timer, preferably once every 10ms, as the time reference for sampling, debouncing, and throttling reporting.

[0118] 3. Communication transmission sub-component, used to realize bidirectional command interaction and uplink data transmission between the device and the host computer. The device connects to the host computer via USB, and preferably uses a USB CDC virtual serial port for communication.

[0119] This sub-component integrates or has the following features:

[0120] USB interface module: completes the physical connection and also provides power supply and communication;

[0121] Downlink command receiving module: receives sampling request commands, trigger enable commands, and trigger disable commands;

[0122] Command buffer parsing module: Writes received data into a circular buffer and parses it in the main loop to avoid blocking the sampling task;

[0123] Sample frame construction module: encapsulates valid samples into fixed frames, preferably 0x5A + 2 bytes of sample + 0x5B;

[0124] Uplink transmission module: Uploads data frames when the USB CDC transmit interface is not busy;

[0125] Upload throttling module: controls the upload frequency to no higher than approximately 100Hz to adapt to real-time judgment by the web page.

[0126] 4. A display sub-component is used to locally display the sampling channel, working mode, waveform results, and operating status, forming a local visualization closed loop of "acquisition—buffering—refresh display". Existing documents have already described this as a preferred embodiment, and clearly state that the display screen is directly driven by the MCU.

[0127] This sub-component integrates or has the following features:

[0128] Display hardware module: TFT LCD display screen of ST7789 controller, 1.9 inches with a resolution of 170*320;

[0129] SPI interface module: Communicates with the MCU via signals such as SCK, MOSI, and DC, and can optionally include CS, RST, and backlight control pins;

[0130] Display initialization module: Completes reset, wake-up, and RGB565 pixel format and landscape orientation settings;

[0131] Interface layout module: Divides the display area into a title area and a waveform area;

[0132] Channel layout module: Automatically selects single-column or double-column display based on the number of channels;

[0133] Sampling caching module: Temporarily caches periodic sampling results and maintains historical sampling sequences;

[0134] Waveform generation module: Converts historical samples into high and low level lines and transition vertical lines;

[0135] Refresh control module: Performs screen refresh based on refresh flags in the main loop or background task;

[0136] DMA block refresh module: The waveform is divided into an upper half window and a lower half window and written to RAM respectively to reduce refresh blocking.

[0137] 5. Power supply and reference sub-components are used to power the device and ensure that the reference relationship between the device and the experimental box is consistent. There are two power supply methods: the first is to draw power through USB, and the second is to draw power through the digital electronics experimental box by connecting VCC and GND.

[0138] This sub-component integrates or has the following features:

[0139] USB power supply module: provides power to the MCU, display screen and interface circuitry;

[0140] Common ground module: Establishes a common ground with the experimental box via GND to ensure consistent sampling reference.

[0141] Upper computer application components

[0142] As the software control center of the system, it is used to receive experimental configurations, establish serial communication with the acquisition device, parse data frames, execute combinational logic or sequential logic judgments, and record and submit experimental results.

[0143] This component is equipped with:

[0144] Configure the receiving and authentication module, truth table parsing and channel determination module, serial communication module, frame synchronization and bit mapping module, combinational logic judgment module, timing logic judgment module, and result recording and submission module.

[0145] 1. Configure the receiving and authentication module, which is used to establish a connection between the host computer and the WebSocket server, complete device authentication and obtain authorization identifier, and then receive experimental configuration. This module is the entry point for the entire system startup.

[0146] 2. The truth table parsing and channel determination module is used to parse the truth table in the experimental configuration into a multi-row bit sequence and determine the number of channels N in this experiment based on the number of bits in a single row. When N is less than 16, only the first N channels are displayed, parsed, and determined. It is also the source of the subsequent "only display the few channels used" instruction.

[0147] 3. Serial communication module, used to establish a communication connection with the acquisition device, send read commands, start commands, stop commands and optional channel display configuration commands to the device, and is responsible for continuously receiving sample frames.

[0148] 4. Frame synchronization and bit mapping module, used to perform frame synchronization based on start flag 0x5A and end flag 0x5B, recover the channel states K1 to K16 from the two-byte payload, and output the target bit sequence in the order of K_N to K1 so that it corresponds to the order of the truth table columns.

[0149] 5. Combinational Logic Decision Module: In combinational logic experiments, the host computer sends a 0x05 read command each time, reads one frame of data within a timeout window, parses it, compares it bit by bit with the specified row of the truth table, and records the read value of that row. This read operation is repeated every time a student changes their state.

[0150] 6. The timing logic determination module is used in timing logic experiments. First, the host computer sends a 0x15 start command to put the device into continuous upload mode. Then, using an event-driven approach instead of active polling, it triggers parsing and determination when a new frame arrives, and sends a 0x25 stop command upon completion. This avoids misalignment between active polling and CLK events in high-frequency scenarios.

[0151] 7. The results recording and submission module records the target bit sequence for each row or state, concatenates them into a result string in row order, and submits it to the results server. Click "Submit Results" after completing the experiment to end the experiment.

[0152] Experiment configuration and certification server components

[0153] Function: Used for device authentication, experiment configuration distribution, and logic type notification. After the teacher publishes the experiment requirements on the server, the host computer receives the configuration and then knows whether the experiment is combinational or sequential logic, how many channels are needed, and what the truth table is.

[0154] This component is equipped with:

[0155] Authentication module: Receives authentication information such as device type, device identifier, and serial number, and returns an authorization identifier;

[0156] Experiment configuration distribution module: Distributes experiment configurations, including Config and Address, to the host computer;

[0157] Logical type identification module: Distinguishes between combinational logic and sequential logic based on fields in the experimental configuration;

[0158] Channel number configuration module: Determines the number of channels N based on the length of the truth table, and provides the host computer with further channel display configurations.

[0159] A method for parallel digital acquisition in a digital circuit experimental box includes the following steps:

[0160] S1: Establish hardware connections and complete power supply and reference configuration:

[0161] A parallel digital acquisition device is connected to a digital circuit experimental box. The input interface and front-end protection sub-component of the parallel digital acquisition device are used to access the experimentally relevant digital signals output from the digital circuit experimental box. The input interface and front-end protection sub-component include a multi-channel input wiring module, a reference wiring module, and a clock access module. The multi-channel input wiring module provides 16 digital input channels for accessing experimentally relevant input signals and / or output signals. The reference wiring module connects the VCC and GND ports to establish a reference level and common ground relationship. The clock access module is used to access the CLK signal in sequential logic experimental mode. Simultaneously, the level compatibility module in the input interface and front-end protection sub-component ensures each input channel has 5V tolerance and is compatible with 3.3V / 5V logic levels. The Schmitt trigger buffer module shapes the input signal and suppresses jitter and glitches. The front-end protection module improves the input's overvoltage, overcurrent, and electrostatic discharge (ESD) resistance through current limiting and ESD protection. The reverse connection protection circuit prevents damage to the circuit from reverse connection of VCC and GND.

[0162] The power supply and reference sub-components in the parallel digital acquisition device are used to power the device and ensure that the sampling reference between the parallel digital acquisition device and the digital circuit experimental box is consistent through a common ground module; the communication transmission sub-component establishes a connection with the host computer application through a USB interface module to realize power supply and data communication.

[0163] S2: Complete device certification and receive experimental configuration:

[0164] The host computer application establishes a communication connection with the experimental configuration and authentication server through the configuration receiving and authentication module, sends authentication information such as device type, device identifier and / or serial number, and receives the authorization identifier returned by the server; after successful authentication, the experimental configuration and authentication server sends the experimental configuration to the host computer application through the experimental configuration distribution module.

[0165] The experimental configuration includes at least logic type identification information and truth table information. The logic type identification information is used to indicate whether the experiment is a combinational logic experiment or a sequential logic experiment, and the truth table information is used as the basis for subsequent logic determination.

[0166] S3: Analyze the experimental configuration and determine the valid acquisition channels:

[0167] The truth table parsing and channel determination module in the host computer application parses the truth table in the experimental configuration, converting it into a multi-line target bit sequence, and determines the actual number of channels N used in this experiment based on the number of bits in a single line of target bit sequence. When N is less than 16, the host computer application only displays, parses data, and performs logical judgments on the first N channels. In some implementations, the host computer application can also send channel display configuration commands to the parallel digital acquisition device via a serial communication module, so that the display sub-component performs interface layout and local display according to the determined number of channels N.

[0168] S4: Establish the communication and control relationship between the host computer application and the parallel digital acquisition device.

[0169] The host computer application establishes a USB CDC virtual serial port communication with the communication transmission sub-component in the parallel digital acquisition device through the serial communication module; the downlink command receiving module in the communication transmission sub-component is used to receive control commands from the host computer application, and the command buffer parsing module is used to write the received control commands into the buffer and parse them to avoid blocking the sampling task.

[0170] The control commands include at least a sampling request command, a trigger enable command, and a trigger disable command; wherein, in combinational logic mode, the host computer application sends a sampling request command to the parallel digital acquisition device; in sequential logic mode, the host computer application sends a trigger enable command to the parallel digital acquisition device, and sends a trigger disable command after the experiment ends or the stop condition is met.

[0171] S5: Detection sampling trigger condition:

[0172] The MCU control sub-component in the parallel digital acquisition device serves as the core control unit, detecting the sampling trigger conditions. This MCU control sub-component includes a mode switching module, a parallel sampling module, a synchronous latch module, a stability decision module, a clock edge detection module, and a timing reference module. When the experiment is in combinational logic mode, the mode switching module responds to the sampling request command to trigger a sampling event.

[0173] When the experiment is in sequential logic mode, the mode switching module enters the trigger detection state after receiving the trigger enable command. The clock edge detection module performs edge detection on the clock signal input to the CLK terminal and triggers a sampling event when a preset rising edge or falling edge is detected. After receiving the trigger disable command, the trigger response to the edge of the CLK terminal is stopped.

[0174] The timing reference module generates periodic interrupts through a timer to provide a time reference for sampling scheduling, stability determination, and upload throttling.

[0175] S6: Perform parallel digital acquisition and generate synchronous samples:

[0176] After detecting the sampling trigger condition, the parallel sampling module in the MCU control sub-component immediately reads one or more GPIO input data registers and combines the reading results into 16-bit sample data to obtain the logic state of each input channel under this sampling event.

[0177] The synchronous latch module is used to complete near-synchronous reading of multiple channels in the same sampling event, so that the sampling time of each channel does not exceed 50ns, thereby obtaining synchronous samples. Each bit of the 16-bit sample data corresponds to the level state of the 16 digital input channels. The level state is sent to the MCU control sub-component after level compatibility, Schmitt trigger buffering, and front-end protection processing by the input interface and front-end protection sub-component, to improve the reliability and robustness of the sampling results.

[0178] S7: Perform a stabilization decision on the synchronized samples and obtain valid samples:

[0179] The stability decision module in the MCU control sub-component performs validity determination on the synchronization samples to filter out invalid state changes caused by contact jitter, glitches, or transient disturbances. Under the periodic sampling cycle provided by the timing reference module, the stability decision module performs consistency comparison on multiple consecutive sampling results. When I consecutive sampling results are consistent, the current sample is determined to be a valid sample, where I is set to 5.

[0180] In combinational logic mode, the valid sample is used to characterize the stable combinational result after the current logic state adjustment; in sequential logic mode, the valid sample is used to characterize the stable sequential state triggered by the corresponding clock edge.

[0181] S8: Construct a data frame and upload it to the host computer application:

[0182] After obtaining a valid sample, the sample frame construction module in the communication transmission sub-component encapsulates the valid sample into a data frame and uploads it to the host computer application via the uplink transmission module through the USB CDC virtual serial port.

[0183] The data frame adopts a fixed frame structure, including at least a frame header, a sample data field, and a frame trailer. The frame header is preferably 0x5A, the sample data field is preferably 2 bytes, and the frame trailer is preferably 0x5B. In some embodiments, the data frame may also include a mode flag field and / or a check field.

[0184] The upload throttling module in the communication transmission sub-component is used to control the data upload frequency to not exceed approximately 100Hz, in order to adapt to the real-time parsing and logical judgment of the host computer application.

[0185] S9: Perform local display and status prompts:

[0186] During the sampling and uploading process, the display sub-component in the parallel digital acquisition device displays the sampling results locally; the display sub-component includes a display hardware module, an SPI interface module, a display initialization module, an interface layout module, a channel layout module, a sampling buffer module, a waveform generation module, a refresh control module, and a DMA block refresh module.

[0187] The display initialization module is used to reset, wake up, set the display format, and set the display orientation of the display screen; the interface layout module is used to divide the display area into a title area and a waveform area; the channel layout module is used to determine the single-column or double-column display mode according to the number of channels N; the sampling cache module is used to cache the current sample and the historical sampling sequence; the waveform generation module is used to generate the high and low level lines and transition lines corresponding to each channel according to the historical sampling sequence; the refresh control module is used to perform screen refresh according to the refresh flag; and the DMA block refresh module is used to reduce the blocking impact of the refresh process on the sampling task.

[0188] Meanwhile, the status indicator sub-component is used to indicate the current working status of the device, which includes at least one or more of the following: power-on status, connection status, sampling status, trigger-enabled status, and data upload status.

[0189] S10: Parse the data frame and perform logical judgment:

[0190] After receiving the data frame, the host computer application performs frame synchronization based on the frame header 0x5A and frame trailer 0x5B. It then recovers the logic state of each channel from the sample data field and outputs the target bit sequence in the order K_N to K1 to correspond to the order of the truth table columns in the experimental configuration. When this experiment is in combinational logic mode, the combinational logic determination module receives one frame of data within a preset timeout window after each sampling request command is sent. It then compares the parsed target bit sequence bit by bit with the specified row of the truth table to record the sampling result corresponding to that row.

[0191] When the experiment is in sequential logic mode, the sequential logic judgment module adopts an event-driven approach during the trigger enable period. When a new data frame arrives, it triggers parsing and judgment, and sends a trigger disable command after completing the predetermined state acquisition, so as to avoid active polling and clock event misalignment in high-frequency scenarios.

[0192] S11: Record and submit the experimental results:

[0193] The result recording and submission module in the host computer application records the target bit sequence corresponding to each row or state and concatenates them into a result string in a predetermined order. After the experiment is completed, the host computer application submits the result string to the result submission server, which receives the experimental results and returns submission feedback to complete the submission of the digital circuit experiment results.

[0194] Finally, it should be noted that the above embodiments are merely examples for clearly illustrating the present invention and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations. However, obvious variations or modifications derived therefrom are still within the scope of protection of this invention.

Claims

1. A parallel digital acquisition and online judgment system for a digital circuit experimental box, characterized in that, include: Digital circuit experiment box, used to output experimental digital signals, clock signals and reference level signals; A parallel digital acquisition device is connected to the digital circuit experimental box and is used to perform parallel acquisition, stability determination, local display, and data upload of the digital signal; the parallel digital acquisition device includes an input interface and front-end protection sub-component, an MCU control sub-component, a communication transmission sub-component, a display sub-component, and a power supply and reference sub-component; The host computer application communicates with the parallel digital acquisition device to receive experimental configurations, interact with the parallel digital acquisition device to receive data, parse data frames, and perform logical judgments. The experimental configuration and authentication server communicates with the host computer application to complete device authentication and distribute experimental configurations. as well as The results are submitted to the server, which communicates with the host computer application to receive the experimental results and return submission feedback.

2. The parallel digital acquisition and online judgment system for a digital circuit experimental box according to claim 1, characterized in that, The input interface and front-end protection sub-component include: The multi-input wiring module provides 16 digital input channels for connecting to experimental signal ports; The reference wiring module provides VCC and GND ports to establish a reference level and ground relationship; The clock input module provides a CLK port for receiving external clock signals in sequential logic mode. The level compatibility module enables the 16 digital inputs to have 5V tolerance and is compatible with 3.3V / 5V logic levels; The Schmitt trigger buffer module provides hysteresis characteristics to the input signal to suppress jitter and glitches; The front-end protection module includes a series current-limiting resistor and ESD / TVS protection device for each input to prevent overvoltage, overcurrent, and electrostatic damage; and Reverse connection protection circuit to prevent VCC and GND from being reversed and burning out the circuit board.

3. The parallel digital acquisition and online judgment system for a digital circuit experimental box according to claim 1, characterized in that, The MCU control sub-component includes: The mode switching module responds to read commands in combinational logic mode and trigger enable / trigger disable commands in sequential logic mode. The parallel sampling module reads one or more GPIO input registers and combines them into a 16-bit sample; The synchronous latch module utilizes register reads within adjacent instruction cycles to ensure that the sampling time difference between multiple channels does not exceed 50ns; The stability decision module performs consistency judgment on continuous sampling results, and determines a valid sample if it is consistent for 5 consecutive times. The clock edge detection module detects the preset edge of CLK and triggers sampling in sequential logic mode; and The timing reference module generates periodic interrupts through a timer, which serve as the time reference for sampling, debouncing, and throttling reporting.

4. The parallel digital acquisition and online judgment system for a digital circuit experimental box according to claim 1, characterized in that, The communication transmission sub-component includes: The USB interface module completes the physical connection with the host computer and also provides power supply and communication. The downlink command receiving module receives sampling request commands, trigger enable commands, and trigger disable commands. The command buffer parsing module writes the received data into a circular buffer and parses it in the main loop, avoiding blocking the sampling task. The sample frame construction module encapsulates valid samples into a fixed frame format; The uplink transmission module uploads data frames when the USB CDC transmit interface is not busy; and The upload throttling module controls the upload frequency to no higher than 100Hz to adapt to real-time judgment on the web page.

5. The parallel digital acquisition and online judgment system for a digital circuit experimental box according to claim 1, characterized in that, The display sub-component includes: The display hardware module uses an ST7789 controller for the TFT LCD display screen; The SPI interface module communicates with the MCU via SCK, MOSI, and DC signals. The display initialization module completes reset, wake-up, and RGB565 pixel format and landscape orientation settings. The interface layout module divides the display area into a title area and a waveform area; The channel layout module automatically selects between single-column or double-column display based on the number of channels. The sampling cache module temporarily caches the periodic sampling results and maintains the historical sampling sequence; The waveform generation module converts historical samples into high and low level lines and transition vertical lines; The refresh control module performs screen refresh based on a refresh flag in the main loop or background task; and The DMA block refresh module divides the waveform into an upper half window and a lower half window, which are written to RAM separately to reduce refresh blocking.

6. The parallel digital acquisition and online judgment system for a digital circuit experimental box according to claim 1, characterized in that, The power supply and reference sub-components include: The USB power supply module supplies power to the MCU, display screen and interface circuits via a USB interface. The common ground module establishes a common ground with the experimental box via GND to ensure consistent sampling references; and The power supply module of the experimental box draws power from the VCC and GND ports of the digital circuit experimental box as an alternative power supply method.

7. The parallel digital acquisition and online judgment system for a digital circuit experimental box according to claim 1, characterized in that, The host computer application includes: Configure the receiving and authentication module, establish a connection between the host computer and the WebSocket server, complete device authentication and obtain the authorization identifier, and then receive the experimental configuration; The truth table parsing and channel determination module parses the truth table in the experimental configuration into a multi-row bit sequence and determines the number of channels N in this experiment based on the number of bits in a single row; when N is less than 16, only the first N channels are displayed, parsed, and determined. The serial communication module establishes a communication connection with the acquisition device, sends read commands, start commands, stop commands, and channel display configuration commands to the device, and is responsible for continuously receiving sample frames; The frame synchronization and bit mapping module performs frame synchronization based on the start and end flags, recovers the channel state from the load, and outputs the target bit sequence in order so that it corresponds to the order of the truth table columns. The combinational logic determination module reads a frame of data within a timeout window each time a read command is sent during the combinational logic experiment. After parsing, it compares the data bit by bit with the specified row of the truth table and records the read value of that row. The timing logic determination module, in the timing logic experiment, first sends a start command to put the device into continuous upload mode, then uses an event-driven approach to trigger parsing and determination when a new frame arrives, and finally sends a stop command after completion; and The result recording and submission module records the target bit sequence for each row or state, concatenates them into a result string in row order, and submits it to the result server.

8. The parallel digital acquisition and online judgment system for a digital circuit experimental box according to claim 1, characterized in that, The experimental configuration and authentication server includes: The authentication module receives authentication information such as device type, device identifier, and serial number, and returns an authorization identifier. The experiment configuration distribution module distributes the experiment configuration, including Config and Address, to the host computer. The logic type identification module distinguishes between combinational logic and sequential logic based on fields in the experimental configuration; and The channel number configuration module determines the number of channels N based on the length of the truth table and provides the host computer with further channel display configurations.

9. A method applied to the parallel digital acquisition and online judgment system according to any one of claims 1 to 8, characterized in that, Includes the following steps: S1: Establish hardware connections and complete power supply and reference configuration: Connect the parallel digital acquisition device to the digital circuit experimental box; S2: Complete device certification and receive experimental configuration: The host computer application establishes a communication connection with the experimental configuration and authentication server through the configuration receiving and authentication module, and the experimental configuration and authentication server sends the experimental configuration to the host computer application through the experimental configuration sending module. S3: Analyze the experimental configuration and determine the valid acquisition channels: The truth table parsing and channel determination module in the host computer application parses the truth table in the experimental configuration, parses the truth table into a multi-row target bit sequence, and determines the actual number of channels N used in this experiment based on the number of bits in a single-row target bit sequence. S4: Establish the communication and control relationship between the host computer application and the parallel digital acquisition device: The host computer application establishes a USBCDC virtual serial port communication with the communication transmission sub-component in the parallel digital acquisition device through the serial port communication module; the downlink command receiving module in the communication transmission sub-component is used to receive control commands from the host computer application, and the command buffer parsing module is used to write the received control commands into the buffer and parse them to avoid blocking the sampling task. S5: Detection sampling trigger condition: The MCU control sub-component in the parallel digital acquisition device serves as the core control unit, detecting the sampling trigger conditions. When the experiment is in combinational logic mode, the mode switching module responds to the sampling request instruction to trigger a sampling event. S6: Perform parallel digital acquisition and generate synchronous samples: After detecting the sampling trigger condition, the parallel sampling module in the MCU control sub-component immediately reads one or more GPIO input data registers and combines the reading results into 16-bit sample data to obtain the logic state of each input channel under this sampling event. S7: Perform a stabilization decision on the synchronized samples and obtain valid samples: The stability decision module in the MCU control sub-component performs validity determination on the synchronization sample to filter out invalid state changes caused by contact jitter, glitches or transient disturbances. Under the periodic sampling beat provided by the timing reference module, the stability decision module performs consistency comparison on the results of multiple consecutive samplings. When the results of I consecutive samplings are consistent, the current sample is determined to be a valid sample. S8: Construct a data frame and upload it to the host computer application: After obtaining a valid sample, the sample frame construction module in the communication transmission sub-component encapsulates the valid sample into a data frame and uploads it to the host computer application via the USB CDC virtual serial port through the uplink transmission module. S9: Perform local display and status prompts: During the sampling and uploading process, the display sub-component in the parallel digital acquisition device displays the sampling results locally; S10: Parse the data frame and perform logical judgment: After the host computer application receives the data frame, the frame synchronization and bit mapping module performs frame synchronization based on the frame header 0x5A and the frame tail 0x5B, recovers the logic state of each channel from the sample data field, and outputs the target bit sequence in the order of K_N to K1 to correspond to the order of the truth table column in the experimental configuration. S11: Record and submit the experimental results: The result recording and submission module in the host computer application records the target bit sequence corresponding to each row or state, and concatenates them in a predetermined order to form a result string; After the experiment is completed, the host computer application submits the result string to the result submission server, which receives the experimental results and returns submission feedback to complete the submission of the digital circuit experiment results.

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