A linearity enhancement module, a differential full inverter type amplifier and applications thereof

Abstract

The application relates to the field of wireless sensing, in particular to a linearity enhancement module, a differential full-inverter type amplifier and application thereof. The linearity enhancement module comprises inverters INV0 and INV1 and diodes D0 and D1; an input / output end of D0 is connected with an input end of INV0 and serves as a non-inverted input end IN+; an output / input end of D0 is connected with an output end of INV1; an input / output end of D1 is connected with an input end of INV1 and serves as an inverted input end IN-; and an output / input end of D1 is connected with an output end of INV0. The linearity enhancement module is applied to the differential full-inverter type amplifier, and two input ends are respectively connected with two output ends of a transconductance inverter in the amplifier. The application utilizes the non-linear term generated by the diode to offset the non-linear term generated by the main inverters INV0 and INV1, thereby solving the problems of input large-signal gain compression, mutual restriction of gain, noise and linearity of the multi-stage inverter structure amplifier.

Description

Technical Field

[0001] This invention relates to the field of integrated circuits, and in particular to a linearity enhancement module, a differential total inverter type amplifier, a baseband amplifier, and a millimeter-wave radar receiver. Background Technology

[0002] With the explosive growth of data centers and cloud computing, the demand for ultra-high-speed, low-power optical receiver front-end chips in fiber optic communication systems is becoming increasingly urgent. Similarly, high-bandwidth, high-gain, and low-noise baseband amplifiers are required in radio frequency millimeter-wave radar front-ends. As a core module of optical receivers and on-chip millimeter-wave radar, the bandwidth, gain, and linearity of transimpedance amplifiers are particularly important. In deep submicron and nanometer-scale CMOS processes, inverter-based amplifiers have become the preferred solution for achieving broadband, low-power designs due to their simple structure, high transconductance efficiency at low supply voltages, and quasi-differential characteristics.

[0003] However, traditional fully inverter amplifiers, while pursuing high bandwidth and high gain, face serious linearity constraints, mainly reflected in the following aspects: (1) Inherent nonlinear distortion of the transconductance stage: The core of the fully inverter amplifier is an inverter pair composed of PMOS and NMOS. When the input signal amplitude is large, the MOS transistor will enter the linear region from the saturation region, causing the transconductance to no longer be a constant, but a function of the input voltage fluctuation. This nonlinearity will cause the output signal to be compressed and distorted, resulting in serious harmonic distortion and third-order intermodulation distortion. (2) Swing limitation and power supply voltage reduction: With the evolution of the process technology, the power supply voltage continues to decrease, leaving extremely limited voltage swing space for the circuit. In the fully inverter structure, in order to ensure bandwidth, a large bias current is usually required, which further compresses the saturation voltage drop of the transistor. When the input signal amplitude increases, the output waveform is very likely to touch the power rail or ground rail, resulting in a serious deterioration of linearity. (3) Challenges of third-order transconductance nonlinearity: In differential or quasi-differential structures, although even harmonics can be canceled to some extent, odd harmonics are mainly affected by the third derivative of transconductance. Traditional inverter cascade structures lack effective elimination or compensation mechanisms, resulting in the continuous accumulation of nonlinear distortion after multiple amplification stages, which ultimately seriously affects the bit error rate performance of the system. (4) Mutual constraints between gain and linearity: In order to obtain high transimpedance gain, it is often necessary to increase the feedback resistor or increase the number of amplification stages, but this will reduce the closed-loop bandwidth and make the subsequent circuit more likely to enter the nonlinear region. In the existing multi-stage amplifier design, how to linearize the transconductance of the intermediate stage while ensuring high bandwidth is an urgent technical problem to be solved. Summary of the Invention

[0004] To address the problem that existing total inverter amplifiers cannot meet the stringent requirements for high linearity in high-performance optical communication systems and on-chip radar systems, this invention provides a linearity enhancement module, a differential total inverter amplifier, a baseband amplifier, and a millimeter-wave radar receiver.

[0005] The technical solution provided by this invention is as follows: A linearity enhancement module, in one embodiment of the present invention, includes two inverters INV0 and INV1 and two diodes D0 and D1. The input terminal of D0 is connected to the input terminal of INV0 and serves as the positive input terminal IN+; the output terminal of D0 is connected to the output terminal of INV1; the input terminal of D1 is connected to the input terminal of INV1 and serves as the negative input terminal IN-; the output terminal of D1 is connected to the output terminal of INV0.

[0006] In another embodiment of the present invention, it includes two inverters INV0 and INV1 and two diodes D0 and D1; the input terminal of D0 is connected to the output terminal of INV0 and serves as the positive input terminal IN+; the input terminal of D0 is connected to the output terminal of INV1; the output terminal of D1 is connected to the input terminal of INV1 and serves as the negative input terminal IN-; the input terminal of D1 is connected to the output terminal of INV0.

[0007] The linearity enhancement modules described above can be applied to differential fully inverting amplifiers to improve their linearity. In practical applications, IN+ and IN- are connected to the positive and negative output terminals of the transconductance amplifier, respectively.

[0008] As a further improvement of the present invention, inverter INV0 is composed of PMOS transistor M0 and NMOS transistor M1. The source of M0 is connected to VDD; the gates of M0 and M1 are connected and serve as the input terminal of INV0; the drains of M0 and M1 are connected and serve as the output terminal of INV0; the source of M1 is grounded. Inverter INV1 is composed of PMOS transistor M2 and NMOS transistor M3. The source of M2 is connected to VDD; the gates of M2 and M3 are connected and serve as the input terminal of INV1; the drains of M2 and M3 are connected and serve as the output terminal of INV1; the source of M3 is grounded.

[0009] As a further improvement of the present invention, diode D0 or D1 is constructed using an NMOS transistor; the drain of the NMOS transistor serves as the input terminal of D0 or D1; the source and gate of the NMOS transistor are connected and serve as the output terminal of D0 or D1.

[0010] The present invention also includes a differential fully inverting amplifier, which includes an amplifier body comprising multiple transconductance amplifiers Gm. It further includes at least one linearity enhancement module as described above; the positive input terminal IN+ and the negative input terminal IN- of the linearity enhancement module are respectively connected to the positive and negative output terminals of the same stage transconductance amplifier Gm in the amplifier body.

[0011] As a further improvement of the present invention, the amplifier body comprises three stages connected in series. The first stage comprises a first transimpedance amplifier TIA1 and a transconductance amplifier Gm connected in series; the second stage comprises a second transimpedance amplifier TIA2 and a transconductance amplifier Gm connected in series; and the third stage comprises a second transimpedance amplifier TIA2 and a buffer connected in series. A linearity enhancement module (LEC) is connected between the positive and negative output terminals of Gm in the second stage; Gm in each stage employs a gain-adjustable transconductance amplifier.

[0012] As a further improvement of the present invention, in the first stage, the first transimpedance amplifier includes one amplifier OP0 and two resistors R0 and R1. R0 is connected between the positive input terminal and the positive output terminal of OP0, and R1 is connected between the negative input terminal and the negative output terminal of OP0.

[0013] As a further improvement of the present invention, in the second and third stages, the second transimpedance amplifier TIA2 includes one amplifier OP1, four resistors R2 to R5, and four capacitors C1 to C4. One end of C1 and R2 is connected and serves as the positive input port Vin+ of TIA2, and the other end of C1 is grounded. The other end of R2, along with the other ends of C2 and R3, is connected to the positive input terminal of OP1. The other ends of C2 and R3 are connected to the positive output terminal of OP1 and serve as the positive output terminal Vout+ of TIA2. One end of C4 and R4 is connected and serves as the negative input port Vin- of TIA2, and the other end of C3 is grounded. The other end of R4, along with the other ends of C4 and R5, is connected to the negative input terminal of OP1. The other ends of C4 and R5 are connected to the negative output terminal of OP1 and serve as the negative output terminal Vout- of TIA2.

[0014] Alternatively, in the second and third stages, the second transimpedance amplifier TIA2 includes one amplifier OP2, four resistors R6-R9, and four capacitors C5-C8. One end of C5, R6, and R7 is connected and serves as the positive input port Vin+ of TIA2; the other end of C5 is grounded; and the other end of R6 and one end of C6 are connected to the positive input port of OP2. The other ends of R7 and C6 are connected to the positive output port of OP2 and serve as the positive output port Vout+ of TIA2. One end of C7, R8, and R9 is connected and serves as the negative input port Vin- of TIA2; the other end of C7 is grounded; and the other end of R8 and one end of C8 are connected to the negative input port of OP2. The other ends of R9 and C8 are connected to the negative output port of OP2 and serve as the negative output port Vout- of TIA2.

[0015] The present invention also includes a baseband amplifier that employs the differential total inverter type amplifier as described above.

[0016] The present invention also includes a millimeter-wave radar receiver that employs the baseband amplifier as described above.

[0017] The present invention has the following beneficial effects: I. Significantly Improved System Linearity and Dynamic Range: This invention introduces a linearity enhancement circuit into the intermediate transconductance stage of a multi-stage amplifier structure, utilizing the positive third-order transconductance component generated by the cross-coupled compensation transistor to cancel the negative third-order nonlinear component generated by the main path inverter. This "nonlinear cancellation technique" can significantly extend the linear input voltage range of the transconductance stage, greatly improving the amplifier's 1dB compression point and third-order intermodulation intercept point, effectively solving the problem of waveform compression that easily occurs in traditional full inverters under large signal input.

[0018] II. Adaptation to Low Power Supply Voltage Processes and Optimized Voltage Margin: Traditional linearization techniques (such as source degradation resistors) typically consume additional DC voltage drops, making it difficult to operate in deep submicron and nanometer-scale low-voltage processes. This invention employs an inverter-based stacked structure with cross-coupling compensation, without introducing additional series voltage drop components, maximizing the utilization of rail-to-rail voltage margin, and maintaining excellent linearity performance even at power supply voltages of 1.0V or even lower.

[0019] Third, performance optimization is achieved without significantly increasing power consumption: The fully inverter architecture used in this invention has extremely high transconductance efficiency. Linearization compensation via the LEC module requires only a very small auxiliary transistor or a tiny bias current to achieve a significant linearity gain. Compared to traditional methods that rigidly improve linearity by increasing quiescent current, this invention has a significant advantage in maintaining low power consumption characteristics, meeting the requirements of green data centers for low-power optical receiver chips.

[0020] Fourth, it enhances support for higher-order modulation formats: In higher-order modulation formats such as PAM4, the signal is extremely sensitive to the linearity of the signal level. This invention effectively suppresses the nonlinear distortion accumulated during the successive amplification process of the signal through in-situ linearization processing in a multi-stage cascaded architecture, reduces the asymmetry of the eye diagram, and thus significantly reduces the system bit error rate and improves the reliability of the communication link.

[0021] V. Excellent process robustness and common-mode rejection capability: The fully differential symmetric structure of this invention, combined with the cross-coupled LEC module, can naturally cancel even-order harmonic distortion (HD2) and has strong suppression capability for substrate noise and power supply noise. At the same time, this structure has strong tolerance to changes in process, voltage, and temperature (PVT) and is easy to implement in large-scale integrated circuits.

[0022] VI. Balancing High Gain and Wide Bandwidth: Since the LEC module achieves linearization by reducing gain through transconductance compensation rather than negative feedback, this invention can provide high transimpedance gain while maintaining high closed-loop bandwidth, effectively alleviating the mutual constraints between bandwidth, gain and linearity in traditional amplifier design. Attached Figure Description

[0023] Figure 1 This is a circuit schematic diagram of one type of linearity enhancement module provided in Embodiment 1 of the present invention.

[0024] Figure 2 A circuit schematic diagram of one type of linearity enhancement module provided in Embodiment 1 of the present invention.

[0025] Figure 3 for Figure 1 Detailed circuit diagram of the linearity enhancement module.

[0026] Figure 4 for Figure 2 Detailed circuit diagram of the linearity enhancement module.

[0027] Figure 5 This is a circuit diagram of a three-stage differential fully inverting amplifier in Embodiment 2 of the present invention.

[0028] Figure 6 This is a circuit diagram of a differential fully inverting amplifier that incorporates a linearity enhancement module in Embodiment 2 of the present invention.

[0029] Figure 7 for Figure 6 The circuit diagram of the first transimpedance amplifier used in the circuit shown.

[0030] Figure 8 for Figure 6 The circuit diagram shown is for one type of second transimpedance amplifier used in the circuit.

[0031] Figure 9 for Figure 6 The circuit diagram shows another type of second transimpedance amplifier used in the circuit shown.

[0032] Figure 10 To test the gain curves of each circuit as a function of the input signal at different gain levels in the experiment. Detailed Implementation

[0033] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0034] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the specification of this invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "or / and" as used herein includes any and all combinations of one or more of the associated listed items.

[0035] Example 1

[0036] To address the issues of input large-signal gain compression and the trade-offs between gain, noise, and linearity in multi-stage inverter amplifiers, this embodiment provides a linearity enhancement module, such as... Figure 1 As shown, in one typical embodiment, it includes two inverters INV0 and INV1 and two diodes D0 and D1. The input terminal of D0 is connected to the input terminal of INV0 and serves as the positive input terminal IN+; the output terminal of D0 is connected to the output terminal of INV1; the input terminal of D1 is connected to the input terminal of INV1 and serves as the negative input terminal IN-; the output terminal of D1 is connected to the output terminal of INV0. Figure 2 As shown, in another typical scheme of this embodiment, it includes two inverters INV0 and INV1 and two diodes D0 and D1; the input terminal of D0 is connected to the output terminal of INV0 and serves as the positive input terminal IN+; the input terminal of D0 is connected to the output terminal of INV1; the output terminal of D1 is connected to the input terminal of INV1 and serves as the negative input terminal IN-; the input terminal of D1 is connected to the output terminal of INV0.

[0037] The only difference between the two circuit schemes is the orientation of diodes D0 and D1; their conduction directions are opposite. The linearity enhancement modules for both schemes can be applied to differential fully inverting amplifiers to improve their linearity. In practical applications, IN+ and IN- are connected to the positive and negative output terminals of the transconductance amplifier, respectively.

[0038] The linearity enhancement module provided in this embodiment can use the nonlinear terms generated by diodes D0 and D1 to cancel the nonlinear terms generated by the main inverter on INV0 and INV2. In traditional inverters, the transconductance decreases with increasing input voltage when a large input signal is received, mainly due to the negative value of the third-order nonlinear coefficient. Through cross-coupling, D0 is controlled by (IN+), but its current is injected into the output terminal of (IN-). Since the differential signals are out of phase, the current generated by D0 has a compensating effect relative to the main path current. By precisely adjusting the dimensions of D0 and D1, a positive gain that increases with power can be generated, thereby neutralizing the negative gain that increases with power from the main amplifying transistors (composed of INV0 and INV1). This "derivative combination" or "cross-coupling compensation" technique can significantly extend the linear input range of the transconductance stage, thereby improving the overall amplifier's 1dB compression point and IIP3 performance.

[0039] In practical applications of this embodiment, such as Figure 3 and Figure 4 As shown, inverter INV0 is composed of PMOS transistor M0 and NMOS transistor M1. The source of M0 is connected to VDD; the gates of M0 and M1 are connected and serve as the input terminal of INV0; the drains of M0 and M1 are connected and serve as the output terminal of INV0; the source of M1 is grounded. Inverter INV1 is composed of PMOS transistor M2 and NMOS transistor M3. The source of M2 is connected to VDD; the gates of M2 and M3 are connected and serve as the input terminal of INV1; the drains of M2 and M3 are connected and serve as the output terminal of INV1; the source of M3 is grounded. Diode D0 or D1 is composed of NMOS transistors; the drain of the NMOS transistor serves as the input terminal of D0 or D1; the source and gate of the NMOS transistor are connected and serve as the output terminal of D0 or D1.

[0040] When the diode's input terminal and the inverter's input terminal are connected according to... Figure 3 When the circuit structure is connected, the signal input to the diode is not amplified by the inverter, so the gain compensation effect occurs when the input power is high. The input terminal and the output terminal of the inverter are connected according to... Figure 4 When the circuit structure is connected, the signal input to the diode is amplified by the inverter, making the signal power required for the diode to conduct less, and the gain compensation effect is better than that of the inverter. Figure 3 The connection method mentioned above occurs when the input power is relatively low.

[0041] Example 2

[0042] Based on the scheme in Example 1, such as Figure 5 As shown, this embodiment further provides a differential fully inverting amplifier, which includes an amplifier body comprising multiple transconductance amplifiers Gm. It also includes at least one linearity enhancement module as shown in Embodiment 1; the positive input terminal IN+ and the negative input terminal IN- of the linearity enhancement module are respectively connected to the positive and negative output terminals of the same stage transconductance amplifier Gm in the amplifier body.

[0043] Figure 5 The amplifier body shown comprises three stages connected in series. The first stage includes a first transimpedance amplifier TIA1 and a transconductance amplifier Gm connected in series; the second stage includes a second transimpedance amplifier TIA2 and a transconductance amplifier Gm connected in series; and the third stage includes a second transimpedance amplifier TIA2 and a buffer connected in series. Figure 5 In the three-stage total inverting amplifier shown, when only one linearity enhancement module (LEC) is included, as... Figure 6 As shown, it can be connected between the positive and negative output terminals of Gm in the second stage. In each stage, Gm employs a gain-adjustable transconductance amplifier.

[0044] In a typical solution of this embodiment, such as Figure 7 As shown, the first transimpedance amplifier TIA in the first stage includes one amplifier OP0 and two resistors R0 and R1. R0 is connected between the positive input and positive output terminals of OP0, and R1 is connected between the negative input and negative output terminals of OP0. In the second and third stages, the second transimpedance amplifier TIA2 can be a novel 2-Order TIA consisting of one amplifier, four resistors, and four capacitors, such as... Figure 8 As shown, the second transimpedance amplifier may include one amplifier OP1, four resistors R2 to R5, and four capacitors C1 to C4. One end of C1 and R2 is connected and serves as the positive input port Vin+ of TIA2, and the other end of C1 is grounded. The other end of R2, along with the other ends of C2 and R3, is connected to the positive input port of OP1. The other ends of C2 and R3 are connected to the positive output port of OP1, serving as the positive output port Vout+ of TIA2. One end of C4 and R4 is connected and serves as the negative input port Vin- of TIA2, and the other end of C3 is grounded. The other end of R4, along with the other ends of C4 and R5, is connected to the negative input port of OP1. The other ends of C4 and R5 are connected to the negative output port of OP1, serving as the negative output port Vout- of TIA2.

[0045] In another option, such as Figure 9As shown, the second transimpedance amplifier TIA2 includes one amplifier OP2, four resistors R6-R9, and four capacitors C5-C8. One end of C5, R6, and R7 is connected and serves as the positive input port Vin+ of TIA2. The other end of C5 is grounded, and the other end of R6 and one end of C6 are connected to the positive input port of OP2. The other ends of R7 and C6 are connected to the positive output port of OP2 and serve as the positive output port Vout+ of TIA2. One end of C7, R8, and R9 is connected and serves as the negative input port Vin- of TIA2. The other end of C7 is grounded, and the other end of R8 and one end of C8 are connected to the negative input port of OP2. The other ends of R9 and C8 are connected to the negative output port of OP2 and serve as the negative output port Vout- of TIA2.

[0046] Figure 8 and Figure 9 The improved 2-Order TIA shown can filter high-frequency input harmonics by adding an RC filter to the input of the TIA; the size of the capacitor used to eliminate out-of-band interference determines the input impedance and voltage fluctuation range of the TIA input.

[0047] Building upon the differential fully inverting amplifier with an enhanced linearity module described above, this embodiment further provides a baseband amplifier that employs the aforementioned differential fully inverting amplifier. In practical applications, this embodiment also provides a millimeter-wave radar receiver that utilizes the aforementioned baseband amplifier.

[0048] In summary, the differential fully inverter amplifier provided in this embodiment introduces an in-situ linearization architecture. Unlike traditional compensation performed in the first or last stage of the amplifier, this embodiment embeds an LEC module in the intermediate Gm stage of the multi-stage amplifier link. This effectively suppresses the accumulation of nonlinearity generated during signal amplification and prevents the signal from entering the saturation region under large swings. The LEC module uses a cross-coupling cancellation mechanism to enhance linearity, the core of which lies in the cross-coupling connection of auxiliary transistors (D0, D1). By connecting the gate and drain of D0 / D1 to the input terminal and the source to the output terminal of the opposite path (or connecting the gate and drain of D0 / D1 to the output terminal and the source to the input terminal of the opposite path), a current with opposite phase and nonlinear characteristics to the main path is generated, thereby achieving precise neutralization of the third-order nonlinear coefficient. In the optimal solution of this embodiment, the LEC module is entirely based on MOSFET stacking, without relying on resistor degradation or large inductors, which perfectly matches the low-voltage and high-speed characteristics of the fully inverter amplifier and has better compatibility with the fully inverter architecture.

[0049] Performance testing To verify the features provided by this invention, Figure 6The circuit performance of the differential fully inverting amplifier shown was simulated and tested by technicians on a 22nm CMOS process.

[0050] During the experiment, respectively compared with the method used Figure 3 and Figure 4 The fully inverting amplifier of the linearity enhancement module shown is used as the experimental group. Figure 5 The fully inverting amplifier without a linearity enhancement module is shown as a control group. The gain of the circuit varies with the input signal power for three different circuit designs using different gain levels of Gm. The results are as follows: Figure 10 The test results are shown.

[0051] The simulation method in this experiment involves inputting signals of different magnitudes into the overall transconductance amplifier and measuring its gain. Figure 10 The solid lines represent test results at different gain levels without an LEC circuit, while the dashed lines represent results with an LEC circuit. Figure 3 Test results for the intermediate structure. The dotted solid line indicates the LEC structure. Figure 4 Test results for the medium structure. Analysis of the data in the graph shows that: When the LEC module is not used, the gain decreases rapidly with increasing input power; when it is used... Figure 3 When using the LEC structure, the gain first increases and then decreases with increasing input power, improving linearity and increasing the 1dB compression point; when using Figure 4 When the structure is in LEC, the gain also increases with the increase of the input signal, but the point of increase is relatively lower than that of the LEC. Figure 3 The structure appears earlier.

[0052] The above-described embodiments are merely one implementation of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the inventive concept, and these all fall within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the appended claims.

Claims

1. A linearity enhancement module, characterized in that, It includes two inverters, INV0 and INV1, and two diodes, D0 and D1; The input terminal of D0 is connected to the input terminal of INV0 and serves as the positive input terminal IN+; the output terminal of D0 is connected to the output terminal of INV1; the input terminal of D1 is connected to the input terminal of INV1 and serves as the negative input terminal IN-; the output terminal of D1 is connected to the output terminal of INV0. Alternatively, the input of D0 can be connected to the output of INV0 and used as the positive input IN+; the input of D0 can be connected to the output of INV1; the output of D1 can be connected to the input of INV1 and used as the negative input IN-; the input of D1 can be connected to the output of INV0. The linearity enhancement module is applied to a differential total inverter type amplifier, with IN+ and IN- connected to the positive and negative output terminals of the transconductance amplifier in the differential total inverter type amplifier, respectively.

2. The linearity enhancement module according to claim 1, characterized in that: The inverter INV0 is composed of a PMOS transistor M0 and an NMOS transistor M1; the source of M0 is connected to VDD; the gates of M0 and M1 are connected and serve as the input terminal of INV0; the drains of M0 and M1 are connected and serve as the output terminal of INV0; the source of M1 is grounded. The inverter INV1 is composed of a PMOS transistor M2 and an NMOS transistor M3; the source of M2 is connected to VDD; the gates of M2 and M3 are connected and serve as the input of INV1; the drains of M2 and M3 are connected and serve as the output of INV1; the source of M3 is grounded.

3. The linearity enhancement module according to claim 2, characterized in that: Diodes D0 or D1 are constructed using NMOS transistors; the drain of the NMOS transistor serves as the input terminal of D0 or D1; the source and gate of the NMOS transistor are connected and serve as the output terminal of D0 or D1.

4. A differential total inverting amplifier, comprising an amplifier body, wherein the amplifier body includes multiple transconductance amplifiers Gm, characterized in that: It also includes at least one linearity enhancement module as described in any one of claims 1-3; the positive input terminal IN+ and the negative input terminal IN- of the linearity enhancement module are respectively connected to the positive output terminal and the negative output terminal of the same stage transconductance amplifier Gm in the amplifier body.

5. The differential total inverter amplifier according to claim 4, characterized in that: The amplifier body comprises three stages connected in series. The first stage comprises a first transimpedance amplifier TIA1 and a transconductance amplifier Gm connected in series. The second stage comprises a second transimpedance amplifier TIA2 and a transconductance amplifier Gm connected in series. The third stage comprises a second transimpedance amplifier TIA2 and a buffer connected in series. The linearity enhancement module is connected between the positive and negative output terminals of Gm in the second stage.

6. The differential fully inverting amplifier according to claim 5, characterized in that: In each stage, Gm uses a gain-adjustable transconductance amplifier.

7. The differential fully inverting amplifier according to claim 5, characterized in that: In the first stage, the first transimpedance amplifier includes an amplifier OP0 and two resistors R0 and R1; R0 is connected between the positive input terminal and the positive output terminal of OP0, and R1 is connected between the negative input terminal and the negative output terminal of OP0.

8. The differential total inverter amplifier according to claim 5, characterized in that: In the second and third stages, the second transimpedance amplifier TIA2 includes one amplifier OP1, four resistors R2 to R5, and four capacitors C1 to C4; one end of C1 and R2 is connected and serves as the positive input port Vin+ of TIA2, and the other end of C1 is grounded; the other end of R2 and the other ends of C2 and R3 are connected to the positive input port of OP1; the other ends of C2 and R3 are connected to the positive output port of OP1 and serve as the positive output port Vout+ of TIA2; one end of C4 and R4 is connected and serves as the negative input port Vin- of TIA2, the other end of C3 is grounded, the other end of R4 and the other ends of C4 and R5 are connected to the negative input port of OP1, and the other ends of C4 and R5 are connected to the negative output port of OP1 and serve as the negative output port Vout- of TIA2; Alternatively, in the second and third stages, the second transimpedance amplifier TIA2 includes one amplifier OP2, four resistors R6 to R9, and four capacitors C5 to C8; one end of C5, R6, and R7 is connected and serves as the positive input port Vin+ of TIA2, the other end of C5 is grounded, and the other end of R6 and one end of C6 are connected to the positive input port of OP2; the other ends of R7 and C6 are connected to the positive output port of OP2 and serve as the positive output port Vout+ of TIA2; one end of C7, R8, and R9 is connected and serves as the negative input port Vin- of TIA2, the other end of C7 is grounded, and the other end of R8 and one end of C8 are connected to the negative input port of OP2; the other ends of R9 and C8 are connected to the negative output port of OP2 and serve as the negative output port Vout- of TIA2.

9. A baseband amplifier, characterized in that: It employs a differential total inverter amplifier as described in any one of claims 5-8.

10. A millimeter-wave radar receiver, characterized in that: It employs the baseband amplifier as described in claim 9.

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