A phased array control chip with beam sweep accelerator

Abstract

This invention discloses a phased array control chip with a beam scanning accelerator, belonging to the field of phased array control technology. The invention includes a CORDIC unit, an amplitude weighting unit, a weight synthesis unit, a weight distribution unit, a configuration interface, and an instruction parser. The CORDIC unit calculates the phase offset based on the target azimuth and elevation angles; the amplitude weighting unit calculates the amplitude weighting coefficients; the weight synthesis unit synthesizes complex weights; the weight distribution unit distributes the weights to each transceiver channel; and the instruction parser parses the main processor instructions and initiates the calculation process. This invention achieves rapid beam weight calculation through a dedicated hardware accelerator, reducing the main processor's CPU utilization by more than 90%; the calculation latency is less than 1μs, and the total weight distribution time is less than 3μs, meeting the requirements of high-speed beam tracking; it supports flexible configuration of multiple amplitude weighting functions; and the power consumption is only 50mW. This invention is suitable for large-scale phased array systems, significantly improving system response speed and reducing the main processor load.

Description

Technical Field

[0001] This invention relates to the field of phased array control technology, and more specifically to a phased array control chip with a beam scanning accelerator, particularly a chip that integrates a dedicated hardware accelerator for rapidly calculating beam pointing weights and reducing the burden on the main processor, suitable for large-scale phased array systems. Background Technology

[0002] Phased array antennas achieve beam scanning by adjusting the amplitude and phase of each channel. Calculating beam weights involves numerous trigonometric function operations and complex number multiplications, placing high demands on the main processor's computing power. Especially in low-Earth orbit satellite communication scenarios, the beam needs to rapidly track high-speed moving satellites, with weight update frequencies reaching kHz levels. If calculated by the main processor software, this would consume significant CPU resources, leading to increased system response latency and power consumption.

[0003] Existing solutions typically use lookup tables to pre-store beam weights, but this is inflexible and cannot adapt to dynamically changing beam pointing requirements. This invention proposes a phased array control chip with a beam scanning accelerator, which achieves rapid beam weight calculation through dedicated hardware circuitry, significantly reducing the burden on the main processor. Summary of the Invention

[0004] The purpose of this invention is to solve the technical problems of excessive main processor resources, large response delay, and poor flexibility in beam weight calculation in existing phased array systems. It provides a phased array control chip with a beam scanning accelerator, which realizes rapid calculation and distribution of weights through a dedicated hardware acceleration architecture, taking into account computational efficiency, flexibility, and low power consumption.

[0005] The phased array control chip of this invention adopts a dedicated hardware accelerator architecture, integrating a CORDIC unit, an amplitude weighting unit, a weight synthesis unit, a weight distribution unit, a configuration interface, and an instruction parser. These units work together to calculate and distribute beam weights. The configuration interface uses the SPI communication protocol, serving as a communication bridge between the chip and the main processor. It receives beam pointing instructions from the main processor, which include core parameters such as target ID, azimuth angle, elevation angle, window function type, and sidelobe level.

[0006] The command parser interfaces with the configuration interface to quickly parse beam pointing commands and generate control signals, initiating the weighting calculation process. The CORDIC unit employs a 16-stage pipelined parallel structure, calculating the phase offset of each phased array antenna element relative to the reference point based on the target azimuth and elevation angles in the command. The single-beam calculation delay is less than 1μs, supporting rapid calculation of continuous multi-beam pointing. The amplitude weighting unit incorporates multiple parallel lookup tables, pre-stores commonly used window function coefficients such as Taylor weighting, Chebyshev weighting, and Hamming weighting, and dynamically selects the window function type and sidelobe level according to the command, outputting the amplitude weighting coefficients of each antenna element to adapt to different beam performance requirements.

[0007] The weight synthesis unit uses a high-speed complex multiplier to synthesize the phase offset output from the CORDIC unit and the amplitude weighting coefficients output from the amplitude weighting unit into a complex weight, calculated as W_ij = A_ij * exp (j*Δφ_ij). It supports synchronous output of either I or Q signals to ensure the accuracy of the weight calculation. The weight distribution unit uses an LVDS high-speed serial interface with a data rate greater than or equal to 1Gbps, distributing the synthesized complex weights to the phase shifters and attenuators of each transceiver channel of the phased array at high speed and synchronously. The total time from receiving the command to completing the weight distribution is less than 3μs.

[0008] This chip is manufactured using 40nm or more advanced CMOS technology, with a power consumption of only 50mW in a 256-channel configuration. It can integrate adaptive calibration function and superimpose channel error correction values ​​to improve beam pointing accuracy. It can also achieve synchronous calculation of multi-beam weights by expanding multiple sets of CORDIC units and amplitude weighting units, further improving system throughput. It is suitable for high-speed beam scanning and tracking scenarios in large-scale phased array systems. Attached Figure Description

[0009] Figure 1 This is a diagram showing the overall architecture of a phased array control chip with a beam scanning accelerator.

[0010] Figure 2 This is a diagram of the CORDIC unit pipeline structure.

[0011] Figure 3 This is a flowchart illustrating the workflow of weight calculation and distribution for phased array control chips. Figure 4 This is a schematic diagram of the overall architecture of the phased array control chip. Detailed Implementation

[0012] The invention will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale. Furthermore, some well-known parts may not be shown in the drawings.

[0013] Many specific details of the invention, such as the structure, materials, dimensions, processing methods, and techniques of the devices, are described below to provide a clearer understanding of the invention. However, as those skilled in the art will understand, the invention may be implemented without following these specific details.

[0014] Figure 1 The diagram shows the overall architecture of a phased array control chip with a beam scanning accelerator.

[0015] like Figure 1 As shown, the phased array control chip 100 of the present invention includes a configuration interface 101, an instruction parser 102, a CORDIC unit 103, an amplitude weighting unit 104, a weight synthesis unit 105, and a weight distribution unit 106. Configuration interface 101 uses the SPI communication protocol to receive beam pointing commands from the main processor. The command format is {target ID, azimuth θ, elevation φ, window function type, sidelobe level}. Command parser 102 interfaces with configuration interface 101, parses the commands, generates control signals, and synchronously sends them to CORDIC unit 103 and amplitude weighting unit 104 to start the weight calculation process. CORDIC unit 103 calculates the phase offset Δφ_ij based on azimuth θ and elevation φ, and amplitude weighting unit 104 outputs the amplitude weighting coefficient A_ij based on window function type and sidelobe level. The two signals are synchronously input to weight synthesis unit 105. Weight synthesis unit 105 synthesizes the complex weights W_ij through a complex multiplier and outputs them to weight distribution unit 106. Weight distribution unit 106 uses LVDS high-speed serial interface to distribute the complex weights to each transceiver channel 107 of the phased array, realizing the parameter configuration of each channel's phase shifter and attenuator.

[0016] Figure 2 shows a schematic diagram of the CORDIC unit pipeline structure.

[0017] As shown in Figure 2, the CORDIC unit 103 in this invention adopts a 16-stage pipelined parallel structure with a working clock of 200MHz and a single-stage pipeline clock period of 5ns. The input of the CORDIC unit 103 receives the target azimuth angle θ and elevation angle φ signals. Each pipeline stage is equipped with a micro-rotation processing module 1031, which integrates core components such as adders and shifters, and performs trigonometric function calculations through iterative micro-rotation operations. The 16-stage pipeline sequentially completes signal preprocessing, iterative calculations, and result output, ultimately outputting the phase offset Δφ_ij of each antenna element relative to the reference point. For a 256-channel phased array system, this unit can complete the phase offset calculation of all channels in parallel within one clock cycle, with a total calculation delay of 80ns (less than 1μs), meeting the real-time requirements of high-speed beam tracking.

[0018] Figure 3 shows the workflow of weight calculation and distribution for the phased array control chip.

[0019] As shown in Figure 3, the complete workflow timing of the chip in this invention is as follows: At time t0, the main processor issues a beam pointing command through the configuration interface 101; 0.5μs after t0, the command parser 102 completes command parsing, generates control signals, and starts the calculation process; 0.58μs after t0, the CORDIC unit 103 completes the phase offset calculation of all antenna elements in the 256 channels and outputs Δφ_ij to the weight synthesis unit 105; 0.6μs after t0, the amplitude weighting unit 104 completes the amplitude weighting coefficient calculation and outputs A_ij to the weight synthesis unit 105; 0.7μs after t0, the weight synthesis unit 105 completes the complex weight synthesis and outputs W_ij to the weight distribution unit 106; 2.7μs after t0, the weight distribution unit 106 transmits the signal to the LVDS... The interface completes the weight distribution of all transmit and receive channels; t0 plus 2.8μs, the chip sends a completion interrupt to the main processor, and the total time of the entire process is 2.8μs (less than 3μs), which is far better than the software implementation scheme (usually greater than 100μs).

[0020] The chip in this embodiment is manufactured using a 40nm CMOS process, with a chip size of 2mm × 2mm and a power consumption of 50mW in full-operation mode with 256 channels. During operation, the main processor sends beam pointing commands via the SPI interface. The command parser quickly parses the commands and initiates the calculation process. The CORDIC unit calculates the phase offset in parallel through a 16-stage pipeline. The amplitude weighting unit retrieves preset window function coefficients and outputs amplitude weighting coefficients. These two coefficients are then combined by the weight synthesis unit into complex weights, which are distributed to each transceiver channel via the LVDS high-speed interface, enabling rapid updates of beam weights. This chip reduces the CPU utilization of the main processor by more than 90%, and the calculation latency and total distribution time meet the requirements for kHz-level weight updates, making it suitable for high-speed beam tracking scenarios in large-scale phased array systems such as low-Earth orbit satellite communications.

[0021] In this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus.

[0022] In this invention, the embodiments do not exhaustively describe all details, nor are they intended to limit the invention to the specific embodiments described. Many variations can be made based on the above description. These embodiments have been selected and specifically described in this specification to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to effectively utilize the invention and make modifications based on it. This invention is limited only by the claims and their full scope and equivalents.

Claims

1. A phased array control chip with a beam scanning accelerator, characterized in that, The chip is a dedicated hardware accelerator architecture, integrating a CORDIC unit, an amplitude weighting unit, a weight synthesis unit, a weight distribution unit, a configuration interface, and an instruction parser. The configuration interface receives beam pointing instructions from the main processor, the instruction parser parses the instructions and initiates the weight calculation process, the CORDIC unit calculates the phase offset, the amplitude weighting unit calculates the amplitude weighting coefficients, the weight synthesis unit combines the two into complex weights, and the weight distribution unit distributes the complex weights to each transceiver channel of the phased array. The chip is manufactured using a 40nm or more advanced CMOS process, and the power consumption is less than or equal to 50mW with 256 channels.

2. The phased array control chip with a beam scanning accelerator according to claim 1, characterized in that, The CORDIC unit is a 16-stage pipeline structure that supports continuous multi-beam pointing fast parallel calculation. Based on the input target azimuth and elevation angles, it calculates the phase offset of each antenna element relative to the reference point, with a single-beam phase offset calculation delay of less than 1μs.

3. The phased array control chip with a beam scanning accelerator according to claim 1, characterized in that, The amplitude weighting unit has multiple built-in parallel lookup tables that pre-store window function coefficients such as Taylor weighting, Chebyshev weighting, and Hamming weighting. It can dynamically select the window function type and sidelobe level according to the instruction and output the amplitude weighting coefficients of each antenna element.

4. The phased array control chip with a beam scanning accelerator according to claim 1, characterized in that, The weight synthesis unit is implemented through a complex multiplier, which synthesizes the phase offset output by the CORDIC unit and the amplitude weighting coefficient output by the amplitude weighting unit into a complex weight W_ij = A_ij * exp (j*Δφ_ij), supporting synchronous output of I or Q signals.

5. The phased array control chip with a beam scanning accelerator according to claim 1, characterized in that, The configuration interface adopts the SPI communication protocol, and the received beam pointing command includes target ID, azimuth angle, elevation angle, window function type, and sidelobe level parameters; the weight distribution unit adopts the LVDS high-speed serial interface with a data rate greater than or equal to 1Gbps, and the total time from receiving the command to completing the weight distribution is less than 3μs.

6. The phased array control chip with a beam scanning accelerator according to claim 1, characterized in that, The chip can integrate adaptive calibration function, superimpose pre-measured channel error correction values ​​on the basis of weight calculation, calibrate the complex weights and redistribute them to improve beam pointing accuracy; it can also realize synchronous calculation of multi-beam weights through the parallel architecture of multiple sets of CORDIC units and amplitude weighting units.

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