Port identification method in a computing device and computing device

Abstract

This application relates to the field of computer technology, providing a port identification method and a computing device. It is applied to a computing device with a BMC, a pass-through card, and a hard disk backplane. The method includes: the BMC writing first identification information of a first target port into the pass-through card; the pass-through card sending the first identification information to the hard disk backplane through the first target port; the hard disk backplane generating a first mapping relationship based on the first identification information and a second target port receiving the first identification information; and the BMC determining a second mapping relationship based on the first mapping relationship read from the hard disk backplane, the second mapping relationship including the correspondence between the first target port and the second target port. Based on this solution, the BMC in the computing device automatically identifies the connection relationship between the hard disk backplane and the pass-through card by multiplexing the port matching information transmitted by the loading signal between the pass-through card and the hard disk backplane, thereby improving the efficiency and accuracy of the computing device in identifying hard disk connection ports.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a port identification method and a computing device. Background Technology

[0002] As server architecture has evolved, the Platform Controller Hub (PCH), which provides storage control functions for servers, has been replaced by pass-through cards. These cards enable protocol conversion between Peripheral Component Interconnect Express (PCIe) and Serial Advanced Technology Attachment (SATA). The pass-through cards can internally manage the hard drives they connect to, enabling low-level hardware control and status monitoring.

[0003] Typical hard drive identification methods require using pulse-width modulation (PWM) signals to identify the hard drive's location, or using a Baseboard Manager Controller (BMC) to sequentially activate each hard drive to confirm the mapping relationship between the hard drive and the port on the pass-through card.

[0004] However, in scenarios with a large number of hard drives or where hard drives are frequently replaced, the server's reliance on sending PWM signals or using BMC to illuminate LEDs one by one presents problems such as complex operation, long processing time, and susceptibility to interference, making it difficult to quickly and accurately update the relationship between the hard drives and their connection ports. Summary of the Invention

[0005] This application provides a port identification method and a computing device, which can automatically identify and map the connection relationship between a hard drive and a pass-through card, thereby improving the efficiency and accuracy of the computing device in identifying hard drive connection ports.

[0006] To achieve the above objectives, the embodiments of this application adopt the following technical solutions: In a first aspect, embodiments of this application provide a port identification method in a computing device. The computing device includes a hard disk backplane, a pass-through card, and a baseboard control manager (BMC). The BMC is connected to the hard disk backplane and the pass-through card, respectively. The method includes: the BMC writing first identification information of a first target port into the pass-through card, the pass-through card including a first port, the first port including a first target port; the pass-through card sending the first identification information to the hard disk backplane through the first target port; the hard disk backplane generating a first mapping relationship based on the first identification information and a second target port receiving the first identification information; the first mapping relationship including the correspondence between the first identification information and the second target port, the hard disk backplane being connected to the first target port through the second target port; and the BMC determining a second mapping relationship based on the first mapping relationship read from the hard disk backplane, the second mapping relationship including the correspondence between the first target port and the second target port.

[0007] Based on this solution, the BMC in the computing device can transmit port matching information through the load signal between the pass-through card and the hard drive backplane. Without additional wiring or complex operations, it can automatically identify the connection relationship between the hard drive backplane and the pass-through card, thereby improving the efficiency and accuracy of the computing device in identifying hard drive connection ports.

[0008] In one possible implementation, the pass-through card includes a first complex programmable logic device (CPLD), and the BMC writes the first identification information of the first target port into the pass-through card, including: the BMC writing the first identification information into the first CPLD.

[0009] Based on this solution, BMC can use the first CPLD in the pass-through card to store the first identification information, providing a stable data source for subsequent SGPIO signal generation; at the same time, it supports dynamic refresh and fault tolerance verification, significantly improving the accuracy of the port identification process.

[0010] In another possible implementation, the BMC writes the first identification information of the first target port into the pass-through card, and also includes: the BMC generating the first identification information corresponding to the first target port based on preset rules.

[0011] Based on this solution, BMC can uniformly generate unique first identification information through preset rules, making the identification of each first target port traceable, which facilitates subsequent fault location and operation and maintenance management.

[0012] In another possible implementation, the BMC generates first identification information corresponding to the first target port based on preset rules, including: the BMC reads the register corresponding to the first CPLD; if identification information is read in the register, the first identification information corresponding to each first target port is determined based on the read identification information; if no identification information is read in the register, the first identification information corresponding to each first target port is generated according to the connection status of each first target port.

[0013] Based on this scheme, the BMC reads the identification information in the register or automatically generates and stores the first identification information, making the identification information of each first target port unique and persistent. This allows the BMC to determine the identification information of each first target port in the subsequent connection relationship identification process, thereby providing a reliable basis for port matching.

[0014] In another possible implementation, the first port in the pass-through card includes at least one sub-port, and the first target port is any one of the at least one sub-port, with different first identification information for different sub-ports.

[0015] Based on this solution, BMC can accurately identify individual physical connection points by finely marking sub-ports, supporting the identification of connection ports for multiple hard drives.

[0016] In another possible implementation, the pass-through card sends first identification information to the hard disk backplane through the first target port, including: based on the Serial General Purpose Input / Output (SGPIO) protocol, the pass-through card sends the first identification information to the hard disk backplane through the first target port.

[0017] Based on this solution, the pass-through card can utilize the inherent timing characteristics of the SGPIO protocol to encode the first identification information into a standardized signal sequence, ensuring that the hard drive backplane can accurately parse and store the identification information, thereby reducing signal transmission errors and protocol compatibility risks.

[0018] In another possible implementation, based on the Serial General Purpose Input / Output (SGPIO) protocol, the pass-through card sends first identification information to the hard disk backplane through a first target port, including: based on the SGPIO protocol, the pass-through card adds the first identification information after the load signal; the load signal includes the signal format defined in the SGPIO protocol for the pass-through card to send data to the hard disk backplane; the pass-through card sends the load signal to the hard disk backplane through the first target port.

[0019] Based on this solution, the pass-through card utilizes the inherent timing and frame structure of the SGPIO protocol to accurately embed the first identification information after the load signal, enabling the hard disk backplane to extract the first identification information unambiguously in the standard parsing process, thus avoiding additional communication overhead.

[0020] In another possible implementation, the hard disk backplane includes a second complex programmable logic device (CPLD). After the hard disk backplane generates a first mapping relationship based on the first identification information and the second target port that receives the first identification information, the method further includes: the hard disk backplane storing the first mapping relationship in the second CPLD; and the BMC reading the first mapping relationship from the second CPLD of the hard disk backplane.

[0021] Based on this solution, the hard drive backplane establishes a mapping relationship between the second target port and the first identification information to realize the logical association between the hard drive backplane port and the pass-through card port, providing an accurate basis for the dynamic identification and maintenance of port connection relationships.

[0022] In another possible implementation, the method further includes: the BMC obtaining the correspondence between the second target port and the hard disk slot in the hard disk backplane; each second target port is connected to at least one hard disk slot; the BMC determines a third mapping relationship based on the correspondence between the second target port and the hard disk slot, and the first mapping relationship, the third mapping relationship including the correspondence between the first target port and the hard disk slot.

[0023] Based on this solution, BMC can achieve full-link mapping from the pass-through card port to the hard drive slot, significantly improving the accuracy of hard drive hot-swap identification and fault location efficiency, and providing computing devices with highly reliable, low-latency port connection identification capabilities.

[0024] In another possible implementation, the computing device also includes a Basic Input / Output System (BIOS), which is connected to both the pass-through card and the BMC. The method further includes: the BIOS obtaining the mapping between the first target port and the hard disk slot from the BMC; the BIOS obtaining the hard disk information corresponding to the first target port from the pass-through card; and the BIOS establishing the mapping between the hard disk slot and the hard disk information based on the third mapping relationship.

[0025] Based on this solution, the BIOS can accurately bind the physical location and logical information of the hard drive at the initial stage of system startup, eliminating recognition delays or misalignments caused by dynamic changes in hardware topology, and providing a reliable storage device view for computing devices.

[0026] Secondly, this application embodiment also provides a computing device, including: a hard disk backplane, a pass-through card, and a baseboard control manager (BMC). The BMC is connected to the hard disk backplane and the pass-through card, respectively. The BMC is configured to write first identification information of a first target port into the pass-through card. The pass-through card includes a first port, and the first port includes a first target port. The pass-through card is configured to send the first identification information to the hard disk backplane through the first target port based on the Serial General Purpose Input / Output (SGPIO) protocol. The hard disk backplane is configured to generate a first mapping relationship based on the first identification information and a second target port that receives the first identification information. The first mapping relationship includes the correspondence between the first identification information and the second target port. The hard disk backplane is connected to the first target port through the second target port. The BMC is also configured to determine the correspondence between the first target port and the second target port based on the first mapping relationship read from the hard disk backplane.

[0027] Thirdly, embodiments of this application also provide a port identification method in a computing device, applied to a pass-through card. The pass-through card is disposed in the computing device, which also includes a baseboard control manager (BMC) and a hard disk backplane. The BMC is connected to the hard disk backplane and the pass-through card respectively. The method includes: the pass-through card acquiring first identification information, the pass-through card including a first port, the first port including a first target port; based on the Serial General Purpose Input / Output (SGPIO) protocol, the pass-through card sending the first identification information to the hard disk backplane through the first target port, so that the hard disk backplane generates a first mapping relationship based on the first identification information and the second target port receiving the first identification information; the first mapping relationship includes the correspondence between the first identification information and the second target port, and the first mapping relationship is used by the BMC to identify the connection relationship of the ports.

[0028] Fourthly, embodiments of this application also provide a port identification method in a computing device, applied to a baseboard control manager (BMC). The BMC is disposed in the computing device, which also includes a hard disk backplane and a pass-through card. The BMC is connected to the hard disk backplane and the pass-through card respectively. The method includes: the BMC writing first identification information of a first target port into the pass-through card, so that the pass-through card sends the first identification information to the hard disk backplane; the pass-through card includes a first port, and the first port includes a first target port; the BMC reads a first mapping relationship from the hard disk backplane; the first mapping relationship includes a correspondence between the first identification information and a second target port on the hard disk backplane; the BMC determines a second mapping relationship based on the first mapping relationship, and the second mapping relationship includes a correspondence between the first target port and the second target port.

[0029] Fifthly, embodiments of this application also provide a port identification method in a computing device, applied to a hard disk backplane. The hard disk backplane is disposed in the computing device, which also includes a baseboard control manager (BMC) and a pass-through card. The BMC is connected to the hard disk backplane and the pass-through card respectively. The method includes: in response to receiving first identification information, the hard disk backplane determines a second target port that received the first identification information; the hard disk backplane generates a first mapping relationship so that the BMC reads the first mapping relationship in the hard disk backplane; the first mapping relationship includes the correspondence between the first identification information and the second target port.

[0030] Sixthly, embodiments of this application provide a chip for performing the methods described in any one of the third, fourth, and fifth aspects above.

[0031] In a seventh aspect, embodiments of this application provide a computer-readable storage medium storing computer-executable instructions, which, when executed by a computer, implement the method as described in any one of the first, third, fourth, and fifth aspects.

[0032] Eighthly, embodiments of this application provide a program product including a computer program that, when executed by a processor, implements the method as described in any one of the first, third, fourth, and fifth aspects. Attached Figure Description

[0033] Figure 1 This application provides a schematic diagram of the connection of a hard disk backplane in a computing device. Figure 2 A schematic flowchart illustrating a port identification method in a computing device provided in an embodiment of this application; Figure 3 A schematic diagram illustrating a process for writing first identification information into a pass-through card, provided as an embodiment of this application; Figure 4 A flowchart illustrating the processing of a first mapping relationship is provided for an embodiment of this application; Figure 5 A schematic diagram of a process for generating a loading signal is provided for an embodiment of this application; Figure 6 A flowchart illustrating the process of determining a third mapping relationship is provided for an embodiment of this application; Figure 7 A schematic diagram of a process for determining a second mapping relationship is provided for an embodiment of this application; Figure 8 A schematic diagram illustrating a hard disk information synchronization process provided in an embodiment of this application; Figure 9 This application provides a schematic diagram of a system architecture for hard disk information synchronization. Figure 10 This is a schematic diagram of a computing device provided in an embodiment of this application. Detailed Implementation

[0034] The technical solutions of the embodiments of this application will now be described with reference to the accompanying drawings. To facilitate a clear description of the technical solutions of the embodiments of this application, the use of terms such as "first," "second," etc., in the embodiments of this application is for illustrative purposes and to distinguish the objects being described. There is no particular order between them, nor does it indicate a specific limitation on the number of devices in the embodiments of this application, and they do not constitute any limitation on the embodiments of this application.

[0035] The Platform Controller Hub (PCH) is an independent input / output control unit in traditional server architectures. It connects the Central Processing Unit (CPU) with various low- and medium-speed devices and manages the communication between the CPU and peripheral devices.

[0036] Serial Advanced Technology Attachment (SATA) is an interface standard used to connect computing devices, such as CPUs, and storage devices, enabling data transfer between the CPU and storage devices such as hard drives.

[0037] A SATA pass-through card is an expansion card used to connect the SATA interface on a server motherboard to the hard drive backplane via a cable, enabling unified management and data transfer of multiple hard drives.

[0038] The Baseboard Manager Controller (BMC) is used to monitor the hardware status of the device, perform remote management operations, and provide monitoring and control functions for the device, ensuring that the server has stable out-of-band management capabilities in complex operating environments.

[0039] Serial General Purpose Input / Output (SGPIO) is a serial communication interface provided by a PCH or SATA pass-through card for transmitting hard drive indicator control signals and synchronizing status.

[0040] Inter-Integrated Circuit (I2C) is a serial communication protocol that supports multiple master and slave devices exchanging data via two bidirectional signal lines.

[0041] A Complex Programmable Logic Device (CPLD) is a programmable logic device used to implement hardware-level logic control and signal processing.

[0042] The application scenarios of the embodiments of this application will be described below.

[0043] With the evolution of server architecture, SATA pass-through cards have integrated PCH functionality, forming a more compact and efficient storage control solution and enabling PCIe-SATA protocol conversion. SATA pass-through cards use a CPLD and firmware to internally number and manage the hard drives connected to them, enabling low-level hardware control and status monitoring.

[0044] Based on this, this application provides a port identification method in a computing device. By reusing the existing SGPIO signal line between the SATA pass-through card and the hard drive backplane, the port matching information is embedded in the SGPIO signal sent by the SATA pass-through card in digital encoding form under the unified control of the BMC. The hard drive backplane CPLD parses the encoded information, thereby realizing the rapid identification and mapping of port connection relationships and improving the efficiency and accuracy of the computing device in identifying hard drive connection ports.

[0045] Figure 1 This is a schematic diagram illustrating the connection of a hard disk backplane in a computing device according to an embodiment of this application. The following is in conjunction with… Figure 1 The content shown is used to illustrate the architecture of a computing device that implements the methods provided in the embodiments of this application.

[0046] like Figure 1 As shown, the method provided in this embodiment is applied to a computing device having a pass-through card 21, a hard disk backplane 22, and a BMC chip 23. The pass-through card 21 is communicatively connected to the hard disk backplane 22, and the BMC chip 23 is communicatively connected to the CPLD on both the pass-through card 21 and the hard disk backplane 22.

[0047] In one example, pass-through card 21 can be a SATA pass-through card. Pass-through card 21 is connected to hard drive backplane 22 via SGPIO signal line 25, enabling communication between pass-through card 21 and hard drive backplane 22 via SGPIO protocol.

[0048] In another example, pass-through card 21 can be connected to motherboard 24 via a multi-channel input / output (Mini Cool Edge I / O, MCIO) interface, enabling motherboard 24 to power and exchange data with pass-through card 21.

[0049] For example, the BMC chip 23 can establish communication with the pass-through card 21 and the CPLD in the hard disk backplane 22 via the I2C interface. Through the I2C interface, the BMC chip 23 can dynamically send port mapping configurations to the pass-through card 21 and the CPLD, and collect the status data fed back by the two in real time to complete the closed-loop verification of the port connection relationship.

[0050] In this embodiment, the first port may be the port on the pass-through card 21 that connects to the hard disk backplane 22, such as... Figure 2 Ports C0 and C1 are shown in the diagram. The first port may include a first target port, and each first target port has a unique corresponding first identifier.

[0051] In one possible implementation, the first port does not include sub-ports. In this case, the first target port can be a first port, and the first identification information of different first ports is different.

[0052] In another possible implementation, when the first port on the pass-through card 21 establishes a physical connection with the hard disk backplane 22, the same first port may have at least one sub-port. The first target port may be a sub-port. Different sub-ports have different first identification information. The pass-through card 21 can use the sub-port in the first port to realize the connection between the pass-through card 21 and the target port on the hard disk backplane 22.

[0053] In one possible implementation, the sub-ports in the first port can be distinguished by occupying different port pins. For example, if the first port has 16 pins and includes two sub-ports, the two sub-ports can independently send their corresponding signals by occupying 8 pins respectively.

[0054] In one example, the hard drive backplane 22 may be provided with a second target port, which includes a port on the hard drive backplane 22 that is connected to the pass-through card 21, such as... Figure 2 The diagram shows ports A and B of hard disk backplane 22a and ports A and B of hard disk backplane 22b. Because the second target port is connected to the first target port in pass-through card 21 via the SGPIO bus, it can receive the signal corresponding to the first identification information of the first target port.

[0055] For example, the first port C0 of the pass-through card 21 is connected to port A and port B of the hard drive backplane 22a via a splitter cable. One end of the splitter cable, labeled SGPIO1, is connected to port A of the hard drive backplane 22a, and the other end, labeled SGPIO2, is connected to port B of the hard drive backplane 22a. Similarly, the first port C1 of the pass-through card 21 is connected to port A and port B of the hard drive backplane 22b via a splitter cable. One end of the splitter cable, labeled SGPIO3, is connected to port A of the hard drive backplane 22b, and the other end, labeled SGPIO4, is connected to port B of the hard drive backplane 22b.

[0056] It should be understood that the label on the end of the 1-to-2 cable connected to the second target port is only set for easy identification and distinction. The first identification information actually transmitted is the digital code added to the load signal by the pass-through card 21.

[0057] Furthermore, different first target ports can be located within the same first port. The first target ports located within the same port can be distinguished by different pins, thereby enabling the pass-through card 21 and the hard disk backplane 22 to be connected via a one-to-two cable, realizing the communication connection between the first target port and the second target port on the hard disk backplane 22.

[0058] It is understandable that the pass-through card 21 can be configured with multiple first ports, some of which have sub-ports and some of which do not.

[0059] Figure 2 This is a flowchart illustrating a port identification method in a computing device provided in an embodiment of this application. The following is based on... Figure 2 The content shown is an exemplary description of the port identification method in the computing device provided in the embodiments of this application.

[0060] like Figure 2 As shown, the port identification method in the computing device provided in this application embodiment may include the following steps S100 to S400.

[0061] S100: BMC writes the first identifier information of the first target port into the pass-through card.

[0062] The SATA pass-through card may include a first port, which may include a first target port. The pass-through card can connect to the hard drive backplane through the first target port, thereby establishing a physical connection between the port and the backplane slot.

[0063] When the first port includes subports, the first destination port can be any one of the subports of the first port. When the first port does not include subports, the first destination port can be any one of the first ports.

[0064] The first identification information can be a preset digital code in the BMC chip 23, or a digital code dynamically generated by the BMC chip 23 according to preset encoding rules. The BMC chip 23 can generate corresponding first identification information for each first target port. At this time, the first identification information of the first target port exists in the same first port. This makes the identification information of each first target port unique and resolvable, which facilitates the subsequent transmission of the first identification information to the hard disk backplane 22 by the pass-through card 21 through its connection line with the hard disk backplane 22.

[0065] For example, the BMC chip 23 can generate identification information corresponding to each sub-port, such as "1", "2", "3", "4", etc., based on the number of sub-ports in the first port. This information serves as the identification information for the sub-port, allowing the pass-through card 21 to obtain the first identification information by calling this identification information when calling the first target port.

[0066] S200: The pass-through card sends the first identification information to the hard drive backplane through the first target port.

[0067] In step S200, after the computing device writes the first identification information into the pass-through card 21 using the BMC chip 23, it can use the communication protocol corresponding to the communication between the pass-through card 21 and the hard disk backplane 22 to enable the pass-through card 21 to embed the first identification information into the signal it transmits to the hard disk backplane 22, so as to transmit the first identification information corresponding to the first target port to the port corresponding to the hard disk backplane 22.

[0068] In one example, the pass-through card 21 can utilize the SGPIO protocol to generate corresponding signals and send them to the hard drive backplane 22. The SGPIO protocol is a low-speed, serial communication bus protocol used for management and status monitoring between the motherboard or expansion card and the hard drive backplane. The SGPIO channel is separate from the SATA data channel and is used to transmit hard drive management and control signals. In this embodiment, the SGPIO signals transmitted between the master device (pass-through card 21) and the slave device (hard drive backplane 22) may include four types: clock signal SClock, load signal SLoad, data output signal SDataOut, and data input signal SDataIn. SClock is issued by the master device to provide a reference clock for synchronizing data transmission; SLoad is used to identify the start or end position of a data frame; SDataOut is issued by the master device to transmit control signals or status information to the slave device; and SDataIn is issued by the slave device to provide status feedback to the master device.

[0069] In the SGPIO protocol, the four bits after SLoad is valid can be used to transmit custom information. In this embodiment, these four bits are used to carry the first identification information. When the pass-through card 21 generates the load signal, it can encode the four consecutive bits after the load signal is valid based on the first identification information to form a data frame containing the port matching information of the first port. This allows the hard disk backplane 22 to obtain the first identification information of the corresponding port by parsing the data frame and complete the parameter transmission process of the physical connection relationship.

[0070] In this embodiment, the four consecutive bits after the load signal is valid refer to the data bits sent by the pass-through card 21 within four consecutive clock cycles triggered by the falling edge of the load signal. The data bits corresponding to these four clock cycles are output by the pass-through card 21 at the rising edge of each SClock, thereby generating corresponding encoded data. In this way, the pass-through card 21 can attach the first identification information to the load signal and send it to the hard disk backplane, optimizing the information transmission effect and avoiding additional communication resource occupation.

[0071] S300: The hard disk backplane generates a first mapping relationship based on the first identification information and the second target port that receives the first identification information.

[0072] In step S300, when the hard disk backplane 22 receives a load signal carrying first identification information, it can accurately sample data bits within the time window corresponding to the load signal based on the synchronous triggering of the clock signal, parse out the first identification information corresponding to each first target port, and generate a corresponding first mapping relationship based on the first identification information of each first target port. The first mapping relationship refers to the correspondence between the first identification information and the second target port.

[0073] In this embodiment, the hard disk backplane 22 can be connected to the first target port on the pass-through card 21 via its second target port. After the pass-through card 21 sends a load signal using the first target port, each second target port can receive data transmitted from a sub-port corresponding to a first target port. Because each second target port corresponds to a unique and non-repeating first target port, each second target port can receive unique and non-repeating first identification information based on the first target port it is connected to.

[0074] The hard disk backplane 22 can determine the first identification information corresponding to each second target port based on the first identification information received by each second target port, thereby establishing a first mapping relationship between the first identification information and the second target port. In this way, the hard disk backplane 22 can generate a complete mapping relationship between the first target port and the interface on the hard disk backplane 22 based on the first identification information it receives and the second target port that receives the first identification information, thereby realizing the positioning from the pass-through card 21 port to the hard disk backplane 22.

[0075] In some embodiments, after obtaining the corresponding first identification information through the second target port, the hard disk backplane 22 can achieve dual authentication of the port identity by acquiring the second identifier of the second target port and associating the second identifier with the first identification information. In one example, the second identifier can be an encoding on the hard disk backplane 22 used to uniquely identify the second target port, such as portA, portB, etc.

[0076] By obtaining the second identifier corresponding to the second target port, the hard disk backplane 22 can establish a complete topological mapping relationship between the first identification information and the second target port, so that the physical connection relationship corresponds one-to-one with the logical mapping, thereby improving the accuracy of the computing device's perception of the hard disk connection status.

[0077] After obtaining the second identifier of the second target port and the first identification information received by the second target port, the hard disk backplane 22 can bind them to generate a corresponding first mapping relationship. In subsequent steps, the BMC chip 23 can use the read first mapping relationship to determine the second target port on the hard disk backplane 22 connected to the first target port on the pass-through card 21, thereby achieving accurate identification and logical binding of the hard disk backplane port connection relationship.

[0078] S400: The BMC determines the second mapping relationship based on the first mapping relationship read from the hard disk backplane.

[0079] In step S400, the BMC chip 23 can read the first mapping relationship determined by the hard disk backplane 22 and generate a second mapping relationship based on the obtained first mapping relationship. The second mapping relationship refers to the correspondence between the first target port and the second target port.

[0080] After obtaining the first mapping relationship, the BMC chip 23 can determine the corresponding first target port on the pass-through card 21 for each second target port through the first mapping relationship. It should be understood that the above method of the BMC determining the first target port on the pass-through card 21 based on the first mapping relationship is only an example of connection port identification provided in this application embodiment. In practical applications, the BMC chip 23 can also realize the mapping between the logic signal ports in the pass-through card 21 and the hard disk backplane ports based on the first mapping relationship.

[0081] In one example, after generating the first mapping relationship, the hard disk backplane 22 can upload it to the BMC chip 23 through the second CPLD for the BMC chip 23 to parse. In this embodiment, the process of the BMC chip 23 obtaining the first mapping relationship is not limited.

[0082] In some embodiments, the BMC chip 23 can also update the second mapping relationship based on the steps in the above embodiments: when the cable connection method changes, the BMC chip 23 can reread the hard disk backplane 22 and compare the historical mapping relationship. If a change in the correspondence between the first identifier information and the second identifier is detected, the mapping update process is triggered to dynamically adjust the second mapping relationship, thereby improving the compatibility and operation and maintenance efficiency of the computing device.

[0083] The steps S100 to S400 described above will be explained in detail below with reference to the accompanying drawings.

[0084] Figure 3 This is a schematic diagram illustrating a process for writing first identification information into a pass-through card, provided as an embodiment of this application. The following is based on... Figure 3 The content shown here is an exemplary illustration of the process by which the BMC writes the first identification information into the pass-through card in this embodiment of the application.

[0085] like Figure 3 As shown in (a), in this embodiment of the application, the process by which the computing device determines the first identification information corresponding to each first target port through the BMC may include the following steps S110 and S120.

[0086] S110: BMC generates first identification information corresponding to the first target port based on preset rules.

[0087] In step S110, after the pass-through card 21 and the hard disk backplane 22 are connected, the BMC chip 23 can generate first identification information corresponding to the first target port using preset rules. In this embodiment, the BMC chip 32 can determine the number of first target ports and other information through the connection line between itself and the pass-through card 21, and generate corresponding first identification information according to preset rules.

[0088] In one example, the preset rule allows the BMC chip 23 to generate a unique number corresponding to each first port or sub-port based on the number of first ports or sub-ports of the first port in the pass-through card 21. For example, if the pass-through card 21 has two first ports, and each first port includes two sub-ports, then the BMC chip 23 can generate first identification information with specific values ​​"1", "2", "3", and "4" for the four sub-ports based on the preset rule, thereby identifying the first target port.

[0089] like Figure 3 As shown in (b), the process of BMC generating the first identification information in step S110 may include the following steps S111 to S113.

[0090] S111: BMC reads the register corresponding to the first CPLD.

[0091] In step S111, the BMC chip 23 can read the register corresponding to the first complex programmable logic device CPLD located in the pass-through card 21 to determine whether the corresponding first identification information already exists in the pass-through card 21.

[0092] In some embodiments, the registers of the pass-through card 21 are used to store configuration information for each port, and the BMC chip 23 can access the registers in the first CPLD through the I2C interface to perform read and write operations on the registers.

[0093] In one example, the BMC chip 23 can reserve a storage area in the registers of the first CPLD to receive and store the first identification information by predefined storage address. This storage area is used to receive and store the first identification information written by the BMC chip 23 and is automatically loaded when the device is powered on or reset.

[0094] The BMC chip 23 can allocate an independent register address segment in the CPLD's register mapping table for each first port or sub-port to store the corresponding first identification information. For example, in a scenario where the pass-through card 21 has two first ports, the computing device can assign register address 0x10 to one first port (port0) and register address 0x11 to the other first port (port1). The BMC chip 23 can store this register mapping table and access the corresponding address segment according to the mapping table to read or write the first identification information.

[0095] It should be noted that the register address corresponding to each first target port in the above register mapping table is set based on the sub-ports contained in the first port on the pass-through card 21, and the first target port in this embodiment also refers to the sub-port on the pass-through card 21 that is connected to the hard disk backplane and is used to transmit SGPIO protocol signals.

[0096] Based on the foregoing embodiments, the sub-ports in the first port can be multiple signal transmission ports determined by distinguishing physical pins within the first port. The pass-through card 21 can determine the signals transmitted in the port by limiting the content of the transmitted signals in each sub-port. Correspondingly, the BMC chip 23 can allocate storage addresses for each sub-port in the first port. When the first identification information generated by the BMC chip 23 is added to the load signal, the pass-through card 21 will add the load signal transmitted in the corresponding sub-port according to the first target port corresponding to the first identification information, so as to realize the data transmission from the pass-through card 21 to the hard disk backplane 22.

[0097] For example, such as Figure 1As shown, the pass-through card 21 has two first ports, each of which contains two sub-ports. The first port C0 of the pass-through card 21 is connected to port A and port B of the hard drive backplane 22a via a splitter cable. The two sub-ports corresponding to the first port C0 are port0 and port1. The first port C1 is connected to port A and port B of another hard drive backplane 22b via a splitter cable. The sub-ports corresponding to the first port C1 are port2 and port3. The first target port can be any one of port0, port1, port2 or port3.

[0098] In one example, when reading the register corresponding to the pass-through card 21, the BMC chip 23 can initiate a read operation to the register of the first CPLD through the I2C interface. By accessing the register address corresponding to the first target port through the register address in the register mapping table, it can determine whether the first identification information has been written into the register corresponding to the first target port.

[0099] S112: If identification information is read from the register, the BMC determines the first identification information corresponding to the first target port based on the read identification information.

[0100] In step S112, if the BMC chip 23 detects that there is already identification information in the register address corresponding to the first target port, the BMC chip 23 can determine the first identification information corresponding to the first target port by reading the obtained identification information from the register address corresponding to the first target port.

[0101] It should be noted that, in this embodiment, if the BMC chip 23 determines the first identification information corresponding to the first target port in the register, the pass-through card 21 can execute step S200 to transmit the first identification information, thereby improving information interaction efficiency. If the BMC chip 23 does not read the identification information in the register, it executes the following step S113 to generate the corresponding first identification information.

[0102] S113: If the identification information is not read from the register, the BMC generates the first identification information corresponding to the first target port based on the connection status of the first target port.

[0103] In step S113, if the BMC chip 23 detects that no identification information has been written to the register address corresponding to the first target port, the BMC chip 23 can generate the first identification information of the first target port according to the connection status of the first target port. After generating the first identification information, the BMC chip 23 can write the newly generated first identification information into the register of the first CPLD through step S120 to realize the storage of the first identification information.

[0104] In some embodiments, the first identification information of the first target port can be generated by the BMC chip 23 using preset rules based on the mapping relationship between the first port and sub-ports on the pass-through card 21. For example, in a scenario where the pass-through card 21 has two first ports, and each first port corresponds to two sub-ports, the BMC chip 23 can generate identifiers according to the numbering order of each sub-port. For instance, the identifiers of the two sub-ports corresponding to the first port C0 can be 1 and 2, and the identifiers of the two sub-ports corresponding to the first port C1 can be 3 and 4. The BMC chip 23 can then determine the generated identifiers as the first identification information.

[0105] It should be noted that the identifier generated by the BMC chip 23 is in binary encoding format. The decimal form shown in the above embodiment is only for ease of understanding. In actual applications, the BMC chip 23 will generate identifiers in binary encoding format with a preset number of bits. For example, in 4-bit binary encoding, 1 can be represented as 0001, 2 as 0010, 3 as 0011, and 4 as 0100, thereby making each first identifier information generated by the BMC chip 23 unique and resolvable.

[0106] In another embodiment of this application, the BMC chip 23 can also determine the first identification information by directly generating the first identification information and overwriting it into the first CPLD after each initialization, thereby avoiding the register reading process in generating the first identification information and optimizing the generation effect of the first identification information.

[0107] S120: The BMC writes the first identification information into the first CPLD.

[0108] In step S120, after the BMC chip 23 generates the identifier of the first target port, it can write the obtained identifier into the specified register address of the corresponding CPLD of the pass-through card 21 through the communication link between the BMC chip 23 and the pass-through card 21, thereby determining the first identification information of the first target port.

[0109] In one example, after establishing SGPIO communication with the hard disk backplane, the pass-through card 21 can transmit the identification information of the first target port to the CPLD of the hard disk backplane by embedding the first identification information in the transmitted signal, so as to realize the port identification process between the pass-through card 21 and the hard disk backplane 22.

[0110] Based on the above embodiments Figure 3 As shown in the steps, the BMC chip 23 can write the first identification information corresponding to the first target port in the pass-through card 21 into the corresponding register address, which facilitates subsequent interface connection status identification and dynamic mapping.

[0111] Figure 4This is a schematic flowchart illustrating the processing of a first mapping relationship, provided as an embodiment of this application. The following is in conjunction with... Figure 4 The content shown herein is used to illustrate the process by which the computing device processes the first mapping relationship in the embodiments of this application.

[0112] like Figure 4 As shown, in this embodiment of the application, the process of the computing device processing the first mapping relationship may include the following steps S310 and S320.

[0113] S310: The hard disk backplane stores the first mapping relationship in the second CPLD.

[0114] In this embodiment, the hard disk backplane 22 may be provided with a second complex programmable logic device (CPLD). The second CPLD can parse and process the signals received by the hard disk backplane 22 and store the data generated by the hard disk backplane 22. For example, after the second target port in the hard disk backplane 22 receives a load signal, the hard disk backplane 22 can use the second CPLD to parse the first identification information added after the load signal, so that the hard disk backplane 22 can obtain the first identification information.

[0115] In step S310, after obtaining the first identification information, the hard disk backplane 22 can use the first identification information and the second target interface that received the first identification information to generate the corresponding first mapping relationship.

[0116] In one example, ports A and B of hard disk backplane 22a receive signals sent from the first port C0 of pass-through card 21, and the first identification information parsed from the signal received by port A is "1", while the first identification information parsed from the signal received by port B is "2". Similarly, ports A and B of hard disk backplane 22b receive load signals sent from the first port C1 of pass-through card 21, where the first identification information received by port A is "3" and the first identification information received by port B is "4".

[0117] The hard disk backplane 22 can establish a key-value pair data between the second target port and the first identification information by receiving the content in the first identification information, and then determine the key-value pair data as the first mapping relationship and store it in the preset storage area of ​​the second CPLD.

[0118] In this embodiment, after the hard disk backplane 22 receives the load signal through the second target port, it can parse the first identification information through the CPLD module and associate each second target port with the first identification information it received to form a record information with the correspondence between the second target port and the first identification information. For example, port A of the hard disk backplane 22a is associated with the first identification information "1", and port B is associated with the first identification information "2".

[0119] After generating the record information, the hard disk backplane 22 can construct a complete mapping relationship between the second target interface on it and the first identification information sent by the pass-through card 21, so that the BMC chip 23 can accurately identify the connection port and connection method by obtaining the first mapping relationship.

[0120] In some embodiments, the second CPLD in the hard disk backplane 22 can support a power-off retention function, so that the first mapping relationship stored therein can still be accurately restored after the computing device restarts. The process by which the hard disk backplane 22 stores the first mapping relationship to the second CPLD can be the same as the method of writing the first identification information into the register of the first CPLD in the pass-through card 21 in the previous embodiments, and will not be described in detail here.

[0121] S320: The BMC reads the first mapping relationship from the second CPLD on the hard drive backplane.

[0122] In step S320, after the BMC chip 23 generates the first mapping relationship on the hard disk backplane 22, it can read the first mapping relationship in the second CPLD so that the BMC chip 23 can identify the port connections in the computing device.

[0123] In this embodiment of the application, the BMC chip 23 can read the first mapping relationship by accessing the preset storage address of the second CPLD corresponding to the hard disk backplane 22. If the storage address contains the corresponding content, the BMC chip 23 can use the content it reads as the first mapping relationship.

[0124] It should be noted that after generating the first identification information, the BMC chip 23 may send a read request to the hard disk backplane 22 after a certain period of time, so as to avoid the hard disk backplane 22 failing to generate the corresponding first mapping relationship through the newly generated first identification information.

[0125] Based on steps S310 and S320, the computing device can use the hard disk backplane 22 to generate and store the first mapping relationship, so that the BMC chip 23 can call it to determine the corresponding port connection relationship.

[0126] Figure 5 This is a schematic diagram illustrating a process for generating a loading signal, provided in an embodiment of this application. The following is based on... Figure 5The content shown herein is an exemplary description of how the through card 21 provided in this application generates a loading signal based on the first identification information.

[0127] like Figure 5 As shown in (a), in this embodiment of the application, the process by which the through card 21 generates a loading signal corresponding to each first port based on the first identification information may include the following steps S210 to S220.

[0128] S210: Based on the SGPIO protocol, the pass-through card adds the first identification information after the load signal.

[0129] In step S210, after obtaining the first identification information, the pass-through card 21 can determine the location for adding the first identification information by combining the formats of various signals defined by the SGPIO protocol. Referring to the content described in step S200 above, the SGPIO protocol defines four types of signals: clock signal, load signal, data output signal, and data input signal.

[0130] In this embodiment, the pass-through card 21 uses the load signal defined by the SGPIO protocol to add the first identification information to the four bits following the load signal, thereby enabling the pass-through card 21 to send the first identification information simultaneously with the load signal. In this way, the pass-through card 21 sends the first identification information to the corresponding hard disk backplane 22 by multiplexing the transmission signal, thus reducing transmission resource consumption.

[0131] It should be noted that the load signal triggers the start and end of data frame transmission by using high and low levels. The process of adding the first identification information after the load signal by the pass-through card 21 is the process of adding the first identification information within four clock cycles after the load signal.

[0132] like Figure 5 As shown in (b), the process of adding the first identification information after the load signal may include the following steps S211 to S214.

[0133] S211: The pass-through card generates the load signal and clock signal defined by the SGPIO protocol.

[0134] In this embodiment, the load signal and clock signal generated by the pass-through card 21 are SLoad and SClock defined in the SGPIO protocol described in the previous embodiments. By acquiring the load signal, the pass-through card 21 can determine the embedding position and encoding rules of the first identification information, ensuring that the first identification information can be accurately embedded after the load signal. This allows the pass-through card 21 to transmit port information to the hard disk backplane 22 through the signals defined by the SGPIO protocol, reducing signal interference and transmission errors, and improving the compatibility of the connection port identification method with the existing SGPIO protocol.

[0135] The clock signal is used to synchronize the loading signal and the sampling timing of the loading signal data frame by the hard disk backplane 22, so that the hard disk backplane 22 can accurately capture the loading signal to obtain the corresponding first identification information.

[0136] S212: Reserved field for determining the load signal of the pass-through card.

[0137] During the generation of the load signal, the pass-through card 21 can determine the reserved field of the load signal based on the SLoad signal format defined in the SGPIO protocol, thereby determining the position and timing rules of the reserved field used to add the first identification information, avoiding conflicts between the load signal generated by the pass-through card 21 and the SGPIO protocol standard, so that the embedding of the first identification information does not affect the functions of other signals.

[0138] S213: The through card writes the first identification information into the reserved field.

[0139] In one example, the reserved field can be a data bit for four consecutive clock cycles after the load signal is valid. This reserved field becomes active after the falling edge of the load signal is triggered, at which time the pass-through card 21 writes the corresponding first identification information into the reserved field. After the falling edge of the load signal arrives, the pass-through card 21 writes the first identification information into the reserved field during the rising edge of four consecutive clock cycles of the clock signal.

[0140] S214: The pass-through card generates a loading signal based on the clock signal, the preset loading signal format, and the reserved fields.

[0141] In this embodiment, the pass-through card 21 can generate a load signal carrying first identification information based on a clock signal, a preset load signal, and a reserved field in the load signal. After generating the load signal carrying the first identification information, the pass-through card 21 transmits the signal to the hard disk backplane 22 via the SGPIO bus, thereby enabling the hard disk backplane 22 to synchronously sample the reserved field in the load signal according to the clock signal and obtain the first identification information corresponding to each second target port.

[0142] In this way, through the SGPIO protocol channel used for communication between the pass-through card 21 and the hard disk backplane 22, the pass-through card 21 can transmit the first identification information to the hard disk backplane 22, so that the first identification information received by the hard disk backplane 22 corresponds one-to-one with the second target port, which makes it easier for the BMC chip 23 to identify the physical connection relationship between each port of the pass-through card 21 and the hard disk backplane 22 in the subsequent process.

[0143] S220: The pass-through card sends the load signal to the hard drive backplane through the first target port.

[0144] In step S220, the pass-through card 21 can process the load signal corresponding to the first target port, so that it can be accurately transmitted to the corresponding second target port of the hard disk backplane 22 through the SGPIO bus, ensuring signal integrity and timing synchronization.

[0145] It should be noted that, in this embodiment, the load signal refers to the signal sent by the pass-through card 21 to the hard disk backplane 22 through the corresponding SLOAD signal line in the SGPIO bus. When the pass-through card 21 attaches the first identification information to the load signal, it converts it into binary code and embeds it into the reserved field of the SLOAD signal. The SLOAD signal line is then transmitted cycle by cycle under clock synchronization, so that the hard disk backplane 22 can parse the binary bits corresponding to each cycle through the SLOAD signal line after receiving the load signal and restore the first identification information.

[0146] Figure 6 This is a schematic diagram illustrating a process for determining a third mapping relationship, provided as an embodiment of this application. The following is based on... Figure 6 The content shown herein provides an exemplary description of the process by which the BMC chip 23 utilizes the internal structure of the hard disk backplane 22 to generate a mapping relationship between the port on the pass-through card 21 and the hard disk slot in this embodiment of the application.

[0147] like Figure 6 As shown, in this embodiment of the application, the process by which the BMC chip 23 generates the mapping relationship between the port on the pass-through card 21 and the hard disk slot may include the following steps S510 and S520.

[0148] S510: BMC obtains the correspondence between the second target port and the hard drive slot in the hard drive backplane.

[0149] In step S510, while the BMC chip 23 is reading the hard disk backplane 22 to generate the first mapping relationship, it can also simultaneously read the correspondence between the second target port and the hard disk slot in the hard disk backplane 22, so as to construct the correspondence between the first target port on the pass-through card 21 and the hard disk slot on the hard disk backplane 22 through the correspondence.

[0150] In this embodiment, the hard disk backplane 22 may include multiple hard disk slots, and each second target port may connect to at least one hard disk slot. The physical connection between each second target port and its corresponding hard disk slot is fixed by hardware wiring. In one example, the hard disk backplane 22 has two second target ports and eight hard disk slots, with each second target port connecting to four hard disk slots respectively.

[0151] For example, the second CPLD in the hard disk backplane 22 may store a physical connection mapping table between the second target port and the hard disk slot. This mapping table may be permanently stored in the registers or other storage units of the second CPLD in a non-volatile manner. For example, the physical connection mapping table stored in the second CPLD can be established through the correspondence between the identifier of the second target port and the silkscreen number of the hard disk slot.

[0152] The identifier can be the code used by the hard disk backplane 22 to uniquely identify the SGPIO port, i.e., the second target port, such as portA, portB, etc. The silkscreen number of the hard disk slot on the hard disk backplane 22 is the number used by the hard disk backplane 22 to identify the physical location of the hard disk slot. The silkscreen number can be set on the PCB board corresponding to the hard disk backplane 22 and correspond one-to-one with each hard disk slot, so that the silkscreen number corresponds one-to-one with the physical location of the hard disk installation, which makes it easy for the BMC chip 23 to locate the connection port and connection position of the hard disk based on the mapping relationship.

[0153] It should be understood that the circuit design of the hard disk backplane 22 has a fixed topology. The physical connection relationship between each second target port and the corresponding hard disk slot is determined in the hardware design stage. Therefore, the correspondence between the silkscreen number and the identifier of the second target port can be solidified and stored in the second CPLD of the hard disk backplane 22 in the hardware design stage to ensure that it will not change during the operation of the device.

[0154] In this embodiment, the BMC chip 23 can determine the physical connection structure between the second target port and the hard disk slot by reading the correspondence between the identifier and the silkscreen number of the second target port, and thus obtain the correspondence between the second target port and the hard disk slot.

[0155] It should be noted that because a second target port transmits and manages signals to a group of hard drive slots, one identifier may correspond to multiple silkscreen numbers. This correspondence reflects the fixed connection logic of the backplane hardware topology. For example, both hard drive backplanes 22a and 22b can have eight hard drive slots, with each second target port corresponding to four hard drive slots. Taking the silkscreen numbers Disk8-Disk15 in hard drive backplane 22a and Disk16-Disk23 in hard drive backplane 22b as examples, port A of hard drive backplane 22a corresponds to Disk8-Disk11, and port B corresponds to Disk12-Disk15; port A of hard drive backplane 22b corresponds to Disk16-Disk19, and port B corresponds to Disk20-Disk23.

[0156] BMC chip 23 can obtain the correspondence between the pre-stored silkscreen number and the identifier by sending a read command to the second CPLD of the hard disk backplane 22, and then obtain the mapping relationship between the corresponding second target port and the hard disk slot.

[0157] In some embodiments, because the mapping relationship between the second target port and the hard disk slot is generated based on a hardware-fixed connection relationship, the mapping relationship is unique and stable, and is not affected by system startup / shutdown or hot-plug operations. When this mapping relationship is required, the BMC chip 23 can obtain the mapping relationship by periodically reading the storage address in the second CPLD of the hard disk backplane 22, and identify the connection port based on the mapping relationship.

[0158] S520: The BMC determines the third mapping relationship based on the correspondence between the second target port and the hard disk slot, as well as the first mapping relationship.

[0159] In step S520, the BMC chip 23 can determine the correspondence between the first target port and the hard disk slot through the correspondence between the second target port and the hard disk slot, as well as the first mapping relationship, thereby obtaining the third mapping relationship.

[0160] In one example, the BMC chip 23 determines the correspondence between the first identification information and the hard drive slot based on the correspondence between the hard drive slot and the second target port on the hard drive backplane 22, combined with the first identification information generated by the hard drive backplane 22 and the first mapping relationship between the second target port. Since the first identification information corresponds one-to-one with the first target port of the pass-through card 31, a third mapping relationship between the first target port and the hard drive slot is finally established, providing a reliable basis for subsequent accurate identification, positioning and management of each physical hard drive.

[0161] Figure 7 This is a schematic flowchart illustrating a method for determining a second mapping relationship, provided in an embodiment of this application. The following is based on... Figure 7 The content shown illustrates, by way of example, the process by which the BMC chip 23 determines the second mapping relationship in the embodiments of this application.

[0162] like Figure 7 As shown, in this embodiment of the application, the process by which the BMC chip 23 determines the second mapping relationship based on the first mapping relationship and the second target port read from the hard disk backplane 22 may include the following steps S410 and S420.

[0163] S410: BMC chip 23 matches the first identification information with the first identification information in the pass-through card to obtain the mapping relationship between the second identification information corresponding to the first target port and the second target port.

[0164] In this embodiment of the application, after obtaining the first mapping relationship, the BMC chip 23 can compare the first identification information in the first mapping relationship with the first identification information stored in the register of the first CPLD in the pass-through card 21, thereby determining the mapping relationship between the first target port and the second target port identifier.

[0165] The first mapping relationship includes the correspondence between the identifier of the second target port and the first identification information carried in the loading signal received by the second target port. When the BMC chip 23 generates and stores the first mapping relationship using the hard disk backplane 22, it can generate key-value pairs of information with the first identification information received by the second target port and its corresponding identifier, and determine them as record information, storing them in the register of the second CPLD module in the hard disk backplane 22.

[0166] In one example, the first identification information in the first mapping relationship can be the key in key-value pair format data, and the identifier is the value. Through this key-value pair structure, the BMC chip 23 can use the first identification information to quickly find the corresponding identifier and determine the connection relationship between the first target port and the second target port.

[0167] Correspondingly, the process by which the BMC chip 23 matches the first identification information in the first mapping relationship with the first identification information in the pass-through card 21 can be described as the process by which the BMC chip 23 searches for the identifier corresponding to the second target port in the BMC chip 23 based on the first identification information stored in the pass-through card 21. After obtaining the relationship between the first identification information and the identifier of the second target port, the mapping relationship between the first target port and the second target port can be determined through the mapping relationship between the first identification information and the first target port, as well as the identifier of the second target port.

[0168] S420: Determine the mapping relationship between the first target port and the second target port as the second mapping relationship.

[0169] In this embodiment, the process by which the BMC chip 23 obtains the mapping relationship between the first target port and the second target port may include determining the mapping relationship between the identifiers corresponding to the first target port and the second target port based on the first identification information in the first mapping relationship, so as to determine the first mapping relationship using the identifiers. In one example, the second mapping relationship may be dynamically updated as the cable connection method between the pass-through card 21 and the hard disk backplane 22 changes, ensuring the real-time performance and accuracy of the mapping relationship.

[0170] Figure 8 This is a schematic diagram illustrating a hard disk information synchronization process provided in an embodiment of this application. Figure 9 This is a schematic diagram of a hard disk information synchronization system architecture provided in an embodiment of this application. The following is in conjunction with… Figure 8and Figure 9 The content shown herein provides an exemplary description of the process of synchronizing hard disk information by a computing device in an embodiment of this application.

[0171] like Figure 8 As shown, in this embodiment of the application, the process of the computing device performing hard disk information synchronization may include the following steps S610 to S630.

[0172] S610: The BIOS obtains the third mapping relationship from the BMC.

[0173] like Figure 9 As shown, the computing device may also include a Basic Input Output System (BIOS) 26, which is located between the pass-through card 21 and the BMC chip 23. The BIOS 26 communicates with the pass-through card 21 via the PCIe bus and interacts with the BMC chip 23 via the One-Block Transfer (BT) channel to achieve collaborative management of hard disk information.

[0174] BIOS26 is the first firmware loaded when a computing device boots up. It is used to initialize hardware devices and prepare for the loading of the operating system. Because BIOS26 needs to identify and configure storage devices during the system initialization phase, it can send hard drive query commands to the SATA passthrough card 21 via the PCIe bus to obtain the logical number and status data of each hard drive.

[0175] In this embodiment, the BIOS 26 can send an information synchronization command to the pass-through card 21, requesting information about the hard drive connected to the pass-through card 21. It can also respond to a request from the BMC chip 23 to synchronize the hard drive information corresponding to the hard drive connected to the pass-through card 21. Upon receiving the information synchronization command, the pass-through card 21 uses the first mapping relationship obtained by the BMC chip 23 in the hard drive backplane 22 and the second mapping relationship generated by the BMC chip 23 to determine the correspondence between each hard drive slot and the first target port of the pass-through card 21, thereby obtaining a third mapping relationship.

[0176] In this way, BIOS26 can simultaneously obtain the third mapping relationship between the first target port and the hard drive slot on the hard drive backplane 22. Based on the third mapping relationship, BIOS26 can convert the first target port and its corresponding internal number into the corresponding silkscreen number of the hard drive backplane 22, realizing the accurate display of the hard drive silkscreen number. In this way, BIOS26 can locate the physical location of the target hard drive on the hard drive backplane 22 based on the internal number of the hard drive in the pass-through card 21, so that the query result corresponds to the physical hard drive slot identification, improving the intuitiveness of the information and optimizing the user experience.

[0177] S620: The BIOS obtains the hard drive information corresponding to the first target port from the pass-through card.

[0178] After obtaining the third mapping relationship based on the BMC chip 23, the BIOS26 can determine the hard drive slot corresponding to each first target port through the third mapping relationship, and then determine the corresponding silkscreen number.

[0179] In this embodiment, the BIOS 26 can also use the obtained third mapping relationship to obtain the hard disk information corresponding to each first target port in the pass-through card 21, and transmit the hard disk information to the BMC chip 23 through the BT channel, so that the BMC chip 23 can complete the update and synchronization of the hard disk silkscreen number.

[0180] S630: Based on the third mapping relationship, the BIOS establishes the correspondence between the hard drive slot and the hard drive information.

[0181] After obtaining the third mapping relationship based on the BMC chip 23, the BIOS26 can process the hard drive information it has obtained with the third mapping relationship to establish the correspondence between the hard drive slot and the hard drive information, thereby realizing the dynamic binding of the silkscreen number and the physical slot.

[0182] Based on the port identification method in the computing device provided in this application embodiment, the BMC in the computing device can utilize the SGPIO signal transmission mechanism between the pass-through card and the hard disk backplane to transmit port matching information through serial signals, thereby realizing the dynamic identification and mapping of the connection relationship between the hard disk backplane and the pass-through card without relying on additional hardware signal lines or complex detection logic, thus improving the efficiency and reliability of connection identification.

[0183] Corresponding to the port identification method in a computing device provided in this application embodiment for a computing device equipped with a hard disk backplane, a pass-through card and a BMC, this application embodiment also provides a port identification method in a computing device for a pass-through card. The pass-through card can be installed in a computing device including a BMC and a hard disk backplane, and the pass-through card is communicatively connected to the BMC and the hard disk backplane in the computing device.

[0184] Similar to the previous embodiments, the pass-through card may include a first port, and the first port includes a first target port.

[0185] In this embodiment, the pass-through card can first obtain the first identification information, and then send the first identification information to the hard disk backplane in the computing device through the first target port based on the Serial General Purpose Input / Output (SGPIO) protocol. This enables the hard disk backplane to generate a first mapping relationship based on the first identification information and the second target port that received the first identification information, including the correspondence between the first identification information and the second target port. This first mapping relationship can be used by the BMC in the computing device to identify the connection relationship between the ports of the pass-through card and the hard disk backplane.

[0186] Corresponding to the port identification method in a computing device provided in this application embodiment for a computing device equipped with a hard disk backplane, a pass-through card, and a BMC, this application embodiment also provides a port identification method in a computing device for a BMC. The BMC can be installed in a computing device including a pass-through card and a hard disk backplane, and the BMC is communicatively connected to the pass-through card and the hard disk backplane in the computing device, respectively.

[0187] Similar to the previous embodiments, the pass-through card in the computing device may include a first port, and the first port includes a first target port.

[0188] In this embodiment, the BMC can write the first identification information of the first target port into the pass-through card in the computing device, so that the pass-through card in the computing device can send the first identification information to the hard disk backplane in the computing device. Then, the BMC can also read the first mapping relationship including the correspondence between the first identification information and the second target port on the hard disk backplane of the computing device, and determine the second mapping relationship including the correspondence between the first target port and the second target port based on the first mapping relationship.

[0189] Corresponding to the port identification method in a computing device provided in this application embodiment for a computing device equipped with a hard disk backplane, a pass-through card, and a BMC, this application embodiment also provides a port identification method in a computing device for a hard disk backplane. The hard disk backplane can be installed in a computing device including a pass-through card and a hard disk backplane, and the hard disk backplane is communicatively connected to the pass-through card and the BMC in the computing device, respectively.

[0190] The hard disk backplane can respond to receiving the first identification information, determine the second target port that received the first identification information, and then generate a first mapping relationship based on the second target port that received the first identification information and its corresponding first identification information, so that the BMC in the computing device can read the first mapping relationship in the hard disk backplane.

[0191] Figure 10 This is a schematic diagram of a computing device provided in an embodiment of this application.

[0192] Corresponding to the aforementioned embodiments of port identification methods in computing devices, this application also provides an embodiment of a computing device. For example... Figure 10 As shown, the computing device 1000 may include: BMC 1010, pass-through card 1020, and hard disk backplane 1030.

[0193] BMC1010 is configured to write the first identification information of the first target port into the pass-through card 1020.

[0194] The pass-through card 1020 is configured to send first identification information to the hard disk backplane 1030 through the first target port based on the Serial General Purpose Input / Output (SGPIO) protocol.

[0195] The hard disk backplane 1030 is configured to generate a first mapping relationship based on the first identification information and the second target port that receives the first identification information.

[0196] BMC1020 is also configured to determine the correspondence between the first target port and the second target port based on the first mapping relationship read from the hard disk backplane 1030.

[0197] Some embodiments of this application provide a computer-readable storage medium storing at least one executable instruction that, when executed on a computing device 1000, causes the computing device 1000 to perform the port identification method in the computing device described in the above embodiments.

[0198] For example, the computer-readable storage medium can be a read-only memory (ROM), a random access memory (RAM), a compact disc read-only memory (CD-ROM), magnetic tape, a floppy disk, and an optical data storage device.

[0199] This application provides a chip system for use in a server. The chip system includes one or more interface circuits and one or more processors. The interface circuits and processors are interconnected via lines. The interface circuits are used to receive signals from the server's memory and send signals to the processors, the signals including computer instructions stored in the memory. When the processor executes the computer instructions, the server performs various steps in the hard disk backplane connection port identification method shown in the above-described method embodiments.

[0200] The beneficial effects that the readable storage medium provided in some embodiments of this application can achieve can be referred to the beneficial effects of the corresponding hard disk backplane connection port identification method provided above, and will not be repeated here.

[0201] The embodiments described above are merely specific embodiments of this application and are not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, improvements, etc., made based on the technical solution of this application should be included within the scope of protection of this application.

Claims

1. A port identification method in a computing device, characterized in that, The computing device includes a hard disk backplane, a pass-through card, and a baseboard controller (BMC). The BMC is connected to the hard disk backplane and the pass-through card, respectively. The method includes: The BMC writes the first identification information of the first target port into the pass-through card, the pass-through card including the first port, and the first port including the first target port; The pass-through card sends the first identification information to the hard disk backplane through the first target port; The hard drive backplane generates a first mapping relationship based on the first identification information and the second target port that receives the first identification information; the first mapping relationship includes the correspondence between the first identification information and the second target port, and the hard drive backplane is connected to the first target port through the second target port; The BMC determines a second mapping relationship based on the first mapping relationship read from the hard disk backplane, and the second mapping relationship includes the correspondence between the first target port and the second target port.

2. The method according to claim 1, characterized in that, The pass-through card includes a first complex programmable logic device (CPLD), and the BMC writes the first identification information of the first target port into the pass-through card, including: The BMC writes the first identification information into the first CPLD.

3. The method according to claim 1 or 2, characterized in that, The BMC writes the first identifier information of the first target port into the pass-through card, and also includes: The BMC generates the first identification information corresponding to the first target port based on preset rules.

4. The method according to any one of claims 1 to 3, characterized in that, The first port in the pass-through card includes at least one sub-port, and the first target port is any one of the at least one sub-port. The first identification information of different sub-ports is different.

5. The method according to any one of claims 1 to 4, characterized in that, The pass-through card sends the first identification information to the hard drive backplane through the first target port, including: Based on the Serial General Purpose Input / Output (SGPIO) protocol, the pass-through card sends the first identification information to the hard disk backplane through the first target port.

6. The method according to claim 5, characterized in that, Based on the Serial General Purpose Input / Output (SGPIO) protocol, the pass-through card sends the first identification information to the hard disk backplane through the first target port, including: Based on the SGPIO protocol, the pass-through card adds the first identification information after the load signal; the load signal includes the signal format defined in the SGPIO protocol for the pass-through card to send data to the hard disk backplane; The pass-through card sends the loading signal to the hard disk backplane through the first target port.

7. The method according to any one of claims 1 to 6, characterized in that, The hard disk backplane includes a second complex programmable logic device (CPLD). After the hard disk backplane generates a first mapping relationship based on first identification information and a second target port that receives the first identification information, the method further includes: The hard disk backplane stores the first mapping relationship in the second CPLD; The BMC reads the first mapping relationship from the second CPLD on the hard disk backplane.

8. The method according to any one of claims 1 to 7, characterized in that, The method further includes: The BMC obtains the correspondence between the second target port and the hard drive slot in the hard drive backplane; the second target port is connected to at least one of the hard drive slots; The BMC determines a third mapping relationship based on the correspondence between the second target port and the hard disk slot, and the first mapping relationship. The third mapping relationship includes the correspondence between the first target port and the hard disk slot.

9. The method according to claim 8, characterized in that, The computing device further includes a Basic Input / Output System (BIOS), which is connected to both the pass-through card and the BMC. The method further includes: The BIOS obtains the third mapping relationship from the BMC; The BIOS obtains the hard drive information corresponding to the first target port from the pass-through card; Based on the third mapping relationship, the BIOS establishes a correspondence between the hard drive slot and the hard drive information.

10. A computing device, characterized in that, include: The hard drive backplane, pass-through card, and baseboard control manager (BMC) are connected to the hard drive backplane and the pass-through card, respectively. The BMC is configured to write the first identification information of the first target port into the pass-through card, the pass-through card including the first port, the first port including the first target port; The pass-through card is configured to send the first identification information to the hard disk backplane through the first target port based on the Serial General Purpose Input / Output (SGPIO) protocol. The hard disk backplane is configured to generate a first mapping relationship based on first identification information and a second target port that receives the first identification information; the first mapping relationship includes the correspondence between the first identification information and the second target port, and the hard disk backplane is connected to the first target port through the second target port; The BMC is also configured to determine the correspondence between the first target port and the second target port based on the first mapping relationship read from the hard disk backplane.

11. A port identification method in a computing device, characterized in that, The method is applied to a pass-through card, the pass-through card being disposed in a computing device, the computing device further including a baseboard control manager (BMC) and a hard disk backplane, the BMC being connected to the hard disk backplane and the pass-through card respectively, the method comprising: The pass-through card acquires first identification information. The pass-through card includes a first port, and the first port includes a first target port. Based on the Serial General Purpose Input / Output (SGPIO) protocol, the pass-through card sends the first identification information to the hard disk backplane through the first target port, so that the hard disk backplane generates a first mapping relationship based on the first identification information and the second target port that receives the first identification information; the first mapping relationship includes the correspondence between the first identification information and the second target port, and the first mapping relationship is used by the BMC to identify the connection relationship of the port.

12. A port identification method in a computing device, characterized in that, A method for using a baseboard control manager (BMC), wherein the BMC is disposed in a computing device, the computing device further includes a hard disk backplane and a pass-through card, and the BMC is connected to the hard disk backplane and the pass-through card respectively, the method comprising: The BMC writes the first identification information of the first target port into the pass-through card, so that the pass-through card sends the first identification information to the hard disk backplane; the pass-through card includes a first port, and the first port includes a first target port; The BMC reads a first mapping relationship from the hard disk backplane; the first mapping relationship includes the correspondence between the first identification information and the second target port on the hard disk backplane; Based on the first mapping relationship, the BMC determines a second mapping relationship, which includes the correspondence between the first target port and the second target port.

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