CXL system, device handshake method, computer device, readable storage medium and program product
By introducing attribute fields and shadow registers in the CXL system, the problems of business conflicts and bus hangs caused by untimely address window synchronization updates were solved, thus improving the security and stability of the CXL system.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHENZHEN JAGUAR MICROSYSTEMS CO LTD
- Filing Date
- 2026-04-17
- Publication Date
- 2026-07-10
AI Technical Summary
In the CXL system, when the upper-layer host modifies the built-in address window of the CXL chip, it cannot be updated to the bus bridge side in a timely manner, resulting in service conflicts and bus hangs.
By introducing capability registers and their shadow registers with first and second attribute fields into the CXL system, the central processing unit and coprocessor cooperate with interrupt service routines to realize synchronous handshaking of the address window, ensuring the synchronization of address window information between the CXL host bridge and bus bridge.
This avoids the bus bridge routing to the old address window when the upper-layer host uses the new address window, thus avoiding business conflicts and bus hangs, and improving the security and stability of the system.
Smart Images
Figure CN122364136A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of chip technology, and in particular to a CXL system, a device handshake method, a computer device, a readable storage medium, and a program product. Background Technology
[0002] Compute Express Link (CXL) is a new open interconnect standard. A CXL system typically includes an upper-layer host (containing local memory and a central processing unit), an interconnect bus, a coprocessor connected to the interconnect bus, a CXL host bridge, CXL hosts, CXL switches, CXL devices, and remote memory.
[0003] Currently, the upper-layer host, CXL chip, and bus bridge exist independently. When the upper-layer host modifies the CXL chip's built-in address window, it cannot update the bus bridge side in a timely manner, and the bus bridge continues to use the old address window. When the upper-layer host uses the new address window to transmit services, the bus bridge routes to the old address window, causing service conflicts and bus hangs. Summary of the Invention
[0004] Therefore, it is necessary to provide a CXL system, device handshake method, computer device, readable storage medium, and program product that can improve security in response to the above-mentioned technical problems.
[0005] In a first aspect, this application provides a CXL system, including: an upper-layer host, an interconnect bus, a coprocessor, and a CXL host bridge; the upper-layer host includes a central processing unit; the CXL host bridge includes: a first capability register storing a first attribute field and a second attribute field, and a first shadow register corresponding to the first capability register; when the first attribute field is a first preset value, it indicates that the information in the corresponding address window in the first capability register has completed a synchronization handshake; when the first attribute field is a second preset value, it indicates that the corresponding address window in the first capability register has not completed a synchronization handshake; when the second attribute field is a first preset value, it indicates that the information in the corresponding address window in the first capability register has been updated, and when the second attribute field is a second preset value, it indicates that the information in the corresponding address window in the first capability register has not been updated; wherein;
[0006] The central processing unit is used to: during the CXL system initialization process, for each address window in the first capability register, read the value of the first attribute field in the address window; if the value of the first attribute field is a second preset value; set the value of the second attribute field in the address window to the second preset value, update the information of the address window, and then set the value of the second attribute field in the address window to the first preset value;
[0007] The CXL host bridge is used to generate an interrupt flag when the value of the second attribute field in the address window is detected to be set to the first preset value.
[0008] The coprocessor is used to: when the interrupt flag is detected, copy the information of the address window to the interconnect bus through the interrupt service routine, and set the value of the first attribute field in the first shadow register to the first preset value;
[0009] The CXL host bridge is used to synchronize the value of the first attribute field in the first shadow register to the first capability register in order to achieve synchronous handshaking of the address window.
[0010] In one embodiment, the first capability register also stores a third attribute field, wherein when the third attribute field is a first preset value, it indicates that the corresponding address window in the first capability register has been locked; and when the third attribute field is a second preset value, it indicates that the corresponding address window in the first capability register has not been locked.
[0011] During the initialization of the CXL system, for each address window in the first capability register, the central processing unit is used to: read the value of the first attribute field and the value of the third attribute field in the address window; if the value of the first attribute field and the value of the third attribute field are both the second preset value, set the value of the second attribute field in the address window to the second preset value; update the information of the address window; and then set the value of the second attribute field in the address window to the first preset value.
[0012] In one embodiment, the first capability register also stores a fourth attribute field, wherein when the fourth attribute field is a first preset value, it indicates that the consistency check of the corresponding address window in the first capability register has failed; and when the fourth attribute field is a second preset value, it indicates that the consistency check of the corresponding address window in the first capability register has passed.
[0013] The CXL host bridge is used to: set the values of the first attribute field and the fourth attribute field in the address window to the second preset value before generating the interrupt flag;
[0014] The coprocessor is used to: check the address window for consistency when the interrupt flag is detected; if the check passes, copy the address window information to the interconnect bus and set the value of the first attribute field in the first shadow register to the first preset value; if the check fails, set the value of the fourth attribute field in the first shadow register to the first preset value.
[0015] The CXL host bridge is used to synchronize the values of the first attribute field and the fourth attribute field in the first shadow register to the first capability register in order to achieve synchronous handshaking of the address window.
[0016] In one embodiment, the central processing unit is configured to: if it detects that the first attribute field in the first capability register is set to a first preset value, then process the next address window; if it detects that the fourth attribute field in the first capability register is set to a first preset value, then execute a handshake failure process.
[0017] In one embodiment, the CXL host bridge includes: a second capability register that does not store the first attribute field and the second attribute field, and a second shadow register corresponding to the second capability register;
[0018] The central processing unit is used to: write the information to be updated into the second shadow register during the CXL system initialization process;
[0019] The CXL host bridge is used to: set the value of the second attribute field in the second shadow register to the first preset value, generate an interrupt flag, and set the value of the first attribute field in the second shadow register to the second preset value;
[0020] The coprocessor is used to: when the interrupt flag is detected, read the information in the second shadow register through the interrupt service routine, copy the read information to the interconnect bus, and set the value of the first attribute field in the second shadow register to the first preset value;
[0021] The CXL host bridge is used to: when it detects that the first attribute field in the second shadow register is set to the first preset value, copy the information in the second shadow register to the second capability register, set the value of the second attribute field in the second shadow register to the second preset value, and send a write success response to the central processing unit.
[0022] Secondly, this application also provides a device handshake method, including:
[0023] During the CXL system initialization process, for each address window in the first capability register, the value of the first attribute field in the address window is read; if the value of the first attribute field is the second preset value, the value of the second attribute field in the address window is set to the second preset value, the information of the address window is updated, and then the value of the second attribute field in the address window is set to the first preset value.
[0024] An interrupt flag is generated when the value of the second attribute field in the address window is set to the first preset value.
[0025] When the interrupt flag is detected, the information copy value of the address window is interconnected via the interrupt service routine, and the value of the first attribute field in the first shadow register is set to the first preset value.
[0026] The value of the first attribute field in the first shadow register is synchronized to the first capability register to achieve synchronous handshaking of the address window.
[0027] Thirdly, this application also provides a computer device, including a memory and a processor. The memory stores a computer program, and when the processor executes the computer program, it implements the steps of the central processing unit, or the steps of the CXL host bridge, or the steps of the coprocessor in the system provided in the first aspect.
[0028] Fourthly, this application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the central processing unit, or the steps of the CXL host bridge, or the steps of the coprocessor in the system provided in the first aspect.
[0029] Fifthly, this application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the central processing unit, or the steps of the CXL host bridge, or the steps of the coprocessor in the system provided in the first aspect.
[0030] The aforementioned CXL system, device handshake method, computer device, readable storage medium, and program product include a central processing unit (CPU) used to read the value of the first attribute field in the address window; if the value of the first attribute field is a second preset value; setting the value of the second attribute field in the address window to the second preset value, updating the address window information, and then setting the value of the second attribute field in the address window to the first preset value. The CXL host bridge generates an interrupt flag when it detects that the value of the second attribute field in the address window has been set to the first preset value. The coprocessor, upon detecting the interrupt flag, copies the address window information to the interconnect bus via an interrupt service routine and sets the value of the first attribute field in the first shadow register to the first preset value; the CXL host bridge synchronizes the value of the first attribute field in the first shadow register to the first capability register to achieve synchronous handshake of the address window. This method ensures that when the upper-layer host modifies the CXL chip's built-in address window, it can synchronize to the bus bridge side, preventing the bus bridge from routing to the old address window when the upper-layer host uses a new address window to transmit services, thus avoiding service conflicts and bus hangs. Attached Figure Description
[0031] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.
[0032] Figure 1 Here is a topology diagram of the CXL system in one embodiment;
[0033] Figure 2 This is a schematic diagram of the handshake process in one embodiment. Figure 1 ;
[0034] Figure 3 This is a schematic diagram of the handshake process in one embodiment. Figure 2 . Detailed Implementation
[0035] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.
[0036] See Figure 1 As shown, the CXL system provided in this application embodiment may include an upper-layer host (including near-end memory 1~N and a central processing unit), an interconnect bus, a coprocessor, a CXL host bridge, CXL hosts 1~N, a CXL switch, CXL devices 1~N, and remote memory 1~N. The CXL host bridge includes a capability register and a shadow register. The connection from the interconnect bus to CXL hosts 1~N can be understood as the local side, the connection from the CXL host bridge to the CXL switch can be understood as the switch side, and the connection from CXL devices 1~N to remote memory 1~N can be understood as the device side. It should be noted that: Figure 1 This is merely an example; the topology from CXL host 1~N to remote memory 1~N can also be other forms, and this application embodiment does not limit this. The interconnect bus may include an address routing register for storing information copied from the registers of the CXL host bridge.
[0037] In some embodiments, the CXL host bridge may include two types of capability registers: one that stores a first attribute field and a second attribute field, and a capability register that does not store the first and second attribute fields. For ease of explanation, in this embodiment, the capability register storing the first and second attribute fields is referred to as the first capability register, and the capability register not storing the first and second attribute fields is referred to as the second capability register. Each capability register in the CXL host bridge has a corresponding shadow register, which can be used to store a copy of all the contents of the corresponding capability register. For ease of explanation, in this embodiment, the shadow register corresponding to the first capability register is referred to as the first shadow register, and the shadow register corresponding to the second capability register is referred to as the second shadow register. During the CXL system initialization process, each capability register needs to be processed to complete the handshake between the upper-layer host and the interconnect bus. It should be noted that including two types of capability registers in the CXL host bridge is only one possible case; the CXL host bridge may also contain only one type of register. This embodiment does not limit this and is related to the configuration of the CXL system itself.
[0038] The following describes the process of processing (configuration update) the first capability register.
[0039] Optionally, the first capability register contains multiple address windows, each storing a first attribute field and a second attribute field. When the first attribute field is at a first preset value, it indicates that the information in the corresponding address window of the first capability register has completed a synchronization handshake; when the first attribute field is at a second preset value, it indicates that the corresponding address window of the first capability register has not completed a synchronization handshake; when the second attribute field is at a first preset value, it indicates that the information in the corresponding address window of the first capability register has been updated, and when the second attribute field is at a second preset value, it indicates that the information in the corresponding address window of the first capability register has not been updated.
[0040] For example, the HDM decoding capability register specified in the CXL protocol can be used as the first capability register.
[0041] Optionally, the first attribute field can be the "committed" field, and the second attribute field can be the "commit" field.
[0042] Optionally, the first preset value can be, for example, 1, and the second preset value can be, for example, 0.
[0043] The following example illustrates this:
[0044] Taking a specific address window in the HDM decoding capability register as an example, a "committed" field of that address window being 1 indicates that the information in that address window has completed the synchronization handshake; a "committed" field being 0 indicates that the information in that address window has not completed the synchronization handshake. A "commit" field of that address window being 1 indicates that the information in that address window has been updated; a "commit" field being 0 indicates that the information in that address window has not been updated.
[0045] For each first capability register, all address windows within that register need to be processed one by one to complete the processing of that first capability register, i.e., to complete the synchronization handshake regarding that first capability register. The processing procedure is illustrated below using one address window as an example.
[0046] The central processing unit (CPU) reads the value of the first attribute field in the address window; if the value of the first attribute field is a second preset value, it sets the value of the second attribute field in the address window to the second preset value. After the address window information is updated, it sets the value of the second attribute field in the address window to the first preset value. The CXL host bridge generates an interrupt flag when it detects that the value of the second attribute field in the address window has been set to the first preset value. The coprocessor, upon detecting the interrupt flag, copies the address window information to the interconnect bus via an interrupt service routine and sets the value of the first attribute field in the first shadow register to the first preset value. The CXL host bridge synchronizes the value of the first attribute field in the first shadow register to the first capability register to achieve address window synchronization handshake.
[0047] The following example illustrates this:
[0048] Taking a specific address window in the HDM decoding capability register as an example, the CPU reads the value of the "committed" field in that address window. If the value of the "committed" field is 0, the CPU sets the "commit" field in that address window to 0, then updates the information in the address window. After the information in the address window is updated, the CPU sets the "commit" field in that address window to 1. When the CXL host bridge detects that the "commit" field in that address window is set to 1, it generates an interrupt flag. When the coprocessor detects this interrupt flag, it triggers an interrupt service routine. The interrupt service routine copies the information of the address window to the interconnect bus. Since the coprocessor can only access shadow registers, and only the CXL host bridge and the CPU can directly access the capability registers in the CXL host bridge, after the copy is completed, the interrupt service routine sets the "committed" field in that address window in the first shadow register corresponding to the HDM decoding capability register to 1. As described above, the shadow register can be used to store a copy of all the contents of the corresponding capability register. The CXL host bridge can be responsible for synchronizing the contents of the capability register and the corresponding shadow register in real time. Therefore, after the interrupt service routine sets the "committed" field in the address window of the first shadow register corresponding to the HDM decoding capability register to 1, the CXL host bridge synchronizes the value of the "committed" field in the address window of the first shadow register to the HDM decoding capability register. That is, it sets the value of the "committed" field in the address window of the HDM decoding capability register to 1, thereby realizing the synchronous handshake of the address window.
[0049] In the above embodiments, the central processing unit (CPU) reads the value of the first attribute field in the address window; if the value of the first attribute field is a second preset value, it sets the value of the second attribute field in the address window to the second preset value, updates the address window information, and after the address window information is updated, sets the value of the second attribute field in the address window to the first preset value. The CXL host bridge generates an interrupt flag when it detects that the value of the second attribute field in the address window has been set to the first preset value. The coprocessor, upon detecting the interrupt flag, copies the address window information to the interconnect bus via an interrupt service routine and sets the value of the first attribute field in the first shadow register to the first preset value. The CXL host bridge synchronizes the value of the first attribute field in the first shadow register to the first capability register to achieve address window synchronization handshake. This method ensures that when the upper-layer host modifies the CXL chip's built-in address window, it can synchronize to the bus bridge side, preventing the bus bridge from routing to the old address window when the upper-layer host uses a new address window to transmit services, thus avoiding service conflicts and bus hangs.
[0050] In some embodiments, the first capability register also stores a third attribute field, wherein when the third attribute field is a first preset value, it indicates that the corresponding address window in the first capability register has been locked; and when the third attribute field is a second preset value, it indicates that the corresponding address window in the first capability register has not been locked.
[0051] Each address window in the first capability register also stores a third attribute field.
[0052] Optionally, the third attribute field can be the "Lock On commit" field.
[0053] Optionally, the first preset value can be, for example, 1, and the second preset value can be, for example, 0.
[0054] During the CXL system initialization process, for each address window in the first capability register, the central processing unit (CPU) reads the values of the first attribute field and the third attribute field of the address window. If both the first and third attribute fields are at a second preset value, the CPU sets the value of the second attribute field in the address window to the second preset value, updates the address window information, and then sets the value of the second attribute field back to the first preset value after the address window information update is complete. In other words, based on the above embodiment, the CPU reads the value of the third attribute field while simultaneously reading the value of the first attribute field. If both the first and third attribute fields are at the second preset value, the CPU then executes the step of setting the value of the second attribute field in the address window to the second preset value, and subsequent steps.
[0055] The following example illustrates this:
[0056] Taking a certain address window in the HDM decoding capability register as an example, the central processing unit reads the values of the "committed" field and the "Lock On commit" field in the address window. If the values of both the "committed" field and the "Lock On commit" field are 0, the "commit" field in the address window is set to 0, and then the information in the address window is updated. After the update is completed, the "commit" field in the address window is set to 1. The steps after setting it to 1 are the same as in the previous embodiment. For details, please refer to the examples in the previous embodiment, which will not be repeated here.
[0057] In the above embodiments, the central processing unit (CPU) reads the values of the first attribute field and the third attribute field in the address window. If both the first and third attribute fields are at a second preset value, it then executes the step of setting the value of the second attribute field in the address window to the second preset value, as well as subsequent steps. The third attribute field can be used to lock the corresponding address window, enabling flexible control over whether to process a specific address window.
[0058] In some embodiments, the first capability register further stores a fourth attribute field, wherein when the fourth attribute field is a first preset value, it indicates that the consistency check of the corresponding address window in the first capability register has failed; and when the fourth attribute field is a second preset value, it indicates that the consistency check of the corresponding address window in the first capability register has passed.
[0059] Each address window in the first capability register also stores a fourth attribute field.
[0060] Optionally, the fourth attribute field can be the "Error not committed" field.
[0061] Optionally, the first preset value can be, for example, 1, and the second preset value can be, for example, 0.
[0062] The CXL host bridge is used to: set the values of the first attribute field and the fourth attribute field in the address window to a second preset value before generating an interrupt flag. The coprocessor is used to: perform a consistency check on the address window if the interrupt flag is detected; if successful, copy the address window information to the interconnect bus and set the value of the first attribute field in the first shadow register to the first preset value; if unsuccessful, set the value of the fourth attribute field in the first shadow register to the first preset value. The CXL host bridge is used to: synchronize the values of the first and fourth attribute fields in the first shadow register to the first capability register to achieve address window synchronization handshake.
[0063] Optionally, the above consistency check can check for issues such as address window conflicts or duplicates.
[0064] The following example illustrates this:
[0065] Taking a specific address window in the HDM decoding capability register as an example, the CPU reads the values of the "committed" and "Lock On commit" fields in that address window. If both the "committed" and "Lock On commit" fields are 0, the CPU sets the "committed" field to 0, updates the information in the address window, and then sets the "committed" field to 1. The CXL host bridge sets the "committed" and "Error not committed" fields to 0 in the address window and generates an interrupt flag. When the coprocessor detects this interrupt flag, it triggers an interrupt service routine. The interrupt service routine performs a consistency check on the address window. If the check passes, it copies the information of the address window to the interconnect bus and sets the "committed" field in the first shadow register corresponding to the HDM decoding capability register to 1, and sets the "Error not committed" field in the first shadow register to 0. The CXL host bridge then sets the "committed" and "Error not committed" fields in the first shadow register to 0. The value of the "committed" field is synchronized to the HDM decoding capability register. Specifically, the value of the "committed" field in that address window of the HDM decoding capability register is set to 1, and the value of the "Error not committed" field in that address window is set to 0. If the consistency check fails, the information in that address window is copied to the interconnect bus, and the "committed" field in that address window of the first shadow register corresponding to the HDM decoding capability register is set to 0, while the "Error not committed" field in that address window is set to 1. The CXL host bridge then synchronizes the values of the "committed" and "Error not committed" fields in that address window of the first shadow register to the HDM decoding capability register. Specifically, the value of the "committed" field in that address window of the HDM decoding capability register is set to 0, and the value of the "Error not committed" field in that address window is set to 1.
[0066] In the above embodiments, when the coprocessor detects the interrupt flag, it performs a consistency check on the address window. If the check passes, it copies the information of the address window to the interconnect bus and sets the value of the first attribute field in the first shadow register to the first preset value. If the check fails, it sets the value of the fourth attribute field in the first shadow register to the first preset value. The setting of the first attribute field and the fourth attribute field can trigger different processes, ensuring the smooth progress of initialization.
[0067] In some embodiments, the central processing unit is configured to: if it detects that the first attribute field in the first capability register is set to a first preset value, then process the next address window; if it detects that the fourth attribute field in the first capability register is set to a first preset value, then execute a handshake failure procedure.
[0068] The address windows in the first capability register are ordered. When the CPU detects that the first attribute field of the current address window in the first capability register is set to a first preset value, it then processes the next address window, and the processing is similar, as detailed in the aforementioned embodiment. When the CPU detects that the fourth attribute field of the current address window in the first capability register is set to a first preset value, it executes the handshake failure procedure.
[0069] The following example illustrates this:
[0070] For the HDM decoding capability register, if the central processing unit detects that the "committed" field of the current address window is 1, it will proceed to process the next address window (if one exists). If it detects that the "Error notcommitted" field of the current address window is 1, it will execute the handshake failure procedure.
[0071] In the above embodiments, if the central processing unit detects that the first attribute field in the first capability register is set to the first preset value, it then processes the next address window; if it detects that the fourth attribute field in the first capability register is set to the first preset value, it executes the handshake failure procedure. This ensures the smooth progress of initialization.
[0072] In some embodiments, see Figure 2 As shown, Figure 2The system includes host software, self-developed logic, and local firmware. The host software is run by the central processing unit (CPU), the self-developed logic is run by the CXL host bridge, and the local firmware is run by the coprocessor. The CPU, CXL host bridge, and coprocessor run their respective programs to achieve the functions described in the previous embodiments. Taking the HDM decoding capability register as an example, the processing procedure for the first capability register is explained. After the CXL host bridge is released by the host power-on, the coprocessor configures the HDM decoding capability register and the Internet bus register. The CPU performs operations such as CXL link establishment and device capability register scanning. Then, it reads whether the values of the "committed" field and the "Lock On commit" field in the current address window of the HDM decoding capability register are both 1. If not (i.e., both are 0), the CPU sets the "commit" field in the current address window to 0, updates the information in the current address window, and then sets the "commit" field in the address window to 1. The CXL host bridge sets the "committed" and "Error not committed" fields in the address window to 0, then generates an interrupt flag. When the coprocessor detects this interrupt flag, it triggers an interrupt service routine. The interrupt service routine performs a consistency check on the address window. If the check passes, it copies the information from the address window to the interconnect bus and sets the "committed" field in the first shadow register corresponding to the HDM decoding capability register to 1, and sets the "Error not committed" field to 0. If the consistency check fails, it copies the information from the address window to the interconnect bus and sets the "committed" field in the first shadow register to 0, and sets the "Error not committed" field to 1. The CXL host bridge then synchronizes the values of the "committed" and "Error not committed" fields in the first shadow register to the HDM decoding capability register. If the CPU detects that the “committed” field of the current address window is 1, it will then update the configuration of the next address window (if it exists). If it detects that the “Error not committed” field of the current address window is 1, it will execute the handshake failure procedure.In the previous check to see if the values of the “committed” field and the “Lock On commit” field in the current address window of the HDM decoding capability register are both 1, if the value of the “committed” field is 1, the configuration of the next address window will also be updated (if it exists).
[0073] The following describes the process of processing (configuration update) the second capability register.
[0074] Since the second capability register does not store the first and second attribute fields, it is necessary to add the first and second attribute fields to the corresponding second shadow register to implement a synchronization handshake regarding the second capability register. When the first attribute field is at a first preset value, it indicates that the information in the second capability register has completed the synchronization handshake; when the first attribute field is at a second preset value, it indicates that the information in the second capability register has not completed the synchronization handshake; when the second attribute field is at a first preset value, it indicates that the information in the second capability register has been updated; when the second attribute field is at a second preset value, it indicates that the information in the second capability register has not been updated.
[0075] For example, the extended security capability register specified in the CXL protocol can serve as a second capability register.
[0076] Optionally, the first attribute field can be the "committed" field, and the second attribute field can be the "commit" field. The first preset value can be, for example, 1, and the second preset value can be, for example, 0.
[0077] The central processing unit (CPU) writes the information to be updated into the second shadow register; the CXL host bridge sets the value of the second attribute field in the second shadow register to the first preset value, generates an interrupt flag, and sets the value of the first attribute field in the second shadow register to the second preset value; the coprocessor, upon detecting the interrupt flag, reads the information in the second shadow register through an interrupt service routine, copies the read information to the interconnect bus, and sets the value of the first attribute field in the second shadow register to the first preset value; the CXL host bridge, upon detecting that the first attribute field in the second shadow register is set to the first preset value, copies the information in the second shadow register to the second capability register, sets the value of the second attribute field in the second shadow register to the second preset value, and sends a write success response to the CPU.
[0078] The following example illustrates this:
[0079] Taking the Extended Security Capability Register (ESC) as an example, the CPU writes the information to be updated into the corresponding shadow register of the ESC. The CXL host bridge sets the "commit" field in the shadow register to 1, generates an interrupt flag, and sets the "committed" field in the shadow register to 0. When the coprocessor detects this interrupt flag, it triggers an interrupt service routine. The interrupt service routine reads the information from the shadow register, copies the information to the interconnect bus, and sets the "committed" field in the shadow register to 1. When the CXL host bridge detects that the "committed" field in the shadow register is set to 1, it copies the information from the shadow register to the ESC, sets the "commit" field in the shadow register to 0, and finally sends a write success response to the CPU. The configuration update of the ESC is then complete.
[0080] The above embodiments describe the configuration update process for the unstored first attribute field, second attribute field, and second capability register. This method completes the synchronous handshake regarding the second capability register. It ensures that when the upper-layer host modifies the CXL chip's built-in address window, the changes are synchronized to the bus bridge side. This avoids the bus bridge routing to the old address window when the upper-layer host uses the new address window to transmit services, thus preventing service conflicts and bus hangs.
[0081] In some embodiments, see Figure 3 As shown, Figure 3The system includes host software, self-developed logic, and local firmware. The host software is run by the central processing unit (CPU), the self-developed logic is run by the CXL host bridge, and the local firmware is run by the coprocessor. The CPU, CXL host bridge, and coprocessor run their respective programs to achieve the functions described in the previous embodiments. Taking the extended security capability register as an example, after the CXL host bridge is powered off by the host, the coprocessor configures the HDM decoding capability register and the Internet bus register. The CPU performs operations such as CXL link establishment and device capability register scanning, and then writes the information to be updated into the shadow register corresponding to the extended security capability register. The CXL host bridge sets the "commit" field in the shadow register to 1, generates an interrupt flag, and sets the "committed" field in the shadow register to 0. When the coprocessor detects the interrupt flag, it triggers an interrupt service routine. The interrupt service routine reads the information in the shadow register, copies the read information to the Internet bus, and sets the "committed" field in the shadow register to 1. When the CXL host bridge detects that the "committed" field in the shadow register is set to 1, it copies the information from the shadow register to the extended security capability register, sets the "commit" field in the shadow register to 0, and finally releases a write success response to the central processing unit. The configuration update of the extended security capability register is then complete. Proceed to the next extended security capability register instance (if any).
[0082] In some embodiments, a device handshake method is provided, applied to the CXL system described above, the method comprising:
[0083] During the CXL system initialization process, for each address window in the first capability register, the value of the first attribute field in the address window is read; if the value of the first attribute field is the second preset value, the value of the second attribute field in the address window is set to the second preset value, the information of the address window is updated, and then the value of the second attribute field in the address window is set to the first preset value.
[0084] An interrupt flag is generated when the value of the second attribute field in the address window is set to the first preset value.
[0085] When the interrupt flag is detected, the information copy value of the address window is interconnected via the interrupt service routine, and the value of the first attribute field in the first shadow register is set to the first preset value.
[0086] The value of the first attribute field in the first shadow register is synchronized to the first capability register to achieve synchronous handshaking of the address window.
[0087] Optionally, the above-mentioned device handshake method also includes:
[0088] During the CXL system initialization process, the information to be updated is written into the second shadow register;
[0089] Set the value of the second attribute field in the second shadow register to the first preset value, generate an interrupt flag, and set the value of the first attribute field in the second shadow register to the second preset value;
[0090] When the interrupt flag is detected, the information in the second shadow register is read through the interrupt service routine, the read information is copied to the interconnect bus, and the value of the first attribute field in the second shadow register is set to the first preset value.
[0091] If the first attribute field in the second shadow register is detected to be set to the first preset value, the information in the second shadow register is copied to the second capability register, the value of the second attribute field in the second shadow register is set to the second preset value, and a write success response is sent to the central processing unit.
[0092] The specific implementation process of the above-mentioned device handshake method is described in the foregoing embodiments and will not be repeated here.
[0093] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.
[0094] In one exemplary embodiment, a computer device is provided, including a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the steps of the central processing unit, or the steps of the CXL host bridge, or the steps of the coprocessor in the foregoing embodiments.
[0095] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the steps of the central processing unit, or the steps of the CXL host bridge, or the steps of the coprocessor in the foregoing embodiments.
[0096] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps of the central processing unit, or the steps of the CXL host bridge, or the steps of the coprocessor in the foregoing embodiments.
[0097] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, artificial intelligence (AI) processors, etc., and are not limited to these.
[0098] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.
[0099] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.
Claims
1. A computationally fast link (CXL) system, characterized in that, include: Upper-layer host, interconnect bus, coprocessor, and CXL host bridge; The upper-layer host includes a central processing unit; The CXL host bridge includes: a first capability register storing a first attribute field and a second attribute field, and a first shadow register corresponding to the first capability register; when the first attribute field is a first preset value, it indicates that the information in the corresponding address window in the first capability register has completed a synchronization handshake; when the first attribute field is a second preset value, it indicates that the corresponding address window in the first capability register has not completed a synchronization handshake; when the second attribute field is a first preset value, it indicates that the information in the corresponding address window in the first capability register has been updated; when the second attribute field is a second preset value, it indicates that the information in the corresponding address window in the first capability register has not been updated; wherein; The central processing unit is configured to: during the initialization process of the CXL system, for each address window in the first capability register, read the value of the first attribute field in the address window; if the value of the first attribute field is a second preset value; set the value of the second attribute field in the address window to the second preset value, update the information of the address window, and then set the value of the second attribute field in the address window to the first preset value; The CXL host bridge is used to generate an interrupt flag when it detects that the value of the second attribute field in the address window is set to a first preset value. The coprocessor is configured to: when the interrupt flag is detected, copy the information of the address window to the interconnect bus through the interrupt service routine, and set the value of the first attribute field in the first shadow register to a first preset value; The CXL host bridge is used to: synchronize the value of the first attribute field in the first shadow register to the first capability register, so as to realize the synchronous handshake of the address window.
2. The system according to claim 1, characterized in that, The first capability register also stores a third attribute field. When the third attribute field is a first preset value, it indicates that the corresponding address window in the first capability register has been locked; when the third attribute field is a second preset value, it indicates that the corresponding address window in the first capability register has not been locked. During the initialization process of the CXL system, for each address window in the first capability register, the central processing unit is configured to: read the value of the first attribute field and the value of the third attribute field in the address window; if the value of the first attribute field and the value of the third attribute field are both second preset values, set the value of the second attribute field in the address window to the second preset value; update the information of the address window; and then set the value of the second attribute field in the address window to the first preset value.
3. The system according to claim 1, characterized in that, The first capability register also stores a fourth attribute field. When the fourth attribute field is a first preset value, it indicates that the consistency check of the corresponding address window in the first capability register has failed; when the fourth attribute field is a second preset value, it indicates that the consistency check of the corresponding address window in the first capability register has passed. The CXL host bridge is used to: set the values of the first attribute field and the fourth attribute field in the address window to a second preset value before generating an interrupt flag; The coprocessor is configured to: when the interrupt flag is detected, perform a consistency check on the address window; if the check passes, copy the information of the address window to the interconnect bus and set the value of the first attribute field in the first shadow register to a first preset value; if the check fails, set the value of the fourth attribute field in the first shadow register to the first preset value. The CXL host bridge is used to synchronize the values of the first attribute field and the fourth attribute field in the first shadow register to the first capability register, so as to realize the synchronous handshake of the address window.
4. The system according to claim 1, characterized in that, The central processing unit is configured to: if it detects that the first attribute field in the first capability register is set to the first preset value, then process the next address window; if it detects that the fourth attribute field in the first capability register is set to the first preset value, then execute a handshake failure process.
5. The system according to claim 1, characterized in that, The CXL host bridge includes: a second capability register that does not store the first attribute field and the second attribute field, and a second shadow register corresponding to the second capability register; The central processing unit is used to: write the information to be updated into the second shadow register during the initialization process of the CXL system; The CXL host bridge is used to: set the value of the second attribute field in the second shadow register to a first preset value, generate an interrupt flag, and set the value of the first attribute field in the second shadow register to a second preset value; The coprocessor is configured to: when the interrupt flag is detected, read the information in the second shadow register through the interrupt service routine, copy the read information to the interconnect bus, and set the value of the first attribute field in the second shadow register to a first preset value; The CXL host bridge is used to: when it detects that the first attribute field in the second shadow register is set to a first preset value, copy the information in the second shadow register to the second capability register, set the value of the second attribute field in the second shadow register to a second preset value, and send a write success response to the central processing unit.
6. A device handshake method, characterized in that, Applied to the system according to any one of claims 1-5, the method comprises: During the initialization process of the CXL system, for each address window in the first capability register, the value of the first attribute field in the address window is read; if the value of the first attribute field is a second preset value, the value of the second attribute field in the address window is set to the second preset value, the information of the address window is updated, and then the value of the second attribute field in the address window is set to the first preset value. If the value of the second attribute field in the address window is detected to be set to the first preset value, an interrupt flag is generated; If the interrupt flag is detected, the information of the address window is copied to the interconnect bus through the interrupt service routine, and the value of the first attribute field in the first shadow register is set to the first preset value. The value of the first attribute field in the first shadow register is synchronized to the first capability register to achieve synchronous handshake of the address window.
7. The method according to claim 6, characterized in that, The method further includes: During the initialization process of the CXL system, the information to be updated is written into the second shadow register; Set the value of the second attribute field in the second shadow register to the first preset value, generate an interrupt flag, and set the value of the first attribute field in the second shadow register to the second preset value; When the interrupt flag is detected, the information in the second shadow register is read through the interrupt service routine, the read information is copied to the interconnect bus, and the value of the first attribute field in the second shadow register is set to the first preset value. If the first attribute field in the second shadow register is detected to be set to the first preset value, the information in the second shadow register is copied to the second capability register, the value of the second attribute field in the second shadow register is set to the second preset value, and a write success response is sent to the central processing unit.
8. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the central processing unit as claimed in claims 1 to 5, or the steps of the CXL host bridge, or the steps of the coprocessor.
9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the steps of the central processing unit as claimed in claims 1 to 5, or the steps of the CXL host bridge, or the steps of the coprocessor.
10. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by the processor, it implements the steps of the central processing unit as claimed in claims 1 to 5, or the steps of the CXL host bridge, or the steps of the coprocessor.