A multi-port series circuit breaker sharing an injection unit and a control method thereof

Abstract

This invention discloses a multi-port series circuit breaker with a shared injection unit and its control method. The circuit breaker includes a shared voltage injection unit, a fault selection unit, an integrated coupling inductor unit, and a multi-port main current-carrying branch. Multiple DC lines share a single voltage injection unit through the fault selection unit. The voltage injection unit injects reverse voltage into the faulty line through a pulse transformer to achieve active limitation and interruption of the fault current. This invention transforms passive commutation into series active current-limiting interruption. By sharing an active injection unit across multiple ports, the number of fully controlled switching transistors is reduced, resulting in fast interruption speed, low current loss, and low cost.

Description

Technical Field

[0001] This invention belongs to the field of power system protection and control technology, specifically relating to a multi-port series hybrid DC circuit breaker topology applied to flexible DC distribution networks, and a fault current active suppression and isolation control method based on this structure. Background Technology

[0002] With the advancement of the "dual carbon" target, renewable energy sources, represented by wind power and photovoltaics, are being integrated into the power grid on a large scale. DC distribution networks, due to their significant advantages in accommodating distributed energy and DC loads, have become an important development direction for new power systems. However, DC grids have the characteristics of low damping and no natural zero-crossing point. Once a short-circuit fault occurs, the fault current rise rate is extremely high. If the fault cannot be cleared within milliseconds, it will seriously threaten the safe and stable operation of the system.

[0003] Currently, fault isolation in DC power grids mainly relies on DC circuit breakers. Existing DC circuit breakers are mainly divided into three types: mechanical, solid-state, and hybrid. Among them, the hybrid DC circuit breaker combines the advantages of low conduction losses of mechanical switches and fast breaking speed of power electronic devices, and is currently the mainstream technical solution.

[0004] However, in multi-terminal DC grids, if each DC branch is independently equipped with a complete hybrid DC circuit breaker, the total number of fully controlled power electronic devices will increase dramatically as the number of grid ports and the breaking current demand increase. This results in high equipment costs, large footprint, and low equipment utilization, severely restricting the large-scale application of hybrid DC circuit breakers in multi-terminal DC grids. Furthermore, existing hybrid DC circuit breakers mostly use parallel commutation, requiring the mechanical switch to generate an arc or relying on auxiliary circuits to generate a zero-crossing point before current transfer can be completed. This passive commutation process results in breaking times typically exceeding 2-3 ms.

[0005] Therefore, there is an urgent need for a new type of DC circuit breaker and its control method that can reduce the number of fully controlled switching devices, lower the cost of multi-port configuration, and shorten the breaking time. Summary of the Invention

[0006] The purpose of this invention is to overcome the shortcomings of existing technologies, such as the large number of fully controlled switching devices, high cost, and long breaking time of parallel switching methods caused by the independent configuration of hybrid DC circuit breakers for multi-terminal DC power grids, and to provide a multi-port series circuit breaker with a shared injection unit and its control method.

[0007] To achieve the above objectives, the present invention provides the following technical solution:

[0008] In a first aspect, the present invention provides a multi-port series circuit breaker with a shared injection unit, comprising: a shared voltage injection unit, a fault selection unit, an integrated coupling inductor unit, and multiple DC ports corresponding to n DC lines respectively; each of the DC ports is provided with a main current-carrying branch, and each of the main current-carrying branches is connected in series with a fast mechanical switch (UFD) for conducting the rated current of the DC line during the normal current-carrying phase;

[0009] The integrated coupling inductor unit includes n pulse transformers, each pulse transformer including a primary winding and a secondary winding. The secondary windings are connected in series in the main current-carrying branch of the corresponding DC port, and are used to transmit the voltage generated by the shared voltage injection unit to the main current-carrying branch through electromagnetic coupling.

[0010] The fault selection unit includes n semi-controlled power devices, where n ≥ 2 and n is an integer; the pulse transformer, the semi-controlled power devices, and each DC port are configured in a one-to-one correspondence; one end of each semi-controlled power device is connected to the primary winding of the corresponding pulse transformer, and the other end is connected to the output terminal of the shared voltage injection unit; when a short-circuit fault is detected in the line of the corresponding DC port, the semi-controlled power device is turned on, connecting the shared voltage injection unit to the primary winding of the corresponding pulse transformer;

[0011] The shared voltage injection unit includes an energy storage capacitor and a fully controlled switching transistor. After being connected in series with the fault selection unit, it is associated with the main current-carrying branch through the electromagnetic coupling of the integrated coupling inductor unit. It is used to inject a reverse voltage in series in the main current-carrying branch of the fault line through a pulse transformer after the corresponding semi-controlled power device is turned on, so as to force the slope of the fault current to be less than zero, thereby realizing the active limitation and interruption of the fault current.

[0012] 2. Furthermore, the shared voltage injection unit adopts a flying capacitor structure, including a first energy storage capacitor (C1), a second energy storage capacitor (C2), a first fully controlled switch (S1), a second fully controlled switch (S2), a first diode (D1), and a second diode (D2).

[0013] The positive terminal of the first energy storage capacitor (C1) is connected to the collector of the first fully controllable switch (S1); the emitter of the first fully controllable switch (S1) is connected to the collector of the second fully controllable switch (S2), and the connection point is point A; the positive terminal of the second energy storage capacitor (C2) is connected to point A.

[0014] The cathode of the first diode (D1) is connected to point A, and the anode of the first diode (D1) is connected to the emitter of the second fully controlled switch (S2), with the connection point being point B; the cathode of the second energy storage capacitor (C2) is connected to point B; the cathode of the second diode (D2) is connected to point B.

[0015] The anode of the second diode (D2) is connected to the cathode of the first energy storage capacitor (C1), and the connection point is point C; point C serves as the common return terminal of the primary windings of each pulse transformer.

[0016] Point B is led outward as a voltage output terminal and connected to one end of each semi-controlled power device in the fault selection unit.

[0017] The first energy storage capacitor (C1) is used to provide discharge energy to the primary winding of the pulse transformer during the rapid fault current suppression phase and the arc suppression phase.

[0018] Furthermore, the semi-controlled power device is a thyristor, which is used to establish an injection channel for fault current through gate-triggered conduction, and automatically restores the blocking state after the loop current naturally decays to below its holding current; the pulse transformer adopts a fully coupled design with a turns ratio of N.

[0019] Furthermore, the first fully controlled switch (S1) and the second fully controlled switch (S2) are insulated gate bipolar transistor (IGBT) devices; the voltages of the first energy storage capacitor (C1) and the second energy storage capacitor (C2) satisfy the following constraint relationship, such that the reverse voltage N·U injected during the fault current rapid suppression phase... C1 Greater than the DC bus voltage U Ceq To force the fault current to decrease, the reverse voltage N·U injected during the fault current zero-limit modulation phase. C2 and N· (U C1 -U C2 All are less than U Ceq This allows the fault current to rise at a slow rate, while the voltage U of the first energy storage capacitor at the end of the arc suppression phase... C1 Termination greater than U Ceq / N to maintain arc suppression capability; where U C1 U is the voltage of the first energy storage capacitor. C2 The voltage of the second energy storage capacitor is denoted by , and N is the turns ratio of the pulse transformer.

[0020] Furthermore, the selection of the turns ratio N simultaneously satisfies the following condition: when the DC bus voltage U Ceq Once the voltage of the energy storage capacitor in the shared voltage injection unit is determined, the turns ratio N ensures that the reverse voltage injected through the pulse transformer during the rapid fault current suppression phase is greater than the DC bus voltage U. Ceq This is used to force the fault current to decrease, and the reverse voltage injected during the fault current zero-limiting modulation phase is less than the DC bus voltage U. Ceq It is used to make the fault current oscillate near zero at a controllable rate.

[0021] Secondly, the present invention provides a control method for a multi-port series circuit breaker with a shared injection unit, applied to the aforementioned multi-port series circuit breaker. The control method includes the following steps executed sequentially: Fault detection and line selection step: Real-time monitoring of the current in each DC port line; when a short-circuit fault is determined to have occurred in a certain line and the fault current reaches the action threshold I... th When the fault selection unit is activated, the semi-controlled power device corresponding to the faulty line is turned on, establishing a fault current injection channel.

[0022] Fault current rapid suppression steps: Control the fully controlled switch in the shared voltage injection unit to turn on, so that the energy storage capacitor discharges; the discharge current of the energy storage capacitor is electromagnetically coupled through the pulse transformer, and generates a reverse voltage in series in the main current-carrying branch of the fault line. The amplitude of the reverse voltage is greater than the DC bus voltage, and the slope of the fault current becomes negative.

[0023] Fault current zero-limit modulation step: In the fault current rapid suppression step, the fault current is reduced to a preset minimum current threshold i. min Subsequently, the fully controlled switching transistor is alternately turned off and on in pulse width modulation mode; by alternately discharging the energy storage capacitor, the fault current is modulated into a high-frequency AC ripple current near zero, thereby creating zero-current breaking conditions for the uninterruptible mechanical switch (UFD).

[0024] Arc suppression step: After the fault current is modulated to a ripple current near zero in the fault current zero-limit modulation step, the fast mechanical switch (UFD) in the main current-carrying branch of the fault line is controlled to disconnect under near-zero current conditions; at the same time, the energy storage capacitor continues to discharge through the excitation inductance of the secondary winding of the pulse transformer to suppress the voltage rise across the contacts of the fast mechanical switch (UFD) and prevent arc generation.

[0025] Residual energy dissipation steps: After the rapid mechanical switch (UFD) is completely disconnected, the trigger signal of the fully controlled switch is removed; the residual energy remaining in the coupling inductor is naturally dissipated through the internal resistance of the winding and the internal resistance of the transmission line; when the circuit current naturally decays to below the holding current of the semi-controlled power device, the semi-controlled power device automatically returns to the blocking state, completing the fault isolation.

[0026] 3. Furthermore, in the fault current zero-limit modulation step, the pulse width modulation mode includes four operating modes that alternate sequentially in the order of mode B, mode C, mode B, and mode D within one modulation cycle:

[0027] Mode B: The first fully controlled switch (S1) is turned on, the second fully controlled switch (S2) is turned on, the first energy storage capacitor (C1) is discharged, and the reverse voltage injected into the main current branch is N·U. C1 The reverse voltage is greater than the DC bus voltage U.Ceq The fault current decreases;

[0028] Mode C: The first fully controlled switch (S1) is turned off, the second fully controlled switch (S2) is turned on, the second energy storage capacitor (C2) is discharged, and the reverse voltage injected into the main current-carrying branch is N·U. C2 The reverse voltage is less than the DC bus voltage U. Ceq The fault current increases;

[0029] Mode B: The first fully controlled switch (S1) is turned on, the second fully controlled switch (S2) is turned on, the first energy storage capacitor (C1) is discharged, and the reverse voltage injected into the main current branch is N·U. C1 The reverse voltage is greater than the DC bus voltage U. Ceq The fault current decreases;

[0030] Mode D: The first fully controlled switch (S1) is turned on, and the second fully controlled switch (S2) is turned off. The voltage difference between the first energy storage capacitor (C1) and the second energy storage capacitor (C2) together injects a reverse voltage of N·(U) into the main current-carrying branch. C1 -U C2 The reverse voltage is less than the DC bus voltage U. Ceq The fault current increases;

[0031] By alternating the above four working modes, the high-frequency ripple of the fault current within one modulation cycle is strictly limited to near zero, while the voltage self-balancing of the first energy storage capacitor (C1) and the second energy storage capacitor (C2) is achieved; the modulation frequency of the pulse width modulation is 20kHz to 100kHz.

[0032] Furthermore, in the arc suppression step, the first fully controlled switch (S1) and the second fully controlled switch (S2) are simultaneously turned on, and the first energy storage capacitor (C1) discharges. The current starts from the positive terminal of the first energy storage capacitor (C1), flows sequentially through the first fully controlled switch (S1) and the second fully controlled switch (S2), and then flows into the corresponding semi-controlled power device in the fault selection unit. It then returns to the negative terminal of the first energy storage capacitor (C1) through the primary winding of the pulse transformer. This causes the first energy storage capacitor (C1) to discharge through the magnetizing inductance of the secondary winding of the pulse transformer, thereby suppressing the voltage rise across the contacts of the fast mechanical switch (UFD).

[0033] 4. Furthermore, the duration of each of the four alternating operating modes within a modulation cycle is determined by the following formulas:

[0034] Modulation frequency ;

[0035]

[0036] in, This represents the maximum change in fault current within a single modulation mode. For equivalent inductance, This refers to stray inductance in the circuit.

[0037] 5. Furthermore, the capacity of the first energy storage capacitor (C1) is selected based on the law of conservation of energy, satisfying the following energy balance equation:

[0038]

[0039] in, and These represent the voltages of the first energy storage capacitor (C1) at time t1 when the fault current reaches the operating threshold and at time t4 when the fast mechanical switch is completely disconnected, respectively. This is the inductance of the primary winding of the pulse transformer. This is the inductance of the secondary winding of the pulse transformer. This represents the peak value of the fault current. The operating threshold current, The load current is given. Since the current in the main current-carrying branch is approximately zero during the fault current zero-limiting modulation stage and the arc suppression stage, the above integral term can be approximately ignored. Simultaneously, it must satisfy...

[0040] After determining the capacitance value of the first energy storage capacitor (C1) based on the above energy balance equation, the capacitance value of the second energy storage capacitor (C2) is selected according to its voltage self-balancing characteristics, thereby selecting a smaller capacitance value than that of the first energy storage capacitor (C1).

[0041] The present invention has the following beneficial effects:

[0042] Multi-port sharing and low cost: Multiple DC lines share a single voltage injection unit and energy storage capacitor. Compared to configuring circuit breakers independently for each line, this greatly reduces the number of fully controlled switching devices, thereby reducing equipment costs and floor space.

[0043] Extremely short interruption time: This invention adopts a series commutation topology and directly injects reverse voltage into the main current-carrying branch, eliminating the passive commutation link and significantly shortening the fault interruption time to the sub-millisecond level. Attached Figure Description

[0044] Figure 1 This is a schematic diagram of a multi-port series circuit breaker topology with a shared injection unit provided in an embodiment of the present invention;

[0045] Figure 2 This is the equivalent circuit model of the multi-port series hybrid DC circuit breaker in the fault isolation process in the embodiments of the present invention;

[0046] Figure 3 This is a key waveform diagram of the fault current interruption process in an embodiment of the present invention;

[0047] Figure 4 This is a current flow diagram of the fault current rapid suppression stage (mode B) in an embodiment of the present invention;

[0048] Figure 5 This is a current flow diagram of mode C in the fault current zero-limit modulation stage in an embodiment of the present invention;

[0049] Figure 6 This is a current flow diagram of mode D in the fault current zero-limit modulation stage in an embodiment of the present invention;

[0050] Figure 7 This is a current flow diagram of the rapid rise phase of fault current (mode A) in an embodiment of the present invention;

[0051] Figure 8 This is a diagram showing the current flow during the energy dissipation stage in an embodiment of the present invention. Detailed Implementation

[0052] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings. The described embodiments are some, but not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. The reverse voltage mentioned in the present invention refers to a voltage with opposite polarity to the DC bus voltage induced in the main current-carrying branch by a pulse transformer, and the direction of this reverse voltage is to impede the further increase of the fault current.

[0053] Reference Figure 1 and Figure 2 This invention provides a multi-port series hybrid circuit breaker (MPS-HCB) with a shared injection unit, applicable to flexible DC distribution networks. The MPS-HCB includes a DC bus, a converter (MMC) connected to the DC bus, and multiple DC lines (line 1 to line n) connected in parallel to the DC bus. The circuit breaker includes a shared voltage injection unit (SVI), a fault selection unit (FS), an integrated coupling inductor unit (ICI), multiple DC ports corresponding to the n DC lines, and a control unit.

[0054] The integrated coupled inductor unit (ICI) comprises n pulse transformers, each pulse transformer comprising a primary winding (T... k-1 ) and secondary winding (T) kThe secondary winding is connected in series to the main current-carrying branch of the DC port corresponding to the k-th DC line, and one end of the primary winding is connected to the corresponding semi-controlled power device (Q). k The other end is connected to the output of the shared voltage injection unit. The fault selection unit (FS) contains n semi-controlled power devices (Q... n The pulse transformer and semi-controlled power devices are configured one-to-one with each DC port. n≥2, where n is an integer. One end of each semi-controlled power device is connected to the primary winding of the corresponding pulse transformer, and the other end is connected to the output terminal of the shared voltage injection unit. This is used to conduct when a short-circuit fault is detected in the corresponding DC port, connecting the shared voltage injection unit to the primary winding of the corresponding pulse transformer. Each DC port's main current-carrying branch has a fast mechanical switch (UFD) connected in series. The normal current-carrying stage described in this invention refers to the steady-state condition where the system is fault-free, the fast mechanical switch (UFD) is closed, the voltage injection unit is not working, the semi-controlled devices of the fault selection unit are off, and the DC grid is operating normally. During the normal current-carrying stage, the fast mechanical switch (UFD) carries the system's rated current, and its operating loss is approximately zero. Since only the fast mechanical switch (UFD) is installed in the main current-carrying branch without fully controlled power electronic devices, a water-cooling system is not required during on-state operation, improving the circuit breaker's reliability.

[0055] The shared voltage injection unit (SVI) includes an energy storage capacitor and a fully controlled switching transistor. The SVI is connected in series with the fault selection unit and is associated with the main current-carrying branch through electromagnetic coupling of the integrated coupling inductor unit. When a short-circuit fault is detected in a DC line, the corresponding semi-controlled power device turns on, connecting the shared voltage injection unit to the primary winding of the pulse transformer of that line. The shared voltage injection unit injects a reverse voltage in series into the main current-carrying branch of the faulty line through the pulse transformer, forcing the slope of the fault current to be less than zero, thus achieving active limitation and interruption of the fault current. Through this multi-port shared architecture, multiple DC lines share a single voltage injection unit and energy storage capacitor. Compared to configuring circuit breakers independently for each line, this significantly reduces the total number of fully controlled switching devices, lowers equipment costs and floor space, and improves component utilization. Simultaneously, because the reverse voltage is directly injected into the main current-carrying branch using a series commutation method, it eliminates the need for the complex timing coordination between the commutator switch and the main switch in traditional parallel circuit breakers, fundamentally eliminating the risk of commutation failure and improving commutation reliability.

[0056] In one specific embodiment, the semi-controlled power device (Q nThe thyristor has the characteristics of gate-triggered conduction and natural turn-off when the current crosses zero, making it suitable for the fault selection application scenario in this invention. The pulse transformer adopts a fully coupled design with a turns ratio of N. By adopting a fully coupled design, the voltage applied to the primary winding can be efficiently and completely coupled to the secondary winding, avoiding injection efficiency loss caused by leakage flux. In addition, the secondary winding of the pulse transformer also serves as the main current-carrying inductor in the main current-carrying branch. During the normal current-carrying phase, it carries the rated current of the system, and during the fault current rapid suppression phase, it withstands the reverse voltage generated by the shared voltage injection unit through electromagnetic coupling and generates a reverse electromotive force that cancels out the DC bus voltage. This eliminates the need to set up a separate current-limiting inductor in the main current-carrying branch, further simplifying the circuit structure.

[0057] Preferably, the shared voltage injection unit (SVI) adopts a flying capacitor structure, including a first energy storage capacitor (C1), a second energy storage capacitor (C2), a first fully controllable switch (S1), a second fully controllable switch (S2), a first diode (D1), and a second diode (D2). The positive terminal of the first energy storage capacitor (C1) is connected to the collector of the first fully controllable switch (S1) (i.e., the top DC bus of the SVI unit). The emitter of the first fully controllable switch (S1) is connected to the collector of the second fully controllable switch (S2), with the connection point being point A; the positive terminal of the second energy storage capacitor (C2) is connected to point A. The cathode of the first diode (D1) is connected to point A, and the anode of the first diode (D1) is connected to the emitter of the second fully controllable switch (S2), with the connection point being point B; the negative terminal of the second energy storage capacitor (C2) is connected to point B; the cathode of the second diode (D2) is connected to point B. The anode of the second diode (D2) is connected to the cathode of the first energy storage capacitor (C1), and the connection point is point C. Point C serves as the common return terminal for the primary windings of each pulse transformer (T1-1, T2-2, etc.). Point B is led outward as a voltage output terminal, connecting to each semi-controlled power device in the fault selection unit. By employing a flying capacitor structure, during the fault current-limited zero modulation stage, the voltage difference between the first energy storage capacitor (C1) and the second energy storage capacitor (C2) can be used for alternating discharge, achieving self-balancing of the voltage of the second energy storage capacitor (C2) within one modulation cycle. This allows the fully controlled switching transistor to switch only within a small voltage difference range, reducing the voltage stress on the switching transistor.

[0058] In one specific embodiment, the first fully controlled switch (S1) and the second fully controlled switch (S2) are insulated gate bipolar transistor (IGBT) devices. The first diode (D1) is connected between points A and B, providing a freewheeling path for the second energy storage capacitor (C2); the second diode (D2) is connected between points B and C, providing a return path for the primary winding current of the pulse transformer.

[0059] In one specific embodiment, the voltages of the first energy storage capacitor (C1) and the second energy storage capacitor (C2) satisfy the following constraint relationship to ensure that the conduction state of the fully controlled switch is determined by the control signal under any operating mode, avoiding forced conduction failure of the freewheeling diode due to reverse voltage:

[0060] During the rapid fault current suppression phase (Mode B):

[0061]

[0062]

[0063] Under mode C during the fault current-limited zero modulation stage:

[0064]

[0065] Under mode D during the fault current-limited zero modulation stage:

[0066]

[0067] in, This refers to the induced voltage in the secondary winding of the pulse transformer. The voltage of the first energy storage capacitor is denoted as . The voltage of the second energy storage capacitor is [value]. This is the DC bus voltage. The terminator is the voltage of the first energy storage capacitor at the end of the arc suppression phase, and N is the turns ratio.

[0068] In addition, the initial voltage UC1 of the first energy storage capacitor (C1) must also satisfy: ≥ ,in This indicates the maximum voltage generated on the primary winding of the pulse transformer when the first fully controlled switch (S1) is turned on.

[0069] In one specific embodiment, the selection of the turns ratio N simultaneously satisfies the following condition: when the DC bus voltage U Ceq Once the voltage of the energy storage capacitor in the shared voltage injection unit is determined, the turns ratio N ensures that the reverse voltage injected through the pulse transformer during the rapid fault current suppression phase is greater than the DC bus voltage U. Ceq (i.e. N·U C1 > U Ceq Furthermore, the reverse voltage injected during the fault current zero-limit modulation phase is less than the DC bus voltage U. Ceq (i.e. N·U C2 < U Ceq And N·(U C1 -U C2 ) < U Ceq). By reasonably selecting the turns ratio N, a sufficiently large reverse voltage can be obtained in the fast fault current suppression stage to force the fault current to decrease, and an appropriate reverse voltage can be obtained in the zero-crossing modulation stage of the fault current to make the fault current oscillate near zero at a controllable rate. The control requirements of the two stages are coordinately met by the same turns ratio N.

[0070] Referring to Figure 2 and Figure 3 , the control method provided by the embodiment of the present invention specifically includes the following five working stages executed in sequence. The states of the switching devices in each stage are summarized in the following table:

[0071] Work phase S1 S2 Q1 UFD1 The fault current rises rapidly (Mode A, t0-t1) Turn off Turn off Turn off closure Rapid suppression of fault current (Mode B, t1-t2) Conductivity Conductivity Conductivity closure Fault current zero-limit modulation (mode C / D alternation, t2-t3) alternately alternately Conductivity closure Arc suppression (Mode B, t3-t4) Conductivity Conductivity Conductivity Breaking off Energy dissipation (t4-t5) Turn off Turn off Natural shutdown It has been broken

[0072] The first stage is the fast rising stage of the fault current (t0 < t < t1), corresponding to mode A. Referring to Figure 7 , a short-circuit fault occurs at t = t0, and the fault current i1 increases rapidly. Before the voltage injection unit is activated, the secondary self-inductance of the pulse transformer generates a reverse transient voltage to passively suppress the rising rate of the fault current. In this stage, the first fully controlled switch (S1) is turned off, the second fully controlled switch (S2) is turned off, the semi-controlled power device (Q1) is turned off, and the fast mechanical switch (UFD1) is closed. Since the secondary winding of the pulse transformer is connected in series in the main current-carrying branch and also serves as the main current-carrying inductor, a reverse transient voltage can be generated instantly at the moment of the fault to suppress the rising rate of the fault current, thus winning a valuable time window for fault detection and line selection.

[0073] The second stage is the fast suppression stage of the fault current (t1 < t < t2), corresponding to mode B. Referring to Figure 4 , at t = t1, the fault current rises to the action threshold Ith, and the control unit triggers the semi-controlled power device (Q1) corresponding to the faulty line in the fault selection unit to conduct, establishing an injection channel for the fault current. At the same time, the first fully controlled switch (S1) and the second fully controlled switch (S2) in the control voltage injection unit are turned on, and the first energy storage capacitor (C1) starts to discharge. The current starts from the positive pole of the first energy storage capacitor (C1), flows through the first fully controlled switch (S1), the second fully controlled switch (S2) in sequence, and then flows into the semi-controlled power device (Q1), and returns to the negative pole (common return terminal) of the first energy storage capacitor (C1) through the primary winding (T1-1) of the pulse transformer. Through electromagnetic coupling, a voltage opposite to the polarity of the DC bus voltage is induced in the secondary winding, and the amplitude of this reverse voltage is N·U C1 , which is greater than the DC bus voltage U Ceq , and the slope of the fault current becomes negative, realizing the fast active suppression of the fault current.

[0074] The third stage is the fault current zero - limit modulation stage (t2 < t < t3). At t = t2, the fault current drops to the preset minimum current threshold i min Hereinafter, the MPS - HCB starts the fault current zero - limit modulation. In a specific embodiment, the minimum current threshold i min is the maximum current value allowed for the fast mechanical switch (UFD) to achieve arcless breaking. Its specific value is related to the equivalent inductance and resistance of the circuit, the inductance of the secondary winding of the pulse transformer, the voltage of the energy - storage capacitor, the turns ratio N, and the switching frequency and duty cycle of the pulse - width modulation.

[0075] The first fully - controlled switch (S1) and the second fully - controlled switch (S2) are alternately turned off and on in a pulse - width modulation mode, and the modulation frequency is from 20 kHz to 100 kHz. In a specific embodiment, the modulation frequency is 40 kHz. One modulation period contains four working modes that are alternately in the order of mode B, mode C, mode B, and mode D:

[0076] Mode C (refer to Figure 5 ) : When the first fully - controlled switch (S1) is turned off and the second fully - controlled switch (S2) is turned on, the second energy - storage capacitor (C2) discharges. The current starts from the positive pole (point A) of the second energy - storage capacitor (C2), flows through the second fully - controlled switch (S2) to point B, then flows into the semi - controlled power device (Q1), reaches point C (the common return terminal) through the primary winding of the pulse transformer (T1 - 1), and returns to point B (the negative pole of the second energy - storage capacitor (C2)) through the second diode (D2). The injected voltage is N·U C2 , and this voltage is less than the DC bus voltage U Ceq , and the fault current rises at a relatively slow rate. [[ID=…]] (The content continues in the original text, and you can provide the full text for a complete translation.)

[0077] Mode D (refer to <00003…]] (The content continues in the original text, and you can provide the full text for a complete translation.) Figure 6 C1 −U C2 ), and this voltage is less than the DC bus voltage U<…]] (The content continues in the original text, and you can provide the full text for a complete translation.) Ceq

[0078] By alternately switching the four modes of B, C, B, and D in sequence within one modulation period, the fault current decreases in mode B and increases in mode C or D, thereby being strictly limited to a high-frequency ripple state near zero. Meanwhile, the second energy storage capacitor (C2) alternately charges and discharges between mode C and mode D, and its voltage achieves self-balancing within one modulation period, enabling the fully controlled switch to switch only within a relatively small voltage difference range. Through the above zero-limiting modulation strategy, the fault current is forced to oscillate near zero, creating a continuous approximate zero-current window for the fast mechanical switch (UFD), allowing the fast mechanical switch (UFD) to trip under approximately arc-free conditions, significantly improving the service life and breaking reliability of the fast mechanical switch (UFD).

[0079] In a specific embodiment, the duration of each mode within the modulation period is determined by the following formula:

[0080] Modulation frequency

[0081]

[0082] Wherein, is the maximum change amount of the fault current within a single modulation mode (i.e., half of the ripple amplitude), is the equivalent inductance of the DC bus, is the stray inductance of the line. The above formula provides a theoretical basis for the control unit to generate the duty cycle of the pulse width modulation signal.

[0083] The fourth stage is the arc suppression stage (t3 < t < t4), corresponding to mode B. Referring to Figure 4 , at t = t3, the fast mechanical switch (UFD) breaks under approximately zero-current conditions. At this time, the first fully controlled switch (S1) and the second fully controlled switch (S2) are controlled to conduct simultaneously, and the first energy storage capacitor (C1) discharges. The current starts from the positive pole of the first energy storage capacitor (C1), flows through the first fully controlled switch (S1) and the second fully controlled switch (S2) in sequence, and then flows into the semi-controlled power device (Q1), and returns to the negative pole (common return terminal) of the first energy storage capacitor (C1) through the primary winding (T1-1) of the pulse transformer. The first energy storage capacitor (C1) discharges through the excitation inductance of the secondary winding of the pulse transformer, suppressing the voltage rise at both ends of the contacts of the fast mechanical switch (UFD), which is beneficial to suppressing the arc reignition and enabling the fast mechanical switch (UFD) to establish voltage blocking ability. The voltage level at both ends of the contacts is directly related to the voltage of the first energy storage capacitor (C1) and the turns ratio N.

[0084] The fifth stage is the energy dissipation stage (t4 < t < t5). Referring to Figure 8At time t=t4, the uncontrolled mechanical switch (UFD) is completely disconnected to block the DC voltage. At this time, the control unit removes the trigger signals of all fully controlled switches, and the remaining energy in the coupling inductor (T1) is naturally dissipated through the winding resistance, the switching devices, and the resistance of the transmission line. As the energy dissipates, the loop current gradually decreases. When the current naturally decays to below the holding current of the semi-controlled power device (Q1) (i.e., approximately zero), Q1, as a semi-controlled device, automatically returns to the blocking state without requiring additional auxiliary shutdown measures. After the energy dissipation is complete, the system returns to standby mode.

[0085] In one specific implementation, the capacity of the first energy storage capacitor (C1) is selected based on the law of conservation of energy, satisfying the following energy balance equation:

[0086]

[0087] in, and These represent the voltages of the first energy storage capacitor (C1) at time t1 when the fault current reaches the operating threshold and at time t4 when the fast mechanical switch is completely disconnected, respectively. This is the inductance of the primary winding of the pulse transformer. This is the inductance of the secondary winding of the pulse transformer. This represents the peak value of the fault current. The operating threshold current, The load current is given. Since the current in the main current-carrying branch is approximately zero during the fault current zero-limiting modulation stage and the arc suppression stage, the above integral term can be approximately ignored. Simultaneously, it must satisfy... .

[0088] After determining the capacitance value of the first energy storage capacitor (C1) based on the aforementioned energy balance equation, the capacitance value of the second energy storage capacitor (C2) is selected according to its voltage self-balancing characteristics. The voltage of the second energy storage capacitor (C2) can achieve self-balancing within one modulation cycle of the fault current interruption, so only a smaller capacitance value needs to be selected. Through the above parameter selection method, the capacitance value of the second energy storage capacitor (C2) is much smaller than that of the first energy storage capacitor (C1), further reducing the size and cost of the energy storage element.

[0089] In one specific embodiment, the present invention further includes a reclosing judgment step. After the remaining energy dissipation step is completed and before the reclosing operation is performed, the equivalent resistance R is extracted using the circuit characteristics of the fault current zero-limit modulation stage. eq Fault nature determination can be performed without the need for additional dedicated fault nature detection circuitry.

[0090] The principle of equivalent resistance calculation: the slope of the fault current and the equivalent resistance R eq (R) eq =R l1 / / R r1 The correlation between the fault current and its amplitude is strong. Under different fault characteristics (short-circuit resistance, stray inductance), the rate of change and amplitude of the fault current during the current modulation stage differ. The sampling method is as follows: at the end of two different modulation modes (mode C and mode D) during the zero-limit modulation stage, snapshots of the current net drive voltage, current, and rate of change of current are collected and recorded respectively. A system of two linear equations is established, and the equivalent resistance R is obtained by solving the system simultaneously. eq .

[0091] According to the fundamental equations of a circuit, in mode C:

[0092]

[0093] In mode D:

[0094]

[0095] At the end of each of the two modes, the current i1 and the rate of change of current were collected respectively. Because the injection voltages of the two modes are different, R eq and( Since they are the same, the two equations above can be combined to eliminate them. Solving for R yields... eq .

[0096] If a permanent metallic ground fault occurs, the impedance at the fault point is extremely low, and the calculated equivalent resistance Req is much smaller than the normal line impedance. In this case, reclosing is blocked to prevent the system from suffering secondary impact. If the fault is determined to be non-permanent, reclosing is performed. The number of modulation cycles required to complete the determination is no less than 50 cycles; the more cycles, the more accurate the calculation results. By utilizing the existing circuit characteristics during the zero-limit modulation stage to extract fault information to determine the fault nature, the cost and complexity of additional detection circuitry are avoided.

[0097] When two or more lines fail simultaneously (a relatively rare occurrence), it is recommended to prioritize troubleshooting the line with the larger fault current. Because each pulse transformer employs a fully coupled design, when the semi-controlled power device (Q) of a certain line... n After the circuit is turned on, the voltage injection unit begins to inject voltage into the primary of the corresponding pulse transformer. The secondary of the pulse transformer of other non-faulty lines may induce voltage due to the coupling effect. However, since the fast mechanical switch (UFD) of the non-faulty lines is in the closed state during the normal current-carrying phase, the line impedance is extremely low, and the induced voltage has little effect on the current of the non-faulty lines.

[0098] The following is a quantitative analysis of the impact on healthy lines (non-faulty lines) during the MPS-HCB fault isolation process.

[0099] When the MPS-HCB performs rapid fault current suppression, the voltage injection unit injects a reverse voltage into the faulty line. This reverse voltage changes the magnitude of the total DC bus current, thereby increasing the equivalent inductance L of the line. eq This generates a voltage that affects the current in the rest of the normally operating line. Specifically, this involves two aspects:

[0100] Maximum current drop rate: When the MPS-HCB operates in mode A (rapid fault current rise phase), the increase in fault current will be at L eq A voltage is generated at both ends, forcing the current in a healthy circuit to decrease. The slope of the current decrease in a healthy circuit k can be calculated by the following formula:

[0101]

[0102] in, This represents the current in the healthy circuit k during mode A; Indicates DC bus voltage Equivalent inductance of the line Load current The influence coefficient of the current drop rate. The maximum current drop of a healthy line during mode A is:

[0103]

[0104] Maximum current increment: When the MPS-HCB operates in mode B (rapid fault current suppression stage), the injected reverse voltage reduces the fault current, which is related to the line equivalent inductance. A reverse voltage is generated at both ends, causing an increase in the current in a healthy circuit. The rising slope of the current in a healthy circuit can be calculated by the following formula:

[0105]

[0106] in, This represents the minimum current that the healthy circuit k can reach after the end of mode A. The maximum current increment of the healthy circuit in mode B is:

[0107]

[0108] A case study is selected to conduct a theoretical analysis of the impact on a healthy transmission line. The parameters of the case study are shown in the table below:

[0109] parameter numerical values parameter numerical values <![CDATA[U Ceq ]]> 200V <![CDATA[L eq ]]> 100μH <![CDATA[R l1 ]]> 0.01Ω <![CDATA[L T1 ]]> 1.6mH <![CDATA[L l1 ]]> 10μH <![CDATA[U C1 ]]> 150V <![CDATA[U C2 ]]> 90V <![CDATA[I th ]]> 40A <![CDATA[C1]]> 2mF <![CDATA[C2]]> 2mF <![CDATA[I prek ]]> 20A n 3 N 2 — —

[0110] Calculations show that during fault isolation in MPS-HCB, the maximum current drop in the healthy line is 1.1A, and the maximum current increment is 2.48A, meaning the current in the healthy line fluctuates between 18.9A and 21.38A. Furthermore, the entire process lasts only a few milliseconds, resulting in minimal impact on the load of the healthy line. These analysis results demonstrate that the multi-port shared architecture of MPS-HCB has negligible impact on non-faulty lines during fault isolation, verifying the engineering feasibility of the proposed solution.

[0111] The control method of this embodiment can be summarized as follows:

[0112] Step 1, Normal Current Flow: The fast mechanical switch (UFD) is closed, the voltage injection unit is not working, and the system is in standby mode.

[0113] Step 2, Fault Detection: Monitor the line current in real time. When the current exceeds the action threshold I... th When this occurs, it is determined to be a short circuit fault.

[0114] Step 3, Fault Selection: Select the semi-controlled power device (Q) corresponding to the faulty circuit. n ), connect the voltage injection circuit.

[0115] Step 4, rapid suppression: The control voltage injection unit is turned on, causing the energy storage capacitor to discharge; the discharge current of the energy storage capacitor generates a reverse voltage N·U through the electromagnetic coupling of the pulse transformer. C1 The slope of the fault current becomes negative.

[0116] Step 5, Zero-limit modulation: When the fault current drops to i min When the current is switched to pulse width modulation control mode, the first energy storage capacitor (C1) and the second energy storage capacitor (C2) work alternately to clamp the current near zero.

[0117] Step 6, Fast Mechanical Switch Disconnection: Drive the fast mechanical switch (UFD) to disconnect during the current zero-crossing window.

[0118] Step 7, Arc Suppression and Energy Dissipation: Maintain the discharge of the first energy storage capacitor (C1) to suppress the arc. After the uncontrolled mechanical switch (UFD) is completely open, remove the trigger signals of all fully controlled switching transistors, and the loop current naturally decays to below that of the semi-controlled power device (Q). n After the holding current of the semi-controlled power device (Q) is reached, n It automatically restores the blocked state, releases the remaining magnetic field energy, and completes fault isolation.

[0119] Step 8, Reclosing Judgment: Based on the equivalent resistance R extracted during the zero-limit modulation stage. eq Determine the nature of the fault. If the equivalent resistance R eqIf the fault value is less than the preset fault determination threshold, it is determined to be a permanent fault and reclosing is blocked; if it is determined to be a non-permanent fault, reclosing is performed.

[0120] The specific principle of the reclosing judgment step is as follows:

[0121] During the zero-limit modulation phase of the fault current, the rate of change of the fault current satisfies the following relationship:

[0122]

[0123] in, This is the DC bus voltage. This refers to the voltage on the secondary winding of the pulse transformer. For fault current, The equivalent resistance at the fault point ( ), For equivalent inductance, This refers to stray inductance in the circuit.

[0124] Because the zero-limited modulation stage includes multiple operating modes, the injection voltage of the pulse transformer secondary winding is different in each mode: in mode B In mode C In mode D In different fault characteristics (short-circuit resistance) Stray inductance of the line Under current modulation, there are differences in the rate of change and amplitude of fault current. By analyzing the slope change of the fault current, it is possible to determine whether the fault is permanent. The slope of the fault current is related to the equivalent resistance. It has a strong correlation.

[0125] Specifically, a system of two linear equations is established using the circuit characteristics under different modulation modes during the zero-limit modulation stage. At the end of mode C:

[0126]

[0127] At the end of mode D:

[0128]

[0129] At the last frame after each of the two different modes, the current net drive voltage and current are captured and recorded respectively. and rate of change of current A snapshot. Due to the injection voltage of the two modes. Different, and and Since they are the same, the two equations above can be combined to eliminate them. The equivalent resistance is obtained by solving. .

[0130] If a permanent metallic grounding fault occurs, the impedance at the fault point is extremely small, and the calculated equivalent resistance... When the value is extremely small, close to zero, reclosing is blocked to prevent the system from suffering secondary impact. If the fault is determined to be non-permanent (equivalent resistance...), If the fault exceeds the preset fault determination threshold, a reclosing operation is performed. The number of modulation cycles required to complete the determination is no less than 50 cycles; the more cycles, the more accurate the calculation result.

[0131] By utilizing the existing circuit characteristics of the zero-limited modulation stage to extract fault information to determine the nature of the fault, there is no need to configure an additional dedicated fault nature detection circuit, which reduces system cost and complexity.

[0132] To verify the feasibility of the present invention, a complete set of simulation parameters and results are given using a two-port system as an example. The simulation parameters are shown in the table below:

[0133] parameter numerical values parameter numerical values <![CDATA[U Ceq (DC bus voltage) 750V <![CDATA[I th (Action threshold current) 100A <![CDATA[U C1 (Initial voltage of C1) 680V <![CDATA[U C2 (Initial voltage of C2) 340V N (variation ratio) 2 <![CDATA[L eq (Equivalent inductance) 200μH <![CDATA[Inductance of the secondary winding T1]]> 2.8mH <![CDATA[T 1-1 (Primary winding inductance) 0.7mH <![CDATA[C1 (Capacitance value of the first energy storage capacitor)]]> 600μF <![CDATA[C2 (Capacitance value of the second energy storage capacitor)]]> 200μF <![CDATA[R l1 (Resistance of the faulty circuit) 15Ω <![CDATA[R r1 (Short-circuit resistance) 0.001Ω <![CDATA[L fl (Faulty line inductance) 20μH M (mutual inductance) 1.4mH

[0134] Parameter verification: Under the above parameters, the injection voltage N·U in mode B C1 = 2 × 680 = 1360V > 750V (U Ceq ), meeting the requirement of rapid fault current suppression; Mode C injection voltage N·U C2 = 2 × 340 = 680V < 750V (U Ceq ), satisfying the requirement of a slow current rise; Mode D injection voltage N·(U C1 -U C2 ) = 2×(680−340) = 680V<750V (U Ceq ).

[0135] Reference Figure 3Simulation results show that, under the above parameter configuration: a short-circuit fault occurs in line 1 at t0≈0.02s, and the fault current rises rapidly; at t1≈0.0212s, the fault current reaches the action threshold Ith=100A, the voltage injection unit is activated, the fault current is rapidly suppressed, and the peak fault current i1max is approximately 200A; at t2≈0.0215s, the fault current drops to imin and enters the zero-limit modulation stage, where the fault current is modulated into a high-frequency ripple near zero; at t3≈0.027s, the uninterruptible mechanical switch (UFD) begins to disconnect at near-zero current; at t4≈0.028s, the uninterruptible mechanical switch (UFD) completely disconnects and enters the energy dissipation stage; at t5≈0.031s, the remaining energy dissipation is completed, and fault isolation ends. The fault interruption time from t1 to t4 is approximately 0.68ms, which is in the sub-millisecond range, verifying the fast interruption capability of the present invention. Meanwhile, during the fault isolation process, the current of the healthy line (line 2) only fluctuated slightly and quickly returned to the steady-state value after the fault isolation was completed, indicating that the multi-port shared architecture of MPS-HCB has little impact on the non-faulty lines.

[0136] In the energy dissipation stage of this invention, the remaining energy in the coupled inductor is naturally dissipated through the internal resistance of the winding and the internal resistance of the transmission line, eliminating the need for surge arresters and further reducing system cost and floor space.

Claims

1. A multi-port series circuit breaker with a shared injection unit, characterized in that, include: The system includes a shared voltage injection unit, a fault selection unit, an integrated coupling inductor unit, and multiple DC ports corresponding to n DC lines. Each DC port is equipped with a main current-carrying branch, and each main current-carrying branch is connected in series with a fast mechanical switch (UFD) to conduct the rated current of the DC line during the normal current-carrying phase. The integrated coupling inductor unit includes n pulse transformers, each pulse transformer including a primary winding and a secondary winding. The secondary windings are connected in series in the main current-carrying branch of the corresponding DC port, and are used to transmit the voltage generated by the shared voltage injection unit to the main current-carrying branch through electromagnetic coupling. The fault selection unit includes n semi-controlled power devices, where n ≥ 2 and n is an integer; the pulse transformer, the semi-controlled power devices, and each DC port are configured in a one-to-one correspondence; one end of each semi-controlled power device is connected to the primary winding of the corresponding pulse transformer, and the other end is connected to the output terminal of the shared voltage injection unit; when a short-circuit fault is detected in the line of the corresponding DC port, the semi-controlled power device is turned on, connecting the shared voltage injection unit to the primary winding of the corresponding pulse transformer; The shared voltage injection unit includes an energy storage capacitor and a fully controlled switching transistor. After being connected in series with the fault selection unit, it is associated with the main current-carrying branch through the electromagnetic coupling of the integrated coupling inductor unit. It is used to inject a reverse voltage in series in the main current-carrying branch of the fault line through a pulse transformer after the corresponding semi-controlled power device is turned on, so as to force the slope of the fault current to be less than zero, thereby realizing the active limitation and interruption of the fault current.

2. The multi-port series circuit breaker with shared injection unit as described in claim 1, characterized in that, The shared voltage injection unit adopts a flying capacitor structure, including a first energy storage capacitor (C1), a second energy storage capacitor (C2), a first fully controllable switch (S1), a second fully controllable switch (S2), a first diode (D1), and a second diode (D2). The positive terminal of the first energy storage capacitor (C1) is connected to the collector of the first fully controllable switch (S1); the emitter of the first fully controllable switch (S1) is connected to the collector of the second fully controllable switch (S2), and the connection point is point A; the positive terminal of the second energy storage capacitor (C2) is connected to point A. The cathode of the first diode (D1) is connected to point A, and the anode of the first diode (D1) is connected to the emitter of the second fully controlled switch (S2), with the connection point being point B; the cathode of the second energy storage capacitor (C2) is connected to point B; the cathode of the second diode (D2) is connected to point B. The anode of the second diode (D2) is connected to the cathode of the first energy storage capacitor (C1), and the connection point is point C; point C serves as the common return terminal of the primary windings of each pulse transformer. Point B is led outward as a voltage output terminal and connected to one end of each semi-controlled power device in the fault selection unit. The first energy storage capacitor (C1) is used to provide discharge energy to the primary winding of the pulse transformer during the rapid fault current suppression phase and the arc suppression phase.

3. The multi-port series circuit breaker with shared injection unit as described in claim 1, characterized in that... The semi-controlled power device is a thyristor, which is used to establish a fault current injection channel through gate-triggered conduction, and automatically restores the blocking state after the loop current naturally decays to below its holding current; the pulse transformer adopts a fully coupled design with a turns ratio of N.

4. The multi-port series circuit breaker with shared injection unit as described in claim 2, characterized in that... The first fully controlled switch (S1) and the second fully controlled switch (S2) are insulated gate bipolar transistor (IGBT) devices; the voltages of the first energy storage capacitor (C1) and the second energy storage capacitor (C2) satisfy the following constraint relationship, such that the reverse voltage N·U injected during the fault current rapid suppression phase... C1 Greater than the DC bus voltage U Ceq To force the fault current to decrease, the reverse voltage N·U injected during the fault current zero-limit modulation phase. C2 and N· (U C1 -U C2 All are less than U Ceq This allows the fault current to rise at a slow rate, while the voltage U of the first energy storage capacitor at the end of the arc suppression phase... C1 Termination greater than U Ceq / N to maintain arc suppression capability; where U C1 U is the voltage of the first energy storage capacitor. C2 The voltage of the second energy storage capacitor is denoted by , and N is the turns ratio of the pulse transformer.

5. The multi-port series circuit breaker with shared injection unit as described in claim 3, characterized in that... The selection of the turns ratio N simultaneously satisfies the following condition: when the DC bus voltage U Ceq Once the voltage of the energy storage capacitor in the shared voltage injection unit is determined, the turns ratio N ensures that the reverse voltage injected through the pulse transformer during the rapid fault current suppression phase is greater than the DC bus voltage U. Ceq This is used to force the fault current to decrease, and the reverse voltage injected during the fault current zero-limiting modulation phase is less than the DC bus voltage U. Ceq It is used to make the fault current oscillate near zero at a controllable rate.

6. A control method for a multi-port series circuit breaker with a shared injection unit, using the multi-port series circuit breaker as described in any one of claims 1-5, characterized in that, The following steps are performed sequentially: Fault detection and line selection steps: Real-time monitoring of the current of each DC port line; when a short circuit fault is determined to have occurred in a certain line and the fault current reaches the action threshold I. th When the fault selection unit is activated, the semi-controlled power device corresponding to the faulty line is turned on, establishing a fault current injection channel. Fault current rapid suppression steps: Control the fully controlled switch in the shared voltage injection unit to turn on, so that the energy storage capacitor discharges; the discharge current of the energy storage capacitor is electromagnetically coupled through the pulse transformer, and generates a reverse voltage in series in the main current-carrying branch of the fault line. The amplitude of the reverse voltage is greater than the DC bus voltage, and the slope of the fault current becomes negative. Fault current zero-limit modulation step: In the fault current rapid suppression step, the fault current is reduced to a preset minimum current threshold i. min Subsequently, the fully controlled switching transistor is alternately turned off and on in pulse width modulation mode; by alternately discharging the energy storage capacitor, the fault current is modulated into a high-frequency AC ripple current near zero, thereby creating zero-current breaking conditions for the uninterruptible mechanical switch (UFD). Arc suppression step: After the fault current is modulated to a ripple current near zero in the fault current zero-limit modulation step, the fast mechanical switch (UFD) in the main current-carrying branch of the fault line is controlled to disconnect under near-zero current conditions; at the same time, the energy storage capacitor continues to discharge through the excitation inductance of the secondary winding of the pulse transformer to suppress the voltage rise across the contacts of the fast mechanical switch (UFD) and prevent arc generation. Residual energy dissipation steps: After the rapid mechanical switch (UFD) is completely disconnected, the trigger signal of the fully controlled switch is removed; the residual energy remaining in the coupling inductor is naturally dissipated through the internal resistance of the winding and the internal resistance of the transmission line; when the circuit current naturally decays to below the holding current of the semi-controlled power device, the semi-controlled power device automatically returns to the blocking state, completing the fault isolation.

7. The control method as described in claim 6, characterized in that, In the fault current zero-limit modulation step, the pulse width modulation mode includes four operating modes that alternate sequentially in the order of mode B, mode C, mode B, and mode D within one modulation cycle: Mode B: The first fully controlled switch (S1) is turned on, the second fully controlled switch (S2) is turned on, the first energy storage capacitor (C1) is discharged, and the reverse voltage injected into the main current branch is N·U. C1 The reverse voltage is greater than the DC bus voltage U. Ceq The fault current decreases; Mode C: The first fully controlled switch (S1) is turned off, the second fully controlled switch (S2) is turned on, the second energy storage capacitor (C2) is discharged, and the reverse voltage injected into the main current-carrying branch is N·U. C2 The reverse voltage is less than the DC bus voltage U. Ceq The fault current increases; Mode B: The first fully controlled switch (S1) is turned on, the second fully controlled switch (S2) is turned on, the first energy storage capacitor (C1) is discharged, and the reverse voltage injected into the main current branch is N·U. C1 The reverse voltage is greater than the DC bus voltage U. Ceq The fault current decreases; Mode D: The first fully controlled switch (S1) is turned on, and the second fully controlled switch (S2) is turned off. The voltage difference between the first energy storage capacitor (C1) and the second energy storage capacitor (C2) together injects a reverse voltage of N·(U) into the main current-carrying branch. C1 -U C2 The reverse voltage is less than the DC bus voltage U. Ceq The fault current increases; By alternating the above four working modes, the high-frequency ripple of the fault current within one modulation cycle is strictly limited to near zero, while the voltage self-balancing of the first energy storage capacitor (C1) and the second energy storage capacitor (C2) is achieved; the modulation frequency of the pulse width modulation is 20kHz to 100kHz.

8. The control method as described in claim 6, characterized in that, In the arc suppression step, the first fully controlled switch (S1) and the second fully controlled switch (S2) are simultaneously turned on, and the first energy storage capacitor (C1) discharges. The current starts from the positive terminal of the first energy storage capacitor (C1), flows through the first fully controlled switch (S1) and the second fully controlled switch (S2) in sequence, and then flows into the corresponding semi-controlled power device in the fault selection unit. It then returns to the negative terminal of the first energy storage capacitor (C1) through the primary winding of the pulse transformer. This causes the first energy storage capacitor (C1) to discharge through the magnetizing inductance of the secondary winding of the pulse transformer, thereby suppressing the voltage rise across the contacts of the fast mechanical switch (UFD).

9. The control method as described in claim 7, characterized in that, The duration of the four alternating operating modes within a modulation period is determined by the following formulas: Modulation frequency ; in, This represents the maximum change in fault current within a single modulation mode. For equivalent inductance, This refers to stray inductance in the circuit.

10. The control method as described in claim 7 or 8, characterized in that, The capacity of the first energy storage capacitor (C1) is selected based on the law of conservation of energy, satisfying the following energy balance equation: in, and These represent the voltages of the first energy storage capacitor (C1) at time t1 when the fault current reaches the operating threshold and at time t4 when the fast mechanical switch is completely disconnected, respectively. This is the inductance of the primary winding of the pulse transformer. This is the inductance of the secondary winding of the pulse transformer. This represents the peak value of the fault current. The operating threshold current, The load current is given. Since the current in the main current-carrying branch is approximately zero during the fault current zero-limiting modulation stage and the arc suppression stage, the above integral term can be approximately ignored. Simultaneously, it must satisfy... After determining the capacitance value of the first energy storage capacitor (C1) based on the above energy balance equation, the capacitance value of the second energy storage capacitor (C2) is selected according to its voltage self-balancing characteristics, thereby selecting a smaller capacitance value than that of the first energy storage capacitor (C1).

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