Communication method, communication device, storage medium, and program product

Abstract

The embodiment of the disclosure provides a communication method, a communication device, a storage medium and a program product, relates to the technical field of communication, and can solve the technical problem of low spectrum efficiency in signal transmission in the related art. The method is applied to a first node, and the method comprises the following steps: obtaining a first bit sequence; performing shaping coding on a first part in the first bit sequence to obtain a second bit sequence; performing channel coding based on a second part in the first bit sequence and the second bit sequence to obtain a third bit sequence; modulating the third bit sequence to obtain a modulation symbol sequence; and sending a signal comprising the modulation symbol sequence to a second node.

Description

Technical Field

[0001] This disclosure relates to the field of communication technology, and in particular to a communication method, communication device, storage medium, and program product. Background Technology

[0002] In the fifth-generation (5G) mobile communication system standard of the 3rd Generation Partnership Project (3GPP), quadrature amplitude modulation (QAM) can be used to modulate and transmit signals, thereby improving link-level spectral efficiency.

[0003] However, signal modulation and transmission based solely on quadrature amplitude modulation suffers from low channel capacity, thus lacking a reliable and highly spectral-efficient communication method. Summary of the Invention

[0004] This disclosure provides a communication method, communication device, storage medium, and program product, which can solve the technical problem of low spectral efficiency during signal transmission in related technologies.

[0005] On the one hand, a communication method is provided, applied to the first node, the method including:

[0006] Obtain the first bit sequence;

[0007] The first part of the first bit sequence is shaped and encoded to obtain the second bit sequence;

[0008] Channel coding is performed on the second part of the first bit sequence and the second bit sequence to obtain the third bit sequence;

[0009] Modulating the third bit sequence yields a modulated symbol sequence;

[0010] Send a signal including a sequence of modulated symbols to the second node.

[0011] In another aspect, a communication device is provided, comprising: an acquisition module, a processing module, and a transmission module;

[0012] The acquisition module is used to acquire the first bit sequence;

[0013] The processing module is used to perform integer encoding on the first part of the first bit sequence to obtain the second bit sequence;

[0014] The processing module is also used to perform channel coding based on the second part of the first bit sequence and the second bit sequence to obtain the third bit sequence;

[0015] The processing module is also used to modulate the third bit sequence to obtain a modulated symbol sequence;

[0016] The transmitting module is used to send a signal including a modulation symbol sequence to the second node.

[0017] On the other hand, a communication method is provided for application to a second node, the method including:

[0018] Obtain the modulation order;

[0019] Receive signals including a modulated symbol sequence;

[0020] Based on the modulation order, the modulation symbol sequence is demodulated to obtain the third bit sequence;

[0021] Decoding the third bit sequence yields the second part of the first bit sequence and the second bit sequence.

[0022] The second bit sequence is shaped and decoded to obtain the first part of the first bit sequence;

[0023] Based on the first part and the second part, the first bit sequence is determined.

[0024] In another aspect, a communication device is provided, comprising: an acquisition module, a receiving module, and a processing module;

[0025] The acquisition module is used to obtain the modulation order;

[0026] A receiving module is used to receive signals including a modulation symbol sequence;

[0027] The processing module is used to demodulate the modulation symbol sequence based on the modulation order to obtain the third bit sequence;

[0028] The processing module is also used to decode the third bit sequence to obtain the second part of the first bit sequence and the second bit sequence;

[0029] The processing module is also used to perform shaping and decoding on the second bit sequence to obtain the first part of the first bit sequence;

[0030] The processing module is also used to determine the first bit sequence based on the first part and the second part.

[0031] In another aspect, a communication device is provided, comprising: a memory and a processor; the memory and the processor are coupled; the memory is used to store a computer program; and the processor, when executing the computer program, implements the method described in any of the above embodiments.

[0032] In another aspect, a computer-readable storage medium is provided, on which computer program instructions are stored, which, when executed by a processor, implement the method described in any of the above embodiments.

[0033] In another aspect, a computer program product is provided, the computer program product including computer program instructions that, when executed by a processor, implement the method described in any of the above embodiments.

[0034] This disclosure provides a communication method applied to a first node, the method including: acquiring a first bit sequence;

[0035] The first part of the first bit sequence is shaped and encoded to obtain the second bit sequence;

[0036] Channel coding is performed on the second part and the second bit sequence of the first bit sequence to obtain the third bit sequence; the third bit sequence is modulated to obtain the modulation symbol sequence; a signal including the modulation symbol sequence is transmitted to the second node. Shaping coding can convert the bit sequence corresponding to the first part into a bit sequence or symbol sequence with unequal probability distribution. Through unequal probability distribution, the frequency of different symbols appearing during signal transmission can be adjusted, thus ensuring that the occurrence of symbols during signal transmission is the desired outcome. Shaping coding only the first part of the first bit sequence allows for flexible adjustment of the spectral efficiency of the scheme compared to shaping coding the entire first bit sequence. Channel coding the second part and the second bit sequence of the first bit sequence yields a third bit sequence containing redundant bits, the second part of the first bit sequence, and the second bit sequence. Since redundant bits can assist in determining whether transmission errors exist and / or assist in correcting transmission errors, the reliability of data transmission can be improved. By shaping coding the first part of the first bit sequence to obtain the second bit sequence, the shaping coding of the bit sequence to be transmitted can be achieved efficiently, flexibly, and reliably, producing the desired effect corresponding to the shaping coding. A third bit sequence containing redundant bits is obtained by channel coding based on the second part of the first bit sequence and the second bit sequence. This ensures that the first node can reliably transmit signals including the modulation symbol sequence to the second node, and improves the reliability of data transmission. Attached Figure Description

[0037] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings.

[0038] Figure 1 This disclosure provides a system architecture diagram of a communication system.

[0039] Figure 2 A block diagram of a transmitter link with probability amplitude shaping provided for some embodiments of this disclosure;

[0040] Figure 3 This is a block diagram of a shaping encoder provided in this disclosure;

[0041] Figure 4 A block diagram of a block code-based shaping encoder link provided in this disclosure;

[0042] Figure 5 A block diagram of a low-density parity check code encoding chain provided in this disclosure;

[0043] Figure 6 A block diagram of another shaping encoder provided in this disclosure;

[0044] Figure 7 A block diagram of another shaping encoder provided in this disclosure;

[0045] Figure 8 A block diagram of a channel encoder provided in this disclosure;

[0046] Figure 9 A flowchart illustrating a communication method provided in this disclosure;

[0047] Figure 10 This is a schematic diagram illustrating the relationship of a bit sequence provided in this disclosure;

[0048] Figure 11 A flowchart illustrating another communication method provided in this disclosure;

[0049] Figure 12 This is a schematic diagram of the structure of a communication device provided in this disclosure;

[0050] Figure 13 A schematic diagram of another communication device provided in this disclosure;

[0051] Figure 14 A schematic diagram of another communication device provided in this disclosure. Detailed Implementation

[0052] The technical solutions of this disclosure will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0053] It should be noted that, in this disclosure, the terms "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in this disclosure should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0054] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature.

[0055] In the description of this disclosure, unless otherwise stated, " / " means "or," for example, A / B can mean A or B. "And / or" in this document is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, and B alone. Furthermore, "at least one" means one or more, and "more than one" means two or more.

[0056] In this disclosure, mod(x,y) represents the modulo operation, that is, the remainder when x is divided by y. ceil(x) or `floor(x)` is the floor function, representing the smallest integer greater than or equal to `x`. Let be the floor function, representing the largest integer less than or equal to x. In the description of this disclosure, the notations S(n) to S(p) and [S(n),...,S(p)] are equivalent and interchangeable, both representing a sequence containing p-n+1 elements. The number of elements p-n+1 contained in the sequence S(n) to S(p) is also called the length or size of the sequence. Without ambiguity, the letter S can also refer to the sequence [S(n),...,S(p)]. For two sequences S1 = [S1(n1),...,S1(p1)] and S2 = [S2(n2),...,S2(p2)], [S1,S2] represents the sequence [S1(n1),...,S1(p1),S2(n2),...,S2(p2)] of length p1-n1+p2-n2+2 formed by concatenating the sequences S1 = [S1(n1),...,S1(p1)] and S2 = [S2(n2),...,S2(p2)] and S2 = [S2(n2),...,S2(p2)].

[0057] In the 5G standard of the 3G Partnership, quadrature amplitude modulation can be used for signal modulation and transmission, thereby improving link spectrum efficiency.

[0058] However, signal modulation and transmission based solely on quadrature amplitude modulation suffers from low channel capacity, thus lacking a reliable and highly spectral-efficient communication method.

[0059] To address the aforementioned technical problems, this disclosure provides a communication method in which shaping encoding can convert the bit sequence corresponding to the first part into a bit sequence or symbol sequence with unequal probability distribution. By using unequal probability distribution, the frequency of different symbols appearing during signal transmission can be adjusted, thus ensuring that the occurrence of symbols during signal transmission is the desired outcome. Shaping encoding only the first part of the first bit sequence allows for flexible adjustment of the spectral efficiency of the scheme compared to shaping encoding the entire first bit sequence. Channel coding of the second part and the second bit sequence in the first bit sequence yields a third bit sequence containing redundant bits, the second part of the first bit sequence, and the second bit sequence. Since redundant bits can assist in determining whether transmission errors exist and / or assist in correcting transmission errors during data transmission, the reliability of data transmission can be improved. Obtaining the second bit sequence by shaping encoding the first part of the first bit sequence allows for efficient, flexible, and reliable shaping encoding of the bit sequence to be transmitted, producing the desired effect corresponding to the shaping encoding. The third bit sequence containing redundant bits is obtained by channel coding of the second part and the second bit sequence in the first bit sequence. This ensures that the first node can reliably send signals, including the modulation symbol sequence, to the second node, and improves the reliability of data transmission.

[0060] The communication method provided in this disclosure can be applied to systems with various communication standards. For example, the systems to which the communication method provided in this disclosure is applicable include, but are not limited to, long-term evolution (LTE) systems, various versions based on LTE evolution, 5th generation mobile communication technology (5G) systems, future mobile communication networks (such as 6G and 7G mobile communication networks), or multiple converged communication systems. Furthermore, the communication method provided in this disclosure can also be applied to future-oriented communication systems.

[0061] For example, the above communication method can be applied to, for example, Figure 1 In the aforementioned communication system, such as Figure 1 As shown, the communication system includes: a first node 101 and a second node 102.

[0062] The first node 101 is used to perform shaping encoding on the first part of the first bit sequence to obtain the second bit sequence; or to perform channel coding on the second part of the first bit sequence and the second bit sequence to obtain the third bit sequence; or to modulate the third bit sequence to obtain the modulation symbol sequence, and send a signal including the modulation symbol sequence to the second node 102.

[0063] The second node 102 is used to receive a signal including a modulation symbol sequence; or to demodulate the modulation symbol sequence based on the modulation order to obtain a third bit sequence; or to decode the third bit sequence to obtain a second part of the first bit sequence and a second bit sequence; or to perform shaping decoding on the second bit sequence to obtain a first part of the first bit sequence; or to determine the first bit sequence based on the first part and the second part.

[0064] In some embodiments, the first bit sequence may be referred to as the information bit sequence.

[0065] In some embodiments, the first node 101 and the second node 102 satisfy one of the following:

[0066] The first node 101 is a base station, and the second node 102 is a terminal;

[0067] The first node 101 is a terminal, and the second node 102 is a base station;

[0068] The first node 101 is a terminal, and the second node 102 is a terminal.

[0069] In some embodiments, the terminal can be a device with wireless transceiver capabilities, which can be deployed on land, including indoors or outdoors, handheld, wearable, or vehicle-mounted; it can also be deployed on water (such as on ships); and it can also be deployed in the air (e.g., on airplanes, balloons, and satellites). The terminal can be a mobile phone, tablet computer, computer with wireless transceiver capabilities, virtual reality (VR) terminal, augmented reality (AR) terminal, wireless terminal in industrial control, wireless terminal in self-driving, wireless terminal in remote medical care, wireless terminal in smart grid, wireless terminal in transportation safety, wireless terminal in smart city, wireless terminal in smart home, etc. The embodiments of this application do not limit the application scenarios. The term "terminal" can sometimes also refer to a user, user equipment (UE), access terminal, UE unit, UE station, mobile station, mobile station, remote station, remote terminal, mobile device, UE terminal, wireless communication device, UE agent, or UE device, etc., but the embodiments of this application do not limit this to these terms.

[0070] In some embodiments, the base station may be a base station in Long Term Evolution (LTE), Long Term Evolution Advanced (LTEA), or an evolved Node B (eNB or eNodeB), a base station device in a 5G network, or a base station in a future communication system, such as gNB, gNodeB, hNB, hNodeB, iNB, or iNodeB. The base station may include various macro base stations, micro base stations, femtocell base stations, wireless remotes, reconfigurable intelligent surfaces (RISS), routers, wireless fidelity (WIFI) devices, or various network-side devices such as primary cells and secondary cells.

[0071] It should be noted that, Figure 1 This is just an example framework diagram. Figure 1 The number of devices included and the names of each device are unlimited.

[0072] like Figure 2 The diagram shown is a block diagram of a probability amplitude shaping transmitter chain provided in an embodiment of this disclosure, including a splitter 201, a shaping encoder 202, a channel encoder 203, and a modulation mapper 204.

[0073] The splitter 201 is used to split, segment, or separate the first bit sequence into a first part and a second part.

[0074] In some embodiments, the first bit sequence can be a bit sequence b(0) to b(K-1) consisting of K bits. One part is a bit sequence [b1(0),...,b1(K1-1)] consisting of K bits, and the second part is a bit sequence [b2(0),...,b2(K2-1)] consisting of K2 bits, where K1 and K2 are non-negative integers, and K, K1, and K2 satisfy K = K1 + K2.

[0075] In some embodiments, b = [b1, b2].

[0076] In some embodiments, b = [b2, b1].

[0077] In some embodiments, a bit sequence b(0) to b(K-1) comprising K bits is a sequence of bits constituting a transport block, wherein the length of the bit sequence b(0) to b(K-1) or the number of bits K is the transport block size.

[0078] In some embodiments, the sequence includes a bit sequence b(0) to b(K-1) of K bits, which is the bits of the transport block and the cyclic redundancy check bits calculated from the bits of the transport block. The length or number of bits K of the bit sequence b(0) to b(K-1) is the sum of the bits of the transport block, the number of bits of the transport block, and the number of cyclic redundancy check bits calculated from the bits of the transport block.

[0079] The shaping encoder 202 takes the data of the first part b1(0) to b1(K1-1) of the bit sequence b(0) to b(K-1) as input. It is used to obtain a shaped encoded bit sequence c(0) to c(N1-1) of length N1 from the K1 bits of the first part b1(0) to b1(K1-1) according to the specified non-uniform probability distribution.

[0080] In some embodiments, the ratio K1 of the number of bits in the first part b1(0) to b1(K1-1) and N1 of the number of bits in the shaped bit sequence c(0) to c(N1-1) is called the shaping rate. In this application, the shaping rate is denoted as R. sh Therefore, we have R. sh =K1 / N1.

[0081] In some embodiments, the first part b1(0) to b1(K1-1) is divided into multiple blocks and then shaped and encoded to obtain a bit sequence c of multiple shaped blocks. r The bit sequence c of multiple shaping blocks. r Concatenate to obtain the integer encoded bit sequence c(0)~c(N1-1).

[0082] The channel encoder 203 takes the second part of the bit sequence b2(0)~b2(K2-1) output by the splitter 201 and the bit sequence c(0)~c(N1-1) output by the shaping encoder 202 as input. The channel encoder 203 encodes the input to obtain a channel encoder output bit sequence g(0)~g(Ng-1) of multiple shaping blocks with a length of Ng. Here, Ng is a positive integer.

[0083] In some embodiments, the output bit sequence g(0)~g(Ng-1) of the channel encoder is called the codeword of the channel encoder.

[0084] In some embodiments, the output bit sequence g(0) to g(Ng-1) of the channel encoder is called the check bit sequence of the channel encoder.

[0085] In some embodiments, the channel encoder 203 is typically implemented using binary forward error correction (FEC) codes.

[0086] In some embodiments, the forward error correction code can be one of the following: polar code, low-density parity check code, convolutional code, turbo code, Reed-Muller code, Reed-Solomon code, Bose-Chaudhuri-Hocquenghem code, concatenated code, cyclic code, block code, Hamming code, Golay code, repetition code, or single-parity-check code.

[0087] In some embodiments, the ratio of the length of the input bit sequence of the channel encoder 203 to the length of the output bit sequence of the channel encoder 203 is called the code rate of the FEC code. In this application, the code rate of the FEC code is denoted as R. fec .

[0088] In some embodiments, the FEC code rate R fec It may be specified by the modulation and coding scheme (MCS) and may be indicated by an MCS table.

[0089] Modulation mapper 204 takes the encoded channel encoder output bit sequence g(0)~g(Ng-1) as input. Modulation mapper 204 is configured to map the channel encoder output bit sequence (g) to symbols (e.g., QAM symbols, amplitude-shift keying (ASK) symbols) to obtain a sequence of shaping symbols X(0)~X(Nx-1).

[0090] In some embodiments, the transmitter link further includes a transmitter. The shaped symbol sequence can be transmitted via the transmitter over a wireless channel.

[0091] like Figure 3 The diagram shown is a block diagram of a shaping encoder 202 provided in an embodiment of this application, including a distribution matcher (DM) 301 and an amplitude-to-bit mapper 302.

[0092] The distribution matcher 301 is used to map the K1 bits of the first part b1(0) to b1(K1-1) to the amplitude symbol sequence A(0) to A(NA-1) of the specified non-uniform probability distribution, where NA is a positive integer.

[0093] In some embodiments, each element A(j) in the amplitude symbol sequence takes a value from the set {1,3,5,...,(2...}. Qm / 2 -3),(2 Qm / 2 -1)}, that is, A(j)∈{1,3,5,...,(2 Qm / 2 -3),(2 Qm / 2 -1)}, where Qm is the modulation order of the quadrature amplitude modulation constellation used by the modulation mapper 204 in the transmitter link.

[0094] In some embodiments, each element A(j) in the amplitude symbol sequence takes a value from the amplitude set {1,3,5,...,(2...}). m -3),(2 m -1)}, where m is the modulation order of the amplitude shift keying modulation used by the modulation mapper 104 in the transmitter link. Hereafter, the set {1,3,5,...,(2)} is referred to as the set {1,3,5,...,(2)}. Qm / 2 -3),(2 Qm / 2 -1)} or {1,3,5,...,(2 m -3),(2 m -1)} is the amplitude set.

[0095] In some embodiments, the ratio K1 of the number of bits K1 in the first part b1(0) to b1(K1-1) and the number of amplitudes NA in the amplitude symbol sequence A(0) to A(NA-1) is called the shaping rate. In this case, the shaping rate is also called the distribution matching rate, and the distribution matching rate is also denoted as R. sh R sh =K1 / NA. Let Pr(A(j)=2i+1) denote the probability that the amplitude symbol A(j) takes the value 2i+1 in all possible amplitude symbol sequences.

[0096] In some embodiments, the integer code rate R sh The amplitude entropy H(A) of the amplitude symbol sequence is determined, and this process satisfies the following formula 1:

[0097]

[0098] Where Qm is the modulation order of the quadrature amplitude modulation constellation used by the modulation mapper 204 in the transmitter link. In some embodiments, the integer code rate R sh The amplitude entropy H(A) of the amplitude symbol sequence is determined, and this process satisfies the following formula 2:

[0099]

[0100] Where m is the modulation order of amplitude shift keying modulation used by modulation mapper 204 in the transmitter link. A non-uniform probability distribution means that there exists i ≠ i' such that Pr(A(j)=2i+1) ≠ Pr(A(j)=2i'+1).

[0101] The bit mapper 302 takes the amplitude symbol sequence A(0)~A(NA-1) output by the distribution matcher 301 as input; the amplitude to bit mapper 302 can output an ordered bit sequence c(0)~c(N1-1).

[0102] In some embodiments, the amplitude-to-bit mapper 302 converts each amplitude A(j) in the amplitude symbol sequence into Qm / 2-1 bits c(j·(Qm / 2-1)), c(j·(Qm / 2-1)+1),...,c(j·(Qm / 2-1)+Qm / 2-2) according to a preset mapping method, and then concatenates them into an ordered bit sequence c(0)~c(N1-1), where the length N1 of the ordered bit sequence c(0)~c(N1-1) is equal to NA·(Qm-2), Qm is the modulation order of the orthogonal amplitude modulation constellation used by the modulation mapper 204 in the transmitter link, and NA is less than or equal to twice the length of the modulation symbol sequence output by the modulation mapper 204 in the transmitter link.

[0103] In some embodiments, the amplitude-to-bit mapper 302 converts each amplitude A(j) in the amplitude symbol sequence into m-1 bits c(j·(m-1)), c(j·(m-1)+1),...,c(j·(m-1)+m-2) according to a preset mapping method, and then concatenates them into an ordered bit sequence c(0)~c(N1-1), where the length N1 of the ordered bit sequence c(0)~c(N1-1) is equal to NA·(m-1), m is the modulation order of the amplitude shift keying modulation used by the modulation mapper 204 in the transmitter link, and NA is less than or equal to the length of the modulation symbol sequence output by the modulation mapper 204 in the transmitter link.

[0104] For example, Table 1 shows a variety of amplitude-to-bit mapping methods.

[0105] Table 1

[0106]

[0107] The diagram shows the bit strings mapped to the amplitude when Qm and m have different values, with N / A indicating that it is not applicable.

[0108] In some embodiments, the ratio K1 of the number of bits K1 in the first part b1(0) to b1(K1-1) input to the distribution matcher 301 and the number of bits N1 in the ordered bit sequence c(0) to c(N1-1) output by the amplitude-to-bit mapper 302 is called the shaping code rate. This shaping code rate is also called the distribution matching code rate, and it is denoted as R. sh R sh =K1 / N1.

[0109] It should be noted that the distributed matcher 301 is the key to the PAS architecture and is the earliest implementation of the shaping encoder in the PAS architecture. A transmitter with a PAS architecture can provide non-uniform (i.e., shaped) probability modulation symbols for the constellation through the distributed matcher. Relying on PAS technology, the distributed matcher 301 can take a sequence containing K1 independent bits as input and provide a sequence of amplitude symbols (containing NA bits) with non-uniform probability as output. This amplitude symbol sequence represents the first part of the message, b1(0) to b1(K1-1).

[0110] In some embodiments, the distributed matcher may use any of a number of suitable algorithms and any of a number of suitable configurations.

[0111] In some embodiments, the distribution matcher 301 can be one of the following: a constant-composition distribution matcher (CCDM), a bit-level distribution matcher (BL-DM), a product distribution matcher (PDM), a multi-composition distribution matcher (MCDM), a multiset-partition distribution matcher (MPDM), a partition-based distribution matcher, a parallel-amplitude distribution matcher with subset ranking, a streaming distribution matcher, a prefix-free code distribution matcher, a shell mapping, an enumerative sphere shaping (ESS), an approximate enumerative sphere shaping (AESS), or a partial enumerative sphere shaping. Sphere shaping (PESS), Huffman-coded sphere shapingFraming of variable-length distribution matcher outputs into fixed-length blocks, distribution matcher with mark ratio control, hierarchical distribution matcher, parallel bisection-based distribution matcher, and polar-coded distribution matcher.

[0112] It should be noted that the distributed matching techniques listed above are all different. However, the general purpose of distributed matching is to generate a probabilistically determined sequence of symbols for constructing shaped signals, such as ASK or QAM signals.

[0113] Figure 4 A block diagram of a shaping encoder chain based on block code is given, including a log-likelihood ratio generator 401, a channel decoder 402, a channel encoder 403, a bit mask 404, and a multiplexer 405.

[0114] Among them, the shaping encoder link can acquire a set of information bits, such as the bit sequence b1(0)~b1(K1-1) of the first part of the output of the splitter 201, i.e., u=b1.

[0115] In some embodiments, the information bit groups may be equally distributed and may be a bit-level sequence u = [u0, u1, u2, ..., u] corresponding to a sequence of amplitude symbols. m-1 ], where m is the modulation order of amplitude shift keying modulation used by the modulation mapper in the transmitter link, or m is half of the modulation order Qm of quadrature amplitude modulation used by the modulation mapper in the transmitter link.

[0116] For example, assuming the transmitter link uses a 64-QAM constellation or a corresponding 8-ASK constellation, the number of bits carried by each amplitude symbol is... Or m = log28 = 3. In this case, u = [u0, u1, u2]. The information bit group may be input to the log-likelihood ratio generator 401 in the shaping encoder link. The log-likelihood ratio generator 401 is configured to generate a set of log-likelihood ratios (LLR) LLR(0) ~ LLR(NL-1) for the corresponding information bit group.

[0117] In some embodiments, the log-likelihood ratio generator 401 further divides the log-likelihood ratio group into multiple integer blocks according to the length of the shaping block, based on at least a portion of the log-likelihood ratio group, for decoding by the channel decoder 402.

[0118] In some embodiments, the goal of probability amplitude shaping is to generate a covering code that maximizes power savings after bit masking. Therefore, the log-likelihood ratio generator 401 can be configured to generate log-likelihood ratios LLR(0) to LLR(NL-1) for the information bit group based on the amount of power saved by bit flipping.

[0119] For example, assuming the amplitude of the corresponding information bit group is set such that (u0, u1) in the symbol sequence u is equal to (1, 1), flipping or masking u0 will yield... The associated power change is 16. In this case, the corresponding LLR is denoted as "16".

[0120] For example, Table 2 shows examples of bit flipping, LLR values, and power savings.

[0121] Table 2

[0122]

[0123] In some embodiments, dividing the log-likelihood ratio set LLR(0) to LLR(NL-1) into multiple integer blocks can be based on one or more parameters. For example, these parameters may include the number of integer blocks (Cs), which can be defined as... Nre is the number of resource elements (REs) used to transmit information bit groups, and Nsmax is the maximum integer block length. In some cases, Nsmax can be a fixed value in wireless communication standards, such as 512 (i.e., 2^9). The integer block length (Ns) can be defined as... If the length NL of the log-likelihood ratio group LLR(0)~LLR(NL-1) or the length Nin of the input symbol (e.g., possibly defined as NL=Nin=2×Nre) is greater than the length of the integer block (Ns), then multiple integer blocks can be generated by segmentation.

[0124] In some embodiments, after the log-likelihood ratio group LLR(0) to LLR(NL-1) is divided into multiple shaping blocks, the shaping blocks can be sent to the channel decoder 402.

[0125] Channel decoder 402 is configured to decode multiple integer blocks using linear codes or forward error correction codes (FEC codes) to obtain shaping bits (s(0)~s(Ks-1)).

[0126] For example, the channel decoder 402 can be configured according to the integer code rate (R). sh Decoding multiple integer blocks, the integer code rate can be defined as R. sh =Ks / Ns, where Ks is the number of integer bits (s) and Ns is the codeword length (i.e., the length of the integer block) output by the channel encoder 403.

[0127] For example, the channel decoder 402 can be configured according to the integer code rate (R). sh Decoding multiple integer blocks, the integer code rate can be defined as R. sh = Ns / Ks, where Ks is the number of integer bits (s) and Ns is the codeword length (i.e., the length of the integer block) output by the channel encoder 403.

[0128] In some embodiments, linear codes or FEC codes may depend on an integer code rate R. sh The length Ns of the shaping block is determined.

[0129] In some embodiments, the generator matrix (G) of a linear code or FEC code can be based on an integer code rate R. sh Construct the shape block with length Ns.

[0130] In some embodiments, the linear code or FEC code can be one of the following: polar code, low-density parity check code, convolutional code, turbo code, Reed-Muller code, Reed-Solomon code, Bose-Chaudhuri-Hocquenghem code, concatenated code, cyclic code, block code, Hamming code, Golay code, repetition code, or single-parity-check code.

[0131] In some embodiments, the length of the shaped block (Ns) can be determined based on the rate distortion bound and the decoding process of the linear code or FEC code.

[0132] It should be noted that the integer block length (Ns) should be as large as possible, because a larger integer block length can asymptotically reach the rate distortion bound. However, a larger integer block length may cause problems for decoding linear codes or FEC codes, such as concerns about decoding complexity and latency.

[0133] In some embodiments, the number of shaped bits (Ks) can be limited based on the signal-to-noise ratio (SNR) of the wireless channel.

[0134] It should be understood that a larger value for the number of shaping bits (e.g., Ks) can provide better shaping performance, but it increases overhead and reduces the amount of effective data that can be transmitted. Therefore, a trade-off needs to be struck between the number of shaping bits (Ks) and overall performance, similar to distribution matching (DM), where optimization is performed for a specific distribution (e.g., CCDM) or to minimize transmission power (e.g., spherical shaping). Thus, the number of shaping bits (Ks) can be limited based on the signal-to-noise ratio (SNR) of the wireless channel.

[0135] The channel encoder 403 takes an integer bit sequence as input. It can re-encode the integer bit sequence according to the integer code rate and generate an integer code word (v(0)~v(Nv-1)) using linear code or FEC code.

[0136] For example, in order to obtain an integer codeword v, the channel encoder 403 can multiply the integer bit sequence (s) with the generator matrix (G) of the linear code or FEC code according to v = s × G.

[0137] Bit mask module 404 can perform shaping operations on a subset of information bit group u to generate a shaped information bit sequence.

[0138] It should be noted that the goal of shaping is to maximize power savings. Therefore, in order to maximize power savings, the bit masking module 404 can be configured to apply the shaped codeword v to the bit-level of amplitude symbols that have the greatest impact on signal power, such as the most-significant bit (MSB) u0.

[0139] For example, bitmasking module 404 may perform a shaping operation on the MSB, and according to Applied to integer codeword v, where ⊕ represents bitwise modulo 2 addition.

[0140] Multiplexer 405, to shape information bit sequences (e.g. The unshaped remaining subset of the information bit group u (e.g., u1, u2, ..., u...) m-1 The input consists of an integer bit sequence (s) and an integer bit sequence (s). Based on the input, the output bit sequence c(0) to c(N1-1) of the integer encoder is generated.

[0141] In some embodiments, the multiplexer 405 shaped the information bit sequence and the unerected remaining subsets u1, u2, ..., u in the information bit group u. m-1 And the shaped bit sequence (s) is combined into the output bit sequence c(0)~c(N1-1) of the shaped encoder.

[0142] For example,

[0143] In other embodiments,

[0144] In some other embodiments,

[0145] In some other embodiments,

[0146] In some embodiments, u in the unshaped residual subset of the information bit group u j It is a sequence of length Nx or 2×Nx, where Nx is the length of the modulation symbol sequence output by the modulation mapper 204 in the transmitter link.

[0147] like Figure 5 The diagram shown is a block diagram of a low-density parity check (LDPC) coding chain provided in an embodiment of this disclosure, including transport block (TB) cyclic redundancy check (CRC) bit attachment 501, code block segmentation and code block CRC attachment 502, LDPC coding 503, rate matching 504, and code block concatenation 505.

[0148] Among them, the CRC attachment 501 of the transmission block is used to determine the CRC attachment output bit sequence b'(0)~b'(Nb'-1) of length Nb'.

[0149] In some embodiments, the transport block CRC attach 501 determines the CRC attach output bit sequence b'(0)~b'(Nb'-1) of length Nb' based on the following parameters: transport block bit sequence a'(0)~a'(Na'-1), the length of transport block bit sequence a' is Na', and the cyclic generator polynomial.

[0150] For example, the cyclic generator polynomial satisfies the following formula 3:

[0151] g CRC (D)=g Lcrc ·D Lcrc +g Lcrc-1 ·D Lcrc-1 +…+g2·D 2 +g1·D 1 +g0 formula 3.

[0152] Where Lcrc is the cyclic generator polynomial g CRC (D) is the highest power, Lcrc is also the number of cyclic redundancy check bits, D is a dummy variable representing the circuit delay, and g Lcrc gLcrc-1 g, ..., g2, g1, g0 are cyclic generating polynomials g CRC (D) The coefficient of the corresponding power term, coefficient g Lcrc-1 g1, g2, and g1 can take values ​​of 0 or 1, and the coefficient g Lcrc =g0=1.

[0153] In some embodiments, the transport block bit sequence a' can be a bit sequence obtained by concatenating the output bit sequence c(0) to c(N1-1) of the shaping encoder output by the shaping encoder 202 and the second part bit sequence b2(0) to b2(K2-1) output by the splitter 201. In one specific example, a' = [c, b2]. In another specific example, a' = [b2, c].

[0154] In some embodiments, the cyclic generator polynomial g CRC The highest power Lcrc of (D) is determined by the length Na' of the transport block bit sequence a' in the following manner:

[0155] When Na' > Nath, Lcrc = 24;

[0156] When Na'≤Nath, Lcrc=16.

[0157] Where Nath is a positive integer. In one specific example, Nath = 3824. In another specific example, Nath = 8424. In yet another specific example, Nath = 1008.

[0158] In some embodiments, the transport block CRC attachment 402 inputs a transport block bit sequence a'(0) to a'(Na'-1) of length Na' into the cyclic generator polynomial g. CRC (D)=g Lcrc ·D Lcrc +g Lcrc-1 ·D Lcrc-1 +…+g2·D 2 +g1·D 1 After calculating Lcrc CRC bits p(0)~p(Lcrc-1), the transport block bit sequence a'(0)~a'(Na'-1) of length Na' is concatenated with Lcrc CRC bits p(0)~p(Lcrc-1) to obtain a CRC attached output bit sequence b'(0)~b'(Nb'-1) of length Nb'=Na'+Lcrc. In this sequence, bits in CRC attached output bit sequence b' with indices less than Na' are bits in transport block bit sequence a', and bits in CRC attached output bit sequence b' with indices greater than or equal to Na' are bits in Lcrc CRC bits p.

[0159] In the CRC appended output bit sequence b', the bits with indices less than Na' are the bits in the transport block bit sequence a', and the bits with indices greater than or equal to Na' in the CRC appended output bit sequence b' are the bits in the Lcrc CRC bits p, satisfying the following formula 4:

[0160] b'(k)=a'(k),k=0,1,2,…,Na'-1,

[0161] b'(k)=p(k-Na'),k=Na',Na'+1,Na'+2,...,Na'+Lcrc-1. Formula 4;

[0162] Code block segmentation and code block CRC attachment 502 are used to segment the CRC-attached output bit sequence b'(0)~b'(Nb'-1) of length Nb' into C code block system bit sequences c'0,c'1,…,c' of length Nc'. C-1 .

[0163] In some embodiments, code block segmentation and code block CRC attachment 502 divide the CRC attachment output bit sequence b'(0)~b'(Nb'-1) of length Nb' into C code block system bit sequences c'0,c'1,…,c' of length Nc' according to the following parameters. C-1 : CRC attached output bit sequence b'(0)~b'(Nb'-1), length of CRC attached output bit sequence Nb', maximum code block size Kcb, number of columns NB of the matrix of the base graph of LDPC code, number of rows MB of the matrix of the base graph of LDPC code, boost value Z.

[0164] Wherein, the boost value Z is the matrix H from the base graph of the LDPC code. BG Extend this to the lifting value of the parity check matrix H, where Kcb and Kb are positive integers.

[0165] In some embodiments, Kcb can take the value 8448 or 3840.

[0166] In some embodiments, Kb can take the value 22, 10, 9, 8 or 6.

[0167] Code block segmentation and code block CRC attachment: 502 divides the CRC-attached output bit sequence b'(0)~b'(Nb'-1) of length Nb' into C code block system bit sequences c'0,c'1,…,c' of length Nc'. C-1 This includes the following steps:

[0168] Step 1: Determine the number of code blocks C, the number of CRC bits per code block L, and the transport block size B' including the CRC bits per code block based on the length Nb' of the CRC attached output bit sequence and the maximum code block size Kcb.

[0169] For example, if LDPC encoding uses the base Figure 1 (base graph 1), set Kcb = 8448; if LDPC encoding uses the base... Figure 2 (base graph 2), set Kcb=3840.

[0170] For example, if Nb' ≤ Kcb, set L = 0, C = 1, and B' = B; if Nb' > Kcb, set L = 24. B' = B + C·L.

[0171] Step 2: Determine the lift value Z for LDPC encoding.

[0172] Step 2-1: Determine the size of the unfilled code block K' = B' / C.

[0173] For example, if LDPC encoding uses the base Figure 1 Set the number of valid system columns to Kb = 22.

[0174] For example, if LDPC encoding uses the base Figure 2 And since B > 640, set Kb = 10.

[0175] For example, if LDPC encoding uses the base Figure 2 And since 640≥B>560, set Kb=9.

[0176] For example, if LDPC encoding uses the base Figure 2 And since 560≥B>192, set Kb=8.

[0177] For example, if LDPC encoding uses the base Figure 2 And B≤192, set Kb=6.

[0178] Step 2-2: Determine the set of elements that satisfy Kb·Z≥K' from the candidate set, and take the minimum value in the set of elements that satisfy the condition as the value of the boost value Z.

[0179] For example, Table 3 shows a candidate set of LDPC lift values ​​Z.

[0180] Table 3

[0181]

[0182] Step 3: Set the length of the bit sequence of a single code block system.

[0183] For example, if LDPC encoding uses the base Figure 1 Set the length Nc' of the bit sequence of a single code block system to Nc' = (NB - MB)·Z = 22·Z.

[0184] For example, if LDPC encoding uses the base Figure 2 Set the length Nc' of the bit sequence of a single code block system to Nc' = (NB - MB)·Z = 10·Z.

[0185] Step 4: Perform code block segmentation and code block CRC attachment operations on r = 0, 1, 2, ..., C-1 to obtain the code block systematic bit sequence c'. r (0)~c' r (Nc'-1).

[0186] Step 4-1: For k = 0, 1, ..., K'-L-1, set c' r (k)=b'((K'-L)·r+k).

[0187] Step 4-2: If the number of code blocks C is greater than 1, then for the bit sequence c' r (0)~c' r (K'-L-1) uses a generating loop to generate the polynomial g'. CRC (D) Calculate L = 24 CRC check bits p r (0)~p r (L-1). Where L is the number of CRC bits in the code block.

[0188] For example, generating a cyclic generator polynomial g′ CRC (D)=g CRC24B (D)=D 24 +D 23 +D 6 +D 5 +D+1 and L=24.

[0189] Step 4-3: Pour L = 24 CRC check bits p r (0)~p r (L-1) is attached to the bit sequence c' r (0)~c' r (K'-L-1) followed by L, where L is the number of CRC bits in the code block.

[0190] For example, for k = K'-L, K'-L+1, ..., K'-1, set c' r (k)=p r (k+L-K').

[0191] For example, for k = K', K'+1, ..., Nc'-1, set c' r (k) = <NULL>, where, <null>This indicates a filler bit or an empty bit that is neither "0" nor "1".

[0192] LDPC encoding 503 is used to encode a code block system bit sequence c' of length Nc'. r Encoded as an LDPC-encoded bit sequence d of length Nd r .

[0193] In some embodiments, LDPC encoding 503 uses the following parameters to encode a code block system bit sequence c' of length Nc'. r Encoded as an LDPC-encoded bit sequence d of length Nd r : Code block system bit sequence c' r The following parameters are considered: length of the systematic bit sequence Nc', boost value Z, number of systematic bit punctures Npunc, number of effective systematic columns Kb, and matrix H of the LDPC code's fundamental graph. BG The number of columns NB of the matrix of the LDPC code's base graph, the number of rows MB of the matrix of the LDPC code's base graph, and the parity check matrix H of the LDPC code.

[0194] In some embodiments, the boost value Z is the boost value determined by code block segmentation and code block CRC attachment 502.

[0195] In some embodiments, the number of system bit punctures Npunc is the code block system bit sequence c' r It does not appear in the encoded bit sequence d r The number of bits.

[0196] In some embodiments, the number of system bit punches Npunc is equal to the boost value Z.

[0197] In some embodiments, the number of system bit punctures, Npunc, is equal to twice the boost value Z.

[0198] In some embodiments, the effective systematic column number Kb is the number of systematic columns corresponding to the information bits and filler bits in the matrix of the base graph of the LDPC code.

[0199] In some embodiments, the number of columns NB of the matrix of the LDPC code's foundation graph is equal to the number of columns H of the LDPC code's foundation graph. BG The number of columns. MB is the number of rows in the matrix of the LDPC code's fundamental graph, and H is the number of columns in the matrix of the LDPC code's fundamental graph. BG The number of rows. The parity check matrix H of the LDPC code is a matrix H derived from the fundamental graph of the LDPC code. BG The matrix obtained by enhancing or expanding.

[0200] LDPC encoding 503 encodes a code block system bit sequence c' of length Nc'. r Encoded as an LDPC-encoded bit sequence d of length Nd r This includes the following steps:

[0201] Step 1: Set the LDPC encoded bit sequence d r The length is Nd = NB × Z - Npunc.

[0202] Step 2: For k = Npunc, Npunc+1, ..., Nc'-1, set the LDPC encoded bit sequence d as follows. r System bit portion:

[0203] If c' r (k) is not equal to <null>Set d r (k-Npunc)=c' r (k);

[0204] If c' r (k) equals <null>Set c' r (k)=0、d r (k-Npunc) = <NULL>.

[0205] Step 3: Generate Nd+Npunc-Nc' parity bits w = [w(0),...,w(Nd+Npunc-Nc'-1)] such that H×[c' r ,w] T =θ, where, [c' r ,w] T Let θ be a column vector of length NB×Z, and let θ be a zero vector of length MB×Z. Matrix and vector multiplication is performed over the Galois field GF(2). The parity check matrix H of the LDPC code is derived from the matrix H of the fundamental graph of the LDPC code. BG The lift value Z and the set index i corresponding to the lift value Z in Table 3 LS It has been determined.

[0206] Step 4: For k = Nc', Nc'+1, ..., Nd+Npunc-1, set the LDPC encoded bit sequence d. r The parity bit portion: d r (k-Npunc)=w(k-Nc').

[0207] Rate matching 504 is used to encode bit sequence d from LDPC. r Determine the rate-matched output bit sequence.

[0208] In some embodiments, rate matching 504 is based on the following parameters from the LDPC encoded bit sequence d r Determine the rate-matched output bit sequence: Circular buffer length Ncb, number of transmission layers N layer Modulation order Qm, number of code blocks C, total number of coded bits Ng, redundancy version number rv id The starting position of the redundant version is k0.

[0209] In some embodiments, rate matching 504 includes two modules: bit selection 5041 and bit interleaving 5042.

[0210] For the code block with index r, bit selection 5041 is used to encode the bit sequence d from the LDPC according to the following parameters. r Determine the bit selection sequence e r : Circular buffer length Ncb, number of transport layers N layer , boost value Z, modulation order Qm, number of code blocks C, total number of coded bits Ng, redundancy version number rv id The redundant version starts at position k0.

[0211] In some embodiments, the circular cache length Ncb is determined by higher layer parameters.

[0212] In some embodiments, the number of transport layers N layer Determined by high-level parameters.

[0213] In some embodiments, the boost value Z is the boost value determined by code block segmentation and code block CRC attachment 502.

[0214] In some embodiments, the modulation order Qm is the modulation order of the modulation constellation used by the modulation mapper 204 in the probability amplitude-shaping transmitter link.

[0215] In some embodiments, the number of code blocks C is the number of code blocks determined by code block segmentation and code block CRC attachment 502 in the LDPC coding chain.

[0216] In some embodiments, the total number of coded bits Ng is the total number of coded bits available for transmission of the transport block, and the number of resource elements Nre and the number of transport layers N, determined by higher-layer parameters, are also included. layer The product of the modulation order Qm, G, and the product of the two is given by G = N. layer ×Nre×Qm.

[0217] In some embodiments, the redundant version number rv id Determined by high-level parameters.

[0218] In some embodiments, the redundant version number rv id Obtained from downlink control information.

[0219] In some embodiments, the redundant version number rv id Obtained from the uplink control information.

[0220] In some embodiments, the redundant version start position k0 is determined by the base graph used by the LDPC code and the redundant version number rv. id The circular cache length Ncb and the boost value Z are determined.

[0221] For example, Table 4 shows the starting position k0 for different redundant versions.

[0222] Table 4

[0223]

[0224] The specific operations of bit selection 5041 include:

[0225] Step 1: Set the bit selection sequence e for each code block r Length E r When the code block index r is less than or equal to set up Otherwise, set in, For floor function, it represents the largest integer less than or equal to x; The integer part is the smallest integer greater than or equal to x.

[0226] Step 2: Based on the base diagram and redundancy version number rv used in LDPC codes id The circular cache length Ncb and the boost value Z are determined from Table 4 to determine the starting position k0 of the redundant version.

[0227] Step 3: For the code block with index r, encode the bit sequence d from the LDPC. r Starting with the bit at index k0, E is selected cyclically with a circular buffer length Ncb. r The bit selection sequence e is obtained from the non-filler bits. r .

[0228] For example, the pseudocode corresponding to step 3 is as follows:

[0229]

[0230]

[0231] Bit interleaving 5042, based on a code block of length E with index r. r bit selection sequence e r Determine the bit interleaving sequence f r .

[0232] In some embodiments, bit interleaving 5042 is based on the following parameters, for a code block with index r, starting from a length of E r bit selection sequence e r Determine the bit interleaving sequence f r Bit selection sequence e r Bit selection sequence e r Length E r Modulation order Qm.

[0233] In some embodiments, the modulation order Qm is the modulation order of the modulation constellation used by the modulation mapper 204 in the probability amplitude-shaping transmitter link.

[0234] In some embodiments, the specific operation of bit interleaving 5042 includes: selecting a bit sequence e for index r. r Select the bit sequence e r Write E in row-first-column order. r A cache matrix of / Qm rows and Qm columns is then read out column by column, followed by row, into a matrix of length E. r bit interleaved sequence f r That is, for r = 0, 1, ..., C-1, j = 0, 1, ..., E r / Qm-1, i = 0, 1, ..., Qm-1, set f r (i+j·Qm)=e r (i·E r / Qm+j).

[0235] In some embodiments, the C bit-interleaved sequences f0, f1, ..., f output by the bit-interleaved 5042 are... C-1 It is also the rate-matched 504 output bit sequence in the LDPC coding chain.

[0236] The specific operation of code block concatenation 505 is as follows: The lengths of C code blocks are E0, E1, ..., E... C-1 The bit interleaved sequence f0, f1, ..., f C-1 Concatenating the bits yields a concatenated bit sequence g of length Ng, i.e., g = [f0, f1, ..., f C-1 ], where the lengths are Ng=E0+E1+…+E C-1 In some embodiments, the code block concatenation bit sequence g of length Ng is the output bit sequence of the channel encoder 203 in the transmitter link.

[0237] In some embodiments, the LDPC code is a quasi-cyclic (QC) LDPC code.

[0238] In some embodiments, LDPC codes can be defined by a parity check matrix (PCM).

[0239] In some embodiments, a quasi-cyclic LDPC code can be defined by an MB×Z row, NB×Z column parity check matrix H consisting of MB×NB submatrices, where each submatrix is ​​a different power of the fundamental permutation matrix P of size Z×Z or a Z×Z all-zero matrix. BG By improving or expanding upon this, we can obtain:

[0240]

[0241] Among them, H BG (i,j) represents the element with row index i and column index j, H BG (i,j) takes the value 0 or 1, and Z is called the lifting size or expansion factor. Therefore, Z is the matrix H from the base graph. BG The lift or expansion factor extended to the parity check matrix H represents the multiple by which the number of rows or columns of the matrix changes, or is lifted or expanded. Lifting or expansion refers to the increase or decrease in the number of rows or columns of the matrix when H... BG When (i,j) is 0, H is set to BG (i,j) is replaced by a Z×Z all-zero matrix and when H BG When (i,j) is 1, H is set to BG The process of replacing (i,j) with different powers of the basic permutation matrix P of size Z×Z to finally obtain the parity check matrix H with MB×Z rows and NB×Z columns.

[0242] For example, the basic permutation matrix P is shown below:

[0243]

[0244] If j = mod(i+1, Z), then P ij =1, otherwise P ij =0. Different powers of the fundamental permutation matrix P of size Z×Z are obtained by cyclic shifting the identity matrix to obtain the corresponding powers.

[0245] For example, P 5 This can be obtained by cyclically shifting the identity matrix five times. The matrix H corresponding to the basic graph of the LDPC code is... BG The MB×NB matrix used to indicate different powers of the fundamental permutation matrix P is shown below:

[0246]

[0247] Where V(i,j) is -1, NULL, or undefined, it indicates that H should be set to 1. BG (i,j) is replaced with a Z×Z matrix of all zeros. If V(i,j) is greater than or equal to 0, it indicates that H is replaced. BG (i,j) is represented by a Z×Z matrix P. V(i,j) , where P V(i,j) V is a matrix that raises the basic permutation matrix P to the power of V(i,j). Therefore, matrix V is also called the shift value matrix. Since there is a one-to-one correspondence between matrix V and parity check matrix H, matrix V is sometimes also called the parity check matrix.

[0248] In some embodiments, the base diagram can be an LDPC base. Figure 1 (LDPC basegraph1) or LDPC base Figure 2 (LDPC basegraph 2). LDPC foundation Figure 1 The matrix has MB = 46 rows and NB = 68 columns. LDPC Basics Figure 2 The matrix has MB = 42 rows and NB = 52 columns.

[0249] For example, Figure 6 A block diagram of another shaping encoder provided in this disclosure includes a shaping block segmentation 601, a distribution matcher (DM) 602, a shaping block concatenation 603, and an amplitude-to-bit mapper 604.

[0250] Among them, the integer block segmentation 601 is used to determine the number of integer blocks Cs and the lengths of the input bit sequences of the Cs integer blocks K1'0, K1'1, ..., K1' Cs-1 And the output amplitude sign sequence A'0, A'1, ..., A' of Cs integer blocks. Cs-1 The lengths NA'0,NA'1,…,NA' Cs-1 Where, K1 = K1'0 + K1'1 + ... + K1' Cs-1 Nx≥NA'0+NA'1+…+NA' Cs-1 Or 2×Nx≥NA'0+NA'1+…+NA' Cs-1 Alternatively, it can be used to segment the first part b1 into Cs segments of length K1'0, K1'1, ..., K1'. Cs-1 The integer block input bit sequence b1'0, b1'1, ..., b1' Cs-1 Where, b1=[b1′0,b1′1,b1′2,…,b1′ Cs-1 ].

[0251] In some embodiments, Nx is the length of the modulation symbol sequence.

[0252] In some embodiments, for all indexes r, K1' r =K1 / Cs.

[0253] In some embodiments, for all indexes r, K1' r =floor(K1 / Cs).

[0254] In some embodiments, for all indexes r, K1' r =ceil(K1 / Cs).

[0255] In some embodiments, there exists an index r, K1' r =floor(K1 / Cs).

[0256] In some embodiments, there exists an index r, K1' r =ceil(K1 / Cs).

[0257] In some embodiments, for index r less than mod(K1,Cs), K1' r =ceil(K1 / Cs), and for any index r greater than or equal to mod(K1,Cs), K1' r =floor(K1 / Cs).

[0258] In some embodiments, for an index r less than Cs-mod(K1,Cs), K1' r =floor(K1 / Cs), and for indices r greater than or equal to Cs-mod(K1,Cs), K1' r =ceil(K1 / Cs).

[0259] In some embodiments, K1'0, K1'1, ..., K1' Cs-1 All values ​​are the same.

[0260] In some embodiments, K1'0, K1'1, ..., K1' Cs-1 The maximum value in K1'0, K1'1, ..., K1' Cs-1 The difference between the minimum values ​​in the range is 1.

[0261] In some embodiments, K1'0, K1'1, ..., K1' Cs-1 The maximum value in K1'0, K1'1, ..., K1' Cs-1 The difference between the minimum values ​​in the range is less than or equal to 1.

[0262] In some embodiments, K1'0, K1'1, ..., K1' Cs-1 The maximum value in K1'0, K1'1, ..., K1' Cs-1 The absolute value of the difference between the minimum values ​​is less than or equal to 1.

[0263] In some embodiments, K1'0, K1'1, ..., K1' Cs-1 The maximum value in K1'0, K1'1, ..., K1' Cs-1 The absolute value of the difference between the minimum values ​​is less than or equal to 1.

[0264] In some embodiments, for all indexes r, NA' r =Nx / Cs.

[0265] In some embodiments, for all indexes r, NA' r =floor(Nx / Cs).

[0266] In some embodiments, there exists an index r, NA' r =floor(Nx / Cs).

[0267] In some embodiments, there exists an index r, NA' r =ceil(Nx / Cs).

[0268] In some embodiments, for index r less than mod(Nx, Cs), NA' r =ceil(Nx / Cs), and for index r greater than or equal to mod(Nx,Cs), NA' r =floor(Nx / Cs).

[0269] In some embodiments, for an index r less than Cs-mod(Nx,Cs), NA' r =floor(Nx / Cs), and for index r greater than or equal to Cs-mod(Nx,Cs), NA' r =ceil(Nx / Cs).

[0270] In some embodiments, for all indexes r, NA' r =floor(2×Nx / Cs).

[0271] In some embodiments, there exists an index r, NA' r =floor(2×Nx / Cs).

[0272] In some embodiments, there exists an index r, NA' r =ceil(2×Nx / Cs).

[0273] In some embodiments, for an index r less than mod(2×Nx,Cs), NA' r =ceil(2×Nx / Cs), and for index r greater than or equal to mod(2×Nx,Cs), NA' r =floor(2×Nx / Cs).

[0274] In some embodiments, for an index r less than Cs-mod(2×Nx,Cs), NA' r =floor(2×Nx / Cs), and for index r greater than or equal to Cs-mod(2×Nx,Cs), NA' r =ceil(2×Nx / Cs).

[0275] In some embodiments, NA'0,NA'1,…,NA' Cs-1 All values ​​are the same.

[0276] In some embodiments, NA'0,NA'1,…,NA' Cs-1 The maximum value in NA'0,NA'1,…,NA' Cs-1 The difference between the minimum values ​​in the range is 1.

[0277] In some embodiments, NA'0,NA'1,…,NA' Cs-1 The maximum value in NA'0,NA'1,…,NA' Cs-1 The difference between the minimum values ​​in the range is less than or equal to 1.

[0278] In some embodiments, NA'0,NA'1,…,NA' Cs-1 The maximum value in NA'0,NA'1,…,NA' Cs-1 The absolute value of the difference between the minimum values ​​is less than or equal to 1.

[0279] In some embodiments, NA'0,NA'1,…,NA' Cs-1 The maximum value in NA'0,NA'1,…,NA' Cs-1 The absolute value of the difference between the minimum values ​​is less than or equal to 1.

[0280] Distributed matcher 602 is used for indices r = 0, 1, ..., Cs-1, where the length of index r is K1'. r The shaped input bit sequence b1' r Performing distributed matching encoding yields a length of NA' r The output amplitude sign sequence A' of the shaping block r .

[0281] In some embodiments, the distributed matcher may use any one of a number of suitable algorithms and any one of a number of suitable configurations.

[0282] In some embodiments, the distribution matcher is one of the following: constant-composition distribution matcher (CCDM), bit-level distribution matcher (BL-DM), product distribution matcher (PDM), multi-composition distribution matcher (MCDM), multiset-partition distribution matcher (MPDM), partition-based distribution matcher, parallel-amplitude distribution matcher with subset ranking, streaming distribution matcher, prefix-free code distribution matcher, shell mapping, enumerative sphereshaping (ESS), approximate enumerative sphere shaping (AESS), or partial enumerative sphere... Sphere shaping (PESS), Huffman-coded sphere shapingFraming of variable-length distribution matcher outputs into fixed-length blocks, distribution matcher with mark ratio control, hierarchical distribution matcher, parallel bisection-based distribution matcher, and polar-coded distribution matcher.

[0283] The shaping block cascade 603 is used to convert the Cs elements of length NA'0, NA'1, ..., NA' output from the distributed matcher 602 into Cs elements of length NA'0, NA'1, ..., NA'1. Cs-1 The output amplitude sign sequence of the shaping block is A'0, A'1, ..., A' Cs-1 Cascading yields an integer amplitude symbol sequence A of length NA, where NA is the Cs integer block output amplitude symbol sequences A'0, A'1, ..., A' determined in the integer block segmentation 601. Cs-1 The sum of the lengths, i.e., NA = NA'0 + NA'1 + ... + NA' Cs-1 .

[0284] In some embodiments, A = [A'0, A'1, ..., A'] Cs-1 That is, the index in the integer amplitude sign sequence A is greater than or equal to NA'0+NA'1+…+NA'. r-1 And less than NA'0+NA'1+…+NA' r The amplitude sign is the output amplitude sign sequence A' of the integer block with index r. r The amplitude sign, i.e., A(NA'0+…+NA') r-1 +j)=A' r (j), j = 0, 1, ..., NA' r -1.

[0285] Amplitude-to-bit mapper 604 is used to convert each amplitude symbol in the long NA-length integer amplitude symbol sequence A output by integer block concatenation 603 into a bit string according to the set amplitude-to-bit mapping rule, and concatenate them to obtain a second bit sequence c of length N1, where NA is the Cs integer block output amplitude symbol sequence A'0, A'1, ..., A' determined in integer block segmentation 601. Cs-1 The sum of the lengths, i.e., NA = NA'0 + NA'1 + ... + NA' Cs-1 .

[0286] In some embodiments, the amplitude-to-bit mapper 604 can convert each amplitude A(j) in the shaped amplitude symbol sequence A into Qm / 2-1 bits c(j·(Qm / 2-1)), c(j·(Qm / 2-1)+1),...,c(j·(Qm / 2-1)+Qm / 2-2) according to a preset mapping method, and then concatenate them into a second bit sequence c, where the length N1 of the second bit sequence c is equal to NA·(Qm-2), and Qm is the modulation order of the modulation symbol sequence X.

[0287] In some embodiments, the amplitude-to-bit mapper 604 can convert each amplitude A(j) in the shaped amplitude symbol sequence A into Qm-1 bits c(j·(Qm-1)), c(j·(Qm-1)+1),...,c(j·(Qm-1)+Qm-2) according to a preset mapping method, and then concatenate them into a second bit sequence c, where the length N1 of the second bit sequence c is equal to NA·(Qm-1), and Qm is the modulation order of the modulation symbol sequence X.

[0288] like Figure 7 The diagram shown is a block diagram of another shaping encoder provided in an embodiment of this disclosure, including: a log-likelihood ratio generator 701, shaping blocks segmentation 702, a channel decoder 703, a channel encoder 704, shaping block concatenation 705, and bit masking and concatenation 706.

[0289] The log-likelihood ratio generator 701 is used to determine a log-likelihood ratio (LLR)LLR(j) for each consecutive Qm / 2-1 bits b1(j·(Qm / 2-1)), b1(j·(Qm / 2-1)+1),...,b1(j·(Qm / 2-1)+Qm / 2-2) of the first part b1 according to a pre-set amplitude-to-bit mapping relationship, and finally obtain a log-likelihood ratio sequence LLR(0)~LLR(NLLR-1) of length NLLR=K1 / (Qm / 2-1), where K1 is the length of the first part b1, Qm is the modulation order of the modulation mapping, and K1 is a multiple of (Qm / 2-1).

[0290] In some embodiments, the log-likelihood ratio generator 701 can determine a log-likelihood ratio LLR(j) for each consecutive Qm-1 bits b1(j·(Qm-1)), b1(j·(Qm-1)+1), ..., b1(j·(Qm-1)+Qm-2) of the first part b1 according to a preset amplitude-to-bit mapping relationship, and finally obtain a log-likelihood ratio sequence LLR(0)~LLR(NLLR-1) of length NLLR=K1 / (Qm-1), where K1 is the length of the first part b1, Qm is the modulation order of the modulation mapping, and K1 is a multiple of (Qm-1).

[0291] In some embodiments, the log-likelihood ratio generator 701 can determine the log-likelihood ratio LLR(j) of the Qm / 2-1 bits b1(j), b1(K1 / (Qm / 2-1)+j), ..., b1((Qm / 2-2)×K1 / (Qm / 2-1)+j with index j, K1 / (Qm / 2-1)+j, ..., b1((Qm / 2-2)×K1 / (Qm / 2-1)+j) according to a preset amplitude-to-bit mapping relationship, and finally obtain a log-likelihood ratio sequence LLR(0)~LLR(NLLR-1) of length NLLR=K1 / (Qm / 2-1), where K1 is the length of the first part b1, Qm is the modulation order of the modulation mapping, and K1 is a multiple of (Qm / 2-1).

[0292] Integer block segmentation 702 is used to determine the number of integer blocks Cs, the input log-likelihood ratio of Cs integer blocks, and the sequence length Ns'0, Ns'1, ..., Ns' Cs-1 And Cs integer blocks output integer bit sequences s'0, s'1, ..., s' Cs-1 The lengths Ks0', Ks1', ..., Ks C ' s-1 Where, NLLR=Ns0'+Ns1'+…+Ns C ' s-1 Nx≥Ns'0+Ns'1+…+Ns' Cs-1 Or 2×Nx≥Ns'0+Ns'1+…+Ns' Cs-1 Nx is the length of the modulation symbol sequence X, and Ks' r ≤Ns' r Then, the log-likelihood ratio sequence LLR(0)~LLR(NLLR-1) is segmented into Cs segments of length Ns'0, Ns'1, …, Ns' Cs-1 The integer block input log-likelihood ratio sequence LLR'0, LLR'1, ..., LLR' Cs-1 , where LLR=[LLR'0,LLR'1,...,LLR' Cs-1 ].

[0293] In some embodiments, Nx is the length of the modulation symbol sequence.

[0294] In some embodiments, NLLR = Nx.

[0295] In some embodiments, NLLR = 2 × Nx.

[0296] In some embodiments, for all indices r, Ns' r =NLLR / Cs.

[0297] In some embodiments, for all indices r, Ns' r =floor(NLLR / Cs).

[0298] In some embodiments, for all indices r, Ns' r =ceil(NLLR / Cs).

[0299] In some embodiments, there exists an index r, Ns' r =floor(NLLR / Cs).

[0300] In some embodiments, there exists an index r, Ns' r =ceil(NLLR / Cs).

[0301] In some embodiments, for index r less than mod(NLLR,Cs), Ns' r =ceil(NLLR / Cs), and for index r greater than or equal to mod(NLLR,Cs), Ns' r =floor(NLLR / Cs).

[0302] In some embodiments, for an index r less than Cs-mod(NLLR,Cs), Ns' r =floor(NLLR / Cs), and for index r greater than or equal to Cs-mod(NLLR,Cs), Ns' r =ceil(NLLR / Cs).

[0303] In some embodiments, Ns'0, Ns'1, ..., Ns' Cs-1 All values ​​are the same.

[0304] In some embodiments, Ns'0, Ns'1, ..., Ns' Cs-1 The maximum value in Ns0', Ns1', ..., Ns' Cs-1 The difference between the minimum values ​​in the range is 1.

[0305] In some embodiments, Ns'0, Ns'1, ..., Ns' Cs-1 The maximum value in Ns0', Ns1', ..., Ns' Cs-1 The difference between the minimum values ​​in the range is less than or equal to 1.

[0306] In some embodiments, Ns'0, Ns'1, ..., Ns' Cs-1 The maximum value in Ns0', Ns1', ..., Ns' Cs-1 The absolute value of the difference between the minimum values ​​is less than or equal to 1.

[0307] In some embodiments, Ns'0, Ns'1, ..., Ns' Cs-1 The maximum value in Ns0', Ns1', ..., Ns' Cs-1 The absolute value of the difference between the minimum values ​​is less than or equal to 1.

[0308] In some embodiments, Ks'0,Ks'1,…,Ks' Cs-1 All values ​​are the same.

[0309] In some embodiments, Ks'0,Ks'1,…,Ks' Cs-1 The maximum value in Ks'0,Ks'1,…,Ks' Cs-1 The difference between the minimum values ​​in the range is 1.

[0310] In some embodiments, Ks'0,Ks'1,…,Ks' Cs-1 The maximum value in Ks'0,Ks'1,…,Ks' Cs-1 The difference between the minimum values ​​in the range is less than or equal to 1.

[0311] In some embodiments, Ks'0,Ks'1,…,Ks' Cs-1 The maximum value in Ks'0,Ks'1,…,Ks' Cs-1 The absolute value of the difference between the minimum values ​​is less than or equal to 1.

[0312] In some embodiments, Ks'0,Ks'1,…,Ks' Cs-1 The maximum value in Ks'0,Ks'1,…,Ks' Cs-1 The absolute value of the difference between the minimum values ​​is less than or equal to 1.

[0313] Channel decoder 703, used for index r = 0, 1, ..., Cs-1, according to Ks' r and Ns' r The generator matrix G is set. r Or the parity check matrix H r Input the integer block with index r into the log-likelihood ratio sequence LLR' r The input is used for channel decoding to obtain a length of Ks' with index r. r The output of the shaped block is the shaped bit sequence s' r .

[0314] In some embodiments, the channel decoder 704 can be configured based on the generator matrix G. r Or the verification matrix H r Arbitrary decoders of linear codes or forward error-correcting codes (FEC codes).

[0315] In some embodiments, the linear code or FEC code can be, but is not limited to, polar code, low-density parity check code, convolutional code, turbo code, Reed-Muller code, Reed-Solomon code, Bose-Chaudhuri-Hocquenghem code, concatenated code, cyclic code, block code, Hamming code, Golay code, repetition code, and single-parity-check code.

[0316] Channel encoder 704 is used for generating a matrix G with the same index r as channel decoder 703, for indices r = 0, 1, ..., Cs-1. r Or the verification matrix H r And the length of index r is Ks' r The output of the shaped block is the shaped bit sequence s' r Determine the length Ns' of index r. r The integer block codeword bit sequence v' r .

[0317] In some embodiments, v' r =s' r ×G r The vector-matrix multiplication is performed over the Galois field GF(2), (v' r ) T It is the transpose of v'r.

[0318] In some embodiments, H r ×(v' r ) T =0 and [v' r (0),…,v' r (Ks' r -1)]=[s' r (0),...,s' r (Ks' r -1)], where the vector-matrix multiplication is performed over the Galois field GF(2), (v' r ) T It is the transpose of v'r.

[0319] In some embodiments, the channel encoder 704 can be configured to be based on the generator matrix G r Or the verification matrix H r Linear codes or forward error-correcting codes (FEC codes).

[0320] In some embodiments, the linear code or FEC code can be, but is not limited to, polar code, low-density parity check code, convolutional code, turbo code, Reed-Muller code, Reed-Solomon code, Bose-Chaudhuri-Hocquenghem code, concatenated code, cyclic code, block code, Hamming code, Golay code, repetition code, and single-parity-check code.

[0321] The shaping block cascade 705 is used to convert Cs outputs of the channel decoder 703 into Cs elements of length Ks'0, Ks'1, ..., Ks'. Cs-1 The integer block outputs an integer bit sequence s'0,s'1,...,s' Cs-1 The cascaded sequence yields an integer bit sequence s of length Ks, and the Cs bits output by the channel encoder 704 are of lengths Ns'0, Ns'1, ..., Ns' Cs-1 The integer block codeword bit sequence v'0,v'1,...,v' Cs-1 The cascaded structure yields a length of NLLR = Ns'0 + Ns'1 + ... + Ns' Cs-1 The integer codeword bit sequence v, where Ks is the Cs integer block output integer bit sequence s'0, s'1, ..., s' determined in the channel decoder 606. Cs-1 The sum of the lengths, i.e., Ks = Ks'0 + Ks'1 + ... + Ks' Cs-1 .

[0322] In some embodiments, s = [s'0, s'1, ..., s' Cs-1 ].

[0323] In some embodiments, NLLR is the length of the log-likelihood ratio sequence LLR(0) to LLR(NLLR-1) determined in the log-likelihood ratio generator 701.

[0324] In some embodiments, v = [v'0, v'1, ..., v' Cs-1 ].

[0325] Bit mask and concatenation 706 are used to XOR the NLLR bits in the first part b1 of length K1 with the integer codeword bit sequence v of length NLLR to obtain the bit mask bit sequence of length K1.

[0326] In some embodiments, a bit mask bit sequence of length K1 This is the second bit sequence c, and the length of the second bit sequence c is N1 = K1.

[0327] In some embodiments, the bit mask and concatenation 706 bit mask bit sequences of length K1 are used. Concatenating the integer bit sequence s with length Ks yields a second bit sequence c with length K1+Ks, i.e., the length of the second bit sequence c is N1 = K1+Ks.

[0328] In some embodiments, the second bit sequence

[0329] In some embodiments, the second bit sequence

[0330] In some embodiments, for index j = 0, 1, ..., K1-1, when mod(j, Qm / 2-1) equals j M At that time, set the bit mask bit sequence. The bit at index j is the result of XORing the bit at index j of the first part b1 with the bits in the integer codeword bit sequence v. When mod(j, Qm / 2-1) is not equal to j M At that time, set the bit mask bit sequence. The bit at index j is the bit b1(j) of the first part b1 at index j. In another specific example, for indices j = 0, 1, ..., K1-1, when mod(j, Qm-1) equals the constant j M At that time, set the bit mask bit sequence. The bit at index j is the result of XORing the bit at index j of the first part b1 with the bits in the integer codeword bit sequence v. When mod(j, Qm-1) is not equal to the constant j M At that time, set the bit mask bit sequence. The bit at index j is the bit b1(j) of the first part b1 at index j.

[0331] In some embodiments, for index j less than NLLR, a bitmask bit sequence is set. The bit at index j is the result of XORing the bit at index j of the first part b1 (b1(j)) with the bit at index j in the integer codeword bit sequence v (v(j)). For index j greater than or equal to NLLR, set the bit mask bit sequence. The bit at index j is the bit b1(j) of the first part b1 at index j.

[0332] In some embodiments, for index j greater than or equal to j M ×NLLR and less than (j M +1)×NLLR, set the bit mask bit sequence The bit at index j is the result of XORing the bit at index j of the first part b1 (b1(j)) with the bit at index j in the integer codeword bit sequence v (v(j)). For index j less than j M ×NLLR or index j is greater than or equal to (j M +1)×NLLR, set the bit mask bit sequence The bit at index j is the bit b1(j) of the first part b1 at index j.

[0333] like Figure 8 The diagram shown is a block diagram of a channel encoder provided in an embodiment of this disclosure, including: code block segmentation and code block CRC attachment 801, LDPC coding 802, rate matching 803, and code block segmentation 804.

[0334] Code block segmentation and code block CRC attachment 801, used to attach the second part b2 and the second bit sequence c through CRC attachment and insert padding bits. <null>"C" fec A fourth bit sequence of length Nc' Where Nc' = (MB - NB) × Z, MB and NB are the number of rows and columns of the matrix of the base graph of the LDPC code used in LDPC encoding 802, respectively, Z is the lift value of the parity check matrix H of the LDPC code used in LDPC encoding 802, which is expanded from the matrix of the base graph of the LDPC code used in LDPC encoding 802. fec This refers to the number of code blocks. Alternatively, it can be used to append and insert padding bits to the second part b2, the second bit sequence c, and the shaped bit sequence s via CRC. <null>"C" fec A fourth bit sequence of length Nc' Where Nc' = (MB - NB) × Z, MB and NB are the number of rows and columns of the matrix of the base graph of the LDPC code used in LDPC encoding 802, respectively, Z is the lift value of the parity check matrix H of the LDPC code used in LDPC encoding 802, which is expanded from the matrix of the base graph of the LDPC code used in LDPC encoding 802. fec This represents the number of code blocks.

[0335] The above describes how the second part b2 and the second bit sequence c are appended and padded with bits via CRC. <null>"C" fec A fourth bit sequence of length Nc' Includes the following steps:

[0336] Step 1: Divide the second part b2 into C fec Each length is respectively The second subsequence in, and

[0337] In some embodiments, for all indexes r, Kb2' r =K2 / C fec .

[0338] In some embodiments, for all indexes r, Kb2' r =floor(K2 / C fec ).

[0339] In some embodiments, for all indexes r, Kb2' r =ceil(K2 / C fec ).

[0340] In some embodiments, there exists an index r, Kb2' r =floor(K2 / C fec ).

[0341] In some embodiments, there exists an index r, Kb2' r =ceil(K2 / C fec ).

[0342] In some embodiments, for index r less than mod(K2,C) fec ), Kb2' r =ceil(K2 / C fec And for index r greater than or equal to mod(K2,C) fec ), Kb2' r =floor(K2 / C fec ).

[0343] In some embodiments, for index r less than C fec -mod(K2,C fec ), Kb2' r =floor(K2 / C fec And for index r greater than or equal to C fec -mod(K2,C fec ), Kb2' r =ceil(K2 / C fec ).

[0344] In some embodiments, All values ​​are the same.

[0345] In some embodiments, The maximum value in and The difference between the minimum values ​​in the range is 1.

[0346] In some embodiments, The maximum value in and The difference between the minimum values ​​in the range is less than or equal to 1.

[0347] In some embodiments, The maximum value in and The absolute value of the difference between the minimum values ​​is less than or equal to 1.

[0348] In some embodiments, The maximum value in and The absolute value of the difference between the minimum values ​​is less than or equal to 1.

[0349] Step 2: Divide the second bit sequence c into C fec Each length is respectively The subsequence of the second bit sequence in, and For all indices r, the subsequence c” of the second bit sequence of index r r Length Kc” r It is a multiple of the integer Q, where the integer Q can take the values ​​Qm-2, Qm / 2-1, or Qm-1, and Qm is the modulation order.

[0350] In some embodiments, All values ​​are the same.

[0351] In some embodiments, The maximum value in and The difference between the minimum values ​​in is Q, where the integer Q can take the values ​​Qm-2, Qm / 2-1 or Qm-1, and Qm is the modulation order.

[0352] In some embodiments, The maximum value in and The absolute value of the difference between the minimum values ​​is Q, where the integer Q can take the values ​​Qm-2, Qm / 2-1 or Qm-1, and Qm is the modulation order.

[0353] In some embodiments, The maximum value in and The difference between the minimum values ​​in is less than or equal to Q, where the integer Q can take the values ​​Qm-2, Qm / 2-1 or Qm-1, and Qm is the modulation order.

[0354] In some embodiments, The maximum value in and The absolute value of the difference between the minimum values ​​in is less than or equal to Q, where the integer Q can take the values ​​Qm-2, Qm / 2-1 or Qm-1, and Qm is the modulation order.

[0355] In some embodiments, The maximum value in and The absolute value of the difference between the minimum values ​​in is less than or equal to Q, where the integer Q can take the values ​​Qm-2, Qm / 2-1 or Qm-1, and Qm is the modulation order.

[0356] Step 3: For index r, calculate the second subsequence b2' at index r. r The subsequence c” of the second bit sequence with index r r The concatenated sequence [b2′] r ,c′' r The Lcrc number of cyclic redundancy check bits p' r (0),p' r (1),…,p' r (Lcrc-1).

[0357] Step 4: Extract the second subsequence b2' with index r. r The subsequence c” of the second bit sequence with index r r And Lcrc cyclic redundancy check bits p' r (0),p' r (1),…,p' r (Lcrc-1) Insert padding bits <null>"To obtain the fourth bit sequence c' of length Nc' with index r." r Wherein, the fourth bit sequence c' with index r r The length Nc' is greater than or equal to Kb2' r Kc” r The sum of Lcrc and Lcrc.

[0358] When the bit index j is less than the system bit puncture number Npunc, the fourth bit sequence c' with index r is set. r The bits are one of the following: the second subsequence b2' with index r. r The bits in the Lcrc cyclic redundancy check bits p' r (0),p' r (1),…,p' r Bits and padding bits in (Lcrc-1) <null>".

[0359] When the bit index j is greater than or equal to the system bit puncture number Npunc, the fourth bit sequence c' with index r is set. r The bits are one of the following: a subsequence c” of the second bit sequence with index r. r The bits in the second subsequence b2' with index r r The bits in the Lcrc cyclic redundancy check bits p' r (0),p' r (1),…,p' r Bits and padding bits in (Lcrc-1) <null>".

[0360] The above describes how the second part b2, the second bit sequence c, and the shaped bit sequence s are appended using CRC and filled with padding bits. <null>"C" fec A fourth bit sequence of length Nc' Includes the following steps:

[0361] Step 1: Divide the concatenated second part b2 and the integer bit sequence s into a sequence of length K2+Ks, which is C. fec Each length is respectively The second subsequence in, and or

[0362] In some embodiments, for index r, Kb2' r It equals one of the following: (K2+Ks) / C fec floor((K2+Ks) / C fec ),ceil((K2+Ks) / C fec ).

[0363] In some embodiments, for all indexes r, Kb2' r =(K2+Ks) / C fec .

[0364] In some embodiments, for all indexes r, Kb2' r =floor((K2+Ks) / C fec ).

[0365] In some embodiments, for all indexes r, Kb2' r =ceil((K2+Ks) / C fec ).

[0366] In some embodiments, there exists an index r, Kb2' r =floor((K2+Ks) / C fec ).

[0367] In some embodiments, there exists an index r, Kb2' r =ceil((K2+Ks) / C fec ).

[0368] In some embodiments, for index r less than mod(K2+Ks,C) f e ), Kb2' r =ceil((K2+Ks) / C fec And for index r greater than or equal to mod(K2+Ks,C) fec ), Kb2' r =floor((K2+Ks) / C fec ).

[0369] In some embodiments, for index r less than Kb2' r =floor((K2+Ks) / C fec And for index r greater than or equal to C fec -mod(K2+Ks,C fec ), Kb2' r =ceil((K2+Ks) / C fec ).

[0370] In some embodiments, All values ​​are the same.

[0371] In some embodiments, The maximum value in and The difference between the minimum values ​​in the range is 1.

[0372] In some embodiments, The maximum value in and The difference between the minimum values ​​in the range is less than or equal to 1.

[0373] In some embodiments, The maximum value in and The absolute value of the difference between the minimum values ​​is less than or equal to 1.

[0374] In some embodiments, The maximum value in and The absolute value of the difference between the minimum values ​​is less than or equal to 1.

[0375] Step 2: Divide the second bit sequence c into C fec Subsequences of length 1 and 2 of the second bit sequence in, and For all indices r, the subsequence c” of the second bit sequence of index r r Length Kc” r It is a multiple of the integer Q, where the integer Q can take the values ​​Qm-2, Qm / 2-1, or Qm-1, and Qm is the modulation order.

[0376] In some embodiments, All values ​​are the same.

[0377] In some embodiments, The maximum value in and The difference between the minimum values ​​in is Q, where the integer Q can take the values ​​Qm-2, Qm / 2-1 or Qm-1, and Qm is the modulation order.

[0378] In some embodiments, The maximum value in and The absolute value of the difference between the minimum values ​​is Q, where the integer Q can take the values ​​Qm-2, Qm / 2-1 or Qm-1, and Qm is the modulation order.

[0379] In some embodiments, The maximum value in and The difference between the minimum values ​​in is less than or equal to Q, where the integer Q can take the values ​​Qm-2, Qm / 2-1 or Qm-1, and Qm is the modulation order.

[0380] In some embodiments, The maximum value in and The absolute value of the difference between the minimum values ​​in is less than or equal to Q, where the integer Q can take the values ​​Qm-2, Qm / 2-1 or Qm-1, and Qm is the modulation order.

[0381] In some embodiments, The maximum value in and The absolute value of the difference between the minimum values ​​in is less than or equal to Q, where the integer Q can take the values ​​Qm-2, Qm / 2-1 or Qm-1, and Qm is the modulation order.

[0382] Step 3: For index r, calculate the subsequence b2' with index r after concatenating the second part b2 and the integer bit sequence s. r The subsequence c” of the second bit sequence with index r r The concatenated sequence [b2′] r ,c′' r The Lcrc number of cyclic redundancy check bits p' r (0),p' r (1),…,p' r (Lcrc-1).

[0383] Step 4: Concatenate the second part b2 and the integer bit sequence s to form the subsequence b2' with index r. r The subsequence c” of the second bit sequence with index r r And Lcrc cyclic redundancy check bits p' r (0),p' r (1),…,p' r (Lcrc-1) Insert padding bits <null>"To obtain the fourth bit sequence c' of length Nc' with index r." r Wherein, the fourth bit sequence c' with index r r The length Nc' is greater than or equal to Kb2' r Kc” r The sum of Lcrc and Lcrc.

[0384] When the bit index j is less than the system bit puncture number Npunc, the fourth bit sequence c' with index r is set. r The bits are one of the following: the subsequence b2' with index r after concatenating the second part b2 and the integer bit sequence s. r The bits in the Lcrc cyclic redundancy check bits p' r (0),p' r (1),…,p' r Bits and padding bits in (Lcrc-1) <null>".

[0385] When the bit index j is greater than or equal to the system bit puncture number Npunc, the fourth bit sequence c' with index r is set. r The bits are one of the following: a subsequence c” of the second bit sequence with index r. r The subsequence b2' with index r is obtained by concatenating the bits in the first part, the second part b2, and the integer bit sequence s. r The bits in the Lcrc cyclic redundancy check bits p' r (0),p' r (1),…,p' r Bits and padding bits in (Lcrc-1) <null>".

[0386] LDPC encoding 802 is used for the fourth bit sequence c' of index r. r The following steps are performed to obtain the LDPC encoded output bit sequence d with index r. r :

[0387] Step 1: For all indices r, set the LDPC encoded output bit sequence d at index r. r The length is Nd = NB × Z - Npunc, where NB is the matrix H of the base graph corresponding to the parity check matrix used by LDPC encoding 802. BG The column number Z is the matrix H of the base graph of the LDPC code used in LDPC encoding 802. BG The boost value of the parity-check matrix H of the LDPC code used for extended LDPC encoding 802, where Npunc is the number of punctures in the system bits.

[0388] Step 2: For k = Npunc, Npunc+1, ..., Nc'-1, set the LDPC encoded output bit sequence d with index r as follows: r System bit portion:

[0389] If c' r (k) is not equal to <null>Set d r (k-Npunc)=c' r (k);

[0390] If c' r (k) equals <null>Set c' r (k)=0、d r (k-Npunc) = <NULL>, where c' r (k) is the fourth bit sequence c' of index r. r The bits of index k, d r (k-Npunc) is the LDPC encoded output bit sequence d with index r. r The bits with index k-Npunc are given, and Nc' is the fourth bit sequence c' of index r. r The length.

[0391] Step 3: Generate Nd+Npunc-Nc' parity bits w = [w(0),...,w(Nd+Npunc-Nc'-1)] such that H×[c' r ,w] T =θ, where, [c' r ,w] T Let θ be a column vector of length NB×Z, and let θ be a zero vector of length MB×Z. Matrix and vector multiplication is performed over the Galois field GF(2). The parity check matrix H of the LDPC code is based at least on the matrix H of the fundamental graph of the LDPC code. BG The increase value Z is determined by the value of the increase.

[0392] Step 4: For k = Nc', Nc'+1, ..., Nd+Npunc-1, set the LDPC encoded output bit sequence d. r The parity bit portion: d r (k-Npunc)=w(k-Nc'), where d r (k-Npunc) is the LDPC encoded output bit sequence d with index r. r The bits with index k-Npunc are given, and Nc' is the fourth bit sequence c' of index r. r The length of w(k-Nc') is the parity bit with index k-Nc'.

[0393] Rate Match 803 is used to encode the LDPC output bit sequence d at index r. r The rate-matched output bit sequence f with index r is obtained by performing the following steps. r :

[0394] Step 1: Determine the rate-matched output bit sequence f with index r. r Length Nf r satisfy Where Qm is the modulation order, and for all indices r, Nf r It is a multiple of Qm.

[0395] In some embodiments, for index r, the rate-matched output bit sequence f at index r r Length Nf r subsequence c” of the second bit sequence r Length Kc” r Satisfy one of the following relationships:

[0396] Step 2: Encode the LDPC bit sequence d at index r. r Split into the first part d1 of the LDPC encoded output bit sequence r and the second part d2 of the LDPC encoded output bit sequence r The first part d1 of the LDPC encoded output bit sequence r The length is Kc” r That is, the subsequence c” of the second bit sequence with index r. r The length of the LDPC encoded output bit sequence, and the first part d1 r Including the LDPC encoded output bit sequence with index r where the index is less than Kc” r bits, d1 r (k)=d r (k), k = 0, 1, ..., Kc” r -1; d2, the second part of the LDPC encoded output bit sequence r The length is Nd-Kc” r Nd is the LDPC encoded output bit sequence d r The length of d2, and the second part of the LDPC encoded output bit sequence. r This includes LDPC encoded output bit sequences with index r whose index is greater than or equal to Kc. r The bits, i.e., d2 r (k-Kc” r )=d r (k),k=Kc” r ,1,…,Nd-1;

[0397] Step 3: Output the first part d1 of the bit sequence from the LDPC encoding. r Bit d1 of the first starting index k1×(Qm-2) r Starting with (k1×(Qm-2)), select (Qm-2)×Nfr / Qm non-padded bits with the first circular cache size Ncb1 and place them in the cache matrix H of row Qm and column Nfr / Qm. buff In the last Qm-2 columns; simultaneously, from the second part d2 of the LDPC encoded output bit sequence. r Bit d2 of the first starting index k2 r (k2) Start by selecting 2×Nf with the second loop buffer size Ncb2. r / Qm non-padded bits are placed in row Nf of Qm. r The cache matrix H of column / Qm buff In the first two columns.

[0398] Step 4: Change the Qm row to Nf r The cache matrix H of column / Qm buff The bits in the array are extracted column-by-row to length Nf r The rate-matched output bit sequence f with index r r .

[0399] 804 code block concatenation is used for C fec A rate-matched output bit sequence Concatenating the sequences yields a third bit sequence g of length Ng, where the length of the third bit sequence g satisfies the following condition: and Nf r For the rate-matched output bit sequence f at index r r The length.

[0400] The application scenarios of the embodiments disclosed herein are not limited. The system architecture and business scenarios described in the embodiments of this disclosure are for the purpose of more clearly illustrating the technical solutions of the embodiments of this disclosure, and do not constitute a limitation on the technical solutions provided by the embodiments of this disclosure. As those skilled in the art will know, with the evolution of network architecture and the emergence of new business scenarios, the technical solutions provided by the embodiments of this disclosure are also applicable to similar technical problems.

[0401] The communication method provided in the embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0402] The communication method provided in this disclosure can be applied to... Figure 1 The first node 101 in the communication system shown. Figure 9 A flowchart of a communication method is shown, such as... Figure 9 As shown, the communication method includes the following S901-S905:

[0403] S901, Obtain the first bit sequence.

[0404] S902. The first part of the first bit sequence is shaped and encoded to obtain the second bit sequence.

[0405] In some embodiments, the second bit sequence includes an integer bit sequence.

[0406] It should be understood that integer coding can convert the bit sequence corresponding to the first part into a bit sequence or symbol sequence with unequal probability distribution. By using unequal probability distribution, the frequency of different symbols appearing during signal transmission can be adjusted, thus ensuring that the occurrence of symbols during signal transmission is the desired outcome, achieving the desired effect.

[0407] For example, unequal probability distributions can be used to reduce the frequency of higher power symbols and increase the frequency of lower power symbols, thereby reducing the average transmit power and increasing channel capacity.

[0408] For example, unequal probability distributions can be used to increase the frequency of high-reliability symbols and decrease the frequency of low-reliability symbols, thereby improving the reliability of transmission.

[0409] It should be understood that performing integer encoding only on the first part of the first bit sequence allows for more flexible adjustment of the spectral efficiency of the scheme compared to performing integer encoding on the entire first bit sequence.

[0410] It should be understood that different bit sequences may yield different results when subjected to integer coding. For example, some bit sequences are not inherently important, and integer coding may not significantly improve data transmission reliability. Conversely, some bit sequences already possess sufficient anti-interference capabilities to adapt to the current channel environment, and the effect of integer coding is relatively small. Therefore, the first part of the first bit sequence can be the bits that need integer coding; that is, only the portion of the first bit sequence requiring integer coding is coded. Compared to coding the entire first bit sequence, the effect is similar or the same. This improves the flexibility of integer coding, increases the utilization of processing resources, and enhances data transmission reliability with fewer processing resources and shorter processing times.

[0411] S903. Channel coding is performed based on the second part of the first bit sequence and the second bit sequence to obtain the third bit sequence.

[0412] It should be understood that channel coding of the second part of the first bit sequence and the second bit sequence can yield a third bit sequence containing redundant bits, the second part of the first bit sequence, and the second bit sequence. Since the redundant bits can help determine whether there are transmission errors and / or help correct transmission errors during data transmission, the reliability of data transmission can be improved.

[0413] In some embodiments, S903, channel coding is performed based on the second part of the first bit sequence and the second bit sequence to obtain a third bit sequence, which is achieved by merging the second part of the first bit sequence and the second bit sequence to obtain a fourth bit sequence. Channel coding is then performed on the fourth bit sequence to obtain the third bit sequence.

[0414] In some embodiments, there are multiple fourth bit sequences. Channel coding of longer bit sequences is more complex than channel coding of shorter bit sequences. Therefore, multiple fourth bit sequences can be used. Channel coding each fourth bit sequence reduces the complexity of channel coding, simplifies the coding and modulation process at the first node, and reduces the difficulty of decoding and demodulation at the receiver. Furthermore, channel coding multiple fourth bit sequences as a whole might require retransmission of the entire sequence if errors occur during transmission. With multiple fourth bit sequences, only the erroneous fourth bit sequence can be retransmitted, thus reducing the amount of retransmitted data and improving resource utilization.

[0415] In some embodiments, the number of fourth bit sequences is equal to the number of integer blocks after the first part of the integer coding segment. This means there is a one-to-one correspondence between the fourth bit sequences and the integer blocks. In this case, the integer blocks can be directly mapped to code blocks, simplifying the channel coding process.

[0416] In some embodiments, the number of fourth bit sequences is not equal to the number of integer blocks after the first part of the integer coding segment. This means that the number of fourth bit sequences is either more or less than the number of integer blocks. When the number of fourth bit sequences is more than the number of integer blocks, the fourth bit sequences can be used to carry more parity bits and redundant bits, improving the error correction capability and reliability of data transmission. When the number of fourth bit sequences is less than the number of integer blocks, the workload corresponding to channel coding can be reduced, the processing steps required for data transmission can be reduced, the data transmission speed can be increased, and the latency can be reduced. When the number of fourth bit sequences is less than the number of integer blocks, the length of each block can be longer, improving the error correction capability of channel coding.

[0417] In some embodiments, there are multiple fourth bit sequences. Bits in the fourth bit sequence with indices less than the number of punctures in the first system include at least one of the following: bits in the second part, bits in the shaped bit sequence, and padding bits.

[0418] It should be understood that the bits in the first system bit puncture count represent the bits that can be punctured. The first system bit puncture count represents the number of bits that can be punctured. The bits in the fourth bit sequence with indices less than the first system bit puncture count are used to indicate the bits that can be punctured.

[0419] It should be understood that in the puncturing operation, the bits that can be punctured are bits of relatively low importance, bits that are easy to recover from the receiver, or parity bits generated by the system bits. Since the bits in the second part can be bits of low importance or bits whose information can be recovered from the receiver, the bits in the second part can be included in the bits that can be punctured.

[0420] It should be understood that the bits in the shaped bit sequence are obtained by shaped coding or distribution matching in shaped coding, or the output bits of the channel decoder in the shaped encoder based on block codes. They are bits used to realize non-uniform probability distribution and may not directly carry effective information, or there may be bits that have little impact on data transmission after removal. Therefore, the bits in the fourth bit sequence with an index less than the number of bit punctures in the first system can include the bits in the shaped bit sequence.

[0421] It should be understood that the padding bits themselves do not carry valid information; they are added to meet length or rate matching requirements. Therefore, the bits in the fourth bit sequence with indices less than the number of punctures in the first system include the padding bits.

[0422] It should be understood that by limiting the contents that bits with indices less than the number of punctures in the first system bit sequence can include, the bits that can be punctured can be determined, puncturing efficiency can be improved, and it can be ensured that the removed bits do not affect the unequal probability distribution of the bit sequence or symbol sequence formed by the integer encoding.

[0423] In some embodiments, the first system bit puncture number can be the configured maximum system bit puncture number or the system bit puncture number of a low-density parity check code.

[0424] In some embodiments, bits in the fourth bit sequence with indices less than the number of punctures in the first system bit sequence do not include bits in the second bit sequence other than the shaped bit sequence. Since the bits in the second bit sequence other than the shaped bit sequence contain amplitude information of the modulation symbols, excluding bits in the second bit sequence other than the shaped bit sequence from the index of the fourth bit sequence ensures that the amplitude information of the modulation symbols in the second bit sequence is not punctured or removed, thus guaranteeing the integrity of the unequal probability distribution of the symbol sequence and improving the reliability of data transmission.

[0425] In some embodiments, there are multiple fourth bit sequences; the bits in the fourth bit sequence whose index is greater than or equal to the number of punctures in the first system bit sequence include at least one of the following: bits in the second part, bits in the integer bit sequence, padding bits, and bits in the second bit sequence other than the integer bit sequence.

[0426] In some embodiments, the bits in the fourth bit sequence whose index equals the number of punctures in the first system bit sequence are bits in the second bit sequence excluding the integer bit sequence. That is, the bits in the fourth bit sequence excluding the integer bit sequence in the second bit sequence are located at the end of the bits that can be punctured. In this way, it can be ensured that when performing the puncturing operation, the bits in the second part, the bits in the integer bit sequence, and the padding bits are punctured first, so that the bit with the smallest index among the remaining bits after puncturing is the bit in the second bit sequence excluding the integer bit sequence, which can simplify the bit selection operation in the channel encoder.

[0427] In some embodiments, among the bits in the fourth bit sequence whose index is greater than or equal to the number of punctured bits in the first system bit sequence, the index of the bits in the second bit sequence other than the shaped bit sequence is less than the index of the bits in the second part, the bits in the shaped bit sequence, or the index of the padding bits. This simplifies the bit selection operation in the channel encoder, ensuring that the first part of the punctured sequence corresponds to the amplitude bits of the modulation symbol, and the second part to the non-amplitude bits of the modulation symbol.

[0428] S904. Modulate the third bit sequence to obtain the modulated symbol sequence.

[0429] In some embodiments, S904, the third bit sequence is modulated to obtain a modulated symbol sequence, which is achieved by obtaining the modulation order. Based on the modulation order, the third bit sequence is modulated to obtain the modulated symbol sequence.

[0430] In some embodiments, the third bit sequence can be modulated based on a constellation diagram to obtain a modulated symbol sequence.

[0431] For example, the modulation symbol sequence is X, and its length is Nx. Each symbol in the modulation symbol sequence X is / corresponds to / maps to a constellation point in the modulation constellation of modulation order Qm.

[0432] S905, Send a signal including the modulation symbol sequence to the second node.

[0433] In this disclosure, a second bit sequence is obtained by shaping and encoding a first portion of a first bit sequence. This allows for efficient, flexible, and reliable shaping and encoding of the bit sequence to be transmitted, achieving the desired effect. A third bit sequence containing redundant bits is obtained by channel coding based on the second portion of the first bit sequence and the second bit sequence. Therefore, it is possible to ensure that the first node can reliably transmit signals including the modulation symbol sequence to the second node, and to improve the reliability of data transmission.

[0434] In some embodiments, the first bit sequence satisfies one of the following:

[0435] The first bit sequence is the transmission block sent from the first node to the second node;

[0436] The first bit sequence includes the transport block sent from the first node to the second node and the cyclic redundancy check bits.

[0437] It should be understood that the inclusion of cyclic redundancy check bits in the first bit sequence enables the second node to perform error verification or correction on the transport blocks sent by the first node, thereby improving the reliability of data transmission.

[0438] In some embodiments, the sum of the length of the first part and the length of the second part is the length of the first bit sequence.

[0439] In some embodiments, the first part and the second part satisfy one of the following:

[0440] The bits in the first part are the bits in the first bit sequence whose index is less than the first value. The bits in the second part are the bits in the first bit sequence whose index is greater than or equal to the first value. The first bit sequence includes the second number of bits.

[0441] The bits in the first part are the bits in the first bit sequence whose index is greater than or equal to the difference between the second value and the first value. The first bit sequence includes the second number of bits. The bits in the second part are the bits in the first bit sequence whose index is less than the difference between the second value and the first value. The first value is the length of the first part, and the second value is the length of the first bit sequence.

[0442] It should be understood that the first part and the second part can be the beginning and end parts of the first bit sequence, respectively, or they can be the end and beginning parts of the first bit sequence.

[0443] Examples of communication methods provided in embodiments of this disclosure are given below:

[0444] The communication method performed by the first node includes: the first node acquiring a first bit sequence b and a modulation order Qm. The first node divides the first bit sequence b into a first part b1 and a second part b2. The first node performs integer encoding on the first part b1 to obtain a second bit sequence c or an integer bit sequence s. The first node determines C using the second part b2, the second bit sequence c, or the integer bit sequence s. fec The fourth bit sequence The first node is C fec The fourth bit sequence Channel coding is performed to obtain the third bit sequence g. The first node modulates the third bit sequence g with modulation order Qm to obtain the modulation symbol sequence X. The first node sends a signal including the modulation symbol sequence X to the second node.

[0445] The communication method performed by the second node includes: the second node acquiring the modulation order Qm; the second node receiving a signal including the modulation symbol sequence X; the second node demodulating the signal including the modulation symbol sequence X with the modulation order Qm to obtain a soft information sequence corresponding to the third bit sequence g; and the second node performing channel decoding estimation on the soft information sequence corresponding to the third bit sequence g to obtain C. fec The fourth bit sequence The second node is from C. fec The fourth bit sequence The second node determines the estimate of the second part b2, the estimate of the second bit sequence c, or the estimate of the shaped bit sequence s. The second node performs shaping decoding on the estimate of the second bit sequence c or the estimate of the shaped bit sequence s to obtain the estimate of the first part b1. The second node determines the estimate of the first bit sequence b from the estimate of the first part b1 and the estimate of the second part b2.

[0446] In some embodiments, the length of the modulation symbol sequence X is Nx, and each symbol in the modulation symbol sequence X is a constellation point in the modulation constellation of modulation order Qm.

[0447] It should be noted that the length of the first bit sequence b is denoted as K, the length of the first part b1 is denoted as K1, the length of the second part b2 is denoted as K2, the length of the second bit sequence c is denoted as N1, the length of the shaped bit sequence s is denoted as Ks, the length of the fourth bit sequence d is denoted as Nd, the length of the third bit sequence g is denoted as Ng, and the length of the modulation symbol sequence X is denoted as Nx.

[0448] In some embodiments, the first bit sequence b is a transport block sent from the first node to the second node. The length K of the first bit sequence b is the transport block size TBS, i.e., K = TBS.

[0449] In some embodiments, the first bit sequence b includes a transport block sent from the first node to the second node and Lcrc cyclic redundancy check bits calculated based on the transport block, wherein the transport block size is TBS, and the length K of the first bit sequence b is K = TBS + Lcrc.

[0450] In some embodiments, the length K of the first bit sequence b, the length K1 of the first part b1, and the length K2 of the second part b2 satisfy K = K1 + K2.

[0451] In some embodiments, the first bit sequence b is divided into a first part b1 and a second part b2 in the following manner: the first part b1 is K1 bits in the first bit sequence b with indices less than K1, and the second part b2 is K2 bits in the first bit sequence b with indices greater than or equal to K1, i.e. [b1(0),...,b1(K1-1)]=[b(0),...,b(K1-1)] and [b2(0),...,b2(K1-1)]=[b(K1),...,b(K1+K2-1)].

[0452] In some embodiments, the first bit sequence b is divided into a first part b1 and a second part b2 in the following manner: the first part b1 is K1 bits in the first bit sequence b with an index greater than or equal to K2, and the second part b2 is K2 bits in the first bit sequence b with an index less than K2, that is, [b1(0),...,b1(K1-1)]=[b(K2),...,b(K2+K1-1)] and [b2(0),...,b2(K2-1)]=[b(0),...,b(K2-1)].

[0453] In some embodiments, the first portion b1 is encoded into a second bit sequence c using distribution-matcher-based integer coding, including the following steps:

[0454] Step 1: The first node determines the number of integer blocks Cs, and the lengths of the Cs integer block input bit sequences K1'0, K1'1, ..., K1' Cs-1 And the output amplitude sign sequence A'0, A'1, ..., A' of Cs integer blocks. Cs-1 The lengths NA'0,NA'1,…,NA' Cs-1 Where, K1 = K1'0 + K1'1 + ... + K1' Cs-1 Nx≥NA'0+NA'1+…+NA' Cs-1 Or 2×Nx≥NA'0+NA'1+…+NA' Cs-1 Then, the first node divides the first part b1 into Cs segments of length K1'0, K1'1, ..., K1'. Cs-1 The integer block input bit sequence b1'0, b1'1, ..., b1' Cs-1 Where b1 = [b1'0, b1'1, ..., b1' Cs-1 ].

[0455] Step 2: For indices r = 0, 1, ..., Cs-1, the length of the first node at index r is K1'. r The shaped input bit sequence b1' r Performing distributed matching encoding yields a length of NA' r The output amplitude sign sequence A' of the shaping block r .

[0456] In some embodiments, distribution matching may use any one of a number of suitable algorithms and any one of a number of suitable configurations.

[0457] In some embodiments, distribution matching can be implemented using one of the following distribution matchers: constant-composition distribution matcher (CCDM), bit-level distribution matcher (BL-DM), product distribution matcher (PDM), multi-composition distribution matcher (MCDM), multiset-partition distribution matcher (MPDM), partition-based distribution matcher, parallel-amplitude distribution matcher with subset ranking, streaming distribution matcher, prefix-free codedistribution matcher, shell mapping, enumerative sphereshaping (ESS), approximate enumerative sphere shaping (AESS), and partial enumerative sphere shaping. Sphere shaping (PESS), Huffman-coded sphere shapingFraming of variable-length distribution matcher outputs into fixed-length blocks, distribution matcher with mark ratio control, hierarchical distribution matcher, parallel bisection-based distribution matcher, and polar-coded distribution matcher.

[0458] It should be noted that the aforementioned distributed matcher is used to generate a probabilistically determined sequence of symbols to construct shaped signals, such as ASK or QAM signals.

[0459] Step 3: The first node outputs Cs distribution matching results with lengths NA'0, NA'1, ..., NA'. Cs-1 The output amplitude sign sequence of the shaping block is A'0, A'1, ..., A' Cs-1 Cascading yields an integer amplitude symbol sequence A of length NA, where NA is the Cs integer block output amplitude symbol sequence A'0, A'1, ..., A' determined by the integer block segmentation. Cs-1 The sum of the lengths, i.e., NA = NA'0 + NA'1 + ... + NA' Cs-1 .

[0460] In some embodiments, A = [A'0, A'1, ..., A'] Cs-1 That is, the index in the integer amplitude sign sequence A is greater than or equal to NA'0+NA'1+…+NA'. r-1 And less than NA'0+NA'1+…+NA' r The amplitude sign is the output amplitude sign sequence A' of the integer block with index r. r The amplitude sign, i.e., A(NA'0+…+NA') r-1 +j)=A' r (j), j = 0, 1, ..., NA' r -1.

[0461] Step 4: The first node converts each amplitude symbol in the NA-length integer amplitude symbol sequence A from the concatenated integer blocks into a bit string according to the set amplitude-to-bit mapping rule, and concatenates them to obtain a second bit sequence c of length N1, where NA is the Cs integer block output amplitude symbol sequence A'0, A'1, ..., A' determined in the integer block segmentation. Cs-1 The sum of the lengths, i.e., NA = NA'0 + NA'1 + ... + NA' Cs-1 .

[0462] In some embodiments, the amplitude-to-bit mapper converts each amplitude A(j) in the shaped amplitude symbol sequence A into Qm / 2-1 bits c(j·(Qm / 2-1)), c(j·(Qm / 2-1)+1),...,c(j·(Qm / 2-1)+Qm / 2-2) according to a preset mapping method, and then concatenates them into a second bit sequence c, where the length N1 of the second bit sequence c is equal to NA·(Qm-2), and Qm is the modulation order of the modulation symbol sequence X.

[0463] In some embodiments, the amplitude-to-bit mapper converts each amplitude A(j) in the shaped amplitude symbol sequence A into Qm-1 bits c(j·(Qm-1)), c(j·(Qm-1)+1), ..., c(j·(Qm-1)+Qm-2) according to a preset mapping method, and then concatenates them into a second bit sequence c, where the length N1 of the second bit sequence c is equal to NA·(Qm-1), and Qm is the modulation order of the modulation symbol sequence X.

[0464] In some embodiments, the first portion b1 is encoded into a second bit sequence c using block code-based integer coding, including the following steps:

[0465] Step 1: For each consecutive Qm / 2-1 bits of the first part b1, b1(j·(Qm / 2-1)), b1(j·(Qm / 2-1)+1),...,b1(j·(Qm / 2-1)+Qm / 2-2), the first node determines a log-likelihood ratio (LLR) LLR(j) according to the pre-set amplitude-to-bit mapping relationship. Finally, the log-likelihood ratio sequence LLR(0)~LLR(NLLR-1) with a length of NLLR=K1 / (Qm / 2-1) is obtained, where K1 is the length of the first part b1, Qm is the modulation order of the modulation mapping, and K1 is a multiple of (Qm / 2-1).

[0466] In some embodiments, the first node determines a log-likelihood ratio LLR(j) for each consecutive Qm-1 bits b1(j·(Qm-1)), b1(j·(Qm-1)+1), ..., b1(j·(Qm-1)+Qm-2) of the first part b1 according to a pre-set amplitude-to-bit mapping relationship, and finally obtains a log-likelihood ratio sequence LLR(0)~LLR(NLLR-1) of length NLLR=K1 / (Qm-1), where K1 is the length of the first part b1, Qm is the modulation order of the modulation mapping, and K1 is a multiple of (Qm-1).

[0467] In some embodiments, the first node determines the log-likelihood ratio LLR(j) at index j, K1 / (Qm / 2-1)+j,…,(Qm / 2-2)×K1 / (Qm / 2-1)+j, for the first part b1, based on the pre-set amplitude-to-bit mapping relationship. Finally, a log-likelihood ratio sequence LLR(0)~LLR(NLLR-1) of length NLLR=K1 / (Qm / 2-1) is obtained, where K1 is the length of the first part b1, Qm is the modulation order of the modulation mapping, and K1 is a multiple of (Qm / 2-1).

[0468] Step 2: The first node determines the number of integer blocks Cs, the input log-likelihood ratio of Cs integer blocks, and the sequence length Ns0,'Ns1,'…,Ns Cs ' -1 And Cs integer blocks output integer bit sequences s'0, s'1, ..., s' Cs-1 The lengths Ks0', Ks1', ..., Ks C ' s-1 Where, NLLR=Ns0'+Ns1'+…+Ns C ' s-1 Nx≥Ns'0+Ns'1+…+Ns' Cs-1 Or 2×Nx≥Ns'0+Ns'1+…+Ns' Cs-1 Nx is the length of the modulation symbol sequence X, and Ks' r ≤Ns' r Then, the first node segments the log-likelihood ratio sequence LLR(0) to LLR(NLLR-1) into Cs segments of length Ns'0, Ns'1, ..., Ns'. Cs-1 The integer block input log-likelihood ratio sequence LLR'0, LLR'1, ..., LLR' Cs-1 , where LLR=[LLR'0,LLR'1,...,LLR' Cs-1 ].

[0469] Step 3: For indices r = 0, 1, ..., Cs-1, the first node is determined according to Ks' r and Ns' r The generator matrix G is set. r Or the parity check matrix (H) r Input the integer block with index r into the log-likelihood ratio sequence LLR' r The input is used for channel decoding to obtain a length of Ks' with index r. r The output of the shaped block is the shaped bit sequence s' r .

[0470] In some embodiments, the generating matrix G r Or the verification matrix H r Corresponding to linear codes or forward error-correcting codes.

[0471] In some embodiments, the linear code or FEC code can be one of the following: polar code, low-density parity check code, convolutional code, turbo code, Reed-Muller code, Reed-Solomon code, Bose-Chaudhuri-Hocquenghem code, concatenated code, cyclic code, block code, Hamming code, Golay code, repetition code, or single-parity-check code.

[0472] Step 4: For indices r = 0, 1, ..., Cs-1, the first node generates a matrix G with the same index r as the channel decoder. r Or the verification matrix H r And the length of index r is Ks' r The output of the shaped block is the shaped bit sequence s' r Determine the length Ns' of index r. r The integer block codeword bit sequence v' r .

[0473] In some embodiments, v' r =s' r ×G r The vector-matrix multiplication is performed over the Galois field GF(2), (v' r ) T It is the transpose of v'r.

[0474] In some embodiments, H r ×(v' r ) T =0 and [v' r (0),…,v' r (Ks' r -1)]=[s' r (0),…,s' r (Ks' r -1)], where the vector-matrix multiplication is performed over the Galois field GF(2), (v' r ) T It is the transpose of v'r.

[0475] In some embodiments, the generating matrix G r Or the verification matrix H r Corresponding to linear codes or forward error-correcting codes.

[0476] In some embodiments, the linear code or FEC code can be one of the following: polar code, low-density parity check code, convolutional code, turbo code, Reed-Muller code, Reed-Solomon code, Bose-Chaudhuri-Hocquenghem code, concatenated code, cyclic code, block code, Hamming code, Golay code, repetition code, or single-parity-check code.

[0477] Step 5: The first node decodes the Cs data points of length Ks'0, Ks'1, ..., Ks' from the channel decoding output. Cs-1 The integer block outputs an integer bit sequence s'0, s'1, ..., s' Cs-1 Concatenating the bits yields an integer bit sequence s of length Ks, and channel coding outputs Cs bits of length Ns0', Ns1', ..., Ns C ' s-1 The integer block codeword bit sequence v'0,v'1,…,v' Cs-1 The cascaded structure yields a length of NLLR = Ns'0 + Ns'1 + ... + Ns' Cs-1 The integer codeword bit sequence v, where Ks is the Cs integer block output integer bit sequence s'0, s'1, ..., s' determined in the channel decoding. Cs-1 The sum of the lengths, i.e., Ks = Ks'0 + Ks'1 + ... + Ks' Cs-1 .

[0478] In some embodiments, s = [s'0, s'1, ..., s' Cs-1 ] NLLR is the log-likelihood ratio sequence LLR(0)~LLR(NLLR-1) determined during the log-likelihood ratio generation process.

[0479] In some embodiments, v = [v'0, v'1, ..., v' Cs-1 ].

[0480] Step 6: The first node performs an XOR operation on the NLLR bits in the first part b1 of length K1 and the integer codeword bit sequence v of length NLLR to obtain the ratio of length K1.

[0481] Special mask bit sequence Among them, the bit mask bit sequence of length K1 This is the second bit sequence c, and the length of the second bit sequence c is N1 = K1.

[0482] In some embodiments, for index j = 0, 1, ..., K1-1, when mod(j, Qm / 2-1) equals j M At that time, set the bit mask bit sequence. The bit at index j is the result of XORing the bit at index j of the first part b1 with the bits in the integer codeword bit sequence v. When mod(j, Qm / 2-1) is not equal to j M At that time, set the bit mask bit sequence. The bit at index j is the bit b1(j) of the first part b1 at index j.

[0483]

[0484] In some embodiments, for indices j = 0, 1, ..., K1-1, when mod(j, Qm-1) equals the constant j M At that time, set the bit mask bit sequence. The bit at index j is the result of XORing the bit at index j of the first part b1 with the bits in the integer codeword bit sequence v. When mod(j, Qm-1) is not equal to the constant j M At that time, set the bit mask bit sequence. The bit at index j is the bit b1(j) of the first part b1 at index j.

[0485] In some embodiments, for index j less than NLLR, a bitmask bit sequence is set. The bit at index j is the result of XORing the bit at index j of the first part b1 (b1(j)) with the bit at index j in the integer codeword bit sequence v (v(j)). For index j greater than or equal to NLLR, set the bit mask bit sequence. The bit at index j is the bit b1(j) of the first part b1 at index j.

[0486] In some embodiments, the first part b2 and the second bit sequence c are determined based on LDPC encoding. fec The fourth bit sequence During the process, the first node attaches and inserts padding bits based on the second part b2 and the second bit sequence c through CRC. <null>"C" fec A fourth bit sequence of length Nc' Where Nc' = (MB - NB) × Z, MB and NB are the number of rows and columns of the matrix of the base graph of the LDPC code used for LDPC encoding, respectively, Z is the lift value of the parity-check matrix H of the LDPC code used for LDPC encoding, which is expanded from the matrix of the base graph of the LDPC code used for LDPC encoding. fec This represents the number of code blocks.

[0487] At this point, code block segmentation and code block CRC attachment include the following steps:

[0488] Step 1: The first node divides the second part b2 into C. fe Each length is respectively The second subsequence in, and

[0489] Step 2: The first node divides the second bit sequence c into C. fec Each length is respectively The subsequence of the second bit sequence in, and For all indices r, the subsequence c” of the second bit sequence of index r r Length Kc” r It is a multiple of the integer Q, where the integer Q can take the values ​​Qm-2, Qm / 2-1, or Qm-1, and Qm is the modulation order.

[0490] Step 3: For index r, calculate the second subsequence b2' at index r. r The subsequence c” of the second bit sequence with index r r The concatenated sequence [b2′] r Lcrc cyclic redundancy check bits p' of c′'r] r (0),p' r (1),…,p' r (Lcrc-1).

[0491] Step 4: Extract the second subsequence b2' with index r. r The subsequence c” of the second bit sequence with index r r And Lcrc cyclic redundancy check bits p' r (0),p' r (1),…,p' r (Lcrc-1) Insert padding bits <null>"To obtain the fourth bit sequence c' of length Nc' with index r." r Wherein, the fourth bit sequence c' with index r r The length Nc' is greater than or equal to Kb2' r Kc” r The sum of Lcrc and Lcrc.

[0492] When the bit index j is less than the system bit puncture number Npunc, the fourth bit sequence c' with index r is set. r The bits are one of the following: the second subsequence b2' with index r. r The bits in the Lcrc cyclic redundancy check bits p' r (0),p' r (1),…,p' r Bits and padding bits in (Lcrc-1) <null>".

[0493] For example, such as Figure 10 As shown, eight examples (a) to (h) are illustrated, where the non-amplitude bits are the second subsequence b2' with index r. r The bits or Lcrc cyclic redundancy check bits p' in the middle r (0),p' r (1),…,p' r In (Lcrc-1), the number of system bit punctures, Npunc, is the number of information bits punctured in the LDPC encoding, and Npm is the configured maximum number of system bit punctures. Npunc is less than or equal to Npm.

[0494] When the bit index j is greater than or equal to the system bit puncture number Npunc, the fourth bit sequence c' with index r is set. r The bits are one of the following: a subsequence c” of the second bit sequence with index r. r The bits in the second subsequence b2' with index r r The bits in the Lcrc cyclic redundancy check bits p' r (0),p' r (1),…,p' r Bits and padding bits in (Lcrc-1) <null>".

[0495] For example, Figure 10 The amplitude bits of the non-amplitude subsequence are the second subsequence b2' with index r. r The bits or Lcrc cyclic redundancy check bits p' in the middle r (0),p' r (1),…,p' r Bits in (Lcrc-1) Figure 10 The intermediate amplitude bits are the subsequence c” of the second bit sequence at index r. r In the LDPC encoding, Npunc is the number of punctured information bits, and Npm is the configured maximum number of punctured system bits. Npunc is less than or equal to Npm. For bit index j less than the number of punctured system bits Npunc, the fourth bit sequence c' with index r is... r The bits do not include the subsequence c” of the second bit sequence at index r. r 0 bits.

[0496] In some embodiments, prior to LDPC encoding, the first node performs CRC attachment and insert padding bits based on the second part b2, the second bit sequence c, and the shaped bit sequence s. <null>"C" fec A fourth bit sequence of length Nc' Where Nc' = (MB - NB) × Z, MB and NB are the number of rows and columns of the matrix of the base graph of the LDPC code used for LDPC encoding, respectively, Z is the lift value of the parity-check matrix H of the LDPC code used for LDPC encoding, which is expanded from the matrix of the base graph of the LDPC code used for LDPC encoding. fec This refers to the number of code blocks. At this point, code block segmentation and code block CRC attachment include the following steps:

[0497] Step 1: The first node concatenates the second part b2 and the integer bit sequence s, resulting in a sequence of length K2+Ks, which is then divided into C. fec Each length is respectively The second subsequence in, and or

[0498] Step 2: The first node divides the second bit sequence c into C. fec Subsequences of length 1 and 2 of the second bit sequence in, and For all indices r, the subsequence c” of the second bit sequence of index r r Length Kc” r It is a multiple of the integer Q, where the integer Q can take the values ​​Qm-2, Qm / 2-1, or Qm-1, and Qm is the modulation order.

[0499] Step 3: For index r, calculate the second subsequence b2' at index r. r The subsequence c” of the second bit sequence with index r r The concatenated sequence [b2′] r ,c′' r The Lcrc number of cyclic redundancy check bits p' r (0),p' r (1),…,p' r (Lcrc-1).

[0500] Step 4: Extract the second subsequence b2' with index r. r The subsequence c” of the second bit sequence with index r r And Lcrc cyclic redundancy check bits p' r (0),p' r (1),…,p' r (Lcrc-1) Insert padding bits <null>"To obtain the fourth bit sequence c' of length Nc' with index r." r Wherein, the fourth bit sequence c' with index r r The length Nc' is greater than or equal to Kb2' r Kc” r The sum of Lcrc and Lcrc.

[0501] When the bit index j is less than the system bit puncture number Npunc, the fourth bit sequence c' with index r is set. r The bits are one of the following: the second subsequence b2' with index r. r The bits in the Lcrc cyclic redundancy check bits p' r (0),p' r (1),…,p' r Bits and padding bits in (Lcrc-1) <null>".

[0502] For example, such as Figure 10 As shown, the non-amplitude bits are the second subsequence b2' with index r. r The bits or Lcrc cyclic redundancy check bits p' in the middle r (0),p' r (1),…,p' r In (Lcrc-1), the number of system bit punctures, Npunc, is the number of information bits punctured in the LDPC encoding, and Npm is the configured maximum number of system bit punctures. Npunc is less than or equal to Npm.

[0503] When the bit index j is greater than or equal to the system bit puncture number Npunc, the fourth bit sequence c' with index r is set. r The bits are one of the following: a subsequence c” of the second bit sequence with index r. r The bits in the second subsequence b2' with index r r The bits in the Lcrc cyclic redundancy check bits p' r (0),p' r (1),…,p' r Bits and padding bits in (Lcrc-1) <null>".

[0504] For example, such as Figure 10 As shown, Figure 10 The amplitude bits of the non-amplitude subsequence are the second subsequence b2' with index r. r The bits or Lcrc cyclic redundancy check bits p' in the middle r (0),p' r (1),…,p' r Bits in (Lcrc-1) Figure 10 The intermediate amplitude bits are the subsequence c” of the second bit sequence at index r. r In the LDPC 802 encoding, Npunc is the number of punctured information bits, and Npm is the configured maximum number of punctured system bits. Npunc is less than or equal to Npm. When bit index j is less than the number of punctured system bits Npunc, the fourth bit sequence c' with index r is... r The bits do not include the subsequence c” of the second bit sequence at index r. r The bits. For bit index j greater than or equal to the system bit puncture number Npunc and less than Npunc + Kc”. r At that time, the fourth bit sequence c' with index r r The bits only include the subsequence c” of the second bit sequence at index r. r The bits, i.e., c' r (Npunc+k)=c” r (k), k = 0, 1, ..., Kc” r -1.

[0505] In some embodiments, the number of code blocks C fec It equals the number of integer blocks Cs.

[0506] In some embodiments, the number of code blocks C fec It is less than the number of integer blocks Cs.

[0507] In some embodiments, for C fec The fourth bit sequence During the process of obtaining the third bit sequence g through channel coding, for indices r = 0, 1, 2, ..., C fec -1, the fourth bit sequence c' of the LDPC coding pair index r in channel coding. r The LDPC encoded output bit sequence d with index r is obtained through the following steps. r :

[0508] Step 1: For all indices r, set the LDPC encoded output bit sequence d at index r. r The length is Nd = NB × Z - Npunc, where NB is the matrix H of the base graph corresponding to the parity check matrix used in LDPC encoding. BG The column number Z is the matrix H of the base graph of the LDPC code used for LDPC encoding. BG The boost value of the parity-check matrix H of the LDPC code used for extended LDPC encoding, where Npunc is the number of punctures in the system bits.

[0509] Step 2: For k = Npunc, Npunc+1, ..., Nc'-1, set the LDPC encoded output bit sequence d with index r as follows: r System bit portion:

[0510] If c' r (k) is not equal to <null>Set d r (k-Npunc)=c' r (k).

[0511] If c' r (k) equals <null>Set c' r (k)=0、d r (k-Npunc) = <NULL>, where c' r (k) is the fourth bit sequence c' of index r. r The bits of index k, d r (k-Npunc) is the LDPC encoded output bit sequence d with index r. r The bits with index k-Npunc are given, and Nc' is the fourth bit sequence c' of index r. r The length.

[0512] Step 3: Generate Nd+Npunc-Nc' parity bits w = [w(0),...,w(Nd+Npunc-Nc'-1)] such that H×[c' r ,w] T =θ, where, [c' r ,w] T Let θ be a column vector of length NB×Z, and let θ be a zero vector of length MB×Z. Matrix and vector multiplication is performed over the Galois field GF(2). The parity check matrix H of the LDPC code is based at least on the matrix H of the fundamental graph of the LDPC code. BG The increase value Z is determined by the value of the increase.

[0513] Step 4: For k = Nc', Nc'+1, ..., Nd+Npunc-1, set the LDPC encoded output bit sequence d. r The parity bit portion: d r (k-Npunc)=w(k-Nc'), where d r (k-Npunc) is the LDPC encoded output bit sequence d with index r. r The bits with index k-Npunc are given, and Nc' is the fourth bit sequence c' of index r. r The length of w(k-Nc') is the parity bit with index k-Nc'.

[0514] It should be noted that the above operations of code block segmentation, code block CRC attachment, and LDPC encoding can make the LDPC encoded output bit sequence d r Starting from index 0, the bits are from the second bit sequence c, which facilitates subsequent rate matching operations.

[0515] In some embodiments, for index r = 0, 1, 2, ..., C fec -1, the LDPC encoded output bit sequence d at index r. r The rate-matched output bit sequence f with index r is obtained by performing the following steps. r :

[0516] Step 1: Determine the rate-matched output bit sequence f with index r. r Length Nf r satisfy Where Qm is the modulation order, and for all indices r, Nf r It is a multiple of Qm.

[0517] Step 2: Encode the LDPC bit sequence d at index r. r Split into the first part d1 of the LDPC encoded output bit sequence r and the second part d2 of the LDPC encoded output bit sequence r The first part d1 of the LDPC encoded output bit sequence r The length is Kc” r That is, the subsequence c” of the second bit sequence with index r. r The length of the LDPC encoded output bit sequence, and the first part d1 r Including the LDPC encoded output bit sequence with index r where the index is less than Kc” r bits, d1 r (k)=d r (k), k = 0, 1, ..., Kc” r -1. The second part d2 of the LDPC encoded output bit sequence. r The length is Nd-Kc” r Nd is the LDPC encoded output bit sequence d r The length of d2, and the second part of the LDPC encoded output bit sequence. r This includes LDPC encoded output bit sequences with index r whose index is greater than or equal to Kc. r The bits, i.e., d2 r (k-Kc” r )=d r (k),k=Kc” r ,1,…,Nd-1.

[0518] Step 3: Output the first part d1 of the bit sequence from the LDPC encoding. r Bit d1 of the first starting index k1×(Qm-2) r Starting with (k1×(Qm-2)), select (Qm-2)×Nfr / Qm non-padded bits with the first circular cache size Ncb1 and place them in the cache matrix H of row Qm and column Nfr / Qm. buff In the last Qm-2 columns. Simultaneously, the second part d2 of the LDPC encoded output bit sequence. r Bit d2 of the first starting index k2 r (k2) Start by selecting 2×Nf with the second loop buffer size Ncb2. r / Qm non-padded bits are placed in row Nf of Qm. r The cache matrix H of column / Qm buff In the first two columns.

[0519] Step 4: Change the Qm row to Nf r The cache matrix H of column / Qm buff The bits in the array are extracted column-by-row to length Nf r The rate-matched output bit sequence f with index r r .

[0520] In some embodiments, C can also be used. fec A rate-matched output bit sequence Concatenating the sequences yields a third bit sequence g of length Ng, where the length of the third bit sequence g satisfies the following condition: and Nf r For the rate-matched output bit sequence f at index r r The length.

[0521] In some embodiments, the third bit sequence g can also be modulated and mapped to obtain the modulation symbol sequence X.

[0522] In some embodiments, the first node performs modulation mapping of the third bit sequence g to obtain the modulation symbol sequence X by modulation order Qm, which includes: mapping the Qm consecutive bits g(j×Qm), g(j×Qm+1), ..., g(j×Qm+Qm-1) in the third bit sequence g to a modulation constellation point X(j) according to a preset modulation mapping method, and finally obtaining the modulation symbol sequence X of length Nx = Ng / Qm.

[0523] The communication method executed by the second node may include the following steps:

[0524] Step 1: The second node obtains the modulation order Qm.

[0525] Step 2: The second node receives a signal including a modulation symbol sequence X, wherein the length of the modulation symbol sequence X is Nx.

[0526] Step 3: The second node demodulates the signal including the modulation symbol sequence X with modulation order Qm to obtain a soft information sequence LLRg(0)~LLRg(Ng-1) with length Ng=Nx×Qm corresponding to the third bit sequence g. Each element in the soft information sequence is a log-likelihood ratio or a probability value.

[0527] Step 4: Channel decoding of the soft information sequence LLRg corresponding to the third bit sequence g of the second node yields C. fec The fourth bit sequence The estimate.

[0528] In some embodiments, step 4 may include the following steps:

[0529] Step 4-1: The second node divides the soft information sequence LLRg(0)~LLRg(Ng-1) corresponding to the third bit sequence g into C fec Subsequences of a soft information sequence Among them, the subsequence LLRg of the soft information sequence of index r r The length of ' is Nf r That is, the rate-matched output bit sequence f with index r in rate-matching 803. r The length, and Qm is the modulation order. For all indices r, Nf r It is a multiple of Qm.

[0530] Step 4-2: For indices r = 0, 1, 2, ..., C fec -1, LLRg r 'Place columns first, then rows into rows Qm and Nf' r The soft information cache matrix H in column / Qm llr_buff middle.

[0531] In some embodiments, the initial LDPC codeword soft information sequence LLRd with index r and length NB×Z is an all-zero sequence, where NB is the matrix H of the base graph corresponding to the parity check matrix used by LDPC encoding 802. BG The column number Z is the matrix H of the base graph of the LDPC code used in LDPC encoding 802. BG The boost value of the parity-check matrix H of the LDPC code used for extended LDPC encoding 802, where Npunc is the number of punctures in the system bits.

[0532] In some embodiments, based on the soft information cache matrix H ll r_b uff The soft information in the middle and later Qm-2 lines is set according to the first circular buffer size Ncb1 and the first starting index k1×(Qm-2) to set the LDPC codeword soft information sequence LLRd. r 'The index is greater than or equal to Npunc and the index is less than Npunc + Kc' r Soft information.

[0533] In some embodiments, based on the soft information cache matrix H llr_buff China Software Information Cache Matrix H llr_buff The soft information in the first two lines is set according to the second loop buffer size Ncb2 and the second starting index k2 to set the LDPC codeword soft information sequence LLRd. r 'Index greater than or equal to Npunc + Kc' r The location of the soft information.

[0534] In some embodiments, for the LDPC encoded output bit sequence d at index r r The index in the middle is the padding bit, and the LDPC codeword soft information sequence LLRd' is set. r The corresponding index is positive infinity.

[0535] In some embodiments, based on the configured LDPC codeword soft information sequence LLRd' r Using the parity-check matrix H of the LDPC code, for example with the belief propagation algorithm or the min-sum algorithm, we obtain the fourth bit sequence c' with index r. r The estimate.

[0536] Step 5: The second node starts from C fec The fourth bit sequence The estimation determines the estimation of the second part b2, the estimation of the second bit sequence c, or the estimation of the integer bit sequence s.

[0537] In some embodiments, for all indices r, the fourth bit sequence c' can be used. r In the estimation, the index is less than Npunc or the index is greater than or equal to Npunc + Kc. r The bits are placed into the corresponding positions in the estimated sequence of the second part b2. From the fourth bit sequence c' r In the estimation, the index is greater than or equal to Npunc and the index is less than Npunc + Kc. r The bits are placed in their corresponding positions in the estimated sequence of the second bit sequence c. Finally, the estimates of the second part b2 and the second bit sequence c are obtained.

[0538] In some embodiments, for all indices r, the fourth bit sequence c' can be used. r In the estimation, the index is less than Npunc or the index is greater than or equal to Npunc + Kc. r The bits are placed into the corresponding positions in the estimated sequence of the second part b2 and the estimated sequence of the shaped bit sequence s. From the fourth bit sequence c' r In the estimation, the index is greater than or equal to Npunc and the index is less than Npunc + Kc. r The bits are placed in their corresponding positions in the estimated sequence of the second bit sequence c. Finally, the estimates of the second part b2, the second bit sequence c, and the shaped bit sequence s are obtained.

[0539] Step 6: The second node performs an integer decoding on the estimate of the second bit sequence c or the estimate of the integer bit sequence s to obtain the estimate of the first part b1.

[0540] In some embodiments, step 6 can be implemented as follows: (1) Convert each consecutive Qm / 2-1 bits in the estimate of the second bit sequence c into an amplitude symbol according to the set amplitude-to-bit mapping rule, and finally obtain the estimate of the integer amplitude symbol sequence A. (2) Divide the estimate of the integer amplitude symbol sequence A into Cs bytes of length NA'0, NA'1, ..., NA' Cs-1 (3) For all indices r, take the estimated integer block output amplitude symbol sequence of index r as input for the corresponding distribution matcher 301 for distribution matching decoding, and obtain the length of index r as K1'. r The shaped input bit sequence b1' r The estimate. (4) Take Cs elements with lengths K1'0, K1'1, ..., K1' Cs-1 The integer input bit sequence b1'0, b1'1, ..., b1' Cs-1 The estimates are cascaded to obtain the estimate of the first part b1.

[0541] In some embodiments, step 6 can be implemented as follows: (1) The estimated integer bit sequence s is divided into Cs segments of length Ks'0, Ks'1, ..., Ks' Cs-1 The integer block outputs an integer bit sequence s'0, s'1, ..., s' Cs-1 The estimate, in a specific example, is s = [s'0, s'1, ..., s' Cs-1 (2) For all indices r, output the integer block as integer s'. r The estimate and according to Ks' r and Ns' r The generator matrix G is set. r Multiplying over the Galois domain GF(2) yields a product of length Ns'. r The integer block codeword bit sequence v' r The estimation. (3) Take the Cs integer block codeword bit sequence v'0,v'1,…,v' Cs-1 The estimated cascade length is NLLR = Ns'0 + Ns'1 + ... + Ns' Cs-1 (4) Perform a bit masking operation on the estimated integer codeword bit sequence v and the estimated second bit sequence c to obtain the estimated first part b1, wherein the estimated bits of the second bit sequence c are replaced by the first part b1 in the bit masking operation, and the estimated integer codeword bit sequence v is replaced by the integer codeword bit sequence v in the bit masking operation.

[0542] Step 7: The second node concatenates the estimates of the first part b1 and the second part b2 to obtain the estimate of the first bit sequence b.

[0543] The communication method provided in this disclosure can be applied to... Figure 1 The second node 102 in the communication system shown. Figure 11 A flowchart of a communication method is shown, such as... Figure 11 As shown, the communication method includes the following S1101-S1106:

[0544] S1101, Obtain the modulation order.

[0545] S1102, Receive a signal including a modulation symbol sequence.

[0546] S1103. Based on the modulation order, demodulate the modulation symbol sequence to obtain the third bit sequence.

[0547] S1104. Decode the third bit sequence to obtain the second part of the first bit sequence and the second bit sequence.

[0548] In some embodiments, S1104, decoding the third bit sequence to obtain the second part of the first bit sequence and the second bit sequence includes: performing channel decoding on the third bit sequence to obtain a fourth bit sequence; and splitting the fourth bit sequence to obtain the second part of the first bit sequence and the second bit sequence.

[0549] S1105. Perform shaping and decoding on the second bit sequence to obtain the first part of the first bit sequence.

[0550] S1106. Based on the first part and the second part, determine the first bit sequence.

[0551] In some embodiments, there are multiple fourth bit sequences.

[0552] In some embodiments, the number of fourth bit sequences is equal to the number of integer blocks after the first part of the integer encoding is segmented.

[0553] In some embodiments, the number of fourth bit sequences is not equal to the number of integer blocks after the first part of the integer encoding is segmented.

[0554] In some embodiments, there are multiple fourth bit sequences; the bits in the fourth bit sequence whose index is less than the number of bit punctures in the first system include at least one of the following: bits in the second part, bits in the shaped bit sequence, and padding bits.

[0555] In some embodiments, bits in the fourth bit sequence whose index is less than the number of punctures in the first system bit sequence do not include bits in the second bit sequence other than the integer bit sequence.

[0556] In some embodiments, the bits in the fourth bit sequence whose index is equal to the number of punctures in the first system bit sequence are bits in the second bit sequence other than the integer bit sequence.

[0557] In some embodiments, there are multiple fourth bit sequences. Bits in the fourth bit sequence with an index greater than or equal to the number of punctures in the first system include at least one of the following: bits in the second part, bits in the shaped bit sequence, padding bits, or bits in the second bit sequence other than the shaped bit sequence.

[0558] In some embodiments, the second bit sequence includes an integer bit sequence.

[0559] In some embodiments, the first bit sequence satisfies one of the following:

[0560] The first bit sequence is the transmission block sent from the first node to the second node;

[0561] The first bit sequence includes the transport block sent from the first node to the second node and the cyclic redundancy check bits.

[0562] In some embodiments, the sum of the length of the first part and the length of the second part is the length of the first bit sequence.

[0563] In some embodiments, the first part and the second part satisfy one of the following:

[0564] The bits in the first part are the bits in the first bit sequence whose index is less than the first value. The bits in the second part are the bits in the first bit sequence whose index is greater than or equal to the first value. The first bit sequence includes the second number of bits.

[0565] The bits in the first part are the bits in the first bit sequence whose index is greater than or equal to the difference between the second value and the first value. The first bit sequence includes the second number of bits. The bits in the second part are the bits in the first bit sequence whose index is less than the difference between the second value and the first value. The first value is the length of the first part, and the second value is the length of the first bit sequence.

[0566] It should be noted that it is applied to Figure 1 The explanation of an embodiment of the communication method of the second node 102 in the communication system shown can be referred to the application of Figure 1 The explanation of an embodiment of the communication method of the first node 101 in the communication system shown will not be repeated here.

[0567] The disclosed embodiments can divide the communication device into functional modules according to the above method embodiments. For example, each function can be divided into a separate functional module, or two or more functions can be integrated into one functional module. The integrated module can be implemented in hardware or software. It should be noted that the module division in this disclosed embodiment is illustrative and only represents one logical functional division. In actual implementation, there may be other division methods. The following description uses the example of dividing each functional module according to each function.

[0568] Figure 12 This is a schematic diagram of another communication device provided in an embodiment of this disclosure. The communication device can execute the communication method provided in the above-described method embodiments. Figure 12 As shown, the communication device includes: an acquisition module 1201, a processing module 1202, and a transmission module 1203.

[0569] Get module 1201, get the first bit sequence.

[0570] The processing module 1202 is used to perform shaping encoding on the first part of the first bit sequence to obtain the second bit sequence.

[0571] The processing module 1202 is also used to perform channel coding based on the second part of the first bit sequence and the second bit sequence to obtain the third bit sequence.

[0572] The processing module 1202 is also used to modulate the third bit sequence to obtain a modulated symbol sequence.

[0573] The transmitting module 1203 is used to transmit a signal including a modulation symbol sequence to the second node.

[0574] In some embodiments, the processing module 1202 is specifically used to merge the second part of the first bit sequence and the second bit sequence to obtain a fourth bit sequence.

[0575] The processing module 1202 is also specifically used to perform channel coding on the fourth bit sequence to obtain the third bit sequence.

[0576] In some embodiments, the fourth bit sequence satisfies one of the following:

[0577] There are multiple fourth bit sequences;

[0578] The number of bits in the fourth bit sequence is equal to the number of integer blocks after the first part of the integer encoding is segmented;

[0579] The number of bits in the fourth bit sequence is not equal to the number of integer blocks after the first part of the integer encoding is segmented.

[0580] In some embodiments, there are multiple fourth bit sequences; the bits in the fourth bit sequence whose index is less than the number of bit punctures in the first system include at least one of the following:

[0581] The second part consists of bits, bits in an integer bit sequence, or padding bits.

[0582] In some embodiments, the bits in the fourth bit sequence whose index is less than the number of punctures in the first system bit sequence do not include the bits in the second bit sequence other than the integer bit sequence.

[0583] In some embodiments, there are multiple fourth bit sequences; the bits in the fourth bit sequence whose index is greater than or equal to the number of bit punctures in the first system include at least one of the following:

[0584] The bits in the second part, the bits in the integer bit sequence, the padding bits, or the bits in the second bit sequence other than the integer bit sequence.

[0585] In some embodiments, the bits in the fourth bit sequence whose index is equal to the number of punctures in the first system bit sequence are bits in the second bit sequence other than the integer bit sequence.

[0586] In some embodiments, the third bit sequence is modulated to obtain a modulated symbol sequence, including:

[0587] Obtain the modulation order;

[0588] Based on the modulation order, the third bit sequence is modulated to obtain the modulation symbol sequence.

[0589] In some embodiments, the second bit sequence includes an integer bit sequence.

[0590] In some embodiments, the first bit sequence satisfies one of the following:

[0591] The first bit sequence is the transmission block sent from the first node to the second node;

[0592] The first bit sequence includes the transport block sent from the first node to the second node and the cyclic redundancy check bits.

[0593] In some embodiments, the sum of the length of the first part and the length of the second part is the length of the first bit sequence.

[0594] In some embodiments, the first part and the second part satisfy one of the following:

[0595] The bits in the first part are the bits in the first bit sequence whose index is less than the first value. The bits in the second part are the bits in the first bit sequence whose index is greater than or equal to the first value. The first bit sequence includes the second number of bits.

[0596] The bits in the first part are the bits in the first bit sequence whose index is greater than or equal to the difference between the second value and the first value. The first bit sequence includes the second number of bits. The bits in the second part are the bits in the first bit sequence whose index is less than the difference between the second value and the first value. The first value is the length of the first part, and the second value is the length of the first bit sequence.

[0597] Figure 13 This is a schematic diagram of another communication device provided in an embodiment of this disclosure. The communication device can execute the communication method provided in the above-described method embodiments. Figure 13 As shown, the communication device includes: an acquisition module 1301, a receiving module 1302, and a processing module 1303.

[0598] The acquisition module 1301 is used to acquire the modulation order.

[0599] The receiving module 1302 is used to receive signals including a modulation symbol sequence.

[0600] The processing module 1303 is used to demodulate the modulation symbol sequence based on the modulation order to obtain the third bit sequence.

[0601] The processing module 1303 is also used to decode the third bit sequence to obtain the second part of the first bit sequence and the second bit sequence.

[0602] The processing module 1303 is also used to perform shaping and decoding on the second bit sequence to obtain the first part of the first bit sequence.

[0603] The processing module 1303 is also used to determine the first bit sequence based on the first part and the second part.

[0604] In some embodiments, the processing module 1303 is specifically used to perform channel decoding on the third bit sequence to obtain the fourth bit sequence.

[0605] The processing module 1303 is also specifically used to split the fourth bit sequence to obtain the second part of the first bit sequence and the second bit sequence.

[0606] In some embodiments, the fourth bit sequence satisfies one of the following: there are multiple fourth bit sequences; the number of fourth bit sequences is equal to the number of integer blocks after the first part of the integer encoding is segmented; the number of fourth bit sequences is not equal to the number of integer blocks after the first part of the integer encoding is segmented.

[0607] In some embodiments, there are multiple fourth bit sequences; the bits in the fourth bit sequence whose index is less than the number of bit punctures in the first system include at least one of the following:

[0608] The second part consists of bits, bits in an integer bit sequence, or padding bits.

[0609] In some embodiments, bits in the fourth bit sequence whose index is less than the number of punctures in the first system bit sequence do not include bits in the second bit sequence other than the integer bit sequence.

[0610] In some embodiments, there are multiple fourth bit sequences; the bits in the fourth bit sequence whose index is greater than or equal to the number of bit punctures in the first system include at least one of the following:

[0611] The bits in the second part, the bits in the integer bit sequence, the padding bits, or the bits in the second bit sequence other than the integer bit sequence.

[0612] In some embodiments, the bits in the fourth bit sequence whose index is equal to the number of punctures in the first system bit sequence are bits in the second bit sequence other than the integer bit sequence.

[0613] In some embodiments, the second bit sequence includes an integer bit sequence.

[0614] In some embodiments, the first bit sequence satisfies one of the following:

[0615] The first bit sequence is the transmission block sent from the first node to the second node;

[0616] The first bit sequence includes the transport block sent from the first node to the second node and the cyclic redundancy check bits.

[0617] In some embodiments, the sum of the length of the first part and the length of the second part is the length of the first bit sequence.

[0618] In some embodiments, the first part and the second part satisfy one of the following:

[0619] The bits in the first part are the bits in the first bit sequence whose index is less than the first value, and the bits in the second part are the bits in the first bit sequence whose index is greater than or equal to the first value. The first bit sequence includes the second number of bits.

[0620] The bits in the first part are the bits in the first bit sequence whose index is greater than or equal to the difference between the second value and the first value. The first bit sequence includes the second number of bits. The bits in the second part are the bits in the first bit sequence whose index is less than the difference between the second value and the first value. The first value is the length of the first part, and the second value is the length of the first bit sequence.

[0621] In implementing the functionality of the integrated modules described above using hardware, this disclosure provides another possible structure for the communication device involved in the above embodiments. For example... Figure 14 As shown, the communication device includes: a processor 1402 and a bus 1404. Optionally, the communication device may also include a memory 1401; alternatively, the communication device may also include a communication interface 1403.

[0622] Processor 1402 may implement or execute various exemplary logic blocks, modules, and circuits described in conjunction with embodiments of this disclosure. Processor 1402 may be a central processing unit, a general-purpose processor, a digital signal processor, an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. It may implement or execute various exemplary logic blocks, modules, and circuits described in conjunction with embodiments of this disclosure. Processor 1402 may also be a combination of functions implementing computational capabilities, such as a combination of one or more microprocessors, a combination of a DSP and a microprocessor, etc.

[0623] Communication interface 1403 is used to connect to other devices via a communication network. This communication network can be Ethernet, wireless access network, wireless local area network (WLAN), etc.

[0624] The memory 1401 may be a read-only memory (ROM) or other type of static storage device capable of storing static information and instructions, random access memory (RAM) or other type of dynamic storage device capable of storing information and instructions, or electrically erasable programmable read-only memory (EEPROM), disk storage medium or other magnetic storage device, or any other medium capable of carrying or storing desired program code in the form of instructions or data structures and accessible by a computer, but is not limited thereto.

[0625] As one possible implementation, the memory 1401 can exist independently of the processor 1402. The memory 1401 can be connected to the processor 1402 via a bus 1404 and is used to store instructions or program code. When the processor 1402 calls and executes the instructions or program code stored in the memory 1401, it can implement the method provided in the embodiments of this disclosure.

[0626] In another possible implementation, the memory 1401 can also be integrated with the processor 1402.

[0627] The 1404 bus can be an extended industry standard architecture (EISA) bus, etc. The 1404 bus can be divided into address bus, data bus, control bus, etc. For ease of representation, Figure 14 The bus is represented by a single thick line, but this does not mean that there is only one bus or one type of bus.

[0628] Some embodiments of this disclosure provide a computer-readable storage medium (e.g., a non-transitory computer-readable storage medium) storing computer program instructions that, when executed on a computer, cause the computer to perform the methods described in any of the above embodiments.

[0629] For example, the aforementioned computer-readable storage media may include, but are not limited to: magnetic storage devices (e.g., hard disks, floppy disks, or magnetic tapes), optical disks (e.g., compact disks (CDs), digital versatile disks (DVDs), etc.), smart cards, and flash memory devices (e.g., erasable programmable read-only memory (EPROMs), cards, sticks, or key drives, etc.). The various computer-readable storage media described in this disclosure may represent one or more devices for storing information and / or other machine-readable storage media. The term "machine-readable storage media" may include, but is not limited to, wireless channels and various other media capable of storing, containing, and / or carrying instructions and / or data.

[0630] This disclosure provides a computer program product containing instructions that, when run on a computer, cause the computer to perform the methods described in any of the above embodiments.

[0631] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions within the technical scope disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.< / null> < / null> < / null> < / null> < / null> < / null> < / null> < / null> < / null> < / null> < / null> < / null> < / null> < / null> < / null> < / null> < / null> < / null> < / null> < / null> < / null> < / null> < / null> < / null> < / null>

Claims

1. A communication method, characterized in that, Applied to the first node, the method includes: Obtain the first bit sequence; The first part of the first bit sequence is shaped and encoded to obtain the second bit sequence; Channel coding is performed based on the second part of the first bit sequence and the second bit sequence to obtain the third bit sequence; The third bit sequence is modulated to obtain a modulated symbol sequence; A signal including the modulation symbol sequence is sent to the second node.

2. The method according to claim 1, characterized in that, The process of channel coding based on the second part of the first bit sequence and the second bit sequence to obtain the third bit sequence includes: The second part of the first bit sequence and the second bit sequence are combined to obtain the fourth bit sequence; The fourth bit sequence is channel-coded to obtain the third bit sequence.

3. The method according to claim 2, characterized in that, The fourth bit sequence satisfies one of the following: There are multiple fourth bit sequences; The number of the fourth bit sequence is equal to the number of integer blocks after the first part of the integer encoding segmentation; The number of the fourth bit sequence is not equal to the number of integer blocks after the first part of the integer encoding segmentation.

4. The method according to claim 2, characterized in that, There are multiple fourth bit sequences; the bits in the fourth bit sequence whose index is less than the number of bit punctures in the first system include at least one of the following: The bits in the second part, bits in the integer bit sequence, or padding bits.

5. The method according to claim 2, characterized in that, The bits in the fourth bit sequence whose index is less than the number of punctures in the first system bit sequence do not include the bits in the second bit sequence other than the integer bit sequence.

6. The method according to claim 2, characterized in that, There are multiple fourth bit sequences; the bits in the fourth bit sequence whose index is greater than or equal to the number of punctures in the first system include at least one of the following: The bits in the second part, the bits in the integer bit sequence, the padding bits, or the bits in the second bit sequence other than the integer bit sequence.

7. The method according to claim 6, characterized in that, The bits in the fourth bit sequence whose index is equal to the number of punctures in the first system bit sequence are bits in the second bit sequence excluding the integer bit sequence.

8. The method according to claim 1, characterized in that, The modulation of the third bit sequence to obtain a modulation symbol sequence includes: Obtain the modulation order; Based on the modulation order, the third bit sequence is modulated to obtain the modulation symbol sequence.

9. The method according to claim 1, characterized in that, The second bit sequence includes an integer bit sequence.

10. The method according to claim 1, characterized in that, The first bit sequence satisfies one of the following: The first bit sequence is a transport block sent from the first node to the second node; The first bit sequence includes the transport block sent by the first node to the second node and cyclic redundancy check bits.

11. The method according to claim 1, characterized in that, The sum of the length of the first part and the length of the second part is the length of the first bit sequence.

12. The method according to claim 11, characterized in that, The first part and the second part satisfy one of the following: The bits in the first part are the bits in the first bit sequence whose index is less than the first value, and the bits in the second part are the bits in the first bit sequence whose index is greater than or equal to the first value. The first bit sequence includes a second number of bits. The bits in the first part are the bits in the first bit sequence whose index is greater than or equal to the difference between the second value and the first value. The first bit sequence includes the second number of bits. The bits in the second part are the bits in the first bit sequence whose index is less than the difference between the second value and the first value. The first value is the length of the first part, and the second value is the length of the first bit sequence.

13. A communication method, characterized in that, Applied to the second node, the method includes: Obtain the modulation order; Receive signals including a modulated symbol sequence; Based on the modulation order, the modulation symbol sequence is demodulated to obtain the third bit sequence; Decoding the third bit sequence yields the second part of the first bit sequence and the second bit sequence; The second bit sequence is shaped and decoded to obtain the first part of the first bit sequence; Based on the first part and the second part, a first bit sequence is determined.

14. The method according to claim 13, characterized in that, Decoding the third bit sequence to obtain the second part of the first bit sequence and the second bit sequence includes: Channel decoding is performed on the third bit sequence to obtain the fourth bit sequence; The fourth bit sequence is split to obtain the second part of the first bit sequence and the second bit sequence.

15. The method according to claim 14, characterized in that, The fourth bit sequence satisfies one of the following: there are multiple fourth bit sequences; the number of fourth bit sequences is equal to the number of integer blocks after the first part of the integer encoding is segmented; the number of fourth bit sequences is not equal to the number of integer blocks after the first part of the integer encoding is segmented.

16. The method according to claim 14, characterized in that, There are multiple fourth bit sequences; the bits in the fourth bit sequence whose index is less than the number of bit punctures in the first system include at least one of the following: The bits in the second part, bits in the integer bit sequence, or padding bits.

17. The method according to claim 14, characterized in that, The fourth bit sequence contains bits with indices less than the number of punctures in the first system bit sequence, excluding bits in the second bit sequence other than the integer bit sequence.

18. The method according to claim 14, characterized in that, There are multiple fourth bit sequences; the bits in the fourth bit sequence whose index is greater than or equal to the number of punctures in the first system include at least one of the following: The bits in the second part, the bits in the integer bit sequence, the padding bits, or the bits in the second bit sequence other than the integer bit sequence.

19. The method according to claim 18, characterized in that, The bits in the fourth bit sequence whose index is equal to the number of punctures in the first system bit sequence are bits in the second bit sequence excluding the integer bit sequence.

20. The method according to claim 13, characterized in that, The second bit sequence includes an integer bit sequence.

21. The method according to claim 13, characterized in that, The first bit sequence satisfies one of the following: The first bit sequence is a transport block sent from the first node to the second node; The first bit sequence includes the transport block sent by the first node to the second node and cyclic redundancy check bits.

22. The method according to claim 13, characterized in that, The sum of the length of the first part and the length of the second part is the length of the first bit sequence.

23. The method according to claim 22, characterized in that, The first part and the second part satisfy one of the following: The bits in the first part are the bits in the first bit sequence whose index is less than the first value, and the bits in the second part are the bits in the first bit sequence whose index is greater than or equal to the first value. The first bit sequence includes a second number of bits. The bits in the first part are the bits in the first bit sequence whose index is greater than or equal to the difference between the second value and the first value. The first bit sequence includes the second number of bits. The bits in the second part are the bits in the first bit sequence whose index is less than the difference between the second value and the first value. The first value is the length of the first part, and the second value is the length of the first bit sequence.

24. A communication device, characterized in that, include: Memory and processor; Memory and processor are coupled; The memory is used to store instructions that can be executed by the processor; When the processor executes the instruction, it performs the method as described in any one of claims 1-12, or the method as described in any one of claims 13-23.

25. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions that, when executed on a computer, cause the computer to perform the method as described in any one of claims 1-12, or the method as described in any one of claims 13-23.

26. A computer program product, characterized in that, The computer program product includes computing technology program instructions, which, when executed by a processor, implement the method as described in any one of claims 1-12, or the method as described in any one of claims 13-23.

Images